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preliminary tx9956cxbg 2004-4-25 1 tx9956cxbg tx9956cxbg-533/-600 (tx9956c) (64-bit risc microprocessor) 1. general description the tx9956c is a 64-bit risc (reduced instruction set computer) microprocessor that is a low-cost, low-power microprocessor developed for interactive consumer applications including set-top terminals, lbp(laser beam printer), and video games. 2. features - true 64-bit microprocessor, with tx99/h4 core. - 7-stage super-scalar pipeline - 64bit system address/data bus (support 32bit bus mode) - single or double-precision floating-point operation - 36-bit physical address space and 64-bit virtual address space. - 64-bit sysad bus interface with r5000 compatible protocol - on-chip 32-kbyte instruction cache, 32-kbyte data cache and 256kb level 2 cache. - low power consumption 3.3v or 2.5v / 1.25v dual power supply (i/o:3.3v or 2.5v, internal:1.25v) power management mode - memory management unit contains 48-double entry jtlb, and 8-entry data tlb - software compatibility with all mips processors mips64 instruction set architecture (isa) and mips-3d ase - ejtag (enhanced jtag) debug support - maximum operating frequency internal: 533 to 600mhz external:133hz - package : 272-pin pbga with 16-pin thermal balls, 27mm x 27mm, 1.27mm pitch ? the information contained herein is subject to change without notice. ? toshiba is continually working to improve the quality and the reliability of its products. nevertheless, semiconductor device s in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibi lity of the buyer, when utilizing toshiba products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a t oshiba product could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent products specifications. also, please keep in mind the precautions and conditions set forth in the toshiba semiconductor rel iability handbook ? the information contained herein is presented only as a guide for the applications of our products. no responsibility is assume d by toshiba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by i mplication or otherwise under any patent or patent rights of toshiba or others. toshiba risc processor
preliminary tx9956cxbg 2004-4-25 2 tx9956cxbg 3. system configuration 3.1 tx9956c block diagram tx99/h4 core 4way set associative 32k byte instruction cache integer execution unit 32 x 64 gpr pipeline control a instruction decode pi p eline queue inst. dis p atch tx9956c-533/600 debug support unit (ejtag) 32 x 64 fpr 256 k byte secondary cache 4way set associative pipeline control b pipeline bypass instruction dispatc unit instruction buffer floatin g -point unit pipeline bypass fp single 0 mips-3d fp single 1 mips-3d return prediction stack branch history table 4 way set associative 32k byte data cache write buffer fill/store buffer mmu control 48double entry joint-tlb 8 entry micro-tlb bus interface unit (mgb ii) clock generator pll test ciurcuit jtag etc. external bus interface unit mgb ii bus to sysad bus 64-bit / 32-bit sysad bus interface ejtag interface input clock
preliminary tx9956cxbg 2004-4-25 3 tx9956cxbg 3.2 block function tx99/h4 core true 64-bit microprocessor 32, 64-bit integer general purpose registers 32, 64-bit floating point general purpose registers 7-stage super-scalar pipeline instruction set mips64 isa 3d graphic?s instructions on-chip 32-kbyte instruction cache, 32-kbyte data cache and 256kb level2 cache 4-way set associative and lock function support : primary cache data cache: write-back and write-through support : primary cache 256kb secondary cache mmu 32-bit physical address space and 64-bit virtual address space 48-double-entry (even/odd) joint tlb 8-entry data tlb ieee754 compatible single and double precision fpu debug support unit (dsu) with ejtag support rp and sleep mode sysad bus i/f bus protocol conversion it converts tx9956c internal mgb ii read/write request into outside syad bus protocol. clock generator generates the internal operating clock of the tx9901 from external crystal oscillator. debug support unit ( dsu ) ejtag function support consists of an enhanced jtag (ejtag) module and a debug support unit (dsu). it can be used to provide single-step execution and hardware break-points for debugging processor systems. ejtag utilizes jtag interface and extends the ability to access the inside register contents, host system peripherals, and system memory.
preliminary tx9956cxbg 2004-4-25 4 tx9956cxbg 4. pin description 4.1 pin out a1 vss b11 syscmd2 d1 reset* f3 sysad47 j17 vss a2 nc b12 vccok d2 coldreset* f4 vccio j18 vccint a3 nc b13 sysadc6 d3 tmode f17 vss j19 sysad13 a4 sysadc4 b14 sysadc7 d4 vss f18 sysad38 j20 sysad12 a5 sysadc5 b15 validout* d5 vccint f19 sysad37 k1 vccio a6 int4* b16 wrrdy* d6 vss f20 vccio k2 sysad22 a7 vccint b17 rdrdy* d7 vss g1 vccint k3 sysad21 a8 vss b18 nc d8 vccio g2 sysad49 k4 vccio a9 syscmd8 b19 nc d9 vss g3 vccint k9 vss a10 syscmd5 b20 vccint d10 vss g4 vss k10 vss a11 syscmd3 c1 nmi* d11 vccio g17 vss k11 vss a12 release* c2 extrqst* d12 vss g18 vccint k12 vss a13 vccio c3 vccio d13 vccio g19 sysad36 k17 vss a14 vss c4 vccint d14 vss g20 vss k18 vccint a15 validin* c5 nc d15 vss h1 endian k19 sysad11 a16 vss c6 int2* d16 vccio h2 sysad17 k20 sysad10 a17 vss c7 vccint d17 vss h3 sysad16 l1 vss a18 nc c8 syscmdp d18 sysad42 h4 vccio l2 sysad23 a19 jtrst* c9 syscmd6 d19 sysad41 h17 vss l3 vccint a20 vss c10 vccint d20 rp h18 vccio l4 vss b1 vccint c11 syscmd1 e1 sysad46 h19 sysad15 l9 vss b2 nc c12 syscmd0 e2 sysad45 h20 sysad14 l10 vss b3 nc c13 nc e3 sysad44 j1 sysad20 l11 vss b4 sysad43 c14 vccint e4 vss j2 sysad19 l12 vss b5 int5* c15 bsize64* e17 vss j3 sysad18 l17 vccio b6 int3* c16 vccint e18 vccio j4 vss l18 sysad8 b7 int1* c17 vss e19 sysad40 j9 vss l19 sysad9 b8 int0* c18 vccio e20 sysad39 j10 vss l20 vccint b9 syscmd7 c19 nc f1 vss j11 vss m1 sysad26 b10 syscmd4 c20 sleep f2 sysad48 j12 vss m2 sysad25
preliminary tx9956cxbg 2004-4-25 5 tx9956cxbg m3 sysad24 p20 sysad35 u9 vss v14 vccint w19 vccpll m4 vccio r1 vss u10 vss v15 sysad62 w20 masterclk m9 vss r2 sysad53 u11 vss v16 sysad63 y1 vss m10 vss r3 sysad52 u12 vccio v17 ejdint y2 sysdiv0 m11 vss r4 vccint u13 vss v18 vccio y3 sysad57 m12 vss r17 vss u14 vss v19 nc y4 vccint m17 vss r18 jtms u15 vss v20 vss y5 vss m18 sysad6 r19 sysad32 u16 vss w1 vccint y6 sysad29 m19 sysad7 r20 sysad33 u17 vss w2 sysdiv1 y7 sysad31 m20 vss t1 sysad55 u18 jtdo w3 sysad56 y8 fmo n1 sysad27 t2 sysad54 u19 bufsel w4 sysad58 y9 vccio n2 sysad51 t3 nc u20 vccint w5 sysad60 y10 vss n3 sysad50 t4 vccio v1 corediv3 w6 sysad28 y11 sysadc1 n4 vss t17 vccio v2 sysdiv2 w7 sysad30 y12 sysad1 n17 vss t18 jtck v3 vccio w8 fmrd y13 nc n18 vccio t19 jtdi v4 vccint w9 fmsi y14 vss n19 sysad4 t20 vss v5 sysad59 w10 sysadc3 y15 vccint n20 sysad5 u1 corediv2 v6 sysad61 w11 sysad0 y16 ejtrig0 p1 vccint u2 corediv1 v7 vccint w12 sysad2 y17 jtagsel p2 vss u3 corediv0 v8 fmclk w13 nc y18 bypasscorecg p3 vccint u4 vss v9 sysadc2 w14 nc y19 vsspll p4 vss u5 vccio v10 sysadc0 w15 nc y20 vss p17 vss u6 vss v11 vccint w16 ejtrig1 p18 vccint u7 vss v12 sysad3 w17 l2bypass p19 sysad34 u8 vccio v13 nc w18 bypasspll
preliminary tx9956cxbg 2004-4-25 6 tx9956cxbg 4.2 pin layout top view a b c d e f g h j k 20 vss vccint sleep rp sysad39 vccio vss sysad14 sysad12 sysad10 19 jtrst* nc nc sysad41 sysad40 sysad37 sysad36 sysad15 sysad13 sysad11 18 nc nc vccio sysad42 vccio sysad38 vccint vccio vccint vccint 17 vss rdrdy* vss vss vss vss vss vss vss vss 16 vss wrrdy* vccint vccio 15 validin* validout* bsize64* vss 14 vss sysadc7 vccint vss 13 vccio sysadc6 nc vccio 12 release* vccok syscmd0 vss 11 syscmd3 syscmd2 syscmd1 vccio 10 syscmd5 syscmd4 vccint vss 9 syscmd8 syscmd7 syscmd6 vss 8 vss int0* syscmdp vccio 7 vccint int1* vccint vss 6 int4* int3* int2* vss 5 sysadc5 int5* nc vccint vss vss vss vss vss vss vss vss top view 4 sysadc4 sysad43 vccint vss vss vccio vss vccio vss vccio 3 nc nc vccio tmode sysad44 sysad47 vccint sysad16 sysad18 sysad21 2 nc nc extrqst* coldreset* sysad45 sysad48 sysad49 sysad17 sysad19 sysad22 1 vss vccint nmi* reset* sysad46 vss vccint endian sysad20 vccio
preliminary tx9956cxbg 2004-4-25 7 tx9956cxbg l m n p r t u v w y vccint vss sysad5 sysad35 sysad33 vss vccint vss masterclk vss 20 sysad9 sysad7 sysad4 sysad34 sysad32 jtdi bufsel nc vccpll vsspll 19 sysad8 sysad6 vccio vccint jtms jtck jtdo vccio bypasspll bypass corecg 18 vccio vss vss vss vss vccio vss ejdint l2bypass jtagsel 17 vss sysad63 ejtrig1 ejtrig0 16 vss sysad62 nc vccint 15 vss vccint nc vss 14 vss nc nc nc 13 vss vss vccio sysad3 sysad2 sysad1 12 vss vss vss vccint sysad0 sysadc1 11 vss vss vss sysadc0 sysadc3 vss 10 vss vss vss sysadc2 fmsi vccio 9 vccio fmclkfmrd fmo 8 vss vccint sysad30 sysad31 7 vss sysad61 sysad28 sysad29 6 top view vccio sysad59 sysad60 vss 5 vss vccio vss vss vccint vccio vss vccint sysad58 vccint 4 vccint sysad24 sysad50 vccint sysad52 nc corediv0 vccio sysad56 sysad57 3 sysad23 sysad25 sysad51 vss sysad53 sysad54 corediv1 sysdiv2 sysdiv1 sysdiv0 2 vss sysad26 sysad27 vccint vss sysad55 corediv2 corediv3 vccint vss 1
preliminary tx9956cxbg 2004-4-25 8 tx9956cxbg 4.3 pin function the following is a list of interface, interrupt, and miscellaneous pins available on the tx9956c. system interface pin name i / o function sysad(63:0) i / o system address / data bus a 64-bit address and data bus for communication between the processor and an external agent. syscmd(8:0) i / o system command / data identifier bus a 9-bit bus for command and data identifier transmission between the processor and an external agent. sysadc(7:0) i / o system command/data check bus a 8-bit bus containing parity check bits for the sysad bus during data cycles. syscmdp i / o reserved for system command/data identifier bus parity for the tx9956c this signal is unused on input and zero on output. validin* i valid input the external agent asserts validin* when it is driving a valid address or data on the sysad bus and a valid command or data identifier on the syscmd bus. validout* o valid output the processor asserts validout* when it is driving a valid address or data on the sysad bus and a valid command or data identifier on the syscmd bus. extrqst* i external request an external agent asserts extrqst* to request use of the system interface. release* o release interface signals that the system interface needs to submit an external request. wrrdy* i write ready signals that an external agent can now accept a processor write request. rdrdy* i read ready signals that an external agent can now accept a processor read request.
preliminary tx9956cxbg 2004-4-25 9 tx9956cxbg clock / control interface pin name i / o function masterclock i master clock master clock input that establishes the processor operating frequency. corediv(3:0) i set the operational frequency of tx99h4 core vs l2 cache corediv( 3:0 ) cpu core : l2 cache 0000 reserved 0001 2:1 0010 3:1 0011 4:1 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111 reserved sysdiv(2:0) i set the operational frequency of mbg ii bus vs sysad bus sysdiv( 2:0 ) mgb ii bus : sysad bus i/f 000 reserved 001 reserved 010 2:1 011 3:1 100 4:1 101 reserved 110 reserved 111 reserved sleep o sleep mode rp o rp mode endian i endianess input indicates the initial setting of the endian during a reset. 0 little endian 1 big endian l2bypass i l2 cache bypass mode bypasspll i test mode bypasscorecg i test mode
preliminary tx9956cxbg 2004-4-25 10 tx9956cxbg interrupt interface pin name i / o function int(5:0)* i interrupt five general processor interrupts, bit-wise ored with bits 5:0 of the interrupt register and visible as bits 15:10 of the cause register. nmi* i non-maskable interrupt non-maskable interrupt, ored with bit 6 of the interrupt register. jtag and ejtag interface pin name i / o function jtdi i jtag data input / debug interrupt input run-time mode : input serial data to data/instruction register of jtag. real-time mode : interrupt line to change the debug unit state from real time mode to run-time mode. jtck i jtag clock input the processor receives a serial clock on jtck. on the rising edge of jtck, both jtdi and jtms are sampled. jtdo o jtag data output / pc trace output run-time mode : output serial data from data/instruction register of jtag. real-time mode : output non-sequential program. jtms i jtag command jtag command signal, indicating the incoming serial data is command data. ejdint i debug interrupt for ejtag ejtrig(1:0) o trigger output for ejtag jtagsel i jtag select jtrst* i test reset input a reset input for a real-time debug system. when jtrst* is asserted, the debug support unit (dsu) is initialized.
preliminary tx9956cxbg 2004-4-25 11 tx9956cxbg initialization interface pin name i / o function vccok i vccok reset* i soft (warm) reset this signal must be asserted synchronously with masterclock for a soft reset. coldreset* i cold reset this signal indicates to the processor that the +3.3v(i/o) and +1.2v(internal) power supply is stable and the processor should initiate a cold reset sequence, resetting the pll. bsize64* i select the bus width of external sysad bus interface bsize64* width 0 64-bit 1 32-bit bufsel i select the output buffer size bufsel buffer size 0 16ma buffer 1 8ma buffer others pin name i / o function fmrd i test signal fmsi i test signal fmo o test signal fmclk i test signal tmode i test mode
preliminary tx9956cxbg 2004-4-25 12 tx9956cxbg power supply pin name i / o function vccpll i quiet v cc for pll quiet v cc for the internal phase locked loop. ( 1.25v ) vsspll i quiet v ss for pll quiet v ss for the internal phase locked loop. vccio i vcc power supply pin for io.( 3.3v or 2.5v ) vccint i vcc power supply pin for internal.( 1.25v ) vss i vss ground pin
preliminary tx9956cxbg 2004-4-25 13 tx9956cxbg 5. electrical characteristics note: ?be careful of static? , please see ?from incoming to shipping? of general safety precautions and usage considerations. 5.1 absolute maximum ratings v ss = 0 v (gnd) parameter symbol ratings unit supply voltage ( for i/o) vcciomax -0.5 to 3.9 v supply voltage ( for internal ) vccintmax -0.5 to 3.0 v input voltage (*1) v in -0.5 to v cc + 0.3 v storage temperature t stg -40 to +125 c note ) if lsi is used above the maximum ratings, permanent destruction of lsi can result. in addition, it is desirable to use lsi for normal operation under the recommended condition. if these conditions are exceeded, reliability of lsi may be adversely affected. (*1) keep (vccio + 0.3v) less than vcciomax 5.2 recommended operating conditions v ss = 0 v (gnd) parameter symbol conditions min. max. unit supply voltage ( for i/o ) vccio 3.3v i/o 3.0 3.6 v 2.5v i/o 2.1 2.7 v supply voltage ( for internal ) vccint 1.118 1.32 v operating case temperature t c -20 +85 c note : the recommended operating conditions for a device are operating conditions under which it can be guaranteed that the device will operate as specified. if the device is used under operating conditions other than the recommended operating conditions (supply voltage, operating temperature range, specified ac and dc values etc.), malfunction may occur. thus, when designing products which include this device, ensure that the recommended operating conditions for the device are always adhered to.
preliminary tx9956cxbg 2004-4-25 14 tx9956cxbg 5.3 dc characteristics 5.3.1 dc chracteristics t c = -20 c to 85 c, vccint = 1.25 5%,vccio = 3.3 v 0.2v or 2.5v 0.2v parameter symb ol conditions min. max. units i oh = -8ma (8ma buffer) output high voltage v oh i oh = -16ma (16ma buffer) vccio-0.6 - v i ol = 8ma (8ma buffer) output low voltage v ol i ol = 16ma (16ma buffer) - 0.4 v input high voltage (*1) v ih 2 vccio+0.3 v input high voltage v ihc masterclock 0.8vccio vccio+0.3 v v il33 3.3v i/o -0.5 0.8 v input low voltage (*1) v il25 2.5v /io -0.5 0.6 v input low voltage v ilc masterclock -0.5 0.2vccio v input leakage i li except (*2), (*3) 10 a input leakage (pull-up) (*2) i liu -70 -10 a input leakage (pull-down) (*3) i lid 10 70 a output leagate i lo 20 a input capacitance c in 10 pf (*1) except for masterclock input (*2) with pull-up resistor : int(5:0)*, nmi*, jtms, jtck, jtdi (*3) with pull-down resistor : jtrst*, ejdint
preliminary tx9956cxbg 2004-4-25 15 tx9956cxbg 5.3.2 operating current parameter symbol conditions max. units operating current 1 cpuclk = 533mhz 3 a (internal : normal operating) i ccint1 cpuclk = 600mhz 3.5 a operating current 2 cpuclk = 533mhz 2.5 a (internal : drystone2.1 operating) i ccint2 cpuclk = 600mhz 3 a operating current 3 cpuclk = 533mhz 1.5 a (internal : sleep mode) i ccint3 cpuclk = 600mhz 2 a operating current 4 (internal : masterclock stop) i ccint4 masterclock=0mhz cpuclk = 0mhz 1 a masterck=133mhz bufsel=1 50%(8ma buffer) load = 25pf 250 ma i/o operating current 1 (using 3.3v i/o) i ccio33 masterclk=133mhz bufsel=1 50%(8ma buffer) load = 25pf 230 ma masterclk=133mhz bufsel=0 100%(16ma buffer) load = 25pf 200 ma i/o operating current 2 (using 2.5v i/o) i ccio25 masterclk=133mhz bufsel=0 100%(16ma buffer) load = 25pf 180 ma
preliminary tx9956cxbg 2004-4-25 16 tx9956cxbg 5.4 ac characteristics 5.4.1 clock timing t c = -20 c to 85 c, vccint = 1.25v 5%, vccio = 3.3 v 0.2v or 2.5v 0.2v parameter symbol conditions min. max. units masterclock high t mch transition 5 ns 2 ns masterclock low t mcl transition 5 ns 2 ns masterclock frequency (*1) f mck 80 133 mhz 533mhz 320 533 mhz internal operation frequency 600mhz 320 600 mhz masterclock period t mcp 7.5 12.5 ns masterclock rise time t mcr 2 ns masterclock fall time t mcf 2 ns (*1) operation of tx9956c is only guaranteed with the phase lock loop enabled. (*2) all output timings assume a 25 pf capacitive load. 5.4.2 system interface t c = -20 c to 85 c, vccint = 1.25v 5%, vccio = 3.3 v 0.2v parameter symbol condition min. max. units 16ma buffer select 1.0 ( *4) 4.0 ns data output (*1,2,3) t do 8ma buffer select 1.0 ( *4) 4.5 ns data setup (*3) t ds 2.3 ns data hold (*3) t dh 0.5 ns t c = -20 c to 85 c, vccint = 1.25v 5%, vccio = 2.5v 0.2v parameter symbol condition min. max. units 16ma buffer select 1.0 ( *4) 4.5 ns data output (*1,2,3) t do 8ma buffer select 1.0 ( *4) 5.0 ns data setup (*3) t ds 2.5 ns data hold (*3) t dh 0.5 ns (*1) timings are measured from 1.2v of the masterclk to 1.2v of signal. (*2) capacitive load for all output timings is 25 pf. (*3) data output, data setup and data hold apply to all logic signals driven out of or driven into the tx9956c on the system interface. clocks are specified separately. (*4) guaranteed by the design.
preliminary tx9956cxbg 2004-4-25 17 tx9956cxbg 5.5 timing diagrams 5.5.1 clock timing t mch t mcl t mcp masterclk 0.8 *vccio 0.2 *vccio t mcr t mcf
preliminary tx9956cxbg 2004-4-25 18 tx9956cxbg 5.5.2 cpuclk to mgb-ii clock divisor of 2 cycle masterclk cpuclk (internal signal) mgb-ii clock (internal signal) sysad driven sysad received 4 3 2 1 d d d d t do d d d d t dh t ds
preliminary tx9956cxbg 2004-4-25 19 tx9956cxbg 5.5.3 system interface timing valid input valid output valid input masterclock sclock (internal signal) sysad syscmd sysadc syscmdp validout*, release* validin*, extrqst*, wrrdy*, rdrdy*, int ( 5:0 ) * , nmi* t dh t ds t do t do t do t dh t ds
preliminary tx9956cxbg 2004-4-25 20 tx9956cxbg 5.5.4 cold reset timing 5.5.5 warm reset timing masterclk corediv(3:0) s y sdiv ( 2:0 ) reset* coldreset* more than 64000 masterclock cycles t ds t dh masterclk reset* coldreset* more than 16 masterclock t ds t dh t ds more than 16 masterclock cycles t dh t ds
preliminary tx9956cxbg 2004-4-25 21 tx9956cxbg 6. package dimension pbga272?2727-1.27a6 : unit : mm
preliminary tx9956cxbg 2004-4-25 22 tx9956cxbg 7. pll passive components the phase locked loop circuit requires several passive components for proper operation, which are connected to vccpll, and vsspll, as illustrated in figure 1. figure 1 pll recommended circuit reference values: r1 = 5.6 ? (*1) r2 = 0 ? (*1) l = 2.2 uh (*1) c1 = 1000 pf (*1) c2 = 0.1 uf (*1) c3 = 10uf (*1) vccint = 1.25 v 5% note *1 : change to the suitable value on each board the inductors (l) can be used as alternatives to the resistors (r) to filter the power supply. it is essential to isolate the analog power and ground for the pll circuit (vccpll/vsspll) from the regular power and ground (vccint/vss). tx9956c vccint vccpll vsspll vss c1 c2 c3 r2 c1, c2, c3, r1, r2 and l are board components which should be placed as close as possible to the processor. r1 l
preliminary tx9956cxbg 2004-4-25 23 tx9956cxbg 8. history 2002-1-29 2002-2-7 added level2 cache. 2004-3-22 added pin-out and pin descriptions 2004-4-5 modified pin-out (b4) 2004-4-25 modified pin-out and ac/dc specification

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