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functional block diagrams 1.3v v out v batt v cc watchdog input (wdi) power fail input (pfi) power fail output (pfo) reset watchdog timer batt on osc in osc sel watchdog output (wdo) reset low line ll in reset generator timebase for reset and watchdog watchdog transition detector adm696 1.3v ce out watchdog input (wdi) power fail input (pfi) power fail output (pfo) reset watchdog timer osc in osc sel watchdog output (wdo) reset low line ll in reset generator timebase for reset and watchdog watchdog transition detector ADM697 ce in rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a microprocessor supervisory circuits adm696/ADM697 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features superior upgrade for max696/max697 specified over temperature adjustable low line voltage monitor power ok/reset time delay reset assertion down to 1 v v cc watchdog timer100 ms, 1.6 s, or adjustable low switch on resistance 1.5 v normal, 20 v in backup 600 na standby current automatic battery backup switching (adm696) fast on-board gating of chip enable signals (ADM697) voltage monitor for power fail or low battery w arning applications microprocessor systems computers controllers intelligent instruments automotive systems critical m p power monitoring general description the adm696/ADM697 supervisory circuits offer complete single chip solutions for power supply monitoring and battery control functions in microprocessor systems. these functions include m p reset, backup-battery switchover, watchdog timer, cmos ram write protection, and power failure warning. the adm696/ADM697 are available in 16-pin dip and small outline packages and provide the following functions: 1. power-on reset output during power-up, power-down and brownout conditions. the reset voltage threshold is adjustable using an external voltage divider. the reset output remains operational with v cc as low as 1 v. 2. a reset pulse if the optional watchdog timer has not been toggled within specified time. 3. separate watchdog time-out and low line status outputs. 4. adjustable reset and watchdog timeout periods. 5. a 1.3 v threshold detector for power fail warning, low bat- tery detection, or to monitor a power supply other than v cc . 6. battery backup switching for cmos ram, cmos micro- processor or other low power logic (adm696). 7. write protection of cmos ram or eeprom (ADM697). the adm696/ADM697 is fabricated using an advanced e pitaxial cmos process combining low power consumption (5 mw), extremely fast chip enable gating (5 ns) and high reliability. reset assertion is guaranteed with v cc as low as 1 v. in addition, the power switching circuitry is designed for minimal voltage drop thereby permitting increased output current drive of up to 100 ma without the need for an external pass transistor.
adm696/ADM697Cspecifications p arameter min typ max units test conditions/comments v cc operating voltage range 3.0 5.5 v v batt operating voltage range 2.0 v cc C 0 3 v battery backup switching (adm696) v out output voltage v cc C 0.05 v cc C 0.025 v i out = 1 ma v cc C 0.5 v cc C 0.25 v i out 100 ma v out in battery backup mode v batt C 0.05 v batt C 0.02 v i out = 250 m a, v cc < v batt C 0.2 v supply current (excludes i out ) 1 1.95 ma i out = 100 ma supply current in battery backup mode 0.6 1 m av cc = 0 v, v batt = 2.8 v battery standby current 5.5 v > v cc > v batt + 0.2 v (+ = discharge, C = charge) C0.1 +0.02 m at a = +25 c C1 +0.02 m a battery switchover threshold 70 mv power-up v cc C v batt 50 mv power-down battery switchover hysteresis 20 mv batt on output voltage 0.4 v i sink = 1.6 ma batt on output short circuit current 7 ma batt on = v out = 2.4 v sink current 0.5 1 25 m a batt on = v out , v cc = 0 v, source current reset and watchdog timer low line threshold (ll in ) 1.25 1.3 1.35 v v cc = +5 v, +3 v reset timeout delay 35 50 70 ms osc sel = high, v cc = 5 v, t a = +25 c watchdog timeout period, internal oscillator 1.0 1.6 2.25 s long period, v cc = 5 v, t a = +25 c 70 100 140 ms short period, v cc = 5 v, t a = +25 c watchdog timeout period, external clock 4032 4097 cycles long period 960 1025 cycles short period minimum wdi input pulse width 50 ns v il = 0.4, v ih = 3.5 v, v cc = 5 v reset output voltage @ v cc = +1 v 4 200 mv i sink = 10 m a, v cc = 1 v reset, reset output voltage 0.4 v i sink = 400 m a, v cc = 2 v, v batt = 0 v 0.4 v i sink = 1.6 ma, 3 v < v cc < 5.5 v 3.5 v i source = 1 m a, v cc = 5 v low line , wdo output voltage 0.4 v i sink = 1.6 ma, 3.5 v i source = 1 m a, v cc = 5 v output short circuit source current 1 3 25 m a wdi input threshold v cc = 5 v 1 logic low 0.8 v logic high 3.5 v wdi input current 20 50 m a wd1 = v out , (v cc ) t a = +25 c C50 C15 m a wd1 = 0 v, t a = +25 c power fail detector pfi input threshold 1.2 1.3 1.4 v v cc = +3 v, +5 v pfiCll in threshold difference C50 15 +50 mv v cc = +3 v, +5 v pfi input current C25 0.01 +25 na ll in input current C50 0.01 +50 na pfo output voltage 0.4 v i sink = 1.6 ma 3.5 v i source = 1 m a, v cc = 5 v pfo short circuit source current 1 3 25 m a pfi = low, pfo = 0 v chip enable gating (ADM697) ce in threshold 0.8 v v il 3.0 v v ih , v cc = 5 v ce in pullup current 3 m a ce out output voltage 0.4 v i sink = 1.6 ma v cc C 0.5 v i source = 800 m a ce propagation delay 5 25 ns oscillator osc in input current 2 m a osc sel input pullup current 5 m a osc in frequency range 0 250 khz osc sel = 0 v osc in frequency with ext. capacitor 4 khz osc sel = 0 v, c osc = 47 pf note 1 wdi is a three-level input which is internally biased to 38% of v cc and has an input impedance of approximately 125 k w . specifications subject to change without notice. rev. 0 C2C (v cc = full operating range, v batt = +2.8 v, t a = t min to t max unless otherwise noted.)
adm696/ADM697 rev. 0 C3C ordering guide model temperature range package option adm696an C40 c to +85 c n-16 adm696ar C40 c to +85 c r-16 adm696aq C40 c to +85 c q-16 adm696sq C55 c to +125 c q-16 ADM697an C40 c to +85 c n-16 ADM697ar C40 c to +85 c r-16 ADM697aq C40 c to +85 c q-16 ADM697sq C55 c to +125 c q-16 absolute maximum ratings* (t a = +25 c unless otherwise noted) v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +6 v v batt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +6 v all other inputs . . . . . . . . . . . . . . . . . . C0.3 v to v out + 0.5 v input current v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 ma v batt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ma digital output current . . . . . . . . . . . . . . . . . . . . . . . . . 20 ma power dissipation, n-16 dip . . . . . . . . . . . . . . . . . . . 600 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 135 c/w power dissipation, q-16 dip . . . . . . . . . . . . . . . . . . . 600 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 100 c/w power dissipation, r-16 soic . . . . . . . . . . . . . . . . . . 600 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 110 c/w operating temperature range industrial (a version) . . . . . . . . . . . . . . . . .C40 c to +85 c extended (s version) . . . . . . . . . . . . . . . . . C55 c to +125 c lead temperature (soldering, 10 sec) . . . . . . . . . . . . . +300 c vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220 c storage temperature range . . . . . . . . . . . . . C65 c to +150 c *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum ratings for extended periods of time may affect device reliability. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adm696/ADM697 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. pin configurations 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 top view (not to scale) adm696 gnd v batt v out pfi pfo wdo v cc reset batt on low line osc in osc sel reset ll in nc wdi 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 top view (not to scale) ADM697 ll in test nc pfi pfo wdo v cc reset gnd low line osc in osc sel reset ce in ce out wdi
adm696/ADM697 rev. 0 C4C pin function description pin no. mnemonic adm696 ADM697 function v cc 3 3 power supply input +3 v to +5 v. v batt 1 backup battery input. connect to ground if a backup battery is not used. v out 2 output voltage, v cc or v batt is internally switched to v out depending on which is at the highest potential. v out can supply up to 100 ma to power cmos ram. connect v out to v cc if v out and v batt are not used. gnd 4 5 0 v. ground reference for all signals. reset 15 15 logic output. reset goes low whenever ll in falls below 1.3 v or when v cc falls below the v batt input voltage. reset remains low for 50 ms after ll in goes above 1.3 v, reset also goes low for 50 ms if the watchdog timer is enabled but not serviced within its timeout period. the reset pulse width can be adjusted as shown in table i. wdi 11 11 watchdog input, wdi is a three level input. if wdi remains either high or low for longer than the watchdog timeout period, reset pulses low and wdo goes low. the timer resets with each transition at the wdi input. the watchdog timer is disabled when wdi is left floating or is driven to midsupply. pfi 9 9 power fail input. pfi is the noninverting input to the power fail comparator when pfi is less than 1.3 v, pfo goes low. connect pfi to gnd or v out when not used. see figure 1. pfo 10 10 power fail output. pfo is the output of the power fail comparator. it goes low when pfi is less than 1.3 v. the comparator is turned off and pfo goes low when v cc is below v batt . ce in 13 logic input. the input to the ce gating circuit. connect to gnd or v out if not used. ce out 12 logic output. ce out is a gated version of the ce in signal. ce out tracks ce in when ll in is above 1.3 v. if ll in is below 1.3 v, ce out is forced high. batt on 5 logic output. batt on goes high when v out is internally switched to the v batt input. it goes low when v out is internally switched to v cc . the output typically sinks 7 ma and can directly drive the base of an external pnp transistor to increase the output current above the 100 ma rating of v out . low line 6 6 logic output. low line goes low when ll in falls below 1.3 v. it returns high as soon as ll in rises above 1.3 v. reset 16 16 logic output. reset is an active high output. it is the inverse of reset . osc sel 8 8 logic oscillator select input. when osc sel is unconnected or driven high, the internal oscillator sets the reset time delay and watchdog time-out period. when osc sel is low, the external oscillator input, osc in, is enabled. osc sel has a 3 m a internal pullup. see table i and figure 4. osc in 7 7 logic oscillator input. when osc sel is low, osc in can be driven by an external clock to adjust both the reset delay and the watchdog time-out period. the timing can also be adjusted by connecting an external capacitor to this pin. see table i and figure 4. when osc sel is high or floating, osc in selects between fast and slow watchdog time-out periods. wdo 14 14 logic output. the watchdog output, wdo , goes low if wdi remains either high or low for longer than the watchdog time-out period. wdo is set high by the next transition at wdi. if wdi is unconnected or at midsupply, wdo remains high. wdo also goes high when low line goes low. nc 12 2 no connect. it should be left open. ll in 13 4 voltage sensing input. the voltage on the low line input, ll in , is compared with a 1.3 v reference voltage. this input is normally used to monitor the power supply voltage. the output of the comparator generates a low line output signal. it also generates a reset/ reset output. test 1 this is a special test pin using during device manufacture. it should be connected to gnd.
adm696/ADM697 rev. 0 C5C low line rese t output reset is an active low output which provides a reset signal to the microprocessor whenever the low line input (ll in ) is below 1.3 v. the ll in input is normally used to monitor the power supply voltage. an internal timer holds reset low for 50 ms after the voltage on ll in rises above 1.3 v. this is in- tended as a power-on reset signal for the processor. it allows time for the power supply and microprocessor to stabilize. on power-down, the reset output remains low with v cc as low as 1 v. this ensures that the microprocessor is held in a stable shutdown condition. the ll in comparator has approximately 12 mv of hysteresis for enhanced noise immunity. in addition to reset , an active high reset output is also available. this is the complement of reset and is useful for processors requiring an active high reset. t 1 t 1 = reset time v1 = reset voltage threshold low v2 = reset voltage threshold high hysteresis = v2?1 v2 v2 v1 v1 t 1 ll in low line reset figure 2. power-fail reset timing watchdog timer reset the watchdog timer circuit monitors the activity of the micro- processor in order to check that it is not stalled in an indefinite loop. an output line on the processor is used to toggle the watchdog input (wdi) line. if this line is not toggled within the selected timeout period, a reset pulse is generated. the adm696/ADM697 may be configured for either a fixed short 100 ms or a long 1.6 second timeout period or for an adjustable timeout period. if the short period is selected some systems may be unable to service the watchdog timer immedi- ately after a reset, so a long timeout is automatically initiated directly after a reset is issued. the watchdog timer is restarted at the end of reset, whether the reset was caused by lack of ac- tivity on wdi or by ll in falling below the reset threshold. the normal (short) timeout period becomes effective following the first transition of wdi after reset has gone inactive. the watchdog timeout period restarts with each transition on the wdi pin. to ensure that the watchdog timer does not time out, either a high-to-low or low-to high transition on the wdi pin must occur at or less than the minimum timeout period. if wdi remains permanently either high or low, reset pulses will be is- sued after each timeout period (1.6 s). the watchdog monitor can be deactivated by floating the watchdog input (wdi) or by connecting it to midsupply. circuit information battery-switchover section (adm696) the battery switchover circuit compares v cc to the v batt input, and connects v out to whichever is higher. switchover occurs when v cc is 50 mv higher than v batt as v cc falls, and when v cc is 70 mv greater than v batt as v cc rises. this 20 mv of hysteresis prevents repeated rapid switching if v cc falls very slowly or remains nearly equal to the battery voltage. during normal operation with v cc higher than v batt , v cc is internally switched to v out via an internal pmos transistor switch. this switch has a typical on resistance of 1.5 w and can supply up to 100 ma at the v out terminal. v out is normally used to drive a ram memory bank which may require instanta- neous currents of greater than 100 ma. if this is the case, then a bypass capacitor should be connected to v out . the capacitor will provide the peak current transients to the ram. a capaci- tance value of 0.1 m f or greater may be used. if the continuous output current requirement at v out exceeds 100 ma or if a lower v cc Cv out voltage differential is desired, an external pnp pass transistor may be connected in parallel with the internal transistor. the batt on output can directly drive the base of the external transistor. a 20 w mosfet switch connects the v batt input to v out during battery backup. this mosfet has very low input-to- output differential (dropout voltage) at the low current levels required for battery backup of cmos ram or other low power cmos circuitry. the supply current in battery backup is typi- cally 0.6 m a. the adm696 operates with battery voltages from 2.0 v to v cc C0.3 v). high value capacitors, either standard electrolytic or the farad-size double layer capacitors, can also be used for short- term memory backup. a small charging current of typically 10 na (0.1 m a max) flows out of the v batt terminal. this cur- rent is useful for maintaining rechargeable batteries in a fully charged condition. this extends the life of the backup battery by compensating for its self discharge current. also note that this current poses no problem when lithium batteries are used for backup since the maximum charging current (0.1 m a) is safe for even the smallest lithium cells. if the battery-switchover section is not used, v batt should be connected to gnd and v out should be connected to v cc . v batt v cc batt on (adm691, adm693, adm695, adm696) v out 700 mv gate drive 100 mv internal shut down signal when v batt > (v cc + 0.7v) figure 1. battery switchover schematic
adm696/ADM697 rev. 0 C6C table i. adm696, ADM697 reset pulse width and watchdog timeout selections watchdog timeout period reset active period osc sel osc in normal immediately after reset low external clock input 1024 clks 4096 clks 512 clks low external capacitor 400 ms c/47 pf 1.6 s c/47 pf 200 ms c/47 pf floating or high low 100 ms 1.6 s 50 ms floating or high floating or high 1.6 s 1.6 s 50 ms note with the osc sel pin low, osc in can be driven by an external clock signal, or an external capacitor can be connected between osc in and gnd. the nominal internal oscillator frequency is 10.24 khz. the nominal oscillator frequency with external capacitor is: f osc (hz) = 184,000/c (pf). t 2 reset wdo wdi t 1 = reset time t 2 = normal (short) watchdog timeout period t 3 = watchdog timeout period immediately following a reset t 1 t 1 t 1 t 3 figure 3. watchdog timeout period and reset active time the watchdog timeout period defaults to 1.6 s and the reset pulse width defaults to 50 ms but these times to be adjusted as shown in table i. figure 4 shows the various oscillator configu- rations which can be used to adjust the reset pulse width and watchdog timeout period. the internal oscillator is enabled when osc sel is high or floating. in this mode, osc in selects between the 1.6 second and 100 ms watchdog timeout periods. in either case, immedi- ately after a reset the timeout period is 1.6 s. this gives the mi- croprocessor time to reinitialize the system. if osc in is low, then the 100 ms watchdog period becomes effective after the first transition of wdi. the software should be written such that the i/o port driving wdi is left in its power-up reset state until the initialization routines are completed and the micropro- cessor is able to toggle wdi at the minimum watchdog timeout period of 70 ms. osc in osc sel adm69x clock 0 to 250khz 8 7 figure 4a. external clock source osc in osc sel adm69x 8 7 c osc figure 4b. external capacitor osc in osc sel adm69x 8 7 nc nc figure 4c. internal oscillator (1.6 s watchdog) osc in osc sel adm69x 8 7 nc figure 4d. internal oscillator (100 ms watchdog) watchdog output ( wdo ) the watchdog output wdo provides a status output which goes low if the watchdog timer times out and remains low until set high by the next transition on the watchdog input. wdo is also set high when ll in goes below the reset threshold.
adm696/ADM697 rev. 0 C7C fail output ( pfo ) goes low when the voltage at pfi is less than 1.3 v. typically pfi is driven by an external voltage divider which senses either the unregulated dc input to the systems 5 v regulator or the regulated 5 v output. the voltage divider ratio can be chosen such that the voltage at pfi falls below 1.3 v several milliseconds before the +5 v power supply falls below the reset threshold. pfo is normally used to interrupt the microprocessor so that data can be stored in ram and the shut- down procedure executed before power is lost. adm69x power fail input r2 input power 1.3v pfo power fail output r1 figure 7. power fail comparator table ii. input and output status in battery backup mode signal status v out (adm696) v out is connected to v batt via an internal pmos switch. reset logic low. reset logic high. the open circuit output voltage is equal to v out . low line logic low. batt on (adm696) logic high. the open circuit voltage is equal to v out . wdi wdi is ignored. it is internally disconnected from the internal pullup resistor and does not source or sink current as long as its input voltage is between gnd and v out . the input voltage does not affect supply current. wdo logic high. the open circuit voltage is equal to v out . pfi the power fail comparator is turned off and has no effect on the power fail output. pfo logic low. ce in ce in is ignored. it is internally disconnected from its internal pullup and does not source or sink current as long as its input voltage is be- tween gnd and v out . the input voltage does not affect supply current. ce out logic high. the open circuit voltage is equal to v out . osc in osc in is ignored. osc sel osc sel is ignored. ce gating and ram write protection (ADM697) the ADM697 contains memory protection circuitry which ensures the integrity of data in memory by preventing write operations when ll in is below the threshold voltage. when ll in is greater than 1.3 v, ce out is a buffered replica of ce in , with a 5 ns propagation delay. when ll in falls below the 1.3 v threshold, an internal gate forces ce out high, independent of ce in . ce out typically drives the ce, cs, or write input of battery backed up cmos ram. this ensures the integrity of the data in memory by preventing write operations when v cc is at an in- valid level. if the 5 ns typical propagation delay of ce out is excessive, con- nect ce in to gnd and use the resulting ce out to control a high speed external logic gate. ADM697 ce out ce in ll in low = 0 ll in ok = 1 figure 5. chip enable gating t 1 t 1 = reset time v1 = reset voltage threshold low v2 = reset voltage threshold high hysteresis = v2?1 v2 v2 v1 v1 t 1 ll in low line reset ce in ce out figure 6. chip enable timing power fail warning comparator an additional comparator is provided for early warning of fail- ure in the microprocessors power supply. the power fail input (pfi) is compared to an internal +1.3 v reference. the power
adm696/ADM697Ctypical performance curves rev. 0 C8C 5.00 4.80 0 100 4.95 4.85 20 4.90 80 60 40 v cc = +5v t a = +25? slope = 1.5 v out ?v i out ?ma figure 8. v out vs. i out normal operation 2.80 2.76 0 1000 2.79 2.77 200 2.78 800 600 400 i out ?? v out ?v slope = 20 v cc = 0v v batt = +2.8v t a = +25 c figure 9. v out vs. battery backup 1.303 1.299 20 120 1.302 1.300 40 1.301 100 80 60 pfi input threshold ?v temperature ? c figure 10. pfi input threshold vs. temperature 53 49 20 120 52 50 40 51 100 80 60 v cc = +5v temperature ? c reset active time ?ms figure 11. reset active time vs. temperature 10 90 100 0% 1v a4 500ms 3.36 v 1v aaa a a a aa aaaa a a aaa aaaa a aaaa aaa figure 12. reset output voltage vs. supply voltage 5.5 3.0 2.0 10 100 10000 1000 4.5 2.5 3.5 4.0 5.0 time delay ?ms v cc ?volts t a = +25 c figure 13. reset timeout delay vs. v cc
adm696/ADM697 rev. 0 C9C applications information increasing the drive current (adm696) if the continuous output current requirements at v out exceeds 100 ma or if a lower v cc Cv out voltage differential is desired, an external pnp pass transistor may be connected in parallel with the internal transistor. the batt on output (adm696) can directly drive the base of the external transistor. v out v cc battery +5v input power 0.1? batt on v batt pnp transistor adm696 0.1? figure 14. increasing the drive current using a rechargeable battery for backup (adm696) if a capacitor or a rechargeable battery is used for backup, then the charging resistor should be connected to v out since this eliminates the discharge path that would exist during power- down if the resistor is connected to v cc . v out v cc rechargable battery +5v input power 0.1? 0.1? v batt adm696 r i = v out ?v batt r figure 15. rechargeable battery adding hysteresis to the power fail comparator for increased noise immunity, hysteresis may be added to the power fail comparator. since the comparator circuit is nonin- verting, hysteresis can be added simply by connecting a resistor between the pfo output and the pfi input as shown in fig- ure 16. when pfo is low, resistor r3 sinks current from the summing junction at the pfi pin. when pfo is high, the series combination of r3 and r4 source current into the pfi summing junction. this results in differing trip levels for the comparator. alternate watchdog input drive circuits the watchdog feature can be enabled and disabled under pro- gram control by driving wdi with a 3-state buffer (figure 17a). when three-stated, the wdi input will float thereby disabling the watchdog timer. this circuit is not entirely foolproof, and it is possible that a software fault could erroneously 3-state the buffer. this would then prevent the adm69x from detecting that the microproces- sor is no longer operating correctly. in most cases a be tter adm69x r2 1.3v pfo r1 7805 r4 r3 +7v to +15v input power +5v pfi v cc to ? nmi v h = 1.3v ( 1+ ?+ ? ) v l = 1.3v ( 1+ ??? ) assuming r 4 < < r 3 then hysteresis v h ?v l = 5v ( ? ) r 1 r 2 r 1 r 3 r 1 r 2 r 1 r 2 r 1 (5v ?1.3v) 1.3v (r 3 + r 4 ) figure 16. adding hysteresis to the power fail comparator method is to extend the watchdog period rather than disabling the watchdog. this may be done under program control using the circuit shown in figure 17b. when the control input is high, the osc sel pin is low and the watchdog timeout is set by the external capacitor. a 0.01 m f capacitor sets a watchdog timeout delay of 100 s. when the control input is low, the osc sel pin is driven high, selecting the internal oscillator. the 100 ms or the 1.6 s period is chosen, depending on which diode in fig- ure 17b is used. with d1 inserted, the internal timeout is set at 100 ms while with d2 inserted the timeout is set at 1.6 s. wdi adm69x watchdog strobe control input figure 17a. programming the watchdog input osc in osc sel adm69x control input* d1 d2 *low = internal timeout high = external timeout figure 17b. programming the watchdog input
adm696/ADM697 rev. 0 C10C replacing the back-up battery when changing the back-up battery with system power on, spu- rious resets can occur when the battery is removed. this occurs because the leakage current flowing out of the v batt pin will charge up the stray capacitance. if the voltage on v batt reaches within 50 mv of v cc , a reset pulse is generated. if spurious resets during battery replacement are acceptable, then no action is required. if not, then one of the following solu- tions should be considered: 1. a capacitor from v batt to gnd. this gives time while the capacitor is charging up to change the battery. the leakage current will charge up the external capacitor towards the v cc level. the time taken is related to the charging current, the size of external capacitor and the voltage differential be- tween the capacitor and the charging voltage supply. t = c ext v diff /i the maximum leakage (charging) current is 1 m a over tem- perature and v diff = v cc v batt . therefore, the capacitor size should be chosen such that sufficient time is available to make the battery replacement. c ext = t reqd (1 m a/ ( v cc C v batt )) if a replacement time of 5 s is allowed and assuming a v cc of 4.5 v and a v batt of 3 v, c ext = 3.33 m f 2. a resistor from v batt to gnd. this will prevent the voltage on v batt from rising to within 50 mv of v cc during battery replacement. r = ( v cc C 50 mv )/1 m a note that the resistor will discharge the battery slightly. with a v cc supply of 4.5 v, a suitable resistor is 4.3 m w . with a 3 v battery, this will draw around 700 na. this will be negligible in most cases. typical applications adm696 figure 18 shows the adm696 in a typical power monitoring, battery backup application. v out powers the cmos ram. under normal operating conditions with v cc present, v out is internally connected to v cc . if a power failure occurs, v cc will decay and v out will be switched to v batt , thereby maintaining power for the cmos ram. power fail reset the v cc power supply is also monitored by the low line in- put, ll in . a reset pulse is generated when ll in falls below 1.3 v. reset will remain low for 50 ms after ll in returns above 1.3 v. this allows for a power-on reset and prevents re- peated toggling of reset if the v cc power supply is unstable. resistors r3 and r4 should be chosen to give the desired v cc reset threshold. watchdog timer the watchdog timer input (wdi) monitors an i/o line from the m p system. this line must be toggled once every 1.6 s to verify correct software execution. failure to toggle the line indi- cates that the m p system is not correctly executing its program and may be tied up in an endless loop. if this happens, a reset pulse is generated to initialize the processor. if the watchdog timer is not needed the wdi input should be left floating. power fail detector the power fail input, pfi, monitors the input power supply via a resistive divider network r1 and r2. this input is intended as an early warning power fail input. the voltage on the pfi input is compared with a precision 1.3 v internal reference. if the in- put voltage drops below 1.3 v, a power fail output (pfo) signal is generated. this warns of an impending power failure and may be used to interrupt the processor so that the system may be shut down in an orderly fashion. the resistors in the sensing network are ratioed to give the desired power fail threshold volt- age v t . the threshold should be set at a higher voltage than the reset threshold so that there is sufficient time available to complete the shutdown procedure before the processor is reset and power is lost. adm696 r2 r1 pfo +5v v cc cmos ram power i/o line ? nmi ? reset ? system ? power v out reset wdi gnd pfi v batt battery + r4 r3 ll in reset figure 18a. adm696 typical application circuit a figure 18b shows a similar application for the adm696 but in this case the pfi input monitors the unregulated input to the 7805 voltage regulator. this gives an earlier warning of an im- pending power failure. it is useful with processors operating at low speeds or where there are a significant number of house- keeping tasks to be completed before the power is lost. adm696 r2 r1 pfo input power v cc v out wdi gnd pfi v batt 0.1? 3v battery reset osc in osc sel low line wdo system status indicators cmos ram i/o line nmi reset a0?15 ? batt on nc v cc ll in ? power reset r4 r3 7805 0.1? figure 18b. adm696 typical application circuit b
adm696/ADM697 rev. 0 C11C this application also shows an optional, external transistor which may be used to provide in excess of 100 ma current on v out . when v cc is higher than v batt , the batt on output goes low, providing 25 ma of base drive for the external pnp transistor. the maximum current available is dependent on the power rating of the external transistor. ram write protection the ADM697 ce out line drives the chip select inputs of the cmos ram. ce out follows ce in as long as ll in is above the reset threshold. if ll in falls below the reset threshold, ce out goes high, independent of the logic level at ce in . this prevents the microprocessor from writing erroneous data into ram dur- ing power-up, power-down, brownouts and momentary power interruptions. outline dimensions dimensions shown in inches and (mm). 16-pin plastic dip (n-16) 0.840 (21.33) 0.745 (18.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) pin 1 0.280 (7.11) 0.240 (6.10) 9 1 6 1 8 0.210 (5.33) 0.200 (5.05) 0.125 (3.18) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) bsc seating plane 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) 0.070 (1.77) 0.045 (1.15) 16-pin cerdip (q-16) pin 1 0.840 (21.34) max 0.060 (1.52) 0.015 (0.38) 0.015 (0.381) 0.008 (0.204) 0.150 (3.81) min 0.200 (5.08) max 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) bsc 0.070 (1.78) 0.30 (0.76) plane seating 0.310 (7.87) 0.220 (5.59) 0.320 (8.13) 0.290 (7.37) 1 8 9 16 16-lead soic (r-16) 0.019 (0.49) 0.05 (1.27) ref 0.104 (2.65) 0.012 (0.3) 0.413 (10.50) 0.419 (10.65) 0.042 (1.07) 0.013 (0.32) 0.030 (0.75) 0.299 (7.60) 1 8 9 16
c1783C18C4/93 printed in u.s.a. C12C

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