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december 2009 doc id 16867 rev 1 1/46 46 PM6652 single phase controller for intel ? mvp 6.5 render voltage regulator, cpu and vr11 cpu features 4.5 v to 28 v input voltage range 0.3 v to 1.5 v output voltage range imvp6.5 gpu/cpu and vr11 cpu mode selection very fast load transient response using constant-on-time loop control remote voltage sensing programmable droop function 7 bit dynamic voltage positioning (vid) programmable pwm frequency lossless current sense with inductor dcr accurate inductor current sense with rsense negative current limit boot diode embedded latched ovp, uvp and overtemperature pulse skipping when suspend state is selected output voltage ripple compensation soft start and soft end power good available current monitor (imon) thermal throttling applications intel mobile graphic core imvp6.5 intel mobile cpu imvp6.5 intel atom? vr11 based devices notebook, netbook and nettop computers handheld and pdas description the PM6652 is a single phase, step-down smps controller with high precision 7 bit dac. it has been designed to supply the cpu and the graphics core (render engine) of the intel? mobile platform, according with intel mvp6.5 specifications. the PM6652 can also be configured to supply the 7-bit family, vr11 compliant, atom? processors. the controller, based on constant on-time (cot) architecture, allows real -time dynamic switching of the core operating voltages and frequencies, working in both performance and suspend render states. an embedded integrator control loop compensates the dc voltage error due to the output ripple. the high efficiency at light load, achieved with pulse skipping working mode, and the extremely low shutdown and quiescent adsorbed current, make the PM6652 the ideal choice in battery powered devices. vfqfpn-32 5x5 mm table 1. device summary order codes package packaging PM6652 vfqfpn-32 5 x 5 mm (exposed pad) tr ay PM6652tr tape and reel www.st.com
contents PM6652 2/46 doc id 16867 rev 1 contents 1 typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 voltage identification (vid) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 typical operating char acteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.1 constant on time pwm control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.1.1 constant on time pwm architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.1.2 output ripple compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.2 mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.3 pulse-skip working mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.4 differential remote sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.5 droop function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.6 voltage dynamic (vid) transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.7 current sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.8 soft-start and soft-end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.9 internal mos drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.10 monitoring and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.10.1 power good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
PM6652 contents doc id 16867 rev 1 3/46 8.10.2 current monitor (imon) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.10.3 thermal throttling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.10.4 overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.10.5 undervoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.10.6 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.10.7 svcc undervoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.10.8 thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.11 system accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.11.1 vcore accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.11.2 current reporting (imon) accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9 layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
list of tables PM6652 4/46 doc id 16867 rev 1 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 5. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 6. vid for intel mvp 6.5 gfx core and cpu operation mode. . . . . . . . . . . . . . . . . . . . . . . 14 table 7. voltage identification (vid) for intel vr11 operation mode . . . . . . . . . . . . . . . . . . . . . . . 16 table 8. PM6652 mode of operation selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 9. vfqfpn 5x5x1.0 mm 32l pitch 0.50 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 10. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
PM6652 list of figures doc id 16867 rev 1 5/46 list of figures figure 1. typical application circuit - imvp6.5 render core supply . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. PM6652 pin out (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. vcore turn on and pgood rising - no load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 5. vcore turn on- cpu imvp6.5 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 6. vcoreworking mode - dprslpvr asserted, no load . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 7. vcoreworking mode (0.9v) - dprslpvr asserted, no load. . . . . . . . . . . . . . . . . . . . . . 18 figure 8. vcore working mode (0.4v) - dprslpvr asserted, no load . . . . . . . . . . . . . . . . . . . . . 19 figure 9. vcore working mode - dprsl pvr not asserted, no load. . . . . . . . . . . . . . . . . . . . . . . . 19 figure 10. vcore working mode - dprslpvr not asserted, 10a load . . . . . . . . . . . . . . . . . . . . . . 19 figure 11. vcore working mode (0.9v) - dprslpvr not asserted, no load . . . . . . . . . . . . . . . . . . 19 figure 12. vcore working mode (0.4v) - dprslpvr not asserted, no load . . . . . . . . . . . . . . . . . . 19 figure 13. vid5 transition - entering and exiting suspend state (fast exit) . . . . . . . . . . . . . . . . . . . . . 19 figure 14. vid5 transition - entering and exiting suspend state (slow exit) . . . . . . . . . . . . . . . . . . . . . 20 figure 15. droop function - 5a to 15a transient response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 16. vcore vid step variation - vr11 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 17. vcore soft end - coreon pin deassertion and pgood transition . . . . . . . . . . . . . . . . 20 figure 18. vcore overvoltage (+200mv). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 19. vcore undervoltage (-300mv) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 20. vcore efficiency (dprslpvr high and low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 21. vcore load regulation - droop function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 22. simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 23. PM6652 integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 24. PM6652 droop function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 25. gfx supply - vid step, skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 26. cpu imvp6.5 - vid step, skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 figure 27. precision resistor current sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 28. inductor's dcr current sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 29. l > c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 30. l < c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 31. thermal compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 32. imvp6.5 gfx mode start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 33. impv6.5 cpu mode start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 34. vdac soft-start voltage slew-rate vs capacitor value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 35. average current limit - recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 36. average current limit detected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 37. current monitor with external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 38. voltage regulator thermal throttling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 39. valley current limit circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 40. valley current limit detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 41. vfqfpn 5x5x1.0 mm 32l pitch 0.50 mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . 44
typical application circuit PM6652 6/46 doc id 16867 rev 1 1 typical application circuit figure 1. typical application circuit - imvp6.5 render core supply # 633?3.3 '&8 #/2 % 2 2 2 #/2%/. 2 2 6). 0'//$ 633?3.3 $023,062 # # 6)$ # # # 6)$ # 2 6## ?3.3 , 6 6)$ 6 6)$ 2 2 2 .4# 1 6)$ # # 2 6 2 6)$ 6)$ )-/. # 2 1 2 2 6). # # # 5 0- 6244 4( %2 - '3.3 63.3 #3.3 6/54 #/-0 36## 3'.$ 6$!# )- /. )- /.& " 334!24 ),)- /3# 072 '$ $023,062 0'.$ ,'!4% 06## #,+%. "//4 ('!4% 0(!3% #/2%/. 6)$ 6)$ 6)$ 6)$ 6)$ 6)$ 6)$ thermal !-v
PM6652 pin settings doc id 16867 rev 1 7/46 2 pin settings 2.1 connections figure 2. PM6652 pin out (top view) 2.2 pin description !-v &/.(1 39&& /*$7( *616 69&& &203 &616 26& 9,' 9,' 9,' 9,' '356/395 9,' ,021 9616 3+$6( %227 ,/,0 +*$7( &25(21 ,021)% 9,' 3:5*' 9287 3*1' 9,' 6*1' 9'$& 66 7$57 9577 7+(50 (;3 26('3$' figure 3. pin functions pin n name description 1 vrtt# thermal throttling indicator, open-drain output. 2 therm thermal throttling input. connect to th e central tap of ntc-based divider for mos or inductor thermal monitoring. 3 gsns output voltage ground remote sensing. 4 vsns output voltage remote sensing. 5csns current sensing input for droop function and imon reporting. it represents the positive input of the differential current comparator. connect to the inductor, for dcr sensing, or to a dedicated resist or fro precision current sensing. 6vout output voltage feedback. it also represent s the negative input of the differential current comparator. 7 comp dc output voltage error compensation pin. 8 svcc +5v analog and digital supply. 9 sgnd analog and digital ground.
pin settings PM6652 8/46 doc id 16867 rev 1 10 vdac internal dac reference output . bypass to gnd with a 10nf capacitor. 11 imon current monitor output. bypass to remote ground through r- c network. 12 imonfb current monitor gain setting pin. connect to vout through a resistor in the range 0.47 k ? to 7 k ? . 13 sstart soft-start programming pin and m ode of operation selection input. 14 ilim current limit input. connect ilim to gnd with a resistor to set the current limit threshold. 15 osc frequency selection pin. connect this pin to the input power supply rail through a resistor. 16 pwrgd power good signal (open drain output). hig h when vcc_gfx output voltage is within +200mv/-300mv of the programmed vdac value. 17 dprslpvr render suspend state enter and render suspend exit mode control input. pulse skipping or forced pwm working mode selection for imvp6.5 cpu and vr11 mode. 18 pgnd power ground. 19 lgate low side gate driver output. 20 pvcc +5v supply for internal driver supply. 21 clken# clock enable open-drain output (active low) and mode of operation selection pin. 22 boot bootstrap capacitor connection. input fo r the supply voltage of the high side gate driver. 23 hgate high side gate driver output. 24 phase switch node connection and return path for the high side gate driver. 25 coreon switching regulator on/off control input. 26 vid0 vids bits of the controller voltage programming dac input. they allow programming the no-load output voltage, depending on the selected mode of operation. vid0 is the lsb and vid6 the msb. connect vidx to a voltage <0.33v to program a ?0?; connect vidx to a voltage >0.77v to program a ?1?. 27 vid1 28 vid2 29 vid3 30 vid4 31 vid5 32 vid6 33 ep exposed pad. connect to sgnd. figure 3. pin functions (continued) pin n name description
PM6652 electrical data doc id 16867 rev 1 9/46 3 electrical data 3.1 maximum rating 3.2 thermal data table 2. absolute maximum ratings (1) 1. free air operating conditions unless otherwise specified. stress es beyond those listed under ?absolute maximum ratings? may cause permanent damage to t he device. exposure to absolute maximum rated conditions for extended periods may affect device reliability. symbol parameter value unit v pvcc pvcc to pgnd -0.3 to 6 v v svcc svcc to sgnd -0.3 to 6 v sgnd to pgnd -0.3 to 0.3 v v boot boot to phase -0.3 to 6 v v hgate hgate to phase -0.3 to v boot +0.3 v v phase phase to pgnd -0.3 to 36 v v lgate lgate to pgnd -0.3 to v pvcc +0.3 v vrtt#, therm, gsns, vsns, csns, vout, comp, vdac, imon, imonfb, ilim, osc, pwrgd, dprslpvr, sstart, clken#, coreon, vidx, to sgnd -0.3 to v svcc + 0.3 v maximum withstanding voltage range test condition: cdf-aec-q100 -002- ?human body model? acceptance criteria: ?normal performance? all the pins 1250 v table 3. thermal data symbol parameter value unit r thja thermal resistance between junction and ambient 35 c/w t j junction operating temperature range -40 to 125 c t a operating ambient temperature range -40 to 85 t stg storage temperature range -50 to 150
electrical data PM6652 10/46 doc id 16867 rev 1 3.3 recommended operating conditions table 4. recommended operating conditions symbol parameter value unit min typ max v in input voltage range 4.5 - 28 v v pvcc pvcc voltage range 4.5 - 5.5 v
PM6652 electrical characteristics doc id 16867 rev 1 11/46 4 electrical characteristics t j = 25 c, v in = +12 v, pvcc = +5 v if not otherwise specified. table 5. electrical characteristics symbol parameter test condition min. typ. max. unit supply section i svcc,quiescent ic supply current coreon=5v, dprslpvr=5v, fb forced above the regulation point 850 a i svcc,shdn operating current in shutdown coreon=sgnd, t a =25 c 1 a v svcc uvlo svcc undevoltage lockout upper threshold rising edge, controller disabled below this level 4.3 4.5 v svcc undervoltage lockout lower threshold falling edge, controller enabled above this level 3.8 3.9 uvlo hysteresis 400 mv on-time t on on-time duration vcore=1.5v osc=250mv 820 920 1020 ns osc=500mv 410 470 530 osc=1v 210 248 280 off-time t offmin minimum off time 250 400 ns integrator v comp overvoltage clamp v ovclamp =v comp -v csns 80 mv undervoltage clamp v uvclamp =v comp -v csns -140 mv integrator offset -2.5 2.5 mv voltages and dac v dac internal dac reference voltage accuracy dac codes from 0.8125v to 1.5000v -0.7% 0.7% mv dac codes from 0.3000v to 0.8000v -10 10 v dac slew-rate vdac output voltage slew rate after vids variation. gfx mode selected, and dprslpvr asserted, positive vdac dv/dt only, or vr11 mode selected. 10 12.5 mv/s gfx mode selected, and dprslpvr deassert, or cpu mode selected. 56.25 mv/s i leakvcc_gfxc vcore voltage sense leakage current 1a vboot boot-up voltage cpu or vr11 mode selected 1.100 v current sensing
electrical characteristics PM6652 12/46 doc id 16867 rev 1 i csns input leakage current 1 a current limit comparator offset v offs =v pgnd -v phase -4 4 mv i lim ilim bias current 4.5 5 5.5 a zero crossing comparator offset -3.5 3.5 mv high side and low side gate drivers hgate driver on- resistance hgate high state (pull-up) 2.0 3 hgate low state (pull-down) 1.6 2.7 lgate driver on- resistance lgate high state (pull-up) 1 1.7 lgate low state (pull-down) 0.6 1 uvp/ovp protections, pw rgd and clken# signals ovp fixed fixed overvoltage threshold 1.55 v ovp latched overvoltage threshold referred to v dac value 200 mv uvp latched undervoltage threshold referred to v dac value -300 mv pwrgd upper threshold referred to v dac value 200 mv lower threshold -300 i pwrgd pwrgd leakage current pwrgd forced to 3.3v 1 a v pwrgd output low voltage isink=4ma 250 350 mv clken# output low voltage isink=4ma 250 350 mv clken# leakage current clken# forced to 3.3v; sstart=5v 1 a current monitor section imon current monitor output v csns ? v out = 60mv; rimonfb=1.8k , rimon=10k 970 1000 1030 mv v csns ? v out = 30mv; rimonfb=1.8k , rimon=10k 474 500 526 v csns ? v out = 15mv; rimonfb=1.8k , rimon=10k 226 250 274 current monitor clamp, referred to gsns 8 k PM6652 electrical characteristics doc id 16867 rev 1 13/46 soft-end section vcc_gfx discharge resistance 7 thermal throttling management therm thermal detection trip threshold measured with respect to sgnd 1.0 v threshold hysteresis 200 mv vrtt# output on resistance therm tied to sgnd 7 i vrtt# vrtt# leakage current vrtt# forced to 3.3v; therm=5v 1 a power management coreon sw regulator enable turn on level 0.800 v sw regulator enable turn off level 0.346 v dprslpvr render suspend pin thresholds render suspend (low) 0.346 v render performance (high) 0.731 vid ih vid high threshold 0.731 v vid il vid low threshold 0.346 v i vid vid pull-up current 1 a thermal shutdown t shdn shutdown temperature (1) 150 c 1. guaranteed by design. not production tested. table 5. electrical characteristics (continued) symbol parameter test condition min. typ. max. unit
voltage identification (vid) PM6652 14/46 doc id 16867 rev 1 5 voltage identification (vid) table 6. vid for intel mvp 6.5 gfx core and cpu operation mode vid6 vid5 vid4 vid3 vid2 vid1 vid0 vcore v id6 vid5 vid4 vid3 vid2 vid1 vid0 vcore 0 0 0 0 0 0 0 1.5000 1 0 0 0 0 0 0 0.7000 0 0 0 0 0 0 1 1.4875 1 0 0 0 0 0 1 0.6875 0 0 0 0 0 1 0 1.4750 1 0 0 0 0 1 0 0.6750 0 0 0 0 0 1 1 1.4625 1 0 0 0 0 1 1 0.6625 0 0 0 0 1 0 0 1.4500 1 0 0 0 1 0 0 0.6500 0 0 0 0 1 0 1 1.4375 1 0 0 0 1 0 1 0.6375 0 0 0 0 1 1 0 1.4250 1 0 0 0 1 1 0 0.6250 0 0 0 0 1 1 1 1.4125 1 0 0 0 1 1 1 0.6125 0 0 0 1 0 0 0 1.4000 1 0 0 1 0 0 0 0.6000 0 0 0 1 0 0 1 1.3875 1 0 0 1 0 0 1 0.5875 0 0 0 1 0 1 0 1.3750 1 0 0 1 0 1 0 0.5750 0 0 0 1 0 1 1 1.3625 1 0 0 1 0 1 1 0.5625 0 0 0 1 1 0 0 1.3500 1 0 0 1 1 0 0 0.5500 0 0 0 1 1 0 1 1.3375 1 0 0 1 1 0 1 0.5375 0 0 0 1 1 1 0 1.3250 1 0 0 1 1 1 0 0.5250 0 0 0 1 1 1 1 1.3125 1 0 0 1 1 1 1 0.5125 0 0 1 0 0 0 0 1.3000 1 0 1 0 0 0 0 0.5000 0 0 1 0 0 0 1 1.2875 1 0 1 0 0 0 1 0.4875 0 0 1 0 0 1 0 1.2750 1 0 1 0 0 1 0 0.4750 0 0 1 0 0 1 1 1.2625 1 0 1 0 0 1 1 0.4625 0 0 1 0 1 0 0 1.2500 1 0 1 0 1 0 0 0.4500 0 0 1 0 1 0 1 1.2375 1 0 1 0 1 0 1 0.4375 0 0 1 0 1 1 0 1.2250 1 0 1 0 1 1 0 0.4250 0 0 1 0 1 1 1 1.2125 1 0 1 0 1 1 1 0.4125 0 0 1 1 0 0 0 1.2000 1 0 1 1 0 0 0 0.4000 0 0 1 1 0 0 1 1.1875 1 0 1 1 0 0 1 0.3875 0 0 1 1 0 1 0 1.1750 1 0 1 1 0 1 0 0.3750 0 0 1 1 0 1 1 1.1625 1 0 1 1 0 1 1 0.3625 0 0 1 1 1 0 0 1.1500 1 0 1 1 1 0 0 0.3500 0 0 1 1 1 0 1 1.1375 1 0 1 1 1 0 1 0.3375 0 0 1 1 1 1 0 1.1250 1 0 1 1 1 1 0 0.3250 0 0 1 1 1 1 1 1.1125 1 0 1 1 1 1 1 0.3125
PM6652 voltage identification (vid) doc id 16867 rev 1 15/46 0 1 0 0 0 0 0 1.1000 1 1 0 0 0 0 0 0.3000 0 1 0 0 0 0 1 1.0875 1 1 0 0 0 0 1 0.2875 0 1 0 0 0 1 0 1.0750 1 1 0 0 0 1 0 0.2750 0 1 0 0 0 1 1 1.0625 1 1 0 0 0 1 1 0.2625 0 1 0 0 1 0 0 1.0500 1 1 0 0 1 0 0 0.2500 0 1 0 0 1 0 1 1.0375 1 1 0 0 1 0 1 0.2375 0 1 0 0 1 1 0 1.0250 1 1 0 0 1 1 0 0.2250 0 1 0 0 1 1 1 1.0125 1 1 0 0 1 1 1 0.2125 0 1 0 1 0 0 0 1.0000 1 1 0 1 0 0 0 0.2000 0 1 0 1 0 0 1 0.9875 1 1 0 1 0 0 1 0.1875 0 1 0 1 0 1 0 0.9750 1 1 0 1 0 1 0 0.1750 0 1 0 1 0 1 1 0.9625 1 1 0 1 0 1 1 0.1625 0 1 0 1 1 0 0 0.9500 1 1 0 1 1 0 0 0.1500 0 1 0 1 1 0 1 0.9375 1 1 0 1 1 0 1 0.1375 0 1 0 1 1 1 0 0.9250 1 1 0 1 1 1 0 0.1250 0 1 0 1 1 1 1 0.9125 1 1 0 1 1 1 1 0.1125 0 1 1 0 0 0 0 0.9000 1 1 1 0 0 0 0 0.1000 0 1 1 0 0 0 1 0.8875 1 1 1 0 0 0 1 0.0875 0 1 1 0 0 1 0 0.8750 1 1 1 0 0 1 0 0.0750 0 1 1 0 0 1 1 0.8625 1 1 1 0 0 1 1 0.0625 0 1 1 0 1 0 0 0.8500 1 1 1 0 1 0 0 0.0500 0 1 1 0 1 0 1 0.8375 1 1 1 0 1 0 1 0.0375 0 1 1 0 1 1 0 0.8250 1 1 1 0 1 1 0 0.0250 0 1 1 0 1 1 1 0.8125 1 1 1 0 1 1 1 0.0125 0 1 1 1 0 0 0 0.8000 1 1 1 1 0 0 0 0.0000 0 1 1 1 0 0 1 0.7875 1 1 1 1 0 0 1 0.0000 0 1 1 1 0 1 0 0.7750 1 1 1 1 0 1 0 0.0000 0 1 1 1 0 1 1 0.7625 1 1 1 1 0 1 1 0.0000 0 1 1 1 1 0 0 0.7500 1 1 1 1 1 0 0 0.0000 0 1 1 1 1 0 1 0.7375 1 1 1 1 1 0 1 0.0000 0 1 1 1 1 1 0 0.7250 1 1 1 1 1 1 0 0.0000 0 1 1 1 1 1 1 0.7125 1 1 1 1 1 1 1 off table 6. vid for intel mvp 6.5 gfx core and cpu operation mode (continued) vid6 vid5 vid4 vid3 vid2 vid1 vid0 vcore v id6 vid5 vid4 vid3 vid2 vid1 vid0 vcore
voltage identification (vid) PM6652 16/46 doc id 16867 rev 1 table 7. voltage identification (vid) for intel vr11 operation mode vid6 vid5 vid4 vid3 vid2 vid1 vid0 vcore v id6 vid5 vid4 vid3 vid2 vid1 vid0 vcore 0 0 0 0 0 0 0 1.5000 1 0 0 0 0 0 0 0.8125 0 0 0 0 0 0 1 1.5000 1 0 0 0 0 0 1 0.8000 0 0 0 0 0 1 0 1.5000 1 0 0 0 0 1 0 0.7875 0 0 0 0 0 1 1 1.5000 1 0 0 0 0 1 1 0.7750 0 0 0 0 1 0 0 1.5000 1 0 0 0 1 0 0 0.7625 0 0 0 0 1 0 1 1.5000 1 0 0 0 1 0 1 0.7500 0 0 0 0 1 1 0 1.5000 1 0 0 0 1 1 0 0.7375 0 0 0 0 1 1 1 1.5000 1 0 0 0 1 1 1 0.7250 0 0 0 1 0 0 0 1.5000 1 0 0 1 0 0 0 0.7125 0 0 0 1 0 0 1 1.5000 1 0 0 1 0 0 1 0.7000 0 0 0 1 0 1 0 1.4875 1 0 0 1 0 1 0 0.6875 0 0 0 1 0 1 1 1.4750 1 0 0 1 0 1 1 0.6750 0 0 0 1 1 0 0 1.4625 1 0 0 1 1 0 0 0.6625 0 0 0 1 1 0 1 1.4500 1 0 0 1 1 0 1 0.6500 0 0 0 1 1 1 0 1.4375 1 0 0 1 1 1 0 0.6375 0 0 0 1 1 1 1 1.4250 1 0 0 1 1 1 1 0.6250 0 0 1 0 0 0 0 1.4125 1 0 1 0 0 0 0 0.6125 0 0 1 0 0 0 1 1.4000 1 0 1 0 0 0 1 0.6000 0 0 1 0 0 1 0 1.3875 1 0 1 0 0 1 0 0.5875 0 0 1 0 0 1 1 1.3750 1 0 1 0 0 1 1 0.5750 0 0 1 0 1 0 0 1.3625 1 0 1 0 1 0 0 0.5625 0 0 1 0 1 0 1 1.3500 1 0 1 0 1 0 1 0.5500 0 0 1 0 1 1 0 1.3375 1 0 1 0 1 1 0 0.5375 0 0 1 0 1 1 1 1.3250 1 0 1 0 1 1 1 0.5250 0 0 1 1 0 0 0 1.3125 1 0 1 1 0 0 0 0.5125 0 0 1 1 0 0 1 1.3000 1 0 1 1 0 0 1 0.5000 0 0 1 1 0 1 0 1.2875 1 0 1 1 0 1 0 0.4875 0 0 1 1 0 1 1 1.2750 1 0 1 1 0 1 1 0.4750 0 0 1 1 1 0 0 1.2625 1 0 1 1 1 0 0 0.4625 0 0 1 1 1 0 1 1.2500 1 0 1 1 1 0 1 0.4500 0 0 1 1 1 1 0 1.2375 1 0 1 1 1 1 0 0.4375 0 0 1 1 1 1 1 1.2250 1 0 1 1 1 1 1 0.4250 0 1 0 0 0 0 0 1.2125 1 1 0 0 0 0 0 0.4125 0 1 0 0 0 0 1 1.2000 1 1 0 0 0 0 1 0.4000
PM6652 voltage identification (vid) doc id 16867 rev 1 17/46 0 1 0 0 0 1 0 1.1875 1 1 0 0 0 1 0 0.3875 0 1 0 0 0 1 1 1.1750 1 1 0 0 0 1 1 0.3750 0 1 0 0 1 0 0 1.1625 1 1 0 0 1 0 0 0.3625 0 1 0 0 1 0 1 1.1500 1 1 0 0 1 0 1 0.3500 0 1 0 0 1 1 0 1.1375 1 1 0 0 1 1 0 0.3375 0 1 0 0 1 1 1 1.1250 1 1 0 0 1 1 1 0.3250 0 1 0 1 0 0 0 1.1125 1 1 0 1 0 0 0 0.3125 0 1 0 1 0 0 1 1.1000 1 1 0 1 0 0 1 0.3000 0 1 0 1 0 1 0 1.0875 1 1 0 1 0 1 0 0.2875 0 1 0 1 0 1 1 1.0750 1 1 0 1 0 1 1 0.2750 0 1 0 1 1 0 0 1.0625 1 1 0 1 1 0 0 0.2625 0 1 0 1 1 0 1 1.0500 1 1 0 1 1 0 1 0.2500 0 1 0 1 1 1 0 1.0375 1 1 0 1 1 1 0 0.2375 0 1 0 1 1 1 1 1.0250 1 1 0 1 1 1 1 0.2250 0 1 1 0 0 0 0 1.0125 1 1 1 0 0 0 0 0.2125 0 1 1 0 0 0 1 1.0000 1 1 1 0 0 0 1 0.2000 0 1 1 0 0 1 0 0.9875 1 1 1 0 0 1 0 0.1875 0 1 1 0 0 1 1 0.9750 1 1 1 0 0 1 1 0.1750 0 1 1 0 1 0 0 0.9625 1 1 1 0 1 0 0 0.1625 0 1 1 0 1 0 1 0.9500 1 1 1 0 1 0 1 0.1500 0 1 1 0 1 1 0 0.9375 1 1 1 0 1 1 0 0.1375 0 1 1 0 1 1 1 0.9250 1 1 1 0 1 1 1 0.1250 0 1 1 1 0 0 0 0.9125 1 1 1 1 0 0 0 0.1125 0 1 1 1 0 0 1 0.9000 1 1 1 1 0 0 1 0.1000 0 1 1 1 0 1 0 0.8875 1 1 1 1 0 1 0 0.0875 0 1 1 1 0 1 1 0.8750 1 1 1 1 0 1 1 0.0750 0 1 1 1 1 0 0 0.8625 1 1 1 1 1 0 0 0.0625 0 1 1 1 1 0 1 0.8500 1 1 1 1 1 0 1 0.0500 0 1 1 1 1 1 0 0.8375 1 1 1 1 1 1 0 0.0375 0 1 1 1 1 1 1 0.8250 1 1 1 1 1 1 1 off table 7. voltage identification (vid) for intel vr11 operation mode (continued) vid6 vid5 vid4 vid3 vid2 vid1 vid0 vcore v id6 vid5 vid4 vid3 vid2 vid1 vid0 vcore
typical operating characteristics PM6652 18/46 doc id 16867 rev 1 6 typical operating characteristics measurement setup: v in = 10v, f sw = 320 khz, v core = 1.2375 v, dprslpvr = 0 v if not otherwise specified figure 4. v core turn on and pgood rising - no load figure 5. v core turn on- cpu imvp6.5 mode figure 6. v core working mode - dprslpvr asserted, no load figure 7. v core working mode (0.9v) - dprslpvr asserted, no load
PM6652 typical operating characteristics doc id 16867 rev 1 19/46 figure 8. v core working mode (0.4v) - dprslpvr asserted, no load figure 9. v core working mode - dprslpvr not asserted, no load figure 10. v core working mode - dprslpvr not asserted, 10a load figure 11. v core working mode (0.9v) - dprslpvr not asserted, no load figure 12. v core working mode (0.4v) - dprslpvr not asserted, no load figure 13. vid5 transi tion - entering and exiting suspend state (fast exit)
typical operating characteristics PM6652 20/46 doc id 16867 rev 1 figure 14. vid5 transition - entering and exiting suspend state (slow exit) figure 15. droop function - 5a to 15a transient response figure 16. v core vid step variation - vr11 mode figure 17. v core soft end - coreon pin deassertion and pgood transition figure 18. v core overvoltage (+200mv) figure 19. v core undervoltage (-300mv)
PM6652 typical operating characteristics doc id 16867 rev 1 21/46 figure 20. v core efficiency (dprslpvr high and low) figure 21. v core load regulation - droop function %fficiency6 #urrent;!= %fficiency 07- 05,3%3+)0 ".w !-v ,oad2egulation6 #urr ent;!= 6##?'&8;6= 6##?'&8 m/hm$2//0
block diagram PM6652 22/46 doc id 16867 rev 1 7 block diagram figure 22. simplified block diagram (3 (3 dr iver dr iver ,evel ,evel shifter shifter ,3 ,3 dr iver dr iver 06## 06 ## #urrent #urrent ,i mit ,i mit :##omp :##omp reference reference 6 6 $023,062 $023,062 36## 36## 0(!3% 0(!3% 0'.$ 0'.$ ,'!4% ,'!4% ('!4% ('!4% "//4 "//4 #3.3 #3.3 4o f f 4o f f min min 4o n 4o n /3# /3# 6/54 6/54 ),)- ),)- 6$!# 6$!# 63.3 63.3 '3.3 '3.3 '.$ '.$ #/-0 #/-0 8 6)$; 6)$; = = 06## 06## )-/.&" )-/.&" )-/. )-/. #3.3 gm gm $!#converter 07- 07- #omp #omp 6)$s 6)$s control control 0'.$ 0(!3% #urrent !mplifier #lamper #,+%. #,+%. 334!24 334!24 #/2%/. #/2%/. #/.42/, ,/')# 072'$ 072'$ 4(%2- 4(%2- 6244 6244 0(!3% 0'.$ /60560 4(%2-!, !nti#ross !nti#ross #onduction #onduction (3 (3 dr iver dr iver ,evel ,evel shifter shifter ,3 ,3 dr iver dr iver 06## 06 ## #urrent #urrent ,i mit ,i mit :##omp :##omp reference reference 6 6 $023,062 $023,062 36## 36## 0(!3% 0(!3% 0'.$ 0'.$ ,'!4% ,'!4% ('!4% ('!4% "//4 "//4 #3.3 #3.3 4o f f 4o f f min min 4o n 4o n /3# /3# 6/54 6/54 ),)- ),)- 6$!# 6$!# 63.3 63.3 '3.3 '3.3 '.$ '.$ #/-0 #/-0 8 6)$; 6)$; = = 06## 06## )-/.&" )-/.&" )-/. )-/. #3.3 gm gm $!#converter 07- 07- #omp #omp 6)$s 6)$s control control 0'.$ 0(!3% #urrent !mplifier #lamper #,+%. #,+%. 334!24 334!24 #/2%/. #/2%/. #/.42/, ,/')# 072'$ 072'$ 4(%2- 4(%2- 6244 6244 0(!3% 0'.$ /60560 4(%2-!, !nti#ross !nti#ross #onduction #onduction ".w
PM6652 device description doc id 16867 rev 1 23/46 8 device description the PM6652 is a single phase, step-down controller which can be easily configured to regulate power to impv6.5 and vr11 devices, as listed below: the graphics (render) core of the intel ? mobile arrandale processor used on calpella platform; the low voltage and ultra low voltage mobile cpu, used on calpella platform; the vr11 compliant cpu, like atom 200/300 family processor. the supply mode and platform compliance are selected by acting on two multi-function pins (refer to section 8.2: mode se lection on page 26 for details), before the device turn-on. the PM6652 is based on constant on-time control architecture. this type of control offers a very fast load transient response with a minimum external component count. a typical application circuit is shown in figure 1 on page 6 . the controller includes a 7 bit digital-to- analog converter (dac) that provides a reference voltage according with the vid pins settings (see ta bl e 6 and ta b l e 7 ). the PM6652 also allows adju sting an active load line (or droop) control, proportional to the inductor dcr or dedicated precision resistor, according to imvp6.5 specifications. the switching frequency can be programmed in the range 200 khz up to 600 khz with an external resistor connected to the input voltage (see section 8.1: constant on time pwm control for details). in order to maximize the efficiency at very light load, a pulse skipping control algorithm is performed. the PM6652 is also fully compliant with the fast and slow render suspend state exit mode, as required by imvp 6.5 spec. for render core supply (see section 8.6: voltage dynamic (vid) transitions on page 28 for details). the device provides protection versus overvoltage, undervoltage, overcurrent and overtemperature as well as power good (pwrgd), current monitor (imon) and thermal throttling (vrtt#) signals for monitoring purposes. the clock enable output signal (clken#), for appropriate platform power-up, is available in cpu supply mode only. 8.1 constant on time pwm control the PM6652 controller uses a pseudo-fixed frequency, constant on-time (cot) controller as the core of the switching section. the co t controller uses a relatively simple algorithm , exploiting the ripple voltage due to inductor resistance dcr (or due to a sense resistor r sns ) to trigger the fixed on-time one-shot generator. nearly constant switching frequency is achieved by the system loop in steady-state operating conditions , avoiding thus the need for a clock generator. a slight switching frequency variation vs the load is the consequence of the switching regulator power losses, which implies the off-time duration decrease. the on-time one shot duration is directly propor tional to the output voltage, sensed at vout pin, and inversely proportional to the input voltage, sensed at the vosc pin, as follows:
device description PM6652 24/46 doc id 16867 rev 1 equation 1 where k osc is a constant value (140 ns typ.) and is the internal propagation delay (40 ns typ.). this leads to a nearly constant switching frequency, regardless of input and output voltages. when the output voltage goes lower than the internal programmed voltage (see section 8.5: droop function on page 27 for details), the on-time one shot generator directly drives the high side mosfet for a fixed on-time, allowing the inductor current to increase; after the on- time, an off-time phase, in which the low side mosfet is turned on, follows. if the dprslpvr control pin is set low, the low-side mosfet is turned off only when the output voltage becomes lower than the programmed value again, and a new cycle begins. in this working mode the switching frequency is almost load independent, as shown below. refer to section 8.4: differential re mote sensing on page 27 section for details about the light load, high-efficiency algorithm. the duty cycle of the buck converter, in steady state conditions, is given by equation 2 the switching frequency is thus calculated as equation 3 where equation 4 can be set by varying the external resistor rosc, placed between vin and vosc pin. rint is the integrated switching frequency programming resistor (typ. 17k ). the resultant switching frequency is theoretically independent from battery and output voltage; actually conduction losses due to mosfet on resistance, inductor dcr and pcb traces can slightly influence the programmed value. + = osc out osc on v v k t in out v v d = osc osc osc out osc in out on sw k 1 v v k v v t d f ? ? + = = osc int int in osc osc r r r v v + = =
PM6652 device description doc id 16867 rev 1 25/46 8.1.1 constant on ti me pwm architecture figure 22 on page 22 shows the simplified block diagram of a constant on time controller. a minimum off-time constrain (250 ns typ.) is introduced to allow inductor valley current sensing on synchronous switch. a minimum on-time (70 ns) is also introduced to assure the start-up switching sequence. PM6652 has a one-shot generator that turns on the high side mosfet when the following conditions are satisfied simultaneously: the pwm comparator is high; the synchronous rectifier current is below the current limit threshold; the minimum off-time has timed out. once the on-time has timed out, the high side switch is turned off, while the synchronous switch is turned on, accord ing to the anti-cross con duction circuitry management. when the negative input voltage at the pwm comparator reaches the valley limit (determined by the output voltage), the low-side mosfet is turned off according to the anti- cross conduction logic once again, and a new cycle begins. 8.1.2 output ri pple compensation in a classic constant on time control, the system regulates the valley value of the output voltage and not the average value. in this condit ion, the half of the output voltage ripple is the equivalent dc static error. to compensate this error, an integrator network has been introduced in the control loop, by connecting the csns pin to the comp pin through a capacitor c int as shown in figure 23 on page 26 . the ripple is generated by the output capacitor esr and by the voltage drop on the sense resistor r sense (inductor?s dcr or dedicated sense resistor). assuming that r out is the cumulative output capacitors? esr, c out is the cumulative output capacitance and g m is an internal parameter (gm = 50 s typ.), the loop stabili ty requires that c int value is: equation 5 the integrator amplifier generates a current, pr oportional to the dc input error, which sets the output voltage in order to compensate the total static error. so doing the dc output voltage value is independent of the output ripple, ensuring a very good line and load regulation. in addition, c int provides an ac path for the r sense voltage ripple. in steady state condition, the voltage at comp pin is the su m of the output voltage and the output ripple. out out m int r c g c ? ?
device description PM6652 26/46 doc id 16867 rev 1 figure 23. PM6652 integrator 8.2 mode selection the PM6652 has two multifunction pins which allow selecting the supply mode of operation. there are three different modes, as shown in table !-v #3.3 #3.3 6/54 6/54 6$!# 6$!# 63 .3 63 .3 '3.3 '3.3 '.$ '.$ #/-0 #/-0 6)$; 6)$; = = gm gm $!#converter 07- 07- #omparator #omparator # # ).4 ).4 0- #3.3 #3.3 6/54 6/54 6$!# 6$!# 63 .3 63 .3 '3.3 '3.3 '.$ '.$ #/-0 #/-0 6)$; 6)$; = = gm gm $!#converter 07- 07- #omparator #omparator # # ).4 ).4 0- table 8. PM6652 mode of operation selection feature mode of operation gfx render imvp6.5 cpu core imvp6.5 cpu core vr11 vdac table table 6 on page 14 table 6 table 7 on page 16 vout minimum voltage slew-rate 5mv/s, dprslpvr=low 5mv/s 10mvs 10mv/s, when dprslpvr=high (render suspend fast exit mode) vboot voltage not required. see section 8.8: soft- start and soft-end on page 31 for details. 1.1v 1.1v clken# not used. connect to 5v. output required not used. connect to sgnd. soft-start slew- rate programmable by ext. cap. fixed, 5mv/s minimum programmable by ext. cap.
PM6652 device description doc id 16867 rev 1 27/46 8.3 pulse-skip working mode the PM6652 can obtain very high efficiency at light load if the low side mosfet is turned off when the inductor current becomes equal to zero. this feature is performed by the zero crossing comparator (see the internal block diagram, figure 22 on page 22 ). in cpu and vr11 mode this feature is activated by asserting dprslpvr pin. in gfx render mode the dprslpvr assertion implies also that the vdac minimum slew-rate is 10mv/s, for increasing programmed output voltage, as requ ired by impv6.5 specifications for render suspend fast exit mode (refer to voltage dynamic (vid) transitions for details). 8.4 differential remote sensing the PM6652 performs a differential remote sensing, between vsns and gsns pins. the error between the sensed output voltage and the programmed one (vsns - vdac) and between the remote ground and local one (gsns - gnd) are the other two inputs of the integrator, as shown in figure 23 on page 26 . the differential remote sense must be directly connected to the mobile proces sor differential feedback pins; only two catch resistors (100 ) are allowed to avoid any vr output voltage runaway, due to a lack of negative feedback when the processor is not mounted. 8.5 droop function in order to reduce the output capacitance am ount, the PM6652 performs a load dependent behavior. the voltage sensed between pins cs ns and vout is proportional to the load current: equation 6 given the network shown in figure 23 on page 26 , the resultant regulated output voltage is: equation 7 from the previous equation the equivalent droop resistance performed by the switching regulator is: equation 8 the sense resistor can be a dedicated precision resistor or the inductor's dcr as explained in section 8.7: current sensing on page 29 . load sns out sns i r v c ? = ? ? ? ? ? ? ? ? ? ? ? + ? = ? sns d sns 1 2 droop r g r r r 1 r ? = ? ? ? ? ? ? ? ? ? + =
device description PM6652 28/46 doc id 16867 rev 1 figure 24. PM6652 droop function 8.6 voltage dynamic (vid) transitions the integrated 7 bit digital-to-analog converte r (dac) can change its output voltage, with 12.5 mv step, following table 6 on page 14 and table 7 on page 16 . after a vid change, the converter starts an internal bit rolling in order to ramp-up (or ramp-down) the vdac output with a minimum voltage slew-rate as declared in table 8 on page 26 . during this time and for a blanking time (typ.30 s) after the transition, the under voltage and the variable over voltage protections are disabled. given the previously described control loop, th e switching regulator output always tracks the vdac reference, with the same voltage slew-rate. in gfx render imvp6.5 mode, if the dprslpvr control signal is asserted (dprslpvr = svcc) the render suspend state is entered, ena bling the pulse-skipping control mode. this high efficiency algorithm allows the low-side mosfet turning off when the inductor's current is zero; so doing the switching frequency becomes fully load-dependent, ensuring a # # ) ) . . 4 4 # # / / 5 5 4 4 , , $ $ # # 3 3 . . 3 3 6 6 r r 0 0 7 7 - - # # o o m m p p a a r r a a t t o o r r 6 6 / / 5 5 4 4 g g m m 6 6 $ $ ! ! # # 6 6 3 3 . . 3 3 $!#converter 6 6 ) ) $ $ s s i i g g n n a a l l s s ' ' 3 3 . . 3 3 ' ' . . $ $ # # / / - - 0 0 2 2 3 3 . . 3 3 # # ! ! 4 4 # # ( ( 2 2 % % 3 3 ) ) 3 3 4 4 / / 2 2 3 3 2 2 2 2 2 2 2 2 6 ) #urrentsenseforthedroop co mpensation 3ettingofthe droopfunction 0- )-60 0rocesso r !-v figure 25. gfx supply - vid step, skip mode figure 26. cpu imvp6.5 - vid step, skip mode !-v !-v
PM6652 device description doc id 16867 rev 1 29/46 very high efficiency at light load. figure 6 on page 18 and figure 9 on page 19 show the inductor current waveform when the dprslpvr pin is asserted high or low. when the dprslpvr control pin is still asserted high and the vdac ramp-up transition is requested, the render suspend fast exit is performed, by increasing vdac output with a minimum voltage slew-rate of 10 mv//s ( figure 24 on page 28 ). if the dprslpvr signal is de-asserted before any vids change, the vdac ramp-up transition is performed with a minimum voltage slew-rate of 5 mv/s (render suspend slow exit). in cpu imvp6.5 and vr11 mode the minimum vo ltage slew-rate is fixed, as reported in table 8 on page 26 , and the dprslpvr control signal, when asserted high, directly activate the pulse-skipping algorithm for higher light load efficiency. 8.7 current sensing as reported in equation 9 the voltage sensed between csns and vout pins must be proportional to the output current. two main techniques can be used: the precision rsns resistor and the inductor's dcr current sensing ( figure 27 on page 29 and figure 28 on page 29 ). the first method is more precise and mo re expensive, since a dedicated precision component must be selected; on the other side, the inductor's current sensing technique is cheaper but it's based on the parasitic induct or resistance whose accuracy is hardly lower than 10%. an r s -c s filter matched with the inductor's ti me constant is also required. if the inductor's dcr value is greater than the required droop an additional r b resistor is necessary. in this case, the se nsed current as suggested by equation 9 becomes: equation 9 figure 27. precision resistor current sensing figure 28. inductor's dcr current sensing !-v 6#/2% 6#/2% 2 2 3.3 3.3 , , 6). #3.3 #3.3 6/54 6/54 6#/2% 6#/2% 2 2 3.3 3.3 , , 6). #3.3 #3.3 6/54 6/54 !-v 6#/2% 6#/2% , , 6). 2 2 ! ! # # ! ! #3.3 #3.3 6/54 6/54 2 2 " " 6#/2% 6#/2% , , 6). 2 2 ! ! # # ! ! #3.3 #3.3 6/54 6/54 2 2 " " a b a a a dcr load dcr a b b out sns c r // r s 1 r sl 1 i r r r r v c ? = ? + + ? ? ? + = ?
device description PM6652 30/46 doc id 16867 rev 1 the previous equation also shows the frequency dependence of the dcr current sensing technique. during load variation the sensed dcr can also increase, if the time constant matching is not adequate; in order to avoid this situation the following equation must be verified: equation 10 figure 29 shows the vcore load transient response when equation 10 is not verified whereas in figure 30 the load transient response shows a better time constant matching. if a thermal compensation is required in order to compensate for the inductor's dcr variation, due to temperature increase, rb is replaced by a complete network, based on a ntc (negative temperature coefficient) thermistor (rn). figure 31 shows an example of ntc-based thermal compensation network (rs, rp and rn). the resultant rb1 equivalent resistance and ntc network attenuation are: equation 11 and the time constant due to ca capacitor can be computed as follows: equation 12 in PM6652 the csns and vout inputs are high-impedance pins so a very small leakage current can be measured, in the range of 50 na to 100 na. this leakage current, sourced by csns, is multiplied by the equivalent resistance measured across ca capacitor, i.e. l dcr a r l = figure 29. l > c figure 30. l < c ( ) a 1 b 1 b ntc n p s 1 b r r r g t r // r r ) t ( r + = + = ( ) 1 b a a a r // r c ? =
PM6652 device description doc id 16867 rev 1 31/46 ra//rb1, and the resultant voltage drop is found on the vcore output voltage, in agreement with equation 7 . equation 13 the result is an output voltage drop also at no load. in order to avoid this no-load voltage drop co ndition, the current sensing filter equivalent resistance, i.e. ra//rb1, should fall in the range 1k 10k . figure 31. thermal compensation network 8.8 soft-start and soft-end the dac voltage slew-rate at start-up can be dec reased, in order to limit the inrush current, in gfx and vr11 supply mode. a soft-start capacitor c ss placed between sstart pin and sgnd is charged and discharged with 50 a (only at start-up). the resultant soft-start capacitor voltage variation is exploited by the internal dac to ramp-up to the vids programmed value (in gfx mode) or to vboot default voltage (in vr11 mode), with 12.5 mv steps. figure 34 shows the soft-start vdac voltage slew-rate vs css capacitance. if the sstart pin is connected to svcc, the vdac ramp-up (and vout output voltage too) is performed with minimum 5mv/s voltage slew-rate. this function is performed in cpu imvp6.5 mode only. figure 32 and figure 33 show the different soft-start mechanism for gfx mode and cpu mode, assuming the following typical values for timing: ton =350 s; tstart depends on the soft-start programmed slew-rate and voltage; for cpu mode, the soft-start slew-rate is 6.25 mv/s (typ.) and vboot = 1.1 v so tstart = 176 s typ. tboot = 70 s tpg = 4ms 1 b a lkg lkg r // r i v ? = 2b #a 2a , 2s 2n 2p #3.3 6/54 !-v
device description PM6652 32/46 doc id 16867 rev 1 in cpu and vr11 mode the soft-start programmed voltage is vboot; the output voltage will be driven to the vids prog rammed voltage value only after tboot delay. when the vr11 mode is selected the clken# signal is not used as output but only as input pin. refer to mode selection se ction for details. figure 4 and figure 5 on page 18 show the different turn-on behavior for gfx mode and cpu/vr11 mode. when the coreon control pin is pulled-down or the shut-down vids sequence is selected, vid[0,...,6]=[1111111], the turn -off sequence is performed. in order to avoid the output voltage to go under ground, the output capacitor is discharged through a dedicated 7 (typ.) internal discharge mosfet, connected between vout and sgnd pins. when vout voltage is lower than 100 mv the low-side external mosfet is turned-on. see figure 16 on page 20 and figure 17 on page 20 for the soft-end waveforms details. figure 34. vdac soft-start voltage slew-rate vs capacitor value figure 32. imvp6.5 gfx mode start-up figure 33. impv6.5 cpu mode start-up !-v #/2%/. 6/54 0'//$ 4on 4pg 6)$s 4start #/2%/. 6/54 0'//$ 4on 4pg 6)$s 4start !-v #/2%/. 6/54 #,+%. 0'//$ 4on 4start 4boot 4pg 6)$s 6 #/2%/. 6/54 #,+%. 0'//$ 4on 4start 4boot 4pg 6)$s 6 !-v 3oft startslew rate 3oft startcapacitor;p&= 3lew rate;m6us=
PM6652 device description doc id 16867 rev 1 33/46 8.9 internal mos drivers the integrated high-current gate drivers allow using different power mosfets. the high side driver, which is supplied by the +5 v rail, uses a bootstrap circuit with integrated boot diode. only one external cera mic capacitor (100 nf or bigger) is required. the boot and phase pins work respectively as supply and return path for the high-side driver, while the low-side driver is directly fed through pvcc and pgnd pins. an important feature of the PM6652 gate dr ivers is the adaptive anti-cross-conduction circuitry, which prevents high-side and low-si de mosfets from being turned on at the same time. when the high-side mosfet is turned off, the voltage at the phase node begins to fall. the low-side mosfet is turned on only when the voltage at the phase node reaches an internal threshold in the range of 2.5 v to 1 v. similarly, when the low-side mosfet is turned off, the high-side one remains off until the lgate pin voltage is above 0.8 v (typical value). 8.10 monitoring and protections 8.10.1 power good the power good signal is an open-drain output which requires an external pull-up resistor. when vout is lower than 300 mv or higher than 200 mv respect to vdac, or when the coreon pin is de-asserted, the pwrgd pin is immediately forced low. at the start-up, the pwrgd pin is allowed to rise only 4 ms after the vdac programmed value is reached, as shown in figure 4 on page 18 , figure 32 and figure 33 . 8.10.2 current monitor (imon) the voltage sensed between csns and vout pins is mirrored across rg external resistor (between imonfb and vout pins) and the resu ltant current is mult iplied by the current monitor block gain. the typical gain value is: equation 14 the current monitor gain can be adjusted by choosing rimon, as shown in figure 37 , in order to program the required v imon at maximum load. the total imon gain becomes: equation 15 g imon,int =3 is a fixed internal parameter. the minimum suggested value for rg is equal to 400 with maximum allowable imonfb current lower than about i max = 40 a (typ.). a good range for rg choice is [0.68k ; 7k ] with a maximum csns-vout voltage up to 60 mv. 3 g int , imon = ? = ?
device description PM6652 34/46 doc id 16867 rev 1 if the current sourced by imonfb pin is greater than i max for more than 4 ms (typ.) the average current limit fault is detected and the ic latches off: the mos drivers are put in high impedance and the internal discharge mosfet is turned on (see figure 35 ). a coreon or svcc toggle is required in order to restart the device. every time the imonfb pin current becomes lo wer than imax, the internal timer is reset (see figure 36 ); as a consequence the inductor current which can cause the average current limit fault is given by: equation 16 in order to set the right average current limit threshold, the PM6652 internal parameters and also external components accuracy must be considered. a complete equation for the average current limit threshold worst case variation is: equation 17 assuming r g /r g the accuracy of r g , imax <10% the internal current reference error, v imon,off <1 mv the imon maximum offset, g sns the ntc thermal compensation network attenuation (see equation 11), r sns /r sns the inductor dcr or precision resistor accuracy and g sns /g sns the thermal compensation network gain error, due to ntc and others resistors accuracy (see equation 25 ). if the thermal compensation network is not used and/or the current sensing f ilter resistors value is highe r than the suggested one (as explained it section 8.7: current sensing on page 29 ) the previous equation must be modified in order to take account of dcr ther mal drift and current se nsing additional offset. dcr g max l avcl , out avcl r r i i i i ? ? = figure 35. average current limit - recovery figure 36. average current limit detected () ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? + + ? ? ? ? ? ? ? ? = sns sns sns sns avcl sns sns off , imon imax g g avcl wc , avcl g g r r i r g v r r i i
PM6652 device description doc id 16867 rev 1 35/46 equation 18 given v lkg the voltage drop across the current sens ing filter resistor, due to the csns pin leakage current (see equation 13 ) and r th /r sns the current sensing element variation due to temperature increase. if the current monitoring function is not required, imonfb should be connected to svcc and imon can be left floating. c filt ( figure 37 ) can be required by the cpu/gpu in order to filter the current monitor ripple due to inductor current ripple. equation 19 a typical value for cfilt is 47 nf or bigger (imvp6.5 specifications suggest c filt *r imon >=300 s). the imon voltage is limited to 1.15 v (maximum value), as required by imvp6.5 specifications, in order to avoid any damage to the cpu. this feature is performed by limiting the current injected by the PM6652 imon pin into rimon resistor. figure 37. current monitor with external components 8.10.3 thermal throttling the voltage regulator thermal throttling functi on is used by the cpu in order to avoid catastrophic thermal damage. vrtt# open-drain output pin is forced down when the therm voltage is lower than an internal threshold (1.0 v typ. and 200 mv hysteresis). an external ntc resistor, placed near ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? + = sns th avcl sns sns lkg avcl wc , avcl avcl avcl r r i r g v i i i i dcr imon filt r l r c ? !-v )-/.&" )-/.&" #3.3 #urrent !mplifier #lamp )-/. )-/. 633 ?3.3 2' 2) -/. #&),4 #/54 0- 0- , , 2 2 ! ! # # ! ! )-/.&" )-/.&" #3.3 #urrent !mplifier #lamp )-/. )-/. 633 ?3.3 2' 2) -/. #&),4 #/54 0- 0- , , , , 2 2 ! ! # # ! !
device description PM6652 36/46 doc id 16867 rev 1 the external mosfet or the inductor, allows the controller monitoring the thermal status of the power components (see figure 38 ). in application where this function is not requ ired (in render core supply, for example) the therm pin must be connected to 5v and vrtt# can be left floating. figure 38. voltage regulator thermal throttling 8.10.4 overvoltage protection the PM6652 can detect two kinds of vout overvoltage: fixed 1.55 v overvoltage threshold; variable +200 mv overvoltage threshold, referred to vdac reference voltage. both overvoltage protections are latched, so a coreon or svcc togg le is required in order to restart the device. if the fixed overvoltage threshold is reached, the high-side mosfet is immediately turned- off and the output capacitor is sharply discharged by turning-on the low-side mosfet. this fault protection is always active. when a variable v out overvoltage is detected, both high-side and low-side external mosfets are turned-off and the output capacitor soft-discharge is performed. the internal discharge mosfet is turned-on until vout is lower than about 100 mv, then the low-side mosfet is turned-on (see figure 18 on page 20 ). this fault detection is masked during vid transitions and, during soft-start, until the power good signal is released. 8.10.5 undervoltage protection if the switching voltage regulator output falls below -300 mv, referred to vdac programmed voltage, the latched under voltage fault is detec ted and the output capacit or soft-discharge is performed. the internal discharge mosfet is turned-on until vcc_gfx is lower than about 100 mv, then the low-side mosfet is turned-on (see figure 19 on page 20 ). this fault detection is masked during vid transitions and, during soft-start, until the power good signal is released. the under voltage protection can't be detected if the programmed vdac voltage is lower than 300 mv. !-v . 4 # 6 4(%2- 6244 6 0- . 4 # 6 4(%2- 6244 6 0-
PM6652 device description doc id 16867 rev 1 37/46 8.10.6 overcurrent protection the PM6652 controller can limit the maximum load current by skipping one or more switching cycles if the valley current limit is detected. the curr ent limit sensing is independent from the current sensing for droop and imon functions. basically, the voltage drop sensed between pgnd and phase pins, when the low side mosfet is on, is compared with the voltage across the external r ilim resistor. the following equation helps to program the valley current limit value (see figure 39 ): equation 20 figure 39. valley current limit circuitry the maximum available load current, with the valley current limit technique, is equal to: equation 21 i.e. the maximum available current is the sum of the valley current limit value plus the half of the inductor current ripple. the valley curren t limit is sensed each switching cycle, during t off time (when the low-side mosfet is turned-on) . this fault protection is not latched but the typical behavior is the one shown in figure 40 on page 38 : ( ) phase pgnd ilim v v 20 a 5 r ? ? = ? !-v 6alley 6alley #urrent,imit #urrent,imit ),)- ),)- 8 0'.$ 0'.$ 0(!3% 0(!3% 07- 07- #omparator #omparator 1 3 2 1 ('!4% ('!4% ,'!4% ,'!4% 6/54 6/54 2 2 ),)- ),)- , , 0- 6). 6). 6alley 6alley #urrent,imit #urrent,imit ),)- ),)- 8 0'.$ 0'.$ 0(!3% 0(!3% 07- 07- #omparator #omparator 1 3 2 1 ('!4% ('!4% ,'!4% ,'!4% 6/54 6/54 2 2 ),)- ),)- , , 0- 6). 6). l 2 1 vcl max , load i i i ? + =
device description PM6652 38/46 doc id 16867 rev 1 figure 40. valley current limit detection if the overload is not removed, the output capacitor keeps discharging until the uv fault is detected. in order to set the right valley current limit threshold, the PM6652 internal parameters and also external components accuracy must be considered. a complete computation of the valley current limit threshold worst case variation can be found in equation 22 . equation 22 the ?key parameter? is the low-side mosfet on resistance, r ds,on , which takes account of the maximum on-resistance value and its thermal drift. the other parameters, with the exception of r ilim (typical accuracy 1%), are all internal parameters: i ilim <0.5 a is the current reference variation and v offset <4 mv is the current lim it comparator offset. 8.10.7 svcc undervoltage protection the PM6652 can detect an svcc under voltage (threshold 3.9 v typ.). when this fault occurs, the high-side mosfet is turned-off and the low-side mosfet is turned-on. the device is turned-on again if the svcc voltage is higher than 4.4 v (typ.). this fault protection is always active. 8.10.8 thermal protection if the device internal temperature is greater than 150 c the thermal shutdown is performed. the internal discharge mosfet is turned-on un til vout is lower than about 100 mv, then the low-side mosfet is turned-on. a coreon or svcc toggle is required to turn-on again the device. this fault detection is masked during vid transitions and, during soft-start, until the power good signal is released. ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? > on , ds on , ds ilim ilim offset iliim iliim ilim ilim vall , l wc , vall , l r r r i v 20 i i r r i i
PM6652 device description doc id 16867 rev 1 39/46 8.11 system accuracy 8.11.1 vcore accuracy starting from equation 7 and equation 9 , the programmed output voltage is given by: equation 23 vdac is the internal reference voltage, i.e. the digital-to-analog converter output programmed by the 7 vids; g d is the droop gain, given by equation 8; g sns is the current sensing filter attenuation. th is element is lower than 1 if there is an ntc thermal compensation network, typically used in dcr current sensing technique; r sns is the current sensing element, i.e. the inductor dcr or the precision resistor; the statistical variation of the output voltage is given by the following equation: equation 24 v dac is the internal reference voltage error, lower than 0.7% of the programmed vid (refer to figure 5 on page 11 ); g d /g d and g sns /g sns are the statistical error of the droop gain and ntc network, if used. this two elements are only influenced by external components; r sns is the current sensing element (inducto r's dcr or precision resistor) variation due to its accuracy; v offset < 2.5 mv is the PM6652 integrator maximum offset. based on equation 7 the droop gain statistical error is: equation 25 the same mathematical approach provides with the following computation, based on equation 11 : ( ) out sns sns d dac sns _ ss sns _ cc i r g g v v v ? ? ? ? = ? ()( ) ()() sns d 2 offset d 2 sns out 2 sns sns 2 d d 2 out sns 2 dac stat , core g g g v g r i g g g g g i r g v v ? = ? + ? ? + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? + = 2 1 1 2 2 2 d d d d 1 2 d r r r r g 1 g g g r r 1 g ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? = + =
device description PM6652 40/46 doc id 16867 rev 1 equation 26 as explained in section 8.7: current sensing on page 29 the current sensing filter, if not properly designed, can impact the overall accuracy. in this case equation 22 must be updated: equation 27 given v lkg the voltage drop across the current sens ing filter resistor, due to the csns pin leakage current ( equation 13 ). equation 27 takes also account of the sensing element variation due to thermal drift: this element is almost negligible if the ntc thermal compensation network is used. 8.11.2 current reporting (imon) accuracy the current monitor feature (imon), as described in section 8.10.2: current monitor (imon) on page 33 , has the following design equation: equation 28 g int = 3 is the internal fixed gain; r imon and rg are external resistors for gain programming; g sns is the current sensin g filter attenuation; r sns is the current sensing element. the statistical error of the imon function can be computed: equation 29 r sns /r sns is the current sensing element accuracy; r imon /r imon and r g /r g are the external resistors accuracy; g int /g int < 1% is the internal fixed gain error; v imon,off < 1 mv is the imon maximum input offset; g sns /g sns is the current sensing filter error (refer to equation 26 for details). the imon accuracy can be influenced by a not properly designed current sensing filter (as explained in section 8.7: current sensing on page 29 ) and by the current sensing element thermal drift, as summarized in equation 30 : () 2 p p 2 s s 2 ntc ntc 2 a a sns sns sns r r r r r r r r g 1 g g ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? = th out lkg stat , core core r i g v v v ? ? + + = out sns sns g imon int imon i r g r r g v ? ? ? ? = 2 sns sns 2 out sns sns off , imon 2 int int 2 imon imon 2 rg g 2 rsns sns imon stat , imon g g i r g v g g r r r r r r v v ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? =
PM6652 device description doc id 16867 rev 1 41/46 equation 30 given v lkg the voltage drop across the current sens ing filter resistor, due to the csns pin leakage current (see equation 13 ). sns th l sns sns lkg imon stat , imon imon imon r r i r g v v v v v + ? ? + =
layout guidelines PM6652 42/46 doc id 16867 rev 1 9 layout guidelines the PM6652 has two separate grounds: pgnd, the power ground, and sgnd, the reference for ic internal circuitry. a 2 separate grounds layout is based on the following guidelines: design an analog/signal ground plane on one inner layer, connect this area to sgnd and exposed pad (trough some vias); design one power ground plane on one internal layer. connect the sgnd (signal ground) plane and pgnd plane in one point (ex. under exposed pad or near the low- side mosfet source). if pgnd plane and sgnd plane are in different layers, use at least 2 vias for the connection. it is recommended not to use a resistor to connect pgnd plane and sgnd plane. alternatively, a single ground pcb can be designed, taking into account the following suggestions (refer to figure 1 on page 6 ): design one power ground plane on one internal layer; connect all the components referred to sgnd (r15, c2, c6, c8 , r10, c9) with a dedicated trace, then connect this trace to sgnd (pin 9) and to the ic thermal pad; connect the ic thermal pad directly to the power ground, through some vias. other suggestions for a good layout follow: gsns, vsns: route the remote feedback sensing nets coupled (7 mils separation) and 18 mils wide. keep 25 mils separation from other signals (this is an intel suggestion); csns, vout: keep the current sensing signals directly from the current sensing element terminals (inductor pads, for dcr sens ing, or precision resistor pads). place the l-dcr filter, if required, near the in ductor and route the current sensing nets coupled and far from noisy nets. place the ntc thermistor, if required, as close as possible to the inductor. use the gnd/sgnd plane for shielding. imon, imonfb: keep far from switching traces (use, if necessary, the gnd/sgnd plane for shielding) and place the ou tput r-c filter close to the cpu; lgate, hgate, phase: design trace width > 20 mils and as short as possible (avoid using vias if possible). keep the ratio 3 m ils_width/100 mils_lenght even for traces longer than 500 mils (ex. trace length: 2000 mils. design a trace width of about 60 mils). keep far from signal traces to avoid noise coupling on signal traces. place the gate resistor near the mosfet gate. boot: place ceramic capacitor close to bo ot pin and phase pin; the trace must be > 20 mils and the spacing with other signal tr ace > 20 mils. minimize the length of the loop between phase pin and boot pin. use at least 3 vias if a layer change is required. svcc, pvcc: place the capacitor close to svcc/pvcc pin. design trace width >= 20 mils. svcc is internally co nnected to pvcc through a few resistor (3 , typ.) so svcc doesn't need to be externally connected to +5 v rail.
PM6652 package mechanical data doc id 16867 rev 1 43/46 10 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com. ecopack is an st trademark. table 9. vfqfpn (1) 5x5x1.0 mm 32l pitch 0.50 mechanical data 1. vfqfpn stands for thermally enhanced very thin fi ne pitch quad flat package no lead. very thin: a = 1.00 mm max. dim. (mm) min. typ. max. a 0.80 0.90 1.00 a1 0 0.02 0.05 a3 0.20 b 0.18 0.25 0.30 d 4.85 5.00 5.15 d2 (2) 2. dimensions d2 and e2 are not in accordance with jedec. 2.90 3.10 3.20 e 4.85 5.00 5.15 e2 (2) 2.90 3.10 3.20 e0.50 l 0.30 0.40 0.50 ddd 0.05
package mechanical data PM6652 44/46 doc id 16867 rev 1 figure 41. vfqfpn 5x5x1.0 mm 32l pitch 0.50 mechanical drawing
PM6652 revision history doc id 16867 rev 1 45/46 11 revision history table 10. document revision history date revision changes 04-dec-2009 1 initial release
PM6652 46/46 doc id 16867 rev 1 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2009 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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