application note AN258/0189 pentawatt-heptawatt packages by r. tiziani thermal characteristics of the introduction this application note is aimed to give a complete thermal characterization of the heptawatt and pen- tawatt package (fig. 1, 2). characterization is performed according with reco- mendationsincludedin the g32-86semi guideline,by means of a dedicated test pattern. it refers to : 1. junction to case thermal resistance r th(j-c) 2. junction to ambient thermal resistance r th(j-a) 3. junction to ambient thermal impedance for sin- gle pulses and repeated pulses, with different pulse width and duty cycle ; 4. thermal resistance in dc and pulsed conditions, with a typical external heat sink. most of the experimental work is related to the ther- mal impedance, as required by the increasing use of switching techniques. experimental conditions the thermal evaluation was performed by means of the test pattern p432, which is a 15k mils 2 die with a dissipating element formed by two transistors wor- king in parallel and one sensing diode. in order to characterize the worst case of a high power density ic, the total size of the element is 2k mils 2 with a po- wer capability of 20w. measurement method is de- scribed in appendix a. samples with the indicated characteristicswere pre- pared : measurement of junction to case thermal resistance r th(j-c) is performed by holding the package against a water cooled heat sink, according with fig. 3. a thermocouple placed in contact with the slug mea- sures the reference temperature of the case. for junction to ambient thermalresistancer th(j-a) the samples are suspended horizontally in a one cubic foot box, to prevent drafts. both dc and pulsed conditions are used ; in the se- cond case the contribution of package thermal ca- pacitance is effective and transient thermal resistances much lower than the steady state r th(j-a) can be found,according with pulse length and duty cycle. the effect of the external heat sink is quantified, using as test vehiclethe commercially available heat sink thm7023 (thermalloy) whose thermal resis- tance in still air is about 9 c/w. the measurement circuit shown in fig. a3 was used for all of the thermal evaluations. junction to case thermal resis- tance the dependance of r th(j-c) on the dissipated power is reported in fig. 4. the absolute value and the be- haviour with the dissipated power are the same for figure 2 : heptawatt. figure 1 : pentawatt. package pentawatt - heptawatt frame material copper slug thickness 1.25mm typ. slug thermal conductivity 3.9w/cm c die attach soft (pbsn) 1/9
both packages as the slug thickness and the die - attach are equal. figure 3 : measurement of r th (j-c) . it is well known that the main contribution to r th(j-c) of power packages is given by the silicon die. for other devices than the test pat- tern p432 the calibration curve of fig. 5 is needed. it shows the relationship between r th(j-c) and the dis- sipating area existing on the silicon die (power dio- des, power transistors, high current resistors), for different die sizes. junction to ambient thermal resistance in medium power application (1w), the pentawatt and heptawatt packagescan be used without exter- nal heat sink thanks to the significant size (about 1.5cm 2 ) of its integrated thermal mass. an effective cost solution for higher power applica- tion (1.5-2.0w) is using a copper area heat sink. an board with the external leads bent down as shown in fig. 7. fig. 6 gives the relationship between r th(j-a) and the power dissipation level for the p432 test pattern in still air, on pc board, on integrated heat sink on bo- ard and on a commercial heat sink. in order to have an accurate value for other devices, with different die size and dissipating area, values of fig. 6 should be corrected through the cali- bration curve of fig. 5 correction term is always in the range of 0-2 c/w ; therefore, it affects the rth (j-a) of no more than 5% in still air or with the package mounted in pc board. figure 4 : r th (j-c ) of pentawatt and heptawatt package vs. power level. figure 5 : r th (j-c) thermal resistance vs. die size and on die dissipating area. application note 2/9
figure 6 : r th (j-a) vs. dissipated power (heptawatt). figure 7 : pentawatt soldered on copper heatsink on p.c board. transient thermal resistance in pulsed condition (without external heat sink) the effect of single pulses of different length and height without any external heat sink is shown in fig. 8. this behaviour is discussed in appendix b. due to a significant thermal capacitance (c = 1j/ c) and a correspondingly long risetime ( t = 80s), single pul- ses up to 20w can be delivered for 1 s with accept- able junction temperature increase. application note 3/9
in order to have accurate r th (t o ) for other devices, with different die size and dissipating area, values of fig. 7 must be corrected as described in example 2 of the last section. repetition of pulses with defined pd, period and duty cycle dc (ratio between pulse lengthand signal period), gives rise to oscillations in junction tempe- rature as described in appendix b. the transient thermal resistance corresponding to the upper limit of the curve of fig. b4 (peak transient thermal resistance) is reported in fig. 9 and depends on pulse length and duty cycle. it can be noticed that dc becomes less effective for longer pulses. appendix a the thermal resistance evaluation is performed with the especially designed test chip p432 which has two bipolar power transistor and one sending diode (fig. a1). the active area is about 2000 mils 2 on a 15000 mils 2 chip. its lay-out was optimized in order to have a uniform temperature area, once the two transistor are powered ; the sensing diode is placed at the center of this area. figure 9 : peak transient r th vs pulse width and duty cycle (heptawatt). figure a1 : test pattern p432 lay-out. figure 8 : transient thermal resistance for single pulses (heptawatt). application note 4/9
the relationship between the forward voltage v f of the diode at a constant current of 100 m a and the temperatureis shownin fig. a2. the curve calibrates the junction temperature through the voltage drop of the diode. the measurement circuit is shown in fig. a3. a sto- rage oscilloscope or a fast digital voltmeter can be used for recording the v f value. figure a2 : calibration curve (sensing diode). figure a3 : measurement circuit. appendix b - thermal management in pulsed condition thermal resistance and capacitance the electrical equivalent of heat dissipation, for a thermal module formed by the active device with its package and the external heat sink is shown in fig. b1. to each cell of the thermal chain are associated a value of thermal resistance r th (c/w) and a value of thermal capacitance c th (j/ c). the former informs about temperature increase due to the element rep- resented by the cell ; as, in the example under con- sideration, heat transfer is mainly based on conductionfor the silicon, the copper integratedheat sink and to metallic body of the external heat sink rth can be calculated from the relationship : 1 kxs r th = where k is the thermal conductivity of the material, 1 the length of the conductive path and s its section. application note 5/9
figure b1 : electrical equivalent of pentawatt and heptawatt package mounted on the external heatsink. thermal capacitancec th is the capability of heat ac- cumulation ; it depends on the specific heat of the material and on the volume effectively interested by heat exchange (this means that the parts which are not heated during heat dissipation do not contri- bute to thermal capacitance). thermal capacitance is given by : c th =dxc t xv where d is the density of the material, c t its specific heat and v the volume interested to heat accumu- lation. the last element of the network, assumed as purely resistive, is due to convection and radiation from the external heat sink towards the ambient. each cell has its own risetime t , given by the product of thermal resistance and capacitance : t =r th xc th the value of the time constant determines whether a cell approachesequilibrium rapidly or slowly : if r th or c th increases, equilibrium is reached at a slower rate. the following relationship is valid for each cell : d t=r th xp d x[1-et/ t ](1) typical values of r th ,c th and t for heptawatt and pentawatt application are shown in fig. b1. when power is switched on, temperature increa- se is ruled by subsequent charging of thermal ca- pacitance while the value reached in the steady state depends on thermal resistance only. qua- litative beahaviour of the network of fig. b1 is shown in fig. b2. figure b2 : qualittative t j increase (network of fig. b1) for repeated power pulse (heptawatt). application note 6/9
single power pulse when the pulse length has an assignedvalue, effec- tive t j can be significantly lower than steady state t j (fig. b3.). figure b3 : effect of a single power pulse. for anypulse length t o , a transient thermal resis-tan- ce r th (t o ) is defined, from the ratio between the jun- ction temperature at the end of the pulse and the dissipated power. obviously, for shorter pulses, r th (t o ) is lower and a higher power can be dissipated, without exceeding the maximum junction tempera- ture t j max allowed to the ic from reliability conside- rations. fig. 7 and 9 of this application note give experimental values of r th (t o ) for the two cases of the heptawatt package without and with external heat sink. repeated pulses when pulses of the same height pd are repeated with a defined duty cycle dc and pulse length is short in comparison with the total risetime of the sy- stem (many tens of seconds) the train of pulses is seen by the system as a continuous source, at a mean power level of p davg =pdxdc the average temperature increase is : d t avg =r th xpd avg =r th xpdxdc on the other hand, the silicon die ( t si =1 2ms) is able to follow frequencies of some khz and jun- ction temperature oscillates about the average, as qualitatively shown in fig. b4. the thermal resistance corresponding to the peak of the oscillation at equilibrium (peakthermalresis-tan- ce r th peak ) is now given by fig. 5, and can be obtai- ned if pulse length and duty cycle are known ; pd max is derived from the same figure. figure b4 : junction temperature increase for operated pulses. application examples example 1 - maximum pd for single pulse of assigned length problem: define the maximum pd for a single pul- se with a length of 20ms in the case of heptawatt package used without heat sink. ambient tempera- ture is 50 c ; maximum temperature is 130 c. die size is 15k mils 2 , with dissipating area of 2k mils 2 (as in p432 test pattern). solution : allowed temperature increase d tis 80 c. having a r th(j-a) of 60 c/w, heptawatt pac- kage can dissipate about 1.3w in steady state from fig. 8 the transient thermal resistance corresponding to one single pulse of 20ms in r th (20ms) p432 = 2.2 c/w. a peak of 80/2.2 = 36.3w can be applied to the circuit. example 2 - correction for die size and dissipating area problem : correct the results obtained in example 1, for assigned die size and dissipating area. pratical case : ic having a die size of 15k mils 2 with a dissipating area of 10k mils 2 . solution : from fig. 5, thermal resistance of p432 and of the ic under consideration are r th p432 = 2.3 c/w and r th(j-c)ic = 1.5 c/w. as the length of the pulse is 10-15 times longer than the risetime of the silicon, the die (first cell of fig. b1) application note 7/9
can be assumed to have reached its equilibrium condition. r th (20ms) found in previous example has to be cor- rected in order to take into account the new value of r th(j-c) . r th (20ms) ic =r th (20ms) p432 r th(j-c)p432 +r th(j-c)ic = = 2.2 - 2.3 + 1.5 c/w = 1.4 c/w a single pulse of 80/1.4 57w can be delivered to such a device. example 3 - correction for single pulses of 13ms problem : correct the results of example 2, for pulse length of 1ms. solution : when the pulse has the same order of magnitude of silicon rise time ( t p432 is about 1ms) another type of correction is needed. in first appro- ximation it is considered that remains constant when the dissipating area gets higher and the rth for the silicon die decreases as the reciprocal of the dissipating area. from relationship (1) : d t=r th (1ms) p432 x 2k/10k x pd x [1- e-t/ t ]fort o = 1ms : r thic (1ms) = 1.05/0.5 c/w 0.21 c/w a single pulse of 80/0.21 380w can be delivered to such a device. example 4 - rth repeated pulses problem : find the peak power which can be dis- sipated by heptawatt package without heatsink, when power is continuously switched on 10ms and switched off 90ms. ambient temperature is 50 c. maximum temperature is allowed to be 125 c. solution : a maximum d t=75 c has to be con- sidered. fig. 9 indicated that for a pulse width of 10ms and a duty cycle of 0.1, rth peak is 8.5 c/w. maximum pd is 75/8.5= 8.8w, with an average tem- perature increase d t peak of 60 x 0.1 x 8.8 68 c. references oimproved thermal evaluation, by means of a simple integrated structureo t. hopkins, c. cognetti, r. ti- ziani - semi therm (usa, 1986). application note 8/9
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specification mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of sgs-thomson microelectronics. ? 1995 sgs-thomson microelectronics printed in italy all rights reserved sgs-thomson microelectronics group of companies australia - brazil - canada - china - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco - the nether- lands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. application note 9/9
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