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| ltc2433-1 1 24331fa the ltc ? 2433-1 is a differential input micropower 16-bit no latency ds tm analog-to-digital converter with an inte- grated oscillator. it provides 0.12lsb inl and 1.45 m v rms noise independent of v ref . it uses delta-sigma technology and provides single conversion settling of the digital filter. through a single pin, the ltc2433-1 can be configured for better than 87db input differential mode rejection at 50hz and 60hz 2%, or it can be driven by an external oscillator for a user defined rejection frequency. the internal oscillator requires no external frequency setting components. the converter accepts any external differential reference voltage from 0.1v to v cc for flexible ratiometric and remote sensing measurement configurations. the full- scale differential input range is from C 0.5 ? v ref to 0.5 ? v ref . the reference common mode voltage, v refcm , and the input common mode voltage, v incm , may be indepen- dently set anywhere between gnd and v cc . the dc common mode input rejection is better than 140db. the ltc2433-1 communicates through a flexible 3-wire digital interface which is compatible with spi and microwire tm protocols. n direct sensor digitizer n weight scales n direct temperature measurement n gas analyzers n strain-gage transducers n instrumentation n data acquisition n industrial process control , ltc and lt are registered trademarks of linear technology corporation. n 16-bit differential adc in a tiny msop n low supply current: 200 m a, 4 m a in autosleep n rail-to-rail differential input/reference n 0.12lsb inl, no missing codes n 0.16lsb full-scale error and 5 m v offset n 1.45 m v rms noise, independent of v ref n very low transition noise: <0.02lsb n operates with a reference as low as 100mv with 16-bit resolution n internal oscillatorno external components required n 87db min, simultaneous 50hz and 60hz notch filter n single supply 2.7v to 5.5v operation n pin compatible with the 20/24-bit ltc2431/ltc2411 n available in 10-lead msop package differential input 16-bit no latency ds adc no latency ds is a trademark of linear technology corporation. microwire is a trademark of national semiconductor corporation. minimum resolvable signal vs v ref v cc ref + f o in + in sck ref sdo gnd cs 110 4 9 3 5 6 8 7 24331 ta01 2 = external clock source = internal osc/simultaneous 50hz/60hz rejection 3-wire spi interface 1 f (100mv) 4.9k 100 5v ref ltc2433-1 v ref (v) 0 *for v ref 3 0.5v the resolution is limited by step size 0 minimum resolvable signal ( v)* 10 30 40 50 2 4 5 90 24331 ta02 20 13 60 70 80 applicatio s u descriptio u features typical applicatio u
ltc2433-1 2 24331fa (notes 1, 2) order part number supply voltage (v cc ) to gnd .......................C 0.3v to 7v analog input voltage to gnd .................................... C 0.3v to (v cc + 0.3v) reference input voltage to gnd .................................... C 0.3v to (v cc + 0.3v) digital input voltage to gnd ........ C 0.3v to (v cc + 0.3v) digital output voltage to gnd ..... C 0.3v to (v cc + 0.3v) operating temperature range ltc2433-1c ............................................ 0 c to 70 c ltc2433-1i ........................................ C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c t jmax = 125 c, q ja = 110 c/w ltc2433-1cms LTC2433-1IMS parameter conditions min typ max units resolution (no missing codes) 0.1v v ref v cc , C0.5 ? v ref v in 0.5 ? v ref , (note 5) l 16 bits integral nonlinearity (note 15) 5v v cc 5.5v, ref + = 2.5v, ref C = gnd, v incm = 1.25v, (note 6) 0.06 lsb 5v v cc 5.5v, ref + = 5v, ref C = gnd, v incm = 2.5v, (note 6) l 0.12 1.25 lsb ref + = 2.5v, ref C = gnd, v incm = 1.25v, (note 6) 0.30 lsb offset error (note 15) 2.5v ref + v cc , ref C = gnd, l 520 m v gnd in + = in C v cc , (note 13) offset error drift 2.5v ref + v cc , ref C = gnd, 20 nv/ c gnd in + = in C v cc positive full-scale error (note 15) 2.5v ref + v cc , ref C = gnd, l 0.16 1.25 lsb in + = 0.75ref + , in C = 0.25 ? ref + positive full-scale error drift 2.5v ref + v cc , ref C = gnd, 0.04 ppm of v ref / c in + = 0.75ref + , in C = 0.25 ? ref + negative full-scale error (note 15) 2.5v ref + v cc , ref C = gnd, l 0.16 1.25 lsb in + = 0.25 ? ref + , in C = 0.75 ? ref + negative full-scale error drift 2.5v ref + v cc , ref C = gnd, 0.04 ppm of v ref / c in + = 0.25 ? ref + , in C = 0.75 ? ref + total unadjusted error 5v v cc 5.5v, ref + = 2.5v, ref C = gnd, v incm = 1.25v 0.20 lsb 5v v cc 5.5v, ref + = 5v, ref C = gnd, v incm = 2.5v 0.20 lsb ref + = 2.5v, ref C = gnd, v incm = 1.25v, (note 6) 0.25 lsb output noise 5v v cc 5.5v, ref + = 5v, ref C = gnd, 1.45 m v rms gnd in C = in + v cc , (note 12) the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (notes 3, 4, 6) ms part marking ltaey ltaez consult ltc marketing for parts specified with wider operating temperature ranges. 1 2 3 4 5 v cc ref + ref in + in 10 9 8 7 6 f o sck sdo cs gnd top view ms10 package 10-lead plastic msop absolute axi u rati gs w ww u package/order i for atio uu w electrical characteristics ltc2433-1 3 24331fa symbol parameter conditions min typ max units in + absolute/common mode in + voltage l gnd C 0.3 v cc + 0.3 v in C absolute/common mode in C voltage l gnd C 0.3 v cc + 0.3 v v in input differential voltage range l Cv ref /2 v ref /2 v (in + C in C ) ref + absolute/common mode ref + voltage l 0.1 v cc v ref C absolute/common mode ref C voltage l gnd v cc C 0.1 v v ref reference differential voltage range l 0.1 v cc v (ref + C ref C ) c s (in + )in + sampling capacitance 6 pf c s (in C )in C sampling capacitance 6 pf c s (ref + )ref + sampling capacitance 6 pf c s (ref C )ref C sampling capacitance 6 pf i dc_leak (in + )in + dc leakage current cs = v cc = 5v, in + = gnd l C100 1 100 na i dc_leak (in C )in C dc leakage current cs = v cc = 5v, in C = 5.5v l C100 1 100 na i dc_leak (ref + )ref + dc leakage current cs = v cc = 5v, ref + = 5.5v l C100 1 100 na i dc_leak (ref C )ref C dc leakage current cs = v cc = 5v, ref C = gnd l C100 1 100 na the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (notes 3, 4) parameter conditions min typ max units input common mode rejection dc 2.5v ref + v cc , ref C = gnd, l 130 140 db gnd in C = in + v cc (note 5) input common mode rejection 2.5v ref + v cc , ref C = gnd, l 140 db 49hz to 61.2hz gnd in C = in + v cc , (notes 5, 7) input normal mode rejection (note 5, 7) l 87 db 49hz to 61.2hz reference common mode 2.5v ref + v cc , gnd ref C 2.5v, l 130 140 db rejection dc v ref = 2.5v, in C = in + = gnd (note 5) power supply rejection, dc ref + = 2.5v, ref C = gnd, in C = in + = gnd 120 db power supply rejection, ref + = 2.5v, ref C = gnd, in C = in + = gnd, (note 7) 120 db simultaneous 50hz/60hz 2% co verter characteristics u u u a alog i put a d refere ce u u ltc2433-1 4 24331fa symbol parameter conditions min typ max units v cc supply voltage l 2.7 5.5 v i cc supply current conversion mode cs = 0v (note 14) l 200 300 m a sleep mode cs = v cc (notes 11, 14) l 413 m a sleep mode cs = v cc , 2.7v v cc 3.3v 2 m a (notes 11, 14) the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) symbol parameter conditions min typ max units v ih high level input voltage 2.7v v cc 5.5v l 2.5 v cs, f o 2.7v v cc 3.3v 2.0 v v il low level input voltage 4.5v v cc 5.5v l 0.8 v cs, f o 2.7v v cc 5.5v 0.6 v v ih high level input voltage 2.7v v cc 5.5v (note 8) l 2.5 v sck 2.7v v cc 3.3v (note 8) 2.0 v v il low level input voltage 4.5v v cc 5.5v (note 8) l 0.8 v sck 2.7v v cc 5.5v (note 8) 0.6 v i in digital input current 0v v in v cc l C10 10 m a cs, f o i in digital input current 0v v in v cc (note 8) l C10 10 m a sck c in digital input capacitance 10 pf cs, f o c in digital input capacitance (note 8) 10 pf sck v oh high level output voltage i o = C800 m a l v cc C 0.5 v sdo v ol low level output voltage i o = 1.6ma l 0.4 v sdo v oh high level output voltage i o = C800 m a (note 9) l v cc C 0.5 v sck v ol low level output voltage i o = 1.6ma (note 9) l 0.4 v sck i oz hi-z output leakage l C10 10 m a sdo power require e ts w u digital i puts a d digital outputs u u ltc2433-1 5 24331fa note 9: the converter is in internal sck mode of operation such that the sck pin is used as digital output. in this mode of operation the sck pin has a total equivalent load capacitance c load = 20pf. note 10: the external oscillator is connected to the f o pin. the external oscillator frequency, f eosc , is expressed in khz. note 11: the converter uses the internal oscillator. f o = 0v. note 12: 1.45 m v rms noise is independent of v ref . since the noise performance is limited by the quantization, lowering v ref improves the effective resolution. note 13: guaranteed by design and test correlation. note 14: the low sleep mode current is valid only when cs is high. note 15: these parameters are guaranteed by design over the full supply and temperature range. automated testing procedures are limited by the lsb step size (v ref /65,536). note 1: absolute maximum ratings are those values beyond which the life of the device may be impaired. note 2: all voltage values are with respect to gnd. note 3: v cc = 2.7v to 5.5v unless otherwise specified. v ref = ref + C ref C , v refcm = (ref + + ref C )/2; v in = in + C in C , v incm = (in + + in C )/2. note 4: f o pin tied to gnd or to an external conversion clock source with f eosc = 139,800hz unless otherwise specified. note 5: guaranteed by design, not subject to test. note 6: integral nonlinearity is defined as the deviation of a code from a precise analog input voltage. maximum specifications are limited by the lsb step size (v ref /2 16 ) and the single shot measurement. typical specifications are measured from the center of the quantization band. note 7: f o = gnd (internal oscillator) or f eosc = 139,800hz 2% (external oscillator). note 8: the converter is in external sck mode of operation such that the sck pin is used as digital input. the frequency of the clock signal driving sck during the data output is f esck and is expressed in khz. symbol parameter conditions min typ max units f eosc external oscillator frequency range l 2.56 2000 khz t heo external oscillator high period l 0.25 390 m s t leo external oscillator low period l 0.25 390 m s t conv conversion time f o = 0v l 143.8 146.7 149.6 ms external oscillator (note 10) l 20510/f eosc (in khz) ms f isck internal sck frequency internal oscillator (note 9) 17.5 khz external oscillator (notes 9, 10) f eosc /8 khz d isck internal sck duty cycle (note 9) l 45 55 % f esck external sck frequency range (note 8) l 2000 khz t lesck external sck low period (note 8) l 250 ns t hesck external sck high period (note 8) l 250 ns t dout_isck internal sck 19-bit data output time internal oscillator (notes 9, 11) l 1.06 1.09 1.11 ms external oscillator (notes 9, 10) l 152/f eosc (in khz) ms t dout_esck external sck 19-bit data output time (note 8) l 19/f esck (in khz) ms t 1 cs to sdo low z l 0 200 ns t2 cs - to sdo high z l 0 200 ns t3 cs to sck (note 9) l 0 200 ns t4 cs to sck - (note 8) l 50 ns t kqmax sck to sdo valid l 220 ns t kqmin sdo hold after sck (note 5) l 15 ns t 5 sck set-up before cs l 50 ns t 6 sck hold after cs l 50 ns the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) ti i g characteristics u w ltc2433-1 6 24331fa v cc (pin 1): positive supply voltage. bypass to gnd with a 10 m f tantalum capacitor in parallel with 0.1 m f ceramic capacitor as close to the part as possible. ref + (pin 2), ref C (pin 3): differential reference input. the voltage on these pins can have any value between gnd and v cc as long as the reference positive input, ref + , is maintained more positive than the reference negative input, ref C , by at least 0.1v. in + (pin 4), in C (pin 5): differential analog input. the voltage on these analog inputs can have any value between gnd and v cc . within these limits the converter bipolar input range (v in = in + C in C ) extends from C 0.5 ? (v ref ) to 0.5 ? (v ref ). outside this input range the converter produces unique overrange and underrange output codes. gnd (pin 6): ground. connect this pin to a ground plane through a low impedance connection. cs (pin 7): active low digital input. a low on this pin enables the sdo digital output and wakes up the adc. following each conversion the adc automatically enters the sleep mode and remains in this low power state as long as cs is high. a low-to-high transition on cs during the data output transfer aborts the data transfer and starts a new conversion. sdo (pin 8): three-state digital output. during the data output period, this pin is used as serial data output. when the chip select cs is high (cs = v cc ) the sdo pin is in a high impedance state. during the conversion and sleep periods, this pin is used as the conversion status output. the conversion status can be observed by pulling cs low. sck (pin 9): bidirectional digital clock pin. in internal serial clock operation mode, sck is used as digital output for the internal serial interface clock during the data output period. in external serial clock operation mode, sck is used as digital input for the external serial interface clock during the data output period. a weak internal pull- up is automatically activated in internal serial clock op- eration mode. the serial clock operation mode is deter- mined by the logic level applied to the sck pin at power up or during the most recent falling edge of cs. f o (pin 10): frequency control pin. digital input that controls the adcs notch frequencies and conversion time. when the f o pin is connected to gnd (f o = 0v), the converter uses its internal oscillator and rejects 50hz and 60hz simultaneously. when f o is driven by an external clock signal with a frequency f eosc , the converter uses this signal as its system clock and the digital filter has 87db minimum rejection in the range f eosc /2560 14% and 110db minimum rejection at f eosc /2560 4%. uu u pi fu ctio s ltc2433-1 7 24331fa figure 1. functional block diagram 1.69k sdo 24361 ta03 hi-z to v oh v ol to v oh v oh to hi-z c load = 20pf 1.69k sdo 24361 ta04 hi-z to v ol v oh to v ol v ol to hi-z c load = 20pf v cc autocalibration and control dac decimating fir internal oscillator serial interface adc gnd v cc in + in sdo sck ref + ref cs f o (int/ext) 24331 fd + fu ctio al diagra u u w test circuits ltc2433-1 8 24331fa converter operation converter operation cycle the ltc2433-1 is a low power, ds adc with differential input/reference and an easy-to-use 3-wire serial interface (see figure 1). its operation is made up of three states. the converter operating cycle begins with the conversion, followed by the low power sleep state and ends with the data output (see figure 2). the 3-wire interface consists of serial data output (sdo), serial clock (sck) and chip select (cs). initially, the ltc2433-1 performs a conversion. once the conversion is complete, the device enters the sleep state. the part remains in the sleep state as long as cs is high. while in this sleep state, power consumption is reduced by nearly two orders of magnitude. the conversion result is held indefinitely in a static shift register while the converter is in the sleep state. once cs is pulled low, the device exits the low power mode and enters the data output state. if cs is pulled high before the first rising edge of sck, the device returns to the low power sleep mode and the conversion result is still held in the internal static shift register. if cs remains low after the first rising edge of sck, the device begins outputting the conversion result. taking cs high at this point will terminate the data output state and start a new conversion. there is no latency in the conversion result. the data output corresponds to the conversion just per- formed. this result is shifted out on the serial data out pin (sdo) under the control of the serial clock (sck). data is updated on the falling edge of sck allowing the user to reliably latch data on the rising edge of sck (see figure 3). the data output state is concluded once 19 bits are read out of the adc or when cs is brought high. the device automatically initiates a new conversion and the cycle repeats. in order to maintain compatibility with 24-/32-bit data transfers, it is possible to clock the ltc2433-1 with additional serial clock pulses. this results in additional data bits which are logic high. through timing control of the cs and sck pins, the ltc2433-1 offers several flexible modes of operation (internal or external sck and free-running conversion modes). these various modes do not require program- ming configuration registers; moreover, they do not dis- turb the cyclic operation described above. these modes of operation are described in detail in the serial interface timing modes section. conversion clock a major advantage the delta-sigma converter offers over conventional type converters is an on-chip digital filter (commonly implemented as a sinc or comb filter). for high resolution, low frequency applications, this filter is typically designed to reject line frequencies of 50hz and 60hz plus their harmonics. the filter rejection perfor- mance is directly related to the accuracy of the converter system clock. the ltc2433-1 incorporates a highly accu- rate on-chip oscillator. this eliminates the need for exter- nal frequency setting components such as crystals or oscillators. clocked by the on-chip oscillator, the ltc2433-1 achieves a minimum of 87db rejection over the range 49hz to 61.2hz. ease of use the ltc2433-1 data output has no latency, filter settling delay or redundant data associated with the conversion cycle. there is a one-to-one correspondence between the conversion and the output data. therefore, multiplexing multiple analog voltages is easy. figure 2. ltc2433-1 state transition diagram convert sleep data output 24331 f02 true false cs = low and sck applicatio s i for atio wu uu ltc2433-1 9 24331fa the ltc2433-1 performs offset and full-scale calibrations every conversion cycle. this calibration is transparent to the user and has no effect on the cyclic operation de- scribed above. the advantage of continuous calibration is extreme stability of offset and full-scale readings with re- spect to time, supply voltage change and temperature drift. power-up sequence the ltc2433-1 automatically enters an internal reset state when the power supply voltage v cc drops below approxi- mately 2v. this feature guarantees the integrity of the conversion result and of the serial interface mode selec- tion. (see the 2-wire i/o sections in the serial interface timing modes section.) when the v cc voltage rises above this critical threshold, the converter creates an internal power-on-reset (por) signal with a typical duration of 1ms. the por signal clears all internal registers. following the por signal, the ltc2433-1 starts a normal conversion cycle and follows the succession of states described above. the first con- version result following por is accurate within the speci- fications of the device if the power supply voltage is restored within the operating range (2.7v to 5.5v) before the end of the por time interval. reference voltage range this converter accepts a truly differential external refer- ence voltage. the absolute/common mode voltage speci- fication for the ref + and ref C pins covers the entire range from gnd to v cc . for correct converter operation, the ref + pin must always be more positive than the ref C pin. the ltc2433-1 can accept a differential reference voltage from 0.1v to v cc . the converter output noise is deter- mined by the thermal noise of the front-end circuits, and as such, its value in microvolts is nearly constant with reference voltage. a decrease in reference voltage will significantly improve the converters effective resolution, since the thermal noise (1.45 m v) is well below the quan- tization level of the device (75.6 m v for a 5v reference). at the minimum reference (100mv) the thermal noise remains constant at 1.45 m v rms (or 8.7 m v p-p ), while the quantization is reduced to 1.5 m v per lsb. as a result, lowering the reference improves the effective resolution for low level input voltages. input voltage range the analog input is truly differential with an absolute/ common mode range for the in + and in C input pins extending from gnd C 0.3v to v cc + 0.3v. outside these limits, the esd protection devices begin to turn on and the errors due to input leakage current increase rapidly. within these limits, the ltc2433-1 converts the bipolar differen- tial input signal, v in = in + C in C , from C fs = C 0.5 ? v ref to +fs = 0.5 ? v ref where v ref = ref + C ref C . outside this range, the converter indicates the overrange or the underrange condition using distinct output codes. input signals applied to the analog input pins may extend by 300mv below ground and above v cc . in order to limit any fault current, resistors of up to 5k may be added in series with the pins without affecting the performance of the device. in the physical layout, it is important to main- tain the parasitic capacitance of the connection between these series resistors and the corresponding pins as low as possible; therefore, the resistors should be located as close as practical to the pins. the effect of the series resistance on the converter accuracy can be evaluated from the curves presented in the input current/reference current sections. in addition, series resistors will intro- duce a temperature dependent offset error due to the input leakage current. a 10na input leakage current will develop a 1lsb offset error on an 8k resistor if v ref = 5v. this error has a very strong temperature dependency. output data format the ltc2433-1 serial output data stream is 19 bits long. the first 3 bits represent status information indicating the conversion state and sign. the next 16 bits are the conver- sion result, msb first. the third and fourth bit together are also used to indicate an underrange condition (the differ- ential input voltage is below Cfs) or an overrange condi- tion (the differential input voltage is above +fs). applicatio s i for atio wu uu ltc2433-1 10 24331fa bit 18 (first output bit) is the end of conversion (eoc) indicator. this bit is available at the sdo pin during the conversion and sleep states whenever the cs pin is low. this bit is high during the conversion and goes low when the conversion is complete. bit 17 (second output bit) is a dummy bit (dmy) and is always low. bit 16 (third output bit) is the conversion result sign indi- cator (sig). if v in is >0, this bit is high. if v in is <0, this bit is low. bit 15 (fourth output bit) is the most significant bit (msb) of the result. this bit in conjunction with bit 16 also provides the underrange or overrange indication. if both bit 16 and bit 15 are high, the differential input voltage is above +fs. if both bit 16 and bit 15 are low, the differential input voltage is below Cfs. the function of these bits is summarized in table 1. table 1. ltc2433-1 status bits bit 18 bit 17 bit 16 bit 15 input range eoc dmy sig msb v in 3 0.5 ? v ref 0011 0v v in < 0.5 ? v ref 0010 C0.5 ? v ref v in < 0v 0001 v in < C 0.5 ? v ref 0000 bits 15-0 are the 16-bit conversion result msb first. bit 0 is the least significant bit (lsb). data is shifted out of the sdo pin under control of the serial clock (sck), see figure 3. whenever cs is high, sdo remains high impedance and any externally generated sck clock pulses are ignored by the internal data out shift register. in order to shift the conversion result out of the device, cs must first be driven low. eoc is seen at the sdo pin of the device once cs is pulled low. eoc changes real time from high to low at the completion of a conversion. this signal may be used as an interrupt for an external micro- controller. bit 18 (eoc) can be captured on the first rising edge of sck. bit 17 is shifted out of the device on the first falling edge of sck. the final data bit (bit 0) is shifted out on the falling edge of the 18th sck and may be latched on the rising edge of the 19th sck pulse. on the falling edge of the 19th sck pulse, sdo goes high indicating the initiation of a new conversion cycle. this bit serves as eoc (bit 18) for the next conversion cycle. table 2 summarizes the output data format. in order to remain compatible with some spi microcontrollers, more than 19 sck clock pulses may be applied. as long as these clock edges are complete before the conversion ends, they will not effect the serial data. however, switching sck during a conversion may gener- ate ground currents in the device leading to extra offset and noise error sources. as long as the voltage on the analog input pins is main- tained within the C 0.3v to (v cc + 0.3v) absolute maximum operating range, a conversion result is generated for any differential input voltage v in from Cfs = C0.5 ? v ref to +fs = 0.5 ? v ref . for differential input voltages greater than +fs, the conversion result is clamped to the value corre- sponding to the +fs + 1lsb. for differential input voltages below Cfs, the conversion result is clamped to the value corresponding to Cfs C 1lsb. figure 3. output data timing msb sig ? 1 2 3 4 5 171819 bit 0 bit 14 bit 1 lsb 16 bit 15 bit 16 bit 17 sdo sck cs eoc bit 18 sleep data output conversion 24331 f03 hi-z applicatio s i for atio wu uu ltc2433-1 11 24331fa simultaneous frequency rejection the ltc2433-1 internal oscillator provides better than 87db normal mode rejection over the range of 49hz to 61.2hz as shown in figure 4. for this simultaneous 50hz/ 60hz rejection, f o should be connected to gnd. when a fundamental rejection frequency different from the range 49hz to 61.2hz is required or when the converter must be sychronized with an outside source, the ltc2433-1 can operate with an external conversion clock. the conveter automatically detects the presence of an external clock signal at the f o pin and turns off the internal oscillator. the frequency f eosc of the external signal must be at least table 2. ltc2433-1 output data format differential input voltage bit 18 bit 17 bit 16 bit 15 bit 14 bit 13 bit 12 bit 0 v in * eoc dmy sig msb v in * 3 0.5 ? v ref ** 0 0110 0 00 0.5 ? v ref ** C 1lsb 0 0101 1 11 0.25 ? v ref ** 0 0101 0 00 0.25 ? v ref ** C 1lsb 0 0100 1 11 0 0 0100 0 00 C1lsb 0 0011 1 11 C 0.25 ? v ref ** 0 0011 0 00 C 0.25 ? v ref ** C 1lsb 0 0010 1 11 C 0.5 ? v ref ** 0 0010 0 00 v in * < C0.5 ? v ref ** 0 0001 1 11 *the differential input voltage v in = in + C in C . **the differential reference voltage v ref = ref + C ref C . figure 4. ltc2433-1 normal mode rejection when using an internal oscillator 48 50 52 54 56 58 60 62 differential input signal frequency (hz) normal mode reection ratio (db) 24361 f04 ?0 ?0 100 100 120 130 140 2560hz to be detected. the external clock signal duty cycle is not significant as long as the minimum and maximum specifications for the high and low periods, t heo and t leo , are observed. while operating with an external conversion clock of a frequency f eosc , the ltc2433-1 provides better than 110db normal mode rejection in a frequency range f eosc /2560 4%. the normal mode rejection as a function of the input frequency deviation from f eosc /2560 is shown in figure 5. whenever an external clock is not present at the f o pin the converter automatically activates its internal oscillator and enters the internal conversion clock mode. the ltc2433-1 figure 5. ltc2433-1 normal mode rejection when using an external oscillator of frequency f eosc differential input signal frequency deviation from notch frequency f eosc /2560(%) 12 8 404812 normal mode rejection (db) 24361 f05 ?0 ?5 ?0 ?5 100 105 110 115 120 125 130 135 140 applicatio s i for atio wu uu ltc2433-1 12 24331fa operation will not be disturbed if the change of conversion clock source occurs during the sleep state or during the data output state while the converter uses an external serial clock. if the change occurs during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected. if the change occurs during the data output state and the converter is in the internal sck mode, the serial clock duty cycle may be affected but the serial data stream will remain valid. table 3 summarizes the duration of each state and the achievable output data rate as a function of f o . serial interface pins the ltc2433-1 transmits the conversion results and receives the start of conversion command through a synchronous 3-wire interface. during the conversion and sleep states, this interface can be used to assess the converter status and during the data output state it is used to read the conversion result. serial clock input/output (sck) the serial clock signal present on sck (pin 9) is used to synchronize the data transfer. each bit of data is shifted out the sdo pin on the falling edge of the serial clock. in the internal sck mode of operation, the sck pin is an output and the ltc2433-1 creates its own serial clock by dividing the internal conversion clock by 8. in the external sck mode of operation, the sck pin is used as input. the internal or external sck mode is selected on power-up and then reselected every time a high-to-low transition is detected at the cs pin. if sck is high or floating at power- up or during this transition, the converter enters the inter- nal sck mode. if sck is low at power-up or during this transition, the converter enters the external sck mode. serial data output (sdo) the serial data output pin, sdo (pin 8), provides the result of the last conversion as a serial bit stream (msb first) during the data output state. in addition, the sdo pin is used as an end of conversion indicator during the conver- sion and sleep states. when cs (pin 7) is high, the sdo driver is switched to a high impedance state. this allows sharing the serial interface with other devices. if cs is low during the convert or sleep state, sdo will output eoc. if cs is low during the conversion phase, the eoc bit appears high on the sdo pin. once the conversion is complete, eoc goes low. chip select input (cs) the active low chip select, cs (pin 7), is used to test the conversion status and to enable the data output transfer as described in the previous sections. table 3. ltc2433-1 state duration state operating mode duration convert internal oscillator f o = low 147ms, output data rate 6.8 readings/s simultaneous 50hz/60hz rejection external oscillator f o = external oscillator 20510/f eosc s, output data rate f eosc /20510 readings/s with frequency f eosc khz (f eosc /2560 rejection) sleep as long as cs = high until cs = low and sck data output internal serial clock f o = low as long as cs = low but not longer than 1.09ms (internal oscillator) (19 sck cycles) f o = external oscillator with as long as cs = low but not longer than 152/f eosc ms frequency f eosc khz (19 sck cycles) external serial clock with as long as cs = low but not longer than 19/f sck ms frequency f sck khz (19 sck cycles) applicatio s i for atio wu uu ltc2433-1 13 24331fa in addition, the cs signal can be used to trigger a new conversion cycle before the entire serial data transfer has been completed. the ltc2433-1 will abort any serial data transfer in progress and start a new conversion cycle anytime a low-to-high transition is detected at the cs pin after the converter has entered the data output state (i.e., after the first rising edge of sck occurs with cs=low). finally, cs can be used to control the free-running modes of operation, see serial interface timing modes section. grounding cs will force the adc to continuously convert at the maximum output rate selected by f o . serial interface timing modes the ltc2433-1s 3-wire interface is spi and microwire compatible. this interface offers several flexible modes of operation. these include internal/external serial clock, 2- or 3-wire i/o, single cycle conversion and autostart. the following sections describe each of these serial interface timing modes in detail. in all these cases, the converter can use the internal oscillator (f o = low) or an external oscillator connected to the f o pin. refer to table 4 for a summary. external serial clock, single cycle operation (spi/microwire compatible) this timing mode uses an external serial clock to shift out the conversion result and a cs signal to monitor and control the state of the conversion cycle, see figure 6. the serial clock mode is selected on the falling edge of cs. to select the external serial clock mode, the serial clock pin (sck) must be low during each cs falling edge. figure 6. external serial clock, single cycle operation table 4. ltc2433-1 interface timing modes conversion data connection sck cycle output and configuration source control control waveforms external sck, single cycle conversion external cs and sck cs and sck figures 6, 7 external sck, 2-wire i/o external sck sck figure 8 internal sck, single cycle conversion internal cs cs figures 9, 10 internal sck, 2-wire i/o, continuous conversion internal continuous internal figure 11 eoc bit 18 sdo sck (external) cs test eoc msb sig ? bit 0 lsb bit 2 bit 1 bit 14 bit 13 bit 15 bit 16 bit 17 sleep sleep test eoc (optional) data output conversion 24331 f06 conversion hi-z hi-z hi-z test eoc = external clock source = internal osc/simultaneous 50hz/60hz rejection v cc f o ref + ref sck in + in sdo gnd cs 110 2 3 9 4 5 8 6 7 reference voltage 0.1v to v cc analog input range 0.5v ref to 0.5v ref 1 f 2.7v to 5.5v ltc2433-1 3-wire spi interface applicatio s i for atio wu uu ltc2433-1 14 24331fa the serial data output pin (sdo) is hi-z as long as cs is high. at any time during the conversion cycle, cs may be pulled low in order to monitor the state of the converter. while cs is pulled low, eoc is output to the sdo pin. eoc = 1 while a conversion is in progress and eoc = 0 if the device is in the sleep state. with cs high, the device automatically enters the low power sleep state once the conversion is complete. when the device is in the sleep state (eoc = 0), its conversion result is held in an internal static shift regis- ter. data is shifted out the sdo pin on each falling edge of sck. this enables external circuitry to latch the output on the rising edge of sck. eoc can be latched on the first rising edge of sck and the last bit of the conversion result can be latched on the 19th rising edge of sck. on the 19th falling edge of sck, the device begins a new conversion. sdo goes high (eoc = 1) indicating a conversion is in progress. at the conclusion of the data cycle, cs may remain low and eoc monitored as an end-of-conversion interrupt. alternatively, cs may be driven high setting sdo to hi-z. as described above, cs may be pulled low at any time in order to monitor the conversion status. typically, cs remains low during the data output state. however, the data output state may be aborted by pulling cs high anytime between the first rising edge and the 19th falling edge of sck, see figure 7. on the rising edge of cs, the device aborts the data output state and imme- diately initiates a new conversion. this is useful for abort- ing an invalid conversion cycle or synchronizing the start of a conversion. figure 7. external serial clock, reduced data output length sdo sck (external) cs data output conversion sleep sleep test eoc (optional) test eoc data output hi-z hi-z hi-z conversion 24331 f07 msb sig ? bit 4 bit 14 bit 5 bit 15 bit 16 bit 17 eoc bit 18 bit 0 eoc hi-z test eoc sleep = external clock source = internal osc/simultaneous 50hz/60hz rejection v cc f o ref + ref sck in + in sdo gnd cs 110 2 3 9 4 5 8 6 7 reference voltage 0.1v to v cc analog input range 0.5v ref to 0.5v ref 1 f 2.7v to 5.5v ltc2433-1 3-wire spi interface applicatio s i for atio wu uu ltc2433-1 15 24331fa figure 8. external serial clock, cs = 0 operation (2-wire) external serial clock, 2-wire i/o this timing mode utilizes a 2-wire serial i/o interface. the conversion result is shifted out of the device by an exter- nally generated serial clock (sck) signal, see figure 8. cs may be permanently tied to ground, simplifying the user interface or isolation barrier. the external serial clock mode is selected at the end of the power-on reset (por) cycle. the por cycle is concluded typically 1ms after v cc exceeds 2v. the level applied to sck at this time determines if sck is internal or external. sck must be driven low prior to the end of por in order to enter the external serial clock timing mode. since cs is tied low, the end-of-conversion (eoc) can be continuously monitored at the sdo pin during the convert and sleep states. eoc may be used as an interrupt to an external controller indicating the conversion result is ready. eoc = 1 while the conversion is in progress and eoc = 0 once the conversion ends. on the falling edge of eoc, the conversion result is loaded into an internal static shift reg- ister. data is shifted out the sdo pin on each falling edge of sck enabling external circuitry to latch data on the ris- ing edge of sck. eoc can be latched on the first rising edge of sck. on the 19th falling edge of sck, sdo goes high (eoc = 1) indicating a new conversion has begun. internal serial clock, single cycle operation this timing mode uses an internal serial clock to shift out the conversion result and a cs signal to monitor and control the state of the conversion cycle, see figure 9. in order to select the internal serial clock timing mode, the serial clock pin (sck) must be floating (hi-z) or pulled high prior to the falling edge of cs. the device will not enter the internal serial clock mode if sck is driven low on the falling edge of cs. an internal weak pull-up resistor is active on the sck pin during the falling edge of cs; therefore, the internal serial clock timing mode is auto- matically selected if sck is not externally driven. the serial data output pin (sdo) is hi-z as long as cs is high. at any time during the conversion cycle, cs may be pulled low in order to monitor the state of the converter. once cs is pulled low, sck goes low and eoc is output to the sdo pin. eoc = 1 while a conversion is in progress and eoc = 0 if the device is in the sleep state. when testing eoc, if the conversion is complete (eoc = 0), the device will exit the sleep state during the eoc test. in order to allow the device to return to the low power sleep state, cs must be pulled high before the first rising edge of sck. in the internal sck timing mode, sck goes high eoc bit 18 sdo sck (external) cs msb sig ? bit 0 lsb bit 2 bit 1 bit 14 bit 13 bit 15 bit 16 bit 17 data output conversion 24331 f08 conversion = external clock source = internal osc/simultaneous 50hz/60hz rejection v cc f o ref + ref sck in + in sdo gnd cs 110 2 3 9 4 5 8 6 7 reference voltage 0.1v to v cc analog input range 0.5v ref to 0.5v ref 1 f 2.7v to 5.5v ltc2433-1 3-wire spi interface applicatio s i for atio wu uu ltc2433-1 16 24331fa and the device begins outputting data at time t eoctest after the falling edge of cs (if eoc = 0) or t eoctest after eoc goes low (if cs is low during the falling edge of eoc). the value of t eoctest is 23 m s if the device is using its internal oscillator (f 0 = logic low). if f o is driven by an external oscillator of frequency f eosc , then t eoctest is 3.6/f eosc . if cs is pulled high before time t eoctest , the device returns to the sleep state and the conversion result is held in the internal static shift register. if cs remains low longer than t eoctest , the first rising edge of sck will occur and the conversion result is serially shifted out of the sdo pin. the data output cycle concludes after the 19th rising edge. data is shifted out the sdo pin on each falling edge of sck. the internally generated serial clock is output to the sck pin. this signal may be used to shift the conversion result into external circuitry. eoc can be latched on the first rising edge of sck and the last bit of the conversion result on the 19th rising edge of sck. after the 19th rising edge, sdo goes high (eoc = 1), sck stays high and a new conversion starts. typically, cs remains low during the data output state. however, the data output state may be aborted by pulling cs high anytime between the first and 19th rising edge of sck, see figure 10. on the rising edge of cs, the device aborts the data output state and immediately initiates a new conversion. this is useful for aborting an invalid conversion cycle, or synchronizing the start of a conver- sion. if cs is pulled high while the converter is driving sck low, the internal pull-up is not available to restore sck to a logic high state. this will cause the device to exit the internal serial clock mode on the next falling edge of cs. this can be avoided by adding an external 10k pull-up resistor to the sck pin or by never pulling cs high when sck is low. whenever sck is low, the ltc2433-1s internal pull-up at pin sck is disabled. normally, sck is not externally driven if the device is in the internal sck timing mode. however, certain applications may require an external driver on sck. if this driver goes hi-z after outputting a low signal, the ltc2433-1s internal pull-up remains figure 9. internal serial clock, single cycle operation sdo sck (internal) cs msb sig ? bit 0 lsb bit 2 bit 1 test eoc bit 14 bit 13 bit 15 bit 16 bit 17 eoc bit 18 sleep data output conversion conversion 24331 f09 ltc2433-1 19 24331fa during the conversion period, the undershoot and/or overshoot of a fast digital signal connected to the ltc2433-1 pins may severely disturb the analog to digital conversion process. undershoot and overshoot can oc- cur because of the impedance mismatch at the converter pin when the transition time of an external control signal is less than twice the propagation delay from the driver to ltc2433-1. for reference, on a regular fr-4 board, signal propagation velocity is approximately 183ps/inch for internal traces and 170ps/inch for surface traces. thus, a driver generating a control signal with a minimum transi- tion time of 1ns must be connected to the converter pin through a trace shorter than 2.5 inches. this problem becomes particularly difficult when shared control lines are used and multiple reflections may occur. the solution is to carefully terminate all transmission lines close to their characteristic impedance. parallel termination near the ltc2433-1 pin will eliminate this problem but will increase the driver power dissipation. a series resistor between 27 w and 56 w placed near the driver will also eliminate this problem without additional power dissipation. the actual resistor value depends upon the trace impedance and connection topology. an alternate solution is to reduce the edge rate of the control signals. it should be noted that using very slow edges will increase the converter power supply current during the transition time. the multiple ground pins used in this package configuration, as well as the differential input and reference architecture, reduce substantially the converters sensitivity to ground currents. particular attention must be given to the connection of the f o signal when the ltc2433-1 is used with an external conversion clock. this clock is active during the conver- sion time and the normal mode rejection provided by the internal digital filter is not very high at this frequency. a normal mode signal of this frequency at the converter reference terminals may result in dc gain and inl errors. a normal mode signal of this frequency at the converter input terminals may result in a dc offset error. such perturbations may occur due to asymmetric capacitive coupling between the f o signal trace and the converter input and/or reference connection traces. an immediate solution is to maintain maximum possible separation between the f o signal trace and the input/reference sig- nals. when the f o signal is parallel terminated near the converter, substantial ac current is flowing in the loop formed by the f o connection trace, the termination and the ground return path. thus, perturbation signals may be inductively coupled into the converter input and/or refer- ence. in this situation, the user must reduce to a minimum the loop area for the f o signal as well as the loop area for the differential input and reference connections. driving the input and reference the input and reference pins of the ltc2433-1 converter are directly connected to a network of sampling capaci- tors. depending upon the relation between the differential input voltage and the differential reference voltage, these capacitors are switching between these four pins transfering small amounts of charge in the process. a simplified equivalent circuit is shown in figure 12, where in + and in C refer to the selected differential channel and the unselected channel is omitted for simplicity. for a simple approximation, the source impedance r s driving an analog input pin (in + , in C , ref + or ref C ) can be considered to form, together with r sw and c eq (see figure 12), a first order passive network with a time constant t = (r s + r sw ) ? c eq . the converter is able to sample the input signal with better than 1lsb accuracy if the sampling period is at least 11 times greater than the input circuit time constant t . the sampling process on the four input analog pins is quasi-independent so each time constant should be considered by itself and, under worst- case circumstances, the errors may add. when using the internal oscillator (f o = low), the ltc2433-1s front-end switched-capacitor network is clocked at 69900hz corresponding to a 14.3 m s sampling applicatio s i for atio wu uu ltc2433-1 20 24331fa period. thus, for settling errors of less than 1lsb, the driving source impedance should be chosen such that t 14.3 m s/11 = 1.3 m s. when an external oscillator of fre- quency f eosc is used, the sampling period is 2/f eosc and, for a settling error of less than 1lsb, t 0.18/f eosc . input current if complete settling occurs on the input, conversion re- sults will be unaffected by the dynamic input current. an incomplete settling of the input signal sampling process may result in gain and offset errors, but it will not degrade the inl performance of the converter. figure 12 shows the mathematical expressions for the average bias currents flowing through the in + and in C pins as a result of the sampling charge transfers when integrated over a sub- stantial time period (longer than 64 internal clock cycles). the effect of this input dynamic current can be analyzed using the test circuit of figure 13. the c par capacitor includes the ltc2433-1 pin capacitance (5pf typical) plus the capacitance of the test fixture used to obtain the results shown in figures 14 and 15. a careful implementation can bring the total input capacitance (c in + c par ) closer to 5pf thus achieving better performance than the one predicted figure 13. an rc network at in + and in C figure 14. +fs error vs r source at in + or in C (small c in ) c in 24331 f13 v incm + 0.5v in r source in + ltc2433-1 c par @ 20pf c in v incm ?0.5v in r source in c par @ 20pf figure 12. ltc2433-1 equivalent analog input circuit v ref + v in + v cc r sw (typ) 20k i leak i leak v cc i leak i leak v cc r sw (typ) 20k c eq 6pf (typ) r sw (typ) 20k i leak i in + v in i in i ref + i ref 24331 f12 i leak v cc i leak i leak switching frequency f sw = 69900hz internal oscillator (f o = low) f sw = 0.5 ?f eosc external oscillator v ref r sw (typ) 20k iin vv v r iin vv v r i ref vv v r v vr i ref vv v r v vr where avg in incm refcm eq avg in incm refcm eq avg ref incm refcm eq in ref eq avg ref incm refcm eq in ref eq + - + - () = +- () = -+ - () = - + - () = - - + + 05 05 15 05 15 05 2 2 . . . . . . :: ./ ./ v ref ref v ref ref vinin v in in r m internal oscillator hz hz notch f low r f external oscillator ref refcm in incm eq o eq eosc =- = + ? ? ? ? =- = - ? ? ? ? == () = () +- +- +- +- 2 2 11 9 50 60 167 10 12 w r source ( ) 1 10 100 1k 10k 100k +fs error (lsb) 24331 f14 3 2 1 0 v cc = 5v ref + = 5v ref = gnd in + = 5v in = 2.5v f o = gnd t a = 25 c c in = 0.01 f c in = 0.001 f c in = 100pf c in = 0pf applicatio s i for atio wu uu ltc2433-1 21 24331fa by figures 14 and 15. for simplicity, two distinct situa- tions can be considered. for relatively small values of input capacitance (c in < 0.01 m f), the voltage on the sampling capacitor settles almost completely and relatively large values for the source impedance result in only small errors. such values for c in will deteriorate the converter offset and gain performance without significant benefits of signal filtering and the user is advised to avoid them. nevertheless, when small values of c in are unavoidably present as parasitics of input multiplexers, wires, connectors or sensors, the ltc2433-1 can maintain its accuracy while operating with relative large values of source resistance as shown in figure 16. +fs error vs r source at in + or in C (large c in ) figure 17. Cfs error vs r source at in + or in C (large c in ) r source ( ) 0 100 200 300 400 500 600 700 800 900 1000 +fs error (lsb) 24331 f16 8 4 0 v cc = 5v ref + = 5v ref = gnd in + = 3.75v in = 1.25v f o = gnd t a = 25 c c in = 1 f c in = 0.1 f c in = 0.01 f c in = 10 f r source ( ) 0 100 200 300 400 500 600 700 800 900 1000 fs error (ppm of v ref ) 24331 f17 ? ? 0 c in = 0.1 f c in = 0.01 f c in = 10 f v cc = 5v ref + = 5v ref = gnd in + = 1.25v in = 3.75v f o = gnd t a = 25 c c in = 1 f figure 15. Cfs error vs r source at in + or in C (small c in ) r source ( ) 1 10 100 1k 10k 100k fs error (lsb) 24331 f15 0 ? ? ? v cc = 5v ref + = 5v ref = gnd in + = gnd in = 2.5v f o = gnd t a = 25 c c in = 0pf c in = 0.001 f c in = 100pf c in = 0.01 f figures 14 and 15. these measured results may be slightly different from the first order approximation suggested earlier because they include the effect of the actual second order input network together with the nonlinear settling process of the input amplifiers. for small c in values, the settling on in + and in C occurs almost independently and there is little benefit in trying to match the source imped- ance for the two pins. larger values of input capacitors (c in > 0.01 m f) may be required in certain configurations for antialiasing or gen- eral input signal filtering. such capacitors will average the input sampling charge and the external source resistance will see a quasi constant input differential impedance. when f o = low (internal oscillator and 50hz/60hz notch), the typical differential input resistance is 6m w which will generate a gain error of approximately 1lsb at full scale for each 180 w of source resistance driving in + or in C . when f o is driven by an external oscillator with a fre- quency f eosc (external conversion clock operation), the typical differential input resistance is 0.84 ? 10 12 /f eosc w and each ohm of source resistance driving in + or in C will result in 3.7 ? 10 C8 ? f eosc lsb gain error at full scale. the effect of the source resistance on the two input pins is additive with respect to this gain error. the typical +fs and Cfs errors as a function of the sum of the source resis- tance seen by in + and in C for large values of c in are shown in figures 16 and 17. applicatio s i for atio wu uu ltc2433-1 22 24331fa in addition to this gain error, an offset error term may also appear. the offset error is proportional with the mismatch between the source impedance driving the two input pins in + and in C and with the difference between the input and reference common mode voltages. while the input drive circuit nonzero source impedance combined with the con- verter average input current will not degrade the inl performance, indirect distortion may result from the modu- lation of the offset error by the common mode component of the input signal. thus, when using large c in capacitor values, it is advisable to carefully match the source imped- ance seen by the in + and in C pins. when f o = low (internal oscillator and 50hz/60hz notch), every 180 w mismatch in source impedance transforms a full-scale common mode input signal into a differential mode input signal of 1lsb. when f o is driven by an external oscillator with a frequency f eosc , every 1 w mismatch in source impedance transforms a full-scale common mode input signal into a differential mode input signal of 3.7 ? 10 C8 ? f eosc lsb. figure 18 shows the typical offset error due to input common mode voltage for various values of source resistance imbalance between the in + and in C pins when large c in values are used. if possible, it is desirable to operate with the input signal common mode voltage very close to the reference signal common mode voltage as is the case in the ratiometric measurement of a symmetric bridge. this configuration eliminates the offset error caused by mismatched source impedances. the magnitude of the dynamic input current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. the accuracy of the internal clock over the entire temperature and power supply range is typically better than 0.5%. such a specification can also be easily achieved by an external clock. when relatively stable resistors (50ppm/ c) are used for the external source impedance seen by in + and in C , the expected drift of the dynamic current, offset and gain errors will be insignificant (about 1% of their respec- tive values over the entire temperature and voltage range). even for the most stringent applications, a one-time calibration operation may be sufficient. in addition to the input sampling charge, the input esd protection diodes have a temperature dependent leakage current. this current, nominally 1na ( 10na max), results in a small offset shift. a 15k source resistance will create a 0lsb typical and 1lsb maximum offset voltage. reference current in a similar fashion, the ltc2433-1 samples the differen- tial reference pins ref + and ref C transfering small amount of charge to and from the external driving circuits thus producing a dynamic reference current. this current does not change the converter offset, but it may degrade the gain and inl performance. the effect of this current can be analyzed in the same two distinct situations. for relatively small values of the external reference capaci- tors (c ref < 0.01 m f), the voltage on the sampling capacitor settles almost completely and relatively large values for the source impedance result in only small errors. such values for c ref will deteriorate the converter offset and gain performance without significant benefits of reference filtering and the user is advised to avoid them. figure 18. offset error vs common mode voltage (v incm = in + = in C ) and input source resistance imbalance ( d r in = r sourcein + C r sourcein C) for large c in values (c in 3 1 m f) v incm (v) 0 offset error (lsb) 3 2 1 0 ? ? ? 4 24331 f18 1 c d f 0.5 2 1.5 3 3.5 4.5 2.5 5 f o = gnd t a = 25 c r sourcein ?= 500 c in = 10 f v cc = 5v ref + = 5v ref = gnd in + = in = v incm a: ? r in = +400 b: ? r in = +200 c: ? r in = +100 d: ? r in = 0 e: ? r in = 100 f: ? r in = 200 g: ? r in = 400 e b a g applicatio s i for atio wu uu ltc2433-1 23 24331fa larger values of reference capacitors (c ref > 0.01 m f) may be required as reference filters in certain configurations. such capacitors will average the reference sampling charge and the external source resistance will see a quasi con- stant reference differential impedance. when f o = low (internal oscillator and 50hz/60hz notch), the typical differential reference resistance is 4.2m w which will gen- erate a gain error of approximately 1lsb full scale for each 120 w of source resistance driving ref + or ref C . when f o is driven by an external oscillator with a frequency f eosc (external conversion clock operation), the typical differen- tial reference resistance is 0.60 ? 10 12 /f eosc w and each ohm of source resistance drving ref + or ref C will result in 5.1 ? 10 C8 ? f eosc lsb gain error at full scale. the effect figure 19. +fs error vs r source at ref + or ref C (small c in ) figure 20. Cfs error vs r source at ref + or ref C (small c in ) figure 21. +fs error vs r source at ref + and ref C (large c ref ) figure 22. Cfs error vs r source at ref + and ref C (large c ref ) r source ( ) 1 10 100 1k 10k 100k +fs error (lsb) 24331 f19 0 ? ? ? v cc = 5v ref + = 5v ref = gnd in + = 3.75v in = 1.25v f o = gnd t a = 25 c c ref = 0.01 f c ref = 0.001 f c ref = 100pf c ref = 0pf r source ( ) 1 10 100 1k 10k 100k fs error (lsb) 24331 f20 3 2 1 0 c ref = 0.01 f c ref = 0.001 f c ref = 100pf c ref = 0pf v cc = 5v ref + = 5v ref = gnd in + = 1.25v in = 3.75v f o = gnd t a = 25 c r source ( ) 0 +fs error (lsb) 0 ? ?0 800 24331 f21 200 400 600 1000 700 100 300 500 900 v cc = 5v ref + = 5v ref = gnd in + = 3.75v in = 1.25v f o = gnd t a = 25 c c ref = 0.01 f c ref = 1 f c ref = 0.1 f c ref = 10 f r source ( ) 0 fs error (lsb) 10 5 0 800 24331 f22 200 400 600 1000 700 100 300 500 900 v cc = 5v ref + = 5v ref = gnd in + = 1.25v in = 3.75v f o = gnd t a = 25 c c ref = 0.01 f c ref = 1 f c ref = 0.1 f c ref = 10 f of the source resistance on the two reference pins is additive with respect to this gain error. the typical +fs and Cfs errors for various combinations of source resistance seen by the ref + and ref C pins and external capacitance c ref connected to these pins are shown in figures 19, 20, 21 and 22. in addition to this gain error, the converter inl perfor- mance is degraded by the reference source impedance. when f o = low (internal oscillator and 50hz/60hz notch), every 1000 w of source resistance driving ref + or ref C translates into about 1lsb additional inl error. when f o is driven by an external oscillator with a frequency f eosc , every 1000 w of source resistance driving ref + or ref C applicatio s i for atio wu uu ltc2433-1 24 24331fa translates into about 7.15 ? 10 C6 ? f eosc lsb additional inl error. figure 23 shows the typical inl error due to the source resistance driving the ref + or ref C pins when large c ref values are used. the effect of the source resistance on the two reference pins is additive with respect to this inl error. in general, matching of source impedance for the ref + and ref C pins does not help the gain or the inl error. the user is thus advised to minimize the combined source impedance driving the ref + and ref C pins rather than to try to match it. the magnitude of the dynamic reference current depends upon the size of the very stable internal sampling capaci- tors and upon the accuracy of the converter sampling clock. the accuracy of the internal clock over the entire temperature and power supply range is typical better than 0.5%. such a specification can also be easily achieved by an external clock. when relatively stable resistors (50ppm/ c) are used for the external source impedance seen by ref + and ref C , the expected drift of the dynamic current gain error will be insignificant (about 1% of its value over the entire temperature and voltage range). even for the most stringent applications a one-time calibration operation may be sufficient. in addition to the reference sampling charge, the reference pins esd protection diodes have a temperature dependent leakage current. this leakage current, nominally 1na ( 10na max), results in a small gain error. a 100 w source resistance will create a 0.05 m v typical and 0.5 m v maxi- mum full-scale error. output data rate when using its internal oscillator, the ltc2433-1 can produce up to 6.8 readings per second. the actual output data rate will depend upon the length of the sleep and data output phases which are controlled by the user and which can be made insignificantly short. when operated with an external conversion clock (f o connected to an external oscillator), the ltc2433-1 output data rate can be in- creased as desired. the duration of the conversion phase is 20510/f eosc . if f eosc = 139,800hz, the converter be- haves as if the internal oscillator is used with simultaneous 50hz/60hz. there is no significant difference in the ltc2433-1 performance between these two operation modes. an increase in f eosc over the nominal 139,800hz will translate into a proportional increase in the maximum output data rate. this substantial advantage is neverthe- less accompanied by three potential effects, which must be carefully considered. first, a change in f eosc will result in a proportional change in the internal notch position and in a reduction of the converter differential mode rejection at the power line frequency. in many applications, the subsequent perfor- mance degradation can be substantially reduced by rely- ing upon the ltc2433-1s exceptional common mode rejection and by carefully eliminating common mode to differential mode conversion sources in the input circuit. the user should avoid single-ended input filters and should maintain a very high degree of matching and symmetry in the circuits driving the in + and in C pins. second, the increase in clock frequency will increase proportionally the amount of sampling charge transferred through the input and the reference pins. if large external figure 23. inl vs differential input voltage (v in = in + C in C ) and reference source resistance (r source at ref + and ref C for large c ref values (c ref 3 1 m f) v indif /v refdif ?.5 0.4 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5 inl (lsb) 1 0 ? v cc = 5v ref+ = 5v ref?= gnd v incm = 0.5 ?(in + + in ) = 2.5v f o = gnd c ref = 10 f t a = 25 c r source = 1000 24331 f23 applicatio s i for atio wu uu ltc2433-1 25 24331fa figure 24. offset error vs output data rate and temperature figure 25. +fs error vs output data rate and temperature figure 26. Cfs error vs output data rate and temperature figure 27. noise histogram (output rate = 100hz, v cc = 5v, v ref = 100mv, 125 c) output data rate (readings/sec) 0 offset error (lsb) ? 0 60 70 80 90 24331 f24 10 20 30 40 50 100 8 v cc = 5v v ref = 5v v incm = 2.5v v in = 0v f o = ext osc t a = 85 c t a = 25 c output data rate (readings/sec) ? +fs error (lsb) 3 9 15 0 6 12 20 40 60 80 24331 f25 100 10 030507090 t a = 85 c v cc = 5v v ref = 5v in + = 3.75v in = 1.25v f o = ext osc t a = 25 c output data rate (readings/sec) 0 fs error (lsb) 0 3 6 40 24331 f26 ? ? ? 10 20 30 50 60 70 80 90 100 t a = 85 c v cc = 5v v ref = 5v in + = 1.25v in = 3.75v f o = ext osc t a = 25 c input and/or reference capacitors (c in , c ref ) are used, the previous section provides formulae for evaluating the effect of the source resistance upon the converter perfor- mance for any value of f eosc . if small external input and/ or reference capacitors (c in , c ref ) are used, the effect of the external source resistance upon the ltc2433-1 typical performance can be inferred from figures 14, 15, 19 and 20 in which the horizontal axis is scaled by 139,800/f eosc . third, an increase in the frequency of the external oscilla- tor above 460800hz (a more than 3 increase in the output data rate) will start to decrease the effectiveness of the internal autocalibration circuits. this will result in a pro- gressive degradation in the converter accuracy and linear- ity. typical measured performance curves for output data rates up to 100 readings per second are shown in fig- ures 24, 25, 26, 27, 28 and 29. in order to obtain the applicatio s i for atio wu uu output code ? number of readings (%) 50 40 30 20 10 0 1 3 4 2433 f27 0 2 5 v cc = 5v v ref = 0.1v v in = 0v ref + = 0.1v ref = gnd in + = gnd in = gnd f o = 2.048mhz t a = 125 c gaussian distribution m = 3.1 v s = 1.59 v rms ltc2433-1 26 24331fa figure 28. integral nonlinearity vs output data rate figure 29. offset error vs output data rate and reference voltage output data rate (readings/sec) ? offset error (lsb) 3 ? ? 0 20 40 60 80 24331 f29 100 10 030507090 v cc = 5v ref = gnd v incm = 2.5v v in = 0v f o = ext osc t a = 25 c v ref = 2.5v v ref = 5v highest possible level of accuracy from this converter at output data rates above 20 readings per second, the user is advised to maximize the power supply voltage used and to limit the maximum ambient operating temperature. in certain circumstances, a reduction of the differential refer- ence voltage may be beneficial. increasing input resolution by reducing reference voltage the resolution of the ltc2433-1 can be increased by reducing the reference voltage. it is often necessary to amplify low level signals to increase the voltage resolution of adcs that cannot operate with a low reference voltage. the ltc2433-1 can be used with reference voltages as low as 100mv, corresponding to a 50mv input range with full 16-bit resolution. reducing the reference voltage is func- tionally equivalent to amplifying the input signal, however no amplifier is required. the ltc2433-1 has a 76 m v lsb when used with a 5v reference, however the thermal noise of the inputs is 1.45 m v rms and is independent of reference voltage. thus reducing the reference voltage will increase the resolution at the inputs as long as the lsb voltage is significantly larger than 1.45 m v rms . a 570mv reference corresponds to a 8.7 m v lsb, which is approximately the peak-to-peak value of the 1.45 m v rms input thermal noise. at this point, the output code will be stable to 1lsb for a fixed input. as the reference is decreased further, the measured noise will approach 1.45 m v rms . figure 30 shows two methods of dividing down the reference voltage to the ltc2433-1. where absolute accu- racy is required, a precision divider such as the vishay mpm series dividers in a sot-23 package may be used. a 51:1 divider provides a 98mv reference to the ltc2433-1 from a 5v source. the resulting 49mv input range and 1.5 m v lsb is suitable for thermocouple and 10mv full- scale strain gauge measurements. if high initial accuracy is not critical, a standard 2% resistor array such as the panasonic exb series may be used. single package resistor arrays provide better tem- perature stability than discrete resistors. an array of eight resistors can be configured as shown to provide a 294mv reference to the ltc2433-1 from a 5v source. the fully differential property of the ltc2433-1 reference terminals allow the reference voltage to be taken from four central resistors in the network connected in parallel, minimizing drift in the presence of thermal gradients. this is an ideal reference for medium accuracy sensors such as silicon micromachined pressure and force sensors. these de- vices typically have accuracies on the order of 2% and full- scale outputs of 50mv to 200mv. applicatio s i for atio wu uu output data rate (readings/sec) 01030507090 resolution (bits) 22 20 18 16 14 12 10 20 40 60 80 2433 f28 100 v cc = 5v v ref + = 5v v ref = gnd v incm = 2.5v ?.5v < v in < 2.5v f o = external oscillator ltc2433-1 27 24331fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. u package descriptio msop (ms) 0802 0.53 0.01 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 0.27 (.007 ?.011) typ 0.13 0.076 (.005 .003) 0.86 (.034) ref 0.50 (.0197) bsc 12 3 45 4.90 0.15 (1.93 .006) 0.497 0.076 (.0196 .003) ref 8 9 10 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) note 4 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ?6 typ detail ? detail ? gauge plane 5.23 (.206) min 3.2 ?3.45 (.126 ?.136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc ms package 10-lead plastic msop (reference ltc dwg # 05-08-1661) ltc2433-1 28 24331fa part number description comments lt1019 precision bandgap reference, 2.5v, 5v 3ppm/ c drift, 0.05% max ltc1043 dual precision instrumentation switched capacitor precise charge, balanced switching, low power building block ltc1050 precision chopper stabilized op amp no external components 5 m v offset, 1.6 m v p-p noise lt1236a-5 precision bandgap reference, 5v 0.05% max, 5ppm/ c drift lt1461 micropower precision ldo reference high accuracy 0.04% max, 3ppm/ c max drift ltc2400 24-bit, no latency ds adc in so-8 0.3ppm noise, 4ppm inl, 10ppm total unadjusted error, 200 m a ltc2401/ltc2402 1-/2-channel, 24-bit, no latency ds adc in msop 0.6ppm noise, 4ppm inl, 10ppm total unadjusted error, 200 m a ltc2404/ltc2408 4-/8-channel, 24-bit, no latency ds adc 0.3ppm noise, 4ppm inl, 10ppm total unadjusted error, 200 m a ltc2410 24-bit, fully differential, no latency ds adc 0.16ppm noise, 2ppm inl, 3ppm total unadjusted error, 200 m a ltc2411 24-bit, no latency ds adc in msop 1.45 m v rms noise, 2ppm inl, pin compatible with ltc2433-1 ltc2412 2-channel, 24-bit, pin compatible with ltc2436-1 800nv noise, 2ppm inl, 3ppm tue, 200 m a ltc2413 24-bit, no latency ds adc simultaneous 50hz/60hz rejection, 800nv rms noise ltc2414/ltc2418 8-/16-channel, 24-bit no latency ds adc 0.2ppm noise, 2ppm inl, 3ppm total unadjusted error, 200 m a ltc2415 24-bit, no latency ds adc with 15hz output rate pin compatible with the ltc2410 ltc2420 20-bit, no latency ds adc in so-8 1.2ppm noise, 8ppm inl, pin compatible with ltc2400 ltc2424/ltc2428 4-/8-channel, 20-bit, no latency ds adcs 1.2ppm noise, 8ppm inl, pin compatible with ltc2404/ltc2408 ltc2431 20-bit, differential no latency ds adc pin compatible with ltc2433-1 ltc2436-1 low cost 16-bit ds adc 800nv rms noise 2-channel ping-pong ltc2440 high speed, low noise 24-bit adc 4khz output rate, 200 m v noise, 24.6 enobs linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com ? linear technology corporation 2003 lt/tp 0104 1k rev a ? printed in usa related parts figure 30. increased resolution bridge/temperature measurement v cc ref + f o in + in sck sdo gnd cs 110 4.7 f 4 9 5 honeywell fsl05n2c 500 gram force sensor 8 6 7 24331 f30 2 ref 3 5v 5v ltc2433-1 0.1 f ref + 5v v ref = 294mv 147mv input range 4.5 v lsb v ref = 95.04mv 49mv input range 1.5 v lsb panasonic exb-2hv202g vishay mpm1001/5002b 8 2k array ref ref + ref 5v 50k 1k u typical applicatio |
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