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final publication# 18879 rev: c amendment/ +2 issue date: may 1998 am28f256a 256 kilobit (32 k x 8-bit) cmos 12.0 volt, bulk erase flash memory with embedded algorithms distinctive characteristics n high performance access times as fast as 70 ns n cmos low power consumption 30 ma maximum active current 100 a maximum standby current no data retention power consumption n compatible with jedec-standard byte-wide 32-pin eprom pinouts 32-pin pdip 32-pin plcc 32-pin tsop n 100,000 write/erase cycles minimum n write and erase voltage 12.0 v 5% n latch-up protected to 100 ma from C1 v to v cc +1 v n embedded erase electrical bulk chip-erase 1.5 seconds typical chip-erase including pre-programming n embedded program 14 s typical byte-program including time-out 0.5 second typical chip program n command register architecture for microprocessor/microcontroller compatible write interface n on-chip address and data latches n advanced cmos flash memory technology low cost single transistor memory cell n embedded algorithms for completely self-timed write/erase operations general description the am28f256a is a 256 k flash memory organized as 32 kbytes of 8 bits each. amds flash memories offer the most cost-effective and reliable read/write non- volatile random access memory. the am28f256a is packaged in 32-pin pdip, plcc, and tsop versions. it is designed to be reprogrammed and erased in-sys- tem or in standard eprom programmers. the am28f256a is erased when shipped from the factory. the standard am28f256a offers access times as fast as 70 ns, allowing operation of high-speed micropro- cessors without wait states. to eliminate bus conten- tion, the am28f256a has separate chip enable (ce#) and output enable (oe#) controls. amds flash memories augment eprom functionality with in-circuit electrical erasure and programming. the am28f256a uses a command register to manage this functionality, while maintaining a standard jedec flash standard 32-pin pinout. the command register allows for 100% ttl level control inputs and fixed power supply levels during erase and programming. amds flash technology reliably stores memory con- tents even after 100,000 erase and program cycles. the amd cell is designed to optimize the erase and programming mechanisms. in addition, the combina- tion of advanced tunnel oxide processing and low inter- nal electric fields for erase and programming operations produces reliable cycling. the am28f256a uses a 12.0v 5% v pp high voltage input to perform the erase and programming functions. the highest degree of latch-up protection is achieved with amds proprietary non-epi process. latch-up pro- tection is provided for stresses up to 100 milliamps on address and data pins from C1 v to v cc +1 v. embedded program the am28f256a is byte programmable using the embedded programming algorithm. the embedded programming algorithm does not require the system to time-out or verify the data programmed. the typical room temperature programming time of the am28f256a is one half second. embedded erase the entire chip is bulk erased using the embedded erase algorithm. the embedded erase algorithm automatically programs the entire array prior to electrical erase. the timing and verification of electrical erase are
2 am28f256a controlled internal to the device. typical erasure at room temperature is accomplished in 1.5 seconds, including preprogramming. amds am28f256a is entirely pin and software com- patible with amds am28f020a, am28f256a and am28f512a flash memories. commands are written to the command register using standard microprocessor write timings. register con- tents serve as inputs to an internal state-machine which controls the erase and programming circuitry. during write cycles, the command register internally latches address and data needed for the programming and erase operations. for system design simplification, the am28f256a is designed to support either we# or ce# controlled writes. during a system write cycle, addresses are latched on the falling edge of we# or ce# whichever occurs last. data is latched on the rising edge of we# or ce# whichever occurs first. to simplify the following discussion, the we# pin is used as the write cycle control pin throughout the rest of this text. all setup and hold times are with respect to the we# signal. amds flash technology combines years of eprom and eeprom experience to produce the highest levels of quality, reliability, and cost effectiveness. the am28f256a electrically erases all bits simultaneously using fowler-nordheim tunneling. the bytes are programmed one byte at a time using the eprom programming mechanism of hot electron injection. comparing embedded algorithms with flasherase and flashrite algorithms am28f256a with embedded algorithms am28f256 using amd flashrite and flasherase algorithms embedded programming algorithm vs. flashrite programming algorithm amds embedded programming algorithm requires the user to only write a program set-up command and a program command (program data and address). the device automatically times the programming pulse width, verifies the programming, and counts the number of sequences. a status bit, data # polling, provides the user with the programming operation status. the flashrite programming algorithm requires the user to write a program set-up command, a program command, (program data and address), and a program verify command, followed by a read and compare operation. the user is required to time the programming pulse width in order to issue the program verify command. an integrated stop timer prevents any possibility of overprogramming. upon completion of this sequence, the data is read back from the device and compared by the user with the data intended to be written; if there is not a match, the sequence is repeated until there is a match or the sequence has been repeated 25 times. embedded erase algorithm vs. flasherase erase algorithm amds embedded erase algorithm requires the user to only write an erase set- up command and erase command. the device automatically pre-programs and verifies the entire array. the device then automatically times the erase pulse width, verifies the erase operation, and counts the number of sequences. a status bit, data # polling, provides the user with the erase operation status. the flasherase erase algorithm requires the device to be completely programmed prior to executing an erase command. to invoke the erase operation, the user writes an erase set-up command, an erase command, and an erase verify command. the user is required to time the erase pulse width in order to issue the erase verify command. an integrated stop timer prevents any possibility of overerasure. upon completion of this sequence, the data is read back from the device and compared by the user with erased data. if there is not a match, the sequence is repeated until there is a match or the sequence has been repeated 1,000 times.
am28f256a 3 block diagram product selector guide erase voltage switch state control command register program voltage switch chip enable output enable logic y-decoder x-decoder 18879c-1 a0Ca14 oe# ce# we# v ss v cc to array dq0Cdq7 input/output buffers v pp address latch low v cc detector program/erase pulse timer embedded algorithms data latch y-gating 262,144 bit cell matrix family part number am28f256a speed options (v cc = 5.0 v 10%) -70 -90 -120 -150 -200 max access time (ns) 70 90 120 150 200 ce # (e # ) access (ns) 70 90 120 150 200 oe # (g # ) access (ns) 35 35 50 55 55
4 am28f256a connection diagrams note: pin 1 is marked for orientation. v pp v cc dq0 a5 a12 a14 1 3 5 7 9 11 12 10 2 4 8 6 32 30 28 26 24 14 21 23 31 29 25 27 nc a7 13 22 20 19 a6 15 16 18 17 a4 a3 a2 a1 a0 dq1 dq2 v ss we# (w#) a13 a8 a9 a11 oe# (g#) a10 ce# (e#) dq7 dq6 dq5 dq4 dq3 18879c-2 pdip nc nc 1 31 30 2 3 4 5 6 7 8 9 10 11 12 13 17 18 19 20 16 15 14 29 28 27 26 25 24 23 22 21 32 a7 a6 a5 a4 a3 a2 a1 a0 dq0 a14 a13 a8 a9 a11 oe# (g#) a10 ce# (e#) dq7 a12 nc nc v pp v cc we# (w#) nc dq1 dq2 v ss dq3 dq4 dq5 dq6 plcc 18879b-3
am28f256a 5 connection diagrams (continued) 32-pin standard pinout 32-pin reverse pinout logic symbol 1 16 2 3 4 5 6 7 8 9 10 11 12 13 14 15 32 17 31 30 29 28 27 26 25 24 23 22 21 20 19 18 a11 a9 a8 a13 a14 nc we v cc v pp nc nc a12 a7 a6 a5 a4 oe# a10 ce# d7 d6 d5 d4 d3 v ss d2 d1 d0 a0 a1 a2 a3 a11 a9 a8 a13 a14 nc we# v cc v pp nc nc a12 a7 a6 a5 a4 oe# a10 ce# d7 d6 d5 d4 d3 v ss d2 d1 d0 a0 a1 a2 a3 32 17 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1 16 2 3 4 5 6 7 8 9 10 11 12 13 14 15 18879c-4 15 8 a0Ca14 ce# (e#) oe# (g#) we# (w#) 18879c-5 dq0Cdq7
6 am28f256a ordering information standard products valid combinations valid combinations list configurations planned to be sup- ported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. device number/description am28f256a 256 kilobit (32 k x 8-bit) cmos flash memory with embedded algorithms am28f256a -70 j c optional processing blank = standard processing b = burn-in contact an amd representative for more information. temperature range c= commercial (0c to +70c) i = industrial (C40c to +85c) e = extended (C55c to +125c) package type p = 32-pin plastic dip (pd 032) j = 32-pin rectangular plastic leaded chip carrier (pl 032) e = 32-pin thin small outline package (tsop) standard pinout (ts 032) f = 32-pin thin small outline package (tsop) reverse pinout (tsr032) speed option see product selector guide and valid combinations b valid combinations am28f256a-70 am28f256a-90 am28f256a-120 am28f256a-150 am28f256a-200 pc, pi, pe, jc, ji, je, ec, ei, ee, fc, fi, fe
am28f256a 7 pin description a0Ca14 address inputs for memory locations. internal latches hold addresses during write cycles. ce # (e # ) chip enable active low input activates the chips control logic and input buffers. chip enable high will deselect the device and operates the chip in stand-by mode. dq0-dq7 data inputs during memory write cycles. internal latches hold data during write cycles. data outputs during memory read cycles. nc no connect-corresponding pin is not connected internally to the die. oe # (g # ) output enable active low input gates the outputs of the device through the data buffers during memory read cycles. output enable is high during command sequencing and program/erase operations. v cc power supply for device operation. (5.0 v 5% or 10%) v pp program voltage input. v pp must be at high voltage in order to write to the command register. the command register controls all functions required to alter the mem- ory array contents. memory contents cannot be altered when v pp v cc +2 v. v ss ground. we # (w) write enable active low input controls the write function of the command register to the memory array. the target address is latched on the falling edge of the write en- able pulse and the appropriate data is latched on the ris- ing edge of the pulse. write enable high inhibits writing to the device.
8 am28f256a basic principles this section contains descriptions about the device read, erase, and program operations, and write opera- tion status of the am29fxxxa, 12.0 volt family of flash devices. references to some tables or figures may be given in generic form, such as command definitions table, rather than table 1. refer to the corresponding data sheet for the actual table or figure. the am28fxxxa family uses 100% ttl-level control inputs to manage the command register. erase and reprogramming operations use a fixed 12.0 v 5% high voltage input. read only memory without high v pp voltage, the device functions as a read only memory and operates like a standard eprom. the control inputs still manage traditional read, standby, output disable, and auto select modes. command register the command register is enabled only when high volt- age is applied to the v pp pin. the erase and repro- gramming operations are only accessed via the register. in addition, two-cycle commands are required for erase and reprogramming operations. the tradi- tional read, standby, output disable, and auto select modes are available via the register. the devices command register is written using standard microprocessor write timings. the register controls an internal state machine that manages all device opera- tions. for system design simplification, the device is de- signed to support either we# or ce# controlled writes. during a system write cycle, addresses are latched on the falling edge of we# or ce# whichever occurs last. data is latched on the rising edge of we# or ce# which- ever occur first. to simplify the following discussion, the we# pin is used as the write cycle control pin throughout the rest of this text. all setup and hold times are with re- spect to the we# signal. overview of erase/program operations embedded erase algorithm amd now makes erasure extremely simple and reli- able. the embedded erase algorithm requires the user to only write an erase setup command and erase com- mand. the device will automatically pre-program and verify the entire array. the device automatically times the erase pulse width, provides the erase verify and counts the number of sequences. a status bit, data# polling, provides feedback to the user as to the status of the erase operation. embedded programming algorithm amd now makes programming extremely simple and reliable. the embedded programming algorithm re- quires the user to only write a program setup command and a program command. the device automatically times the programming pulse width, provides the pro- gram verify and counts the number of sequences. a status bit, data# polling, provides feedback to the user as to the status of the programming operation. data protection the device is designed to offer protection against acci- dental erasure or programming caused by spurious system level signals that may exist during power transi- tions. the device powers up in its read only state. also, with its control register architecture, alteration of the memory contents only occurs after successful comple- tion of specific command sequences. the device also incorporates several features to pre- vent inadvertent write cycles resulting from v cc power-up and power-down transitions or system noise. low v cc write inhibit to avoid initiation of a write cycle during v cc power-up and power-down, the device locks out write cycles for v cc < v lko (see dc characteristics section for volt- ages). when v cc < v lko , the command register is dis- abled, all internal program/erase circuits are disabled, and the device resets to the read mode. the device ig- nores all writes until v cc > v lko . the user must ensure that the control pins are in the correct logic state when v cc > v lko to prevent unintentional writes. write pulse glitch protection noise pulses of less than 10 ns (typical) on oe#, ce# or we# will not initiate a write cycle. logical inhibit writing is inhibited by holding any one of oe# = v il , ce#=v ih or we# = v ih . to initiate a write cycle ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit power-up of the device with we# = ce# = v il and oe# = v ih will not accept commands on the rising edge of we#. the internal state machine is automati- cally reset to the read mode on power-up.
am28f256a 9 functional description description of user modes table 1. am28f256a device bus operations (notes 7 and 8) legend: x = dont care, where dont care is either v il or v ih levels. v ppl = v pp < v cc + 2 v. see dc characteristics for voltage levels of v pph . 0 v < an < v cc + 2 v, (normal ttl or cmos input levels, where n = 0 or 9). notes: 1. v ppl may be grounded, connected with a resistor to ground, or < v cc + 2.0 v. v pph is the programming voltage specified for the device. refer to the dc characteristics. when v pp = v ppl , memory contents can be read but not written or erased. 2. manufacturer and device codes may also be accessed via a command register write sequence. refer to table 2. 3. 11.5 < v id < 13.0 v. minimum v id rise time and fall time (between 0 and v id voltages) is 500 ns. 4. read operation with v pp = v pph may access array data or the auto select codes. 5. with v pp at high voltage, the standby current is i cc + i pp (standby). 6. refer to table 3 for valid d in during a write operation. 7. all inputs are dont care unless otherwise stated, where dont care is either v il or v ih levels. in the auto select mode all addresses except a 9 and a 0 must be held at v il . 8. if v cc 1.0 volt, the voltage difference between v pp and v cc should not exceed 10.0 volts. also, the am28f256 has a v pp rise time and fall time specification of 500 ns minimum. operation ce # (e # ) oe # (g # ) we # (w # ) v pp (note 1) a0 a9 i/o read-only read v il v il xv ppl a0 a9 d out standby v ih xxv ppl x x high z output disable v il v ih v ih v ppl x x high z auto-select manufacturer code (note 2) v il v il v ih v ppl v il v id (note 3) code (01h) auto-select device code (note 2) v il v il v ih v ppl v ih v id (note 3) code (2fh) read/write read v il v il v ih v pph a0 a9 d out (note 4) standby (note 5) v ih xxv pph x x high z output disable v il v ih v ih v pph x x high z write v il v ih v il v pph a0 a9 d in (note 6)
10 am28f256a read-only mode when v pp is less than v cc + 2 v, the command register is inactive. the device can either read array or autose- lect data, or be standby mode. read the device functions as a read only memory when v pp < v cc + 2 v. the device has two control functions. both must be satisfied in order to output data. ce# controls power to the device. this pin should be used for spe- cific device selection. oe# controls the device outputs and should be used to gate data to the output pins if a device is selected. address access time t acc is equal to the delay from stable addresses to valid output data. the chip enable access time t ce is the delay from stable addresses and stable ce# to valid data at the output pins. the output enable access time is the delay from the falling edge of oe# to valid data at the output pins (assuming the ad- dresses have been stable at least t acc - t oe ). standby mode the device has two standby modes. the cmos standby mode (ce# input held at v cc 0.5 v), con- sumes less than 100 a of current. ttl standby mode (ce# is held at v ih ) reduces the current requirements to less than 1 ma. when in the standby mode the out- puts are in a high impedance state, independent of the oe# input. if the device is deselected during erasure, program- ming, or program/erase verification, the device will draw active current until the operation is terminated. output disable output from the device is disabled when oe# is at a logic high level. when disabled, output pins are in a high impedance state. auto select flash memories can be programmed in-system or in a standard prom programmer. the device may be sol- dered to the circuit board upon receipt of shipment and programmed in-system. alternatively, the device may initially be programmed in a prom programmer prior to soldering the device to the board. the auto select mode allows the reading out of a binary code from the device that will identify its manufacturer and type. this mode is intended for the purpose of automati- cally matching the device to be programmed with its cor- responding programming algorithm. this mode is functional over the entire temperature range of the device. programming in a prom programmer to activate this mode, the programming equipment must force v id (11.5 v to 13.0 v) on address a9. two identifier bytes may then be sequenced from the device outputs by toggling address a0 from v il to v ih . all other address lines must be held at v il , and v pp must be less than or equal to v cc + 2.0 v while using this auto select mode. byte 0 (a0 = v il ) represents the manufac- turer code and byte 1 (a0 = v ih ) the device identifier code. for the device the two bytes are given in the table 2 of the device data sheet. all identifiers for manufac- turer and device codes will exhibit odd parity with the msb (dq7) defined as the parity bit. table 2. am28f256a auto select code type a0 code (hex) manufacturer code v il 01 device code v ih 2f
am28f256a 11 erase, program, and read mode when v pp is equal to 12.0 v 5%, the command reg- ister is active. all functions are available. that is, the device can program, erase, read array or autoselect data, or be standby mode. write operations high voltage must be applied to the v pp pin in order to activate the command register. data written to the reg- ister serves as input to the internal state machine. the output of the state machine determines the operational function of the device. the command register does not occupy an address- able memory location. the register is a latch that stores the command, along with the address and data infor- mation needed to execute the command. the register is written by bringing we# and ce# to v il , while oe# is at v ih . addresses are latched on the falling edge of we#, while data is latched on the rising edge of the we# pulse. standard microprocessor write timings are used. the device requires the oe# pin to be v ih for write op- erations. this condition eliminates the possibility for bus contention during programming operations. in order to write, oe# must be v ih , and ce# and we# must be v il . if any pin is not in the correct state a write command will not be executed. refer to ac write characteristics and the erase/pro- gramming waveforms for specific timing parameters. command definitions the contents of the command register default to 00h (read mode) in the absence of high voltage applied to the v pp pin. the device operates as a read only memory. high voltage on the v pp pin enables the command register. device operations are selected by writing specific data codes into the command register. table 3 in the device data sheet defines these register commands. read command memory contents can be accessed via the read com- mand when v pp is high. to read from the device, write 00h into the command register. standard microproces- sor read cycles access data from the memory. the de- vice will remain in the read mode until the command register contents are altered. the command register defaults to 00h (read mode) upon v pp power-up. the 00h (read mode) register de- fault helps ensure that inadvertent alteration of the memory contents does not occur during the v pp power transition. refer to the ac read characteristics and waveforms for the specific timing parameters. table 3. am28f256a command definitions notes: 1. bus operations are defined in table 1. 2. ra = address of the memory location to be read. pa = address of the memory location to be programmed. addresses are latched on the falling edge of the we # pulse. x = dont care. 3. rd = data read from location ra during read operation. pd = data to be programmed at location pa. data latched on the rising edge of we # . 4. please reference reset command section. command first bus cycle second bus cycle operation (note 1) address (note 2) data (note 3) operation (note 1) address (note 2) data (note 3) read memory (note 4) write x 00h/ffh read ra rd read auto select write x 80h or 90h read 00h/01h 01h/2fh embedded erase set-up/ embedded erase write x 30h write x 30h embedded program set-up/ embedded program write x 10h or 50h write pa pd reset (note 4) write x 00h/ffh write x 00h/ffh
12 am28f256a flash memory program/erase operations embedded erase algorithm the automatic chip erase does not require the device to be entirely pre-programmed prior to executing the embedded set-up erase command and embedded erase command. upon executing the embedded erase command the device automatically will program and verify the entire memory for an all zero data pattern. the system is not required to provide any controls or timing during these operations. when the device is automatically verified to contain an all zero pattern, a self-timed chip erase and verify be- gin. the erase and verify operation are complete when the data on dq7 is 1" (see write operation status sec- tion) atwhich time the device returns to read mode. the system is not required to provide any control or timing during these operations. when using the embedded erase algorithm, the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase ver- ify command is required). the margin voltages are in- ternally generated in the same manner as when the standard erase verify command is used. the embedded erase set-up command is a command only operation that stages the device for automatic electrical erasure of all bytes in the array. embedded erase setup is performed by writing 30h to the com- mand register. to commence automatic chip erase, the command 30h must be written again to the command register. the au- tomatic erase begins on the rising edge of the we and terminates when the data on dq7 is 1" (see write op- eration status section) at which time the device returns to read mode. figure 1 and table 4 illustrate the embedded erase al- gorithm, a typical command string and bus operation. table 4. embedded erase algorithm note: see ac and dc characteristics for values of v pp parameters. the v pp power supply can be hard-wired to the device or switchable. when v pp is switched, v ppl may be ground, no connect with a resistor tied to ground, or less than v cc + 2.0 v. refer to functional description. bus operations command comments standby wait for v pp ramp to v pph (see note) write embedded erase setup command data = 30h embedded erase command data = 30h read data # polling to verify erasure standby compare output to ffh read available for read operations start apply v pph erasure completed data# poll from device write embedded erase command write embedded erase setup command 18879c-6 figure 1. embedded erase algorithm
am28f256a 13 embedded programming algorithm the embedded program setup is a command only op- eration that stages the device for automatic program- ming. embedded program setup is performed by writing 10h or 50h to the command register. once the embedded setup program operation is per- formed, the next we# pulse causes a transition to an active programming operation. addresses are latched on the falling edge of ce# or we# pulse, whichever happens later. data is latched on the rising edge of we# or ce#, whichever happens first. the rising edge of we# also begins the programming operation. the system is not required to provide further controls or timings. the device will automatically provide an ade- quate internally generated program pulse and verify margin. the automatic programming operation is completed when the data on dq7 is equivalent to data written to this bit (see write operation status section) at which time the device returns to read mode. figure 2 and table 5 illustrate the embedded program algorithm, a typical command string, and bus operation. table 5. embedded programming algorithm note: see ac and dc characteristics for values of v pp parameters. the v pp power supply can be hard-wired to the device or switchable. when v pp is switched, v ppl may be ground, no connect with a resistor tied to ground, or less than v cc + 2.0 v. refer to functional description. device is either powered-down, erase inhibit or program inhibit. bus operations command comments standby wait for v pp ramp to v pph (see note) write embedded program setup command data = 10h or 50h write embedded program command valid address/data read data # polling to verify completion read available for read operations start apply v pph write embedded setup program command write embedded program command (a/d) programming completed ye s data# poll device increment address no 18879c-7 figure 2. embedded programming algorithm last address
14 am28f256a write operation status data pollingdq7 the device features data# polling as a method to indi- cate to the host system that the embedded algorithms are either in progress or completed. while the embedded programming algorithm is in oper- ation, an attempt to read the device at a valid address will produce the complement of expected valid data on dq7. upon completion of the embedded program algo- rithm an attempt to read the device at a valid address will produce valid data on dq7. the data# polling feature is valid after the rising edge of the second we# pulse of the two write pulse sequence. while the embedded erase algorithm is in operation, dq7 will read 0" until the erase operation is com- pleted. upon completion of the erase operation, the data on dq7 will read 1. the data# polling feature is valid after the rising edge of the second we# pulse of the two write pulse sequence. the data# polling feature is only active during embed- ded programming or erase algorithms. see figures 3 and 4 for the data# polling timing spec- ifications and diagrams. data# polling is the standard method to check the write operation status, however, an alternative method is available using toggle bit. start fail no dq7 = data ? dq7 = data ? dq5 = 1 ? no pass ye s no ye s read byte (dq0Cdq7) addr = va read byte (dq0Cdq7) addr = va ye s va = byte address for programming = xxxxh during chip erase 18879c-8 note: dq7 is rechecked even if dq5 = 1 because dq7 may change simultaneously with dq5 or after dq5. figure 3. data # polling algorithm
am28f256a 15 t ch t oeh t oe t ce t whwh 3 or 4 dq7# dq7 = valid data high z ce# oe# we# dq7 t oh t df dq0Cdq6 = invalid dq0Cdq6 dq0Cdq7 valid data * 18879c-9 *dq7 = valid data (the device has completed the embedded operation.) figure 4. ac waveforms for data # polling during embedded algorithm operations
16 am28f256a toggle bitdq6 the device also features a toggle bit as a method to indicate to the host system that the embedded algo- rithms are either in progress or completed. successive attempts to read data from the device at a valid address, while the embedded program algorithm is in progress, or at any address while the embedded erase algorithm is in progress, will result in dq6 tog- gling between one and zero. once the embedded pro- gram or erase algorithm is completed, dq6 will stop toggling to indicate the completion of either embedded operation. only on the next read cycle will valid data be obtained. the toggle bit is valid after the rising edge of the first we# pulse of the two write pulse sequence, un- like data# polling which is valid after the rising edge of the second we# pulse. this feature allows the user to determine if the device is partially through the two write pulse sequence. see figures 5 and 6 for the toggle bit timing specifica- tions and diagrams. start fail no dq6 = toggle ? dq5 = 1 ? pass ye s no read byte (dq0Cdq7) addr = va read byte (dq0Cdq7) addr = va ye s no ye s dq6 = toggle ? va = byte address for programming = xxxxh during chip erase 18879c-10 note: dq6 is rechecked even if dq5 = 1 because dq6 may stop toggling at the same time as dq5 changing to 1. figure 5. toggle bit algorithm
am28f256a 17 dq5 exceeded timing limits dq5 will indicate if the program or erase time has exceeded the specified limits. this is a failure condi- tion and the device may not be used again (internal pulse count exceeded). under these conditions dq5 will produce a 1. the program or erase cycle was not successfully completed. data# polling is the only op- erating function of the device under this condition. the ce# circuit will partially power down the device under these conditions (to approximately 2 ma). the oe# and we# pins will control the output disable functions as described in the command definitions table in the corresponding device data sheet. parallel device erasure the embedded erase algorithm greatly simplifies par- allel device erasure. since the erase process is internal to the device, a single erase command can be given to multiple devices concurrently. by implementing a paral- lel erase algorithm, total erase time may be minimized. note that the flash memories may erase at different rates. if this is the case, when a device is completely erased, use a masking code to prevent further erasure (over-erasure). the other devices will continue to erase until verified. the masking code applied could be the read command (00h). power-up/power-down sequence the device powers-up in the read only mode. power supply sequencing is not required. note that if v cc 1.0 volt, the voltage difference between v pp and v cc should not exceed 10.0 volts. also, the device has a rise v pp rise time and fall time specification of 500 ns minimum. reset command the reset command initializes the flash memory de- vice to the read mode. in addition, it also provides the user with a safe method to abort any device operation (including program or erase). the reset must be written two consecutive times after the setup program command (10h or 50h). this will reset the device to the read mode. following any other flash command, write the reset command once to the device. this will safely abort any previous operation and initialize the device to the read mode. the setup program command (10h or 50h) is the only command that requires a two-sequence reset cycle. the first reset command is interpreted as program data. however, ffh data is considered as null data during pro- gramming operations (memory cells are only pro- grammed from a logical 1" to 0"). the second reset command safely aborts the programming operation and resets the device to the read mode. memory contents are not altered in any case. ce# t oeh we# oe# data dq0Cdq7 dq6 = dq6 = dq6 stop toggling dq0Cdq7 valid t oe * 18879c-11 note: *dq6 stops toggling (the device has completed the embedded operation.) figure 6. ac waveforms for toggle bit during embedded algorithm operations
18 am28f256a this detailed information is for your reference. it may prove easier to always issue the reset command two consecutive times. this eliminates the need to deter- mine if you are in the setup program state or not. in-system programming considerations flash memories can be programmed in-system or in a standard prom programmer. the device may be sol- dered to the circuit board upon receipt of shipment and programmed in-system. alternatively, the device may initially be programmed in a prom programmer prior to soldering the device to the circuit board. auto select command amds flash memories are designed for use in appli- cations where the local cpu alters memory contents. in order to correctly program any flash memories in-system, manufacturer and device codes must be accessible while the device resides in the target system. prom programmers typically access the sig- nature codes by raising a9 to a high voltage. however, multiplexing high voltage onto address lines is not a generally desired system design practice. the device contains an auto select operation to supple- ment traditional prom programming methodologies. the operation is initiated by writing 80h or 90h into the command register. following this command, a read cycle address 0000h retrieves the manufacturer code of 01h (amd). a read cycle from address 0001h returns the device code (see the auto select code table of the corresponding device data sheet). to terminate the op- eration, it is necessary to write another valid command, such as reset (00h or ffh), into the register.
am28f256a 19 absolute maximum ratings storage temperature . . . . . . . . . . . . C65 c to +150 c plastic packages . . . . . . . . . . . . . . . C65 c to +125 c ambient temperature with power applied. . . . . . . . . . . . . .C55 c to + 125 c voltage with respect to ground all pins except a9 and v pp (note 1) . . . . . . . . . . . . . . . . . . . . . . .C2.0 v to +7.0 v v cc (note 1). . . . . . . . . . . . . . . . . . . . C2.0 v to +7.0 v a9 (note 2). . . . . . . . . . . . . . . . . . . . C2.0 v to +14.0 v v pp (note 2). . . . . . . . . . . . . . . . . . . C2.0 v to +14.0 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is C0.5 v. during voltage transitions, inputs may overshoot v ss to C2.0 v for periods of up to 20 ns. maximum dc voltage on input and i/o pins is v cc + 0.5 v. during voltage transitions, input and i/o pins may overshoot to v cc + 2.0 v for periods up to 20ns. 2. minimum dc input voltage on a9 and v pp pins is C0.5 v. during voltage transitions, a9 and v pp may overshoot v ss to C2.0 v for periods of up to 20 ns. maximum dc input voltage on a9 and v pp is +13.0 v which may overshoot to 14.0 v for periods up to 20 ns. 3. no more than one output shorted to ground at a time. duration of the short circuit should not be greater than one second. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the op- erational sections of this specification is not implied. expo- sure of the device to absolute maximum rating conditions for extended periods may affect device reliability. operating ranges commercial (c) devices ambient temperature (t a ) . . . . . . . . . . .0 c to +70 c industrial (i) devices ambient temperature (t a ) . . . . . . . . . C40 c to +85 c extended (e) devices ambient temperature (t a ) . . . . . . . .C55 c to +125 c v cc supply voltages v cc . . . . . . . . . . . . . . . . . . . . . . . . +4.50 v to +5.50 v v pp voltages read . . . . . . . . . . . . . . . . . . . . . . . . C0.5 v to +12.6 v program, erase, and verify . . . . . . +11.4 v to +12.6 v operating ranges define those limits between which the functionality of the device is guaranteed.
20 am28f256a maximum overshoot 20 ns 20 ns +0.8 v C0.5 v 20 ns C2.0 v 18879c-12 maximum negative input overshoot 20 ns v cc + 0.5 v 2.0 v 20 ns 20 ns v cc + 2.0 v 18879c-13 maximum positive input overshoot 18879c-14 maximum v pp overshoot 20 ns 13.5 v v cc + 0.5 v 20 ns 20 ns 14.0 v
am28f256a 21 dc characteristics over operating range unless otherwise specified (notes 1-4) ttl/nmos compatible notes: 1. caution: the am28f256a must not be removed from (or inserted into) a socket when v cc or v pp is applied. if v cc e 1.0 volt, the voltage difference between v pp and v cc should not exceed 10.0 volts. also, the am28f256a has a v pp rise time and fall time specification of 500 ns minimum. 2. i cc1 is tested with oe# = v ih to simulate open outputs. 3. maximum active power usage is the sum of i cc and i pp . 4. not 100% tested. parameter symbol parameter description test conditions min typ max unit i li input leakage current v cc = v cc max, v in = v cc or v ss 1.0 a i lo output leakage current v cc = v cc max, v out = v cc or v ss 1.0 a i ccs v cc standby current v cc = v cc max, ce # = v ih 0.2 1.0 ma i cc1 v cc active read current v cc = v cc max, ce # = v il, oe # = v ih i out = 0 ma, at 6 mhz 20 30 ma i cc2 v cc programming current ce # = v il programming in progress (note 4) 20 30 ma i cc3 v cc erase current ce # = v il erasure in progress (note 4) 20 30 ma i pps v pp standby current v pp = v ppl 1.0 a i pp1 v pp read current v pp = v pph 70 200 a v pp = v ppl 1.0 i pp2 v pp programming current v pp = v pph programming in progress (note 4) 10 30 ma i pp3 v pp erase current v pp = v pph erasure in progress (note 4) 10 30 ma v il input low voltage C0.5 0.8 v v ih input high voltage 2.0 v cc + 0.5 v v ol output low voltage i ol = 5.8 ma, v cc = v cc min 0.45 v v oh1 output high voltage i oh = C2.5 ma, v cc = v cc min 2.4 v v id a9 auto select voltage a9 = v id 11.5 13.0 v i id a9 auto select current a9 = v id max, v cc = v cc max 5 50 a v ppl v pp during read-only operations note: erase/program are inhibited when v pp = v ppl 0.0 v cc +2.0 v v pph v pp during read/write operations 11.4 12.6 v v lko low v cc lock-out voltage 3.2 3.7 v
22 am28f256a dc characteristics cmos compatible notes: 1. caution: the am28f256a must not be removed from (or inserted into) a socket when v cc or v pp is applied. if v cc e 1.0 volt, the voltage difference between v pp and v cc should not exceed 10.0 volts. also, the am28f256a has a v pp rise time and fall time specification of 500 ns minimum. 2. i cc1 is tested with oe # = v ih to simulate open outputs. 3. maximum active power usage is the sum of i cc and i pp . 4. not 100% tested. parameter symbol parameter description test conditions min typ max unit i li input leakage current v cc = v cc max, v in = v cc or v ss 1.0 a i lo output leakage current v cc = v cc max, v out = v cc or v ss 1.0 a i ccs v cc standby current v cc = v cc max, ce# = v cc 0.5 v 15 100 a i cc1 v cc active read current v cc = v cc max, ce# = v il, oe # = v ih i out = 0 ma, at 6 mhz 20 30 ma i cc2 v cc programming current ce # = v il programming in progress (note 4) 20 30 ma i cc3 v cc erase current ce # = v il erasure in progress (note 4) 20 30 ma i pps v pp standby current v pp = v ppl 1.0 a i pp1 v pp read current v pp = v pph 70 200 a i pp2 v pp programming current v pp = v pph programming in progress (note 4) 10 30 ma i pp3 v pp erase current v pp = v pph erasure in progress (note 4) 10 30 ma v il input low voltage C0.5 0.8 v v ih input high voltage 0.7 v cc v cc + 0.5 v v ol output low voltage i ol = 5.8 ma, v cc = v cc min 0.45 v v oh1 output high voltage i oh = C2.5 ma, v cc = v cc min 0.85 v cc v v oh2 i oh = C100 a, v cc = v cc min v cc C0.4 v id a9 auto select voltage a9 = v id 11.5 13.0 v i id a9 auto select current a9 = v id max, v cc = v cc max 5 50 a v ppl v ppl during read-only operations note: erase/program are inhibited when v pp = v ppl 0.0 v cc + 2.0 v v pph v pp during read/write operations 11.4 12.6 v v lko low v cc lock-out voltage 3.2 3.7 v
am28f256a 23 test conditions table 6. test specifications 18879c-15 figure 7. am28f256aaverage i cc active vs. frequency v cc = 5.5 v, addressing pattern = minmax data pattern = checkerboard i cc active in ma 25 20 15 10 5 0 0123456789101112 frequency in mhz 55c 0c 25c 70c 125c 2.7 k w c l 6.2 k w 5.0 v device under te s t 18879c-16 figure 8. test setup note: diodes are in3064 or equivalent test condition -70 all others unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 100 pf input rise and fall times 10 ns input pulse levels 0.0C3.0 0.45C2.4 v input timing measurement reference levels 1.5 0.8, 2.0 v output timing measurement reference levels 1.5 0.8, 2.0 v
24 am28f256a switching test waveforms switching characteristics over operating range unless otherwise specified ac characteristicsread only operation notes: 1. guaranteed by design not tested. 2. not 100% tested. parameter symbols parameter description am28f256a speed options unit jedec standard -70 -90 -120 -150 -200 t avav t rc read cycle time (note 2) min 70 90 120 150 200 ns t elqv t ce chip enable access time max 70 90 120 150 200 ns t avqv t acc address access time max 70 90 120 150 200 ns t glqv t oe output enable access time max 35 35 50 55 55 ns t elqx t lz chip enable to output in low z (note 2) min00000ns t ehqz t df chip disable to output in high z (note 1) max2020303535ns t glqx t olz output enable to output in low z (note 2) min00000ns t ghqz t df output disable to output in high z (note 2) max2020303535ns t axqx t oh output hold from first of address, ce # , or oe # change (note 2) min00000ns t vcs v cc setup time to valid read (note 2) min 50 50 50 50 50 s 18879c-17 3 v 0 v input output 1.5 v 1.5 v te s t po i n t s ac testing for -70 devices: inputs are driven at 3.0 v for a logic 1 and 0 v for a logic 0. input pulse rise and fall time s are 10 ns. 2.4 v 0.45 v input output test points 2.0 v 2.0 v 0.8 v 0.8 v ac testing (all speed options except -70): inputs are driven at 2.4 v for a logic 1 and 0.45 v for a logic 0. input pulse rise and fall times are 10 ns.
am28f256a 25 ac characteristicswrite/erase/program operations notes: 1. read timing characteristics during read/write operations are the same as during read-only operations. refer to ac characteristics for read only operations. 2. embedded program operation of 14 s consists of 10 s program pulse and 4 s write recovery before read. this is the minimum time for one pass through the programming algorithm. 3. embedded erase operation of 5 sec consists of 4 sec array pre-programming time and 1 sec array erase time. this is a typical time for one embedded erase operation. 4. not 100% tested. parameter symbols parameter description am28f256a speed options unit jedec standard -70 -90 -120 -150 -200 t avav t wc write cycle time (note 4) min 70 90 120 150 200 ns t avwl t as address setup time min00000ns t wlax t ah address hold time min 45 45 50 60 75 ns t dvwh t ds data setup time min 45 45 50 50 50 ns t whdx t dh data hold time min 10 10 10 10 10 ns t oeh output enable hold time for embedded algorithm only min 10 10 10 10 10 ns t ghwl read recovery time before writemin00000 s t elwle t cse chip enable embedded algorithm setup time min 20 20 20 20 20 ns t wheh t ch chip enable hold time min00000ns t wlwh t wp write pulse width min 45 45 50 60 60 ns t whwl t wph write pulse width high min 20 20 20 20 20 ns t whwh3 embedded programming operation (note 2) min 14 14 14 14 14 s t whwh4 embedded erase operation (note3)typ55555sec t vpel v pp setup time to chip enable low (note 4) min 100 100 100 100 100 ns t vcs v cc setup time to chip enable low (note 4) min 50 50 50 50 50 s t vppr v pp rise time 90% v pph (note 4) min 500 500 500 500 500 ns t vppf v pp fall time 90% v ppl (note 4) min 500 500 500 500 500 ns t lko v cc < v lko to reset (note 4) min 100 100 100 100 100 ns
26 am28f256a key to switching waveforms switching waveforms waveform inputs outputs steady changing from h to l changing from l to h dont care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) addresses ce# oe# (g#) we# (w#) data (dq) 5.0 v v cc 0 v power-up, standby device and address selection outputs enabled data valid standby, power-down addresses stable high z high z t whgl t avqv (t acc ) t ehqz (t df ) t ghqz (t df ) t elqx (t lz ) t glqx (t olz ) t elqv (t ce ) t glqv (t oe ) t axqx (t oh ) output valid t avav (t rc ) t vcs 18879c-18 figure 9. ac waveforms for read operations
am28f256a 27 switching waveforms t wc dq7# 30h t rc data# polling read t df t oh t ce t oe t ds t cse t wph t dh t wp t ghwl t whwh3 or 4 addresses ce# oe# we# data v cc v pp embedded erase setup embedded erase erase standby 30h t ah t as t vcs t vpel dq7# 18879c-19 note: dq7# is the complement of the data written to the device. figure 10. ac waveforms for embedded erase operation
28 am28f256a switching waveforms t wc t ds dq7# d in t as t ah t rc data# polling read t df t oh t ce t oe t wph t dh t wp t ghwl embedded program setup embedded program t cse t whwh3 or 4 50h pa t vcs t vpel pa dq7# d out 18879c-20 notes: d in is data input to the device. dq7 # is the complement of the data written to the device. d out is the data written to the device. figure 11. ac waveforms for embedded programming operation addresses ce# oe# we# data v cc v pp
am28f256a 29 ac characteristicswrite/erase/program operations alternate ce # controlled writes notes: 1. read timing characteristics during read/write operations are the same as during read-only operations. refer to ac characteristics for read only operations. 2. embedded program operation of 14 s consists of 10 s program pulse and 4 s write recovery before read. this is the minimum time for one pass through the programming algorithm. 3. embedded erase operation of 5 sec consists of 4 sec array pre-programming time and one sec array erase time. this is a typical time for one embedded erase operation. 4. not 100% tested. parameter symbols parameter description am28f256a speed options unit jedec standard -70 -90 -120 -150 -200 t avav t wc write cycle time (note 4) min 70 90 120 150 200 ns t avel t as address setup time min 0 0 0 0 0 ns t elax t ah address hold time min 45 45 50 60 75 ns t dveh t ds data setup time min 45 45 50 50 50 ns t ehdx t g data hold time min 10 10 10 10 10 ns t oeh output enable hold time for embedded algorithm only min1010101010ns t ghel read recovery time before write min 0 0 0 0 0 s t wlel t ws we # setup time by ce # min00000ns t ehwk t wh we # hold time min 0 0 0 0 0 ns t eleh t cp write pulse width min 65 65 70 80 80 ns t ehel t cph write pulse width high min 20 20 20 20 20 ns t eheh3 embedded programming operation (note 2) min1414141414s t eheh4 embedded erase operation (note 3) typ 5 5 5 5 5 sec t vpel v pp setup time to chip enable low (note 4) min 100 100 100 100 100 ns t vcs v cc setup time to chip enable low (note 4) min5050505050s t vppr v pp rise time 90% v pph (note 4) min 500 500 500 500 500 ns t vppf v pp fall time 90% v ppl (note 4) min 500 500 500 500 500 ns t lko v cc < v lko to reset (note 4) min 100 100 100 100 100 ns
30 am28f256a switching waveforms t vpel t wc data# polling pa dq7# d in 50h t as t ah t ghel t dh t cph t eheh3 or 4 t ws t ds t cp embedded program setup embedded program pa d out dq7# 18879c-21 notes: 1. d in is data input to the device. 2. dq7# is complement of the data written to the device. 3. d out is the data written to the device. figure 12. ac waveforms for embedded programming operation using ce# controlled writes addresses we# oe# ce# data v cc v pp
am28f256a 31 erase and programming performance notes: 1. 25c, 12 v v pp . 2. maximum time specified is lower than worst case. worst case is derived from the embedded algorithm internal counter which allows for a maximum 6000 pulses for both program and erase operations. typical worst case for program and erase is significantly less than the actual device limit. 3. typical worst case = 84 s. dq5 = 1 only after a byte takes longer than 96 ms to program. latchup characteristics pin capacitance note: sampled, not 100% tested. test conditions t a = 25c, f = 1.0 mhz. data retention parameter limits comments min typ (note 1) max (note 2) unit chip erase time 1 10 sec excludes 00h programming prior to erasure chip programming time 0.5 12.5 sec excludes system-level overhead write/erase cycles 100,000 cycles byte programming time 14 s 96 (note 3) ms parameter min max input voltage with respect to v ss on all pins except i/o pins (including a9 and v pp ) C1.0 v 13.5 v input voltage with respect to v ss on all pins i/o pins C1.0 v v cc + 1.0 v current C100 ma +100 ma includes all pins except v cc . test conditions: v cc = 5.0 v, one pin at a time. parameter symbol parameter description test conditions typ max unit c in input capacitance v in = 0 8 10 pf c out output capacitance v out = 0 8 12 pf c in2 v pp input capacitance v pp = 0 8 12 pf parameter test conditions min unit minimum pattern data retention time 150c 10 years 125c 20 years
32 am28f256a physical dimensions pd03232-pin plastic dip (measured in inches) pl03232-pin plastic leaded chip carrier (measured in inches) pin 1 i.d. 1.640 1.670 .530 .580 .005 min .045 .065 .090 .110 .140 .225 .120 .160 .016 .022 seating plane .015 .060 16-038-s_ag pd 032 ec75 5-28-97 lv 32 17 16 .630 .700 0 10 .600 .625 .009 .015 .050 ref. .026 .032 top view pin 1 i.d. .485 .495 .447 .453 .585 .595 .547 .553 16-038fpo-5 pl 032 da79 6-28-94 ae side view seating plane .125 .140 .009 .015 .080 .095 .042 .056 .013 .021 .400 ref. .490 .530
am28f256a 33 physical dimensions ts03232-pin standard thin small outline package (measured in millimeters) pin 1 i.d. 1 18.30 18.50 7.90 8.10 0.50 bsc 0.05 0.15 0.95 1.05 16-038-tsop-2 ts 032 da95 3-25-97 lv 19.80 20.20 1.20 max 0.50 0.70 0.10 0.21 0 5 0.08 0.20
34 am28f256a physical dimensions tsr03232-pin reversed thin small outline package (measured in millimeters) 1 18.30 18.50 19.80 20.20 7.90 8.10 0.50 bsc 0.05 0.15 0.95 1.05 16-038-tsop-2 tsr032 da95 3-25-97 lv pin 1 i.d. 1.20 max 0.50 0.70 0.10 0.21 0 5 0.08 0.20
am28f256a 35 data sheet revision summary for am28f256a deleted -75, -95, and -250 speed options. matched for- matting to other current data sheets. revision c+1 programming in a prom programmer: deleted the paragraph (refer to the auto select paragraph in the erase, program, and read mode section for programming the flash memory de- vice in-system). revision c+2 product selector guide corrected maximum access time for -200 to 200 ns. erase and programming performance chip programming timetypical: changed value from 2 to 0.5 sec. trademarks copyright ? 1998 advanced micro devices, inc. all rights reserved. expressflash is a trademark of advanced micro devices, inc. amd, the amd logo, and combinations thereof are registered trademarks of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies .

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