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1 features ? full compliance with usb spec rev 1.1 four downstream ports full-speed and low-speed data transfers per port overcurrent monitoring individual port power control usb connection status indicators overview introduction the at43312a is a 5-port usb hub chip supporting one upstream and four down- stream ports. the at43312a connects to an upstream hub or host/root hub via port0 and the other ports connect to external downstream usb devices. the hub re-trans- mits the usb differential signal between port0 and ports[1:4] in both directions. a usb hub with the at43312a can operate as a bus-powered or self-powered through chip?s power mode configuration pin. in the self-powered mode, port power can be switched or unswitched. overcurrent reporting and port power control can be individual or glo- bal. an on-chip power supply eliminates the need for an external 3.3v supply. the at43312a supports the 12 mb/s full speed as well as 1.5 mb/s slow speed usb transactions. to reduce emi, the at43312a?s oscillator frequency is 6 mhz even though some internal circuitry operates at 48 mhz. the at43312a consists of a serial interface engine, a hub repeater, and a hub controller. self- and bus- powered usb hub controller at43312a rev. 1255c?12/01 pdip/soic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 pwr2 pwr3 pwr4 vcc5 vss osc1 osc2 lft test ovc4 ovc3 ovc2 ovc1 lpstat self/bus stat4 pwr1 dp4 dm4 dp3 dm3 vss dp2 dm2 cext dp1 dm1 dp0 dm0 stat1 stat2 stat3 lqfp top view 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 dp3 dm4 dp4 pwr1 pwr2 pwr3 pwr4 vcc5 dmo stat1 stat2 stat3 stat4 self/bus lpstat ovc1 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 vss osc1 osc2 lft test ovc4 ovc3 ovc2 dm3 vss dp2 dm2 cext dp1 dm1 dp0
2 at43312a 1255c?12/01 the serial interface engine?s tasks are: manage the usb communication protocol usb signaling detection/generation clock/data separation, data encoding/decoding, crc generation/checking data serialization/de-serialization the hub repeater is responsible for: providing upstream connectivity between the selected device and the host managing connectivity setup and tear-down handling bus fault detection and recovery detecting connect/disconnect on each port the hub controller is responsible for: hub enumeration providing configuration information to the host providing status of each port to the host controlling each port per host command figure 1. block diagram note: this document assumes that the reader is familiar with the universal serial bus and therefore only describes the unique features of the at43312a chip. for detailed information about the usb and its operation, the reader should refer to the universal serial bus specification version 1.1, september 23, 1998. hub controller serial interface engine hub repeater endpoint 0 endpoint 1 port 1 port 2 port 3 port 4 to downstream devices upstream port port 0
3 at43312a 1255c ? 12/01 pdip/soic pin assignment ty p e : i = input, o = output, od = output, open drain, b = bi-directional, v = power supply, ground table 1. 32-pin pdip/soic assignment pin signal type 1pwr2 o 2pwr3 o 3pwr4 o 4vcc5 v 5 vss v 6osc1 i 7osc2 o 8lft i 9 test i 10 ovc4 i 11 ovc3 i 12 ovc2 i 13 ovc1 i 14 lpstat i 15 self/bus i 16 stat4 o 17 stat3 o 18 stat2 o 19 stat1 o 20 dm0 b 21 dp0 b 22 dm1 b 23 dp1 b 24 cext o 25 dm2 b 26 dp2 b 27 vss v 28 dm3 b 29 dp3 b 30 dm4 b 31 dp4 b 32 pwr1 o
4 at43312a 1255c ? 12/01 lqfp pin assignment ty p e : i = input, o = output, od = output, open drain, b = bi-directional, v = power supply, ground table 2. 32-pin lqfp assignment pin signal type 1dp3b 2dm4b 3dp4b 4pwr1 o 5pwr2 o 6pwr3 o 7pwr4 o 8 vcc5 v 9 vss v 10 osc1 i 11 osc2 o 12 lft i 13 test i 14 ovc4 i 15 ovc3 i 16 ovc2 i 17 ovc1 i 18 lpstat i 19 self/bus i 20 stat4 o 21 stat3 o 22 stat2 o 23 stat1 o 24 dmo b 25 dp0 b 26 dm1 b 27 dp1 b 28 cext o 29 dm2 b 30 dp2 b 31 vss v 32 dm3 b
5 at43312a 1255c ? 12/01 signal description osc1 oscillator input. input to the inverting 6 mhz oscillator amplifier. osc2 oscillator output. output of the inverting oscillator amplifier. lft pll filter. for proper operation of the pll, this pin should be connected through a 2.2 nf capacitor in parallel with a 100 ? resistor in series with a 10 nf capacitor to ground (vss). self/bus hub power mode. input signal that sets the bus or self-powered mode operation. a high on this pin enables the self-powered mode, a low enables the bus-powered mode. lpstat local power status. in the self-powered mode, this is an input pin that should be con- nected to the local power supply through a 47 k ? resistor. the voltage on this pin is used by the chip for reporting the condition of the local power supply. in the bus-pow- ered mode, this pin is not used. dp0 upstream plus usb i/o. this pin should be connected to cext through an external 1.5 k ? pull-up resistor. dp0 and dm0 form the differential signal pin pairs connected to the host controller or an upstream hub. dm0 upstream minus usb i/o. dp[1:4] port plus usb i/o. this pin should be connected to vss through an external 15 k ? resistor. dp[1:4] and dm[1:4] are the differential signal pin pairs to connect downstream usb devices. dm[1:4] port minus usb i/o. this pin should be connected to vss through an external 15 k ? resistor ovc [1:4] overcurrent. this is the input signal used to indicate to the at43312a that an overcur- rent is detected at the port. if ovcx is asserted, at43312a will assert the pwrx pin and report the status to the usb host. pwr [1:4] power switch. this is an output signal used to enable or disable the external voltage regulator supplying power to a port. pwrx is de-asserted when a power supply problem is detected at ovcx . stat [1:4] connect status. this is an output pin indicating that a port is properly connected. statx is asserted when the port is enabled.
6 at43312a 1255c ? 12/01 cext external capacitor. for proper operation of the on chip regulator, a 0.27 f capacitor must be connected to this pin. test test. this pin should be connected to a logic high for normal operation. vcc 5v power supply. vss ground. functional description summary the atmel at43312a is a usb hub controller for use in a standalone hub as well as an add-on hub for an existing non-usb peripheral such a pc display monitor or keyboard. in addition to supporting the standard usb hub functionality, the at43312a has addi- tional features to enhance the user friendliness of the hub. usb ports the at43312a ? s upstream port, port0, is a full-speed port. a 1.5 k ? pull-up resistor to the 3.3v regulator output, cext, is required for proper operation. the downstream ports support both full-speed as well as low-speed devices. 15 k ? pull-down resistors are required at their inputs. full-speed signal requirements demand controlled rise/fall times and impedance match- ing of the usb ports. to meet these requirements, 22 ? resistors must be inserted in series between the usb data pins and the usb connectors. hub repeater the hub repeater is responsible for port connectivity setup and tear-down. it also sup- ports exception handling such as bus fault detection and recovery, and connect/disconnect detection. port0 is the root port and is connected to the root hub or an upstream hub. when a packet is received at port0, the at43312a propagates it to all the enabled downstream ports. conversely, a packet from a downstream port is trans- mitted from port0. the at43312a supports downstream port data signaling at both 1.5 mb/s and 12 mb/s. devices attached to the downstream ports are determined to be either full-speed or low- speed depending which data line (dp or dm) is pulled high. if a port is enumerated as low-speed, its output buffers operate at a slew rate of 75 - 300 ns, and the at43312a will not propagate any traffic to that port unless it is prefaced with a preamble pid. low- speed data following the preamble pid is propagated to both low- and full-speed devices. the at43312a will enable low-speed drivers within four full-speed bit times of the last bit of a preamble pid, and will disable them at the end of an eop. packets out of port0 are always transmitted using the full-speed drivers. all the at43312a ports independently drive and monitor their dp and dm pins so that they are able to detect and generate the ? j ? , ? k ? , and se0 bus signaling states. each hub port has single-ended and differential receivers on its dp and dm lines. the port i/o buffers comply with the voltage levels and drive requirements as specified in the usb specifications rev 1.0.
7 at43312a 1255c ? 12/01 the hub repeater implements a frame timer which is timed by the 12 mhz usb clock and gets reset every time an sof token is received from the host. serial interface engine the serial interface engine handles the usb communication protocol. it performs the usb clock/data separation, the nrzi data encoding/decoding, bit stuffing, crc genera- tion and checking, usb packet id decoding and generation, and data serialization and de-serialization. the on-chip phase locked loop generates the high frequency clock for the clock/data separation circuit. power management a hub is a high-powered device and is allowed to draw up to 500 ma of current from the host or upstream hub. the at43312a chip itself and its external hub circuitry consume much less than 100 ma. the at43312a ? s power management logic works with external devices to detect overcurrent and control power to the ports. overcurrent sensing is on a per port basis and is achieved through the ovcx pins. whenever the voltage at ovcx is asserted, the at43312a treats it as an overcurrent condition. this could be caused by an overload, or even a short circuit, and causes the at43312a to set the port ? s port_over_current status bit and its c_port_over_current status change bit. at the same time, power to the offend- ing port is shut off and its statx generates a square wave with a frequency of about 1 second. an external device is needed to monitor the overcurrent condition and perform the actual switching of the ports ? power under control of the at43312a. the signals to con- trol the external switches are the pwrx pins. any type of suitable switch or device is acceptable. however, it should have a low-voltage drop across it even when the port absorbs full-power. in its simplest form this switch can be a p-channel mosfet. one advantage of using a mosfet switch is its very low-voltage drop and low-cost. each one of the at43312a ? s port has its own power control pin which is asserted only when a setportfeature[port-power] request is received from the host. pwrx is de- asserted under the following conditions: 1. power-up 2. reset and initialization 3. overcurrent condition 4. requested by the host through a clearportfeature [port_power] for all the ports self-powered mode in the self-powered mode, power to the downstream ports must be supplied by an exter- nal power supply. this power supply must be capable of supplying 500 ma per port for a total of 2a. the usb specifications require that the voltage drop at the power switch and board traces be no more than 100 mv. a good conservative maximum drop at the power switch itself should be no more than 75 mv. careful design and selection of the power switch and pc board layout is required to meet the specifications. when using a mos- fet switch, its resistance must be 140 m ? or less under worst case conditions. a suitable mosfet switch for an at43312a based hub is an integrated high side dual mosfet switch such as the micrel mic2526.
8 at43312a 1255c ? 12/01 bus powered mode in the bus powered mode, all the power for the hub itself as well as the downstream ports is supplied by the root hub or upstream hub through the usb. only 100 ma is available for each of the hub ? s downstream devices and therefore only low power devices are supported. the power switch and overcurrent protection works exactly like the self-powered mode, except that the allowable switch resistance is higher: 700 m ? or less under the worst case condition. the diagrams of figure 2 and figure 3 show examples of the power supply and man- agement connections for a typical at43312a port in the self-powered mode and bus powered mode. figure 2. self-powered hub power supply figure 3. bus powered hub power supply gnd power supply port_power 5v output gnd switch in out flg ctl to downstream device gnd vcc at43312a pwr ovc lpstat u2 u1 ps5 bus_power gnd r1 47k gnd port power switch in out flg ctl to downstream device gnd vcc at43312a pwr ovc lpstat u2 u1 bus_power gnd
9 at43312a 1255c ? 12/01 port status pin the statx pins are signals that are not required by the usb specification. their func- tion is to allow the hub to provide feedback to the user whenever a device is properly connected to the port. an led and series resistor connected to statx can be used to provide a visual feedback. if an overcurrent condition is detected at a port, the statx of the offending port will alternately turn on and off causing an led to blink. the led will continue to blink until power to the offending port is turned off by the host or until the hub is re-enumerated. the default state of statx is inactive. after a port is enabled at43312a will assert the port ? s statx . any condition that causes the port to be disabled inactivates statx . hub controller the hub controller of the at43312a provides the mechanism for the host to enumerate the hub and the at43312a to provide the host with its configuration information. it also provides a mechanism for the host to monitor and control the downstream ports. power is applied, on a per port basis, by the hub controller upon receiving a command, set- portfeature[port_power], from the host. the at43312a must be configured first by the host before the hub controller can apply power to external devices. the hub controller contains two endpoints, endpoint0 and endpoint1 and maintains a status register, controller status register, which reflects the at43312a ? s current set- tings. at power up, all bits in this register will be set to 0 ? s. endpoint 0 endpoint 0 is the at43312a ? s default endpoint used for enumeration of the hub and exchange of configuration information and requests between the host and the at43312a. endpoint 0 supports control transfers. the hub controller supports the following descriptors: device descriptor, configuration descriptor, interface descriptor, endpoint descriptor, and hub descriptor. these descriptors are described in detail elsewhere in this document. standard usb device requests and class-specific hub requests are also supported through endpoint 0. there is no endpoint descriptor for endpoint0. endpoint 1 endpoint1, an interrupt endpoint, is used by the hub controller to send status change information to the host. the hub controller samples the changes at the end of every frame at time marker eof2 in preparation for a potential data transfer in the subsequent frame. the sampled information is stored in a byte wide register, the status change register, using a bitmap scheme. each bit in the status change register corresponds to one port as shown on the follow- ing page. table 3. control status register bit function value description 0 hub configuration status 0 1 set to 0 or 1 by a set_configuration request hub is not currently configured hub is currently configured 1 hub remote wakeup status 0 1 set to 0 or 1 by clearfeature or setfeature request default value is 0 hub is currently not enabled to request remote wakeup hub is currently enabled to request remote wakeup 2 endpoint0 stall status 0 1 endpoint0 is not stalled endpoint0 is stalled 3 endpoint1 stall status 0 1 endpoint1 is not stalled endpoint1 is stalled
10 at43312a 1255c ? 12/01 an in token packet from the host to endpoint 1 indicates a request for port change status. if the hub has not detected any change on its ports, or any changes in itself, then all bits in this register will be 0 and the hub controller will return a nak to requests on endpoint1. if any of bits 0 - 4 is 1, the hub controller will transfer the whole byte. the hub controller will continue to report a status change when polled until that particular change has been removed by a clearportfeature request from the host. no status change will be reported by endpoint 1 until the at43312a has been enumerated and configured by the host via endpoint 0. oscillator and phase-locked- loop all clock signals required to run the at43312a are derived from an on-chip oscillator. to reduce emi and power dissipation in the system, the oscillator is designed to operate with a 6 mhz crystal. an on-chip pll generates the high frequency for the clock/data separator of the serial interface engine. in the suspended state, the oscillator circuitry is turned off. to assure quick startup, a crystal with a high q, or low esr, should be used. to meet the usb hub fre- quency accuracy and stability requirements for hubs, the crystal should have an accuracy and stability of better than 100 ppm. even though the oscillator circuit would work with a ceramic resonator, its use is not recommended because a resonator would not have the frequency accuracy and stability. a 6 mhz series resonance quartz crystal with a load capacitance of approximately 10 pf is recommended. the oscillator is a special low-power design and in most cases no external capacitors and resistors are necessary. if the crystal used cannot tolerate the drive levels of the oscillator, a series resistor between osc2 and the crystal pin is recommended. the clock can also be externally sourced. in this case, connect the clock source to the osc1 pin, while leaving osc2 pin floating. the switching level at the osc1 pin can be as low as 0.47v (see table 8) and a cmos device is required to drive this pin to maintain good noise margins at the low switching level. table 4. status change register bit function value meaning 0 hub status change 0 1 no change in status change in status detected 1 port1 status change 0 1 no change in status change in status detected 2 port2 status change 0 1 no change in status change in status detected 3 port3 status change 0 1 no change in status change in status detected 4 port4 status change 0 1 no change in status change in status detected 5-7 reserved 000 default values
11 at43312a 1255c ? 12/01 figure 4. oscillator and pll connections for proper operation of the pll, an external rc filter consisting of a series rc network of 100 ? and 10 nf in parallel with a 2 nf capacitor must be connected from the lft pin to vss. to provide the best operating condition for the at43312a, careful consideration of the power supply connections are recommended. use short, low-impedance connections to all power supply lines: vcc5, and vss. use sufficient decoupling capacitors to reduce noise: 0.1 f decoupling capacitors of high quality, soldered as close as possible to the package pins are recommended. at43312a osc1 osc2 lft y1 6.000 mhz r1 100 c1 10nf c2 2nf u1
12 at43312a 1255c ? 12/01 electrical specification absolute maximum ratings* dc characteristics the values shown in this table are valid for t a = 0 c to 85 c, v cc = 4.4v to 5.25v, unless otherwise noted. operating temperature (t o ) .......................-40 c to +125 c *notice: stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reli- ability. storage temperature (t s )...........................-65 c to +150 c maximum 5v power supply (v cc5 ) ................................5.5v dc input voltage (v i ) ...............-0.3v ? v cext + 0.3, 4.6 max dc output voltage (v o ) ...........-0.3v ? v cext + 0.3, 4.6 max table 5. power supply symbol parameter condition min max unit v cc 5v power supply 4.4 5.25 v i cc 5v supply current 24 ma i ccs suspended device current 150 a table 6. usb signals: dpx, dmx symbol parameter condition min max unit v ih input level high (driven) 2.0 v v ihz input level high (floating) 2.7 v v il input level low 0.8 v v di differential input sensitivity dpx and dmx 0.2 v v cm differential command mode range 0.8 2.5 v v ol1 static output low rl of 1.5 k ? to 3.6v 0.3 v v oh1 static output high rl of 1.5 k ? to gnd 2.8 3.6 v v crs output signal crossover 1.3 2.0 v c in input capacitance 20 pf
13 at43312a 1255c ? 12/01 note: osc2 must not be used to drive other circuitry. note: 1. with external 22 ? series resistor. figure 5. data signal rise and fall time table 7. pwr , stat , ovc symbol parameter condition min max unit v ol2 output low level, pwr , stat , ovc i ol = 4 ma 0.5 v v oh2 output high level, pwr i oh = 4 ma 0.5 v cext v c out output capacitance 1 mhz 10 pf v il3 input low level 0.3 v cext v v ih3 input high level 0.7 v cext v c out output capacitance 1 mhz 10 pf table 8. oscillator signals: osc1, osc2 symbol parameter condition min max unit v lh osc1 switching level 0.47 1.20 v v hl osc1 switching level 0.67 1.44 v c x1 input capacitance, osc1 17 pf c x2 output capacitance, osc2 17 pf c 12 osc1/2 capacitance 1pf t su start-up time 6 mhz, fundamental 2 ms d l drive level v cc = 3.3v, 6 mhz crystal, 100 ? equiv. series resistor 150 w table 9. dpx, dmx driver characteristics, full-speed operation symbol parameter condition min max unit t r rise time c l = 50 pf 4 20 ns t f fall time c l = 50 pf 4 20 ns t rfm tr/tf matching 90 110 % z drv driver output resistance (1) steady state drive 28 44 ? v crs rise time fall time differential data l i n e s 10% 90% 90% 10% t r t f
14 at43312a 1255c ? 12/01 note: 1. with 6.000 mhz, 100 ppm crystal. figure 6. full-speed load table 10. dpx, dmx source timings, full-speed operation symbol parameter condition min max unit t drateq full speed data rate (1) average bit rate 11.97 12.03 mb/s t frame frame interval (1) 0.9995 1.0005 ms t rfi consecutive frame interval jitter (1) no clock adjustment 42 ns t rfiadj consecutive frame interval jitter (1) no clock adjustment 126 ns source diff driver jitter t dj1 to next transition -2 2 ns t dj2 for paired transitions -1 1 ns t fdeop source jitter for differential transition to seo transitions -2 5 ns t deop differential to eop transition skew -2 5 ns recvr data jitter tolerance t jr1 to next transition -18.5 18.5 ns t jr2 to paired transitions -9 9 ns t feopt source seo interval of eop 160 175 ns t feopr receiver seo interval of eop 82 ns t fst width of seo interval during differential transition 14 ns txd+ txd- r s c l r s c l c l = 50 pf table 11. dpx, dmx driver characteristics, low-speed operation symbol parameter condition min max unit t r rise time c l = 200 - 600 pf 75 300 ns t f fall time c l = 200 - 600 pf 75 300 ns t rfm tr/tf matching 80 125 %
15 at43312a 1255c ? 12/01 figure 7. low-speed downstream port load txd+ txd- r s c l r s c l c l = 200 pf to 600 pf 3.6v 1.5 k ? table 12. dpx, dmx hub timings, full-speed operation symbol parameter condition min max unit t hdd2 hub differential data delay without cable 44 ns hub diff driver jitter t hdj1 to n ex t tr a n s i t i o n - 3 3 n s t hdj2 to paired transition -1 1 ns t fsop data bit width distortion after sop -5 5 ns t feopd hub eop delay relative to thdd 0 15 ns t fhesk hub eop output width skew -15 15 ns table 13. dpx, dmx hub timings, low-speed operation symbol parameter condition min max unit t lhdd hub differential data delay 300 ns downstr hub diff driver jitter t lhdj1 to next transition, downst -45 45 ns t lhdj2 for paired transition, downst -15 15 ns t lukj1 to next transition, upstr -45 45 ns t lukj2 for paired transition, upstr -45 45 ns t sop data bit width distortion after sop -60 60 ns t leopd hub eop delay relative to thdd 0 200 ns t lhesk hub eop output width skew -300 300 ns
16 at43312a 1255c ? 12/01 figure 8. differential data jitter figure 9. differential-to-eop transition skew and eop width figure 10. receiver jitter tolerance t period crossover points differential data lines consecutive transitions n*t period +t xjr1 paired transitions n*t period +t xjr2 t period crossover point extended differential data lines diff. data-to- se0 skew n*t period +t deop source eop width: t feopt t leopt receiver eop width: t feopr, t leopr t period differential data lines consecutive transitions n*t period +t jr1 t jr t jr1 t jr2 consecutive transitions n*t period +t jr1
17 at43312a 1255c ? 12/01 figure 11. hub differential delay, differential jitter, and sop distortion figure 12. hub eop delay and eop skew crossover point differential data lines a. downstream hub delay with cable 50% point of initial swing upstream end of cable hub delay downstream t hdd1 crossover point downstream port crossover point hub delay upstream t hdd2 upstream port v ss v ss v ss v ss b. upstream hub delay without cable crossover point downstream port crossover point hub delay upstream t hdd1, t hdd2 upstream port or end of cable v ss v ss c. upstream hub delay with or without cable crossover point extended downstream port a. downstream eop delay with cable 50% point of initial swing upstream end of cable upstream port v ss v ss v ss v ss b. downstream eop delay without cable downstream port upstream port or end of cable v ss v ss c. upstream eop delay with or without cable t eop- t eop+ crossover point extended downstream port t eop- t eop+ crossover point extended crossover point extended t eop- t eop+ crossover point extended
18 at43312a 1255c ? 12/01 table 14. hub event timings symbol parameter condition min max unit t dcnn time to detect a downstream port connect event awake hub suspended hub 2.5 2.5 2000 12000 s s t ddis time to detect a disconnect event and downstream port awake hub suspended hub 2.5 2.5 2.5 10000 s s t ursm time from detecting downstream resume to rebroadcast 100 s t drst duration of driving reset to a downstream device only for a setportfeature (port_reset) request 10 20 ms t urlk time to detect a long k from upstream 2.5 100 s t urlseo time to detect a long seo from upstream 2.5 10,000 s t urpseo time of repeating seo upstream 23 fs bit time
19 at43312a 1255c ? 12/01 0 ordering information ordering code package operating range at43312a-6ac AT43312A-6PC at43312a-6sc 32a 32p6 32r commercial (0 c to 70 c) package type 32a 32-lead, low-profile (1.4 mm) plastic quad flat package (lqfp) 32r 32-lead, 0.440" wide, plastic gull wing small outline (soic) 32p6 32-lead, 0.600" wide, plastic dual inline package (pdip)
20 at43312a 1255c ? 12/01 packaging information 32a 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 32a, 32-lead, 7 x 7 mm body size, 1.0 mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (tqfp) b 32a 10/5/2001 pin 1 identifier 0?~7? pin 1 notes: 1. this package conforms to jedec reference ms-026, variation aba. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10 mm maximum. common dimensions (unit of measure = mm) symbol min nom max note a 1.20 a1 0.05 0.15 a2 0.95 1.00 1.05 d 8.75 9.00 9.25 d1 6.90 7.00 7.10 note 2 e 8.75 9.00 9.25 e1 6.90 7.00 7.10 note 2 b 0.30 0.45 c 0.09 0.20 l 0.45 0.75 e 0.80 typ l c a1 a2 a d1 d e e1 e b
21 at43312a 1255c ? 12/01 32r 0.508(0.020) 0.356(0.014) 11.30(0.445) 11.05(0.435) 14.40(0.567) 14.05(0.553) 1.27(0.050) bsc 2.54(0.100) 2.29(0.090) 21.08(0.830) 20.83(0.820) 0.254(0.010) 0.102(0.004) 0.22(0.0085) 0.10(0.0040) 1.04(0.041) 0.53(0.021) pin 1 dimensions in millimeters and (inches). controlling dimension: inches. 0 o ~ 8 o 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 32r , 32-lead, 0.440" body, plastic gull wing small outline (soic) a 32r 04/11/01
22 at43312a 1255c ? 12/01 32p6 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 32p6 , 32-lead (0.600"/15.24 mm wide) plastic dual inline package (pdip) b 32p6 09/28/01 pin 1 e1 a1 b ref e b1 c l seating plane a 0 ~ 15 d e eb common dimensions (unit of measure = mm) symbol min nom max note a 4.826 a1 0.381 d 41.783 42.291 note 1 e 15.240 15.875 e1 13.462 13.970 note 1 b 0.356 0.559 b1 1.041 1.651 l 3.048 3.556 c 0.203 0.381 eb 15.494 17.526 e 2.540 typ note: 1. dimensions d and e1 do not include mold flash or protrusion. mold flash or protrusion shall not exceed 0.25 mm (0.010").
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