83240-580-00 b ISP1240 1 features n 64-bit pci host bus interface, complaint with pci local bus speci?cation revision 2.1 n compliance with ansi fast-20 standard x3t10/1071d n compliance with ansi x3t10/855d scsi-3 parallel interface (spi) standard n supports fast, wide, and ultra (fast-20) scsi data transfer rates n two concurrently operating wide, ultra scsi channels n supports single-ended and differential scsi n scsi initiator and target modes of operation n onboard risc processor to execute operations at the i/o control-block level from the host memory n supports pci dual-address cycle (64-bit addressing) n scsi operations executed from start to ?nish without host intervention n simultaneous, multiple logical threads n supports jtag boundary scan product description the ISP1240 adds dual channel, ultra scsi support to the expanding functionality of the isp product family. the ISP1240 is a single-chip, highly integrated, bus master, dual-channel scsi i/o processor for scsi initiator and target applications. this device interfaces the 64-bit pci bus to two ultra scsi buses and contains an onboard risc processor. the ISP1240 is a fully autonomous device, capable of managing multiple i/o operations and associated data transfers simultaneously on two scsi channels from start to ?nish without host intervention. the ISP1240 is host-software compatible with the qlogic single channel isp1040, requiring only a minor input/output control block (iocb) change to select the additional channel. the ISP1240 block diagram is illustrated in ?gure 1. figure 1. ISP1240 block diagram dma bus 0 scsi engines pci interface host memory host software driver request queue response queue 64-bit pci bus iocbs 512-byte fifo wcs and buffers sequencers ctrl regs fifo wcs and buffers sequencers ctrl regs dma bus 1 sxp 0 sxp 1 command fifo dma control mailbox registers ctrl/config registers risc register file alu boot code memory interface ultra wide scsi bus 0 ultra wide scsi bus 1 ISP1240 data fifo 512-byte data fifo 128-byte i/o bus data 16 address 16 external code/data memory flash bios nvram qlogic corporation ISP1240 intelligent, dual scsi processor data sheet
2 ISP1240 83240-580-00 b qlogic corporation isp initiator and target firmware the ISP1240 ?rmware implements a cooperative, multitasking host adapter that provides the host system with complete scsi command and data transport capabilities, thus freeing the host system from the demands of the scsi bus protocol. the ?rmware provides two interfaces to the host system: the command interface and the scsi transport interface. the single-threaded command interface facilitates debugging, con?guration, and error recovery. the multithreaded scsi transport interface maximizes use of the scsi and host buses. the ISP1240 can switch between initiator and target modes. software drivers bios ?rmware is available for the ISP1240. software drivers are available for the following operating systems: n aix n i 2 o n dos/windows n novell netware n os/2 n sco unix n unixware n windows 95 n windows nt subsystem organization to maximize i/o throughput and improve host and scsi bus utilization, the ISP1240 incorporates a high-speed, proprietary risc processor; two intelligent scsi bus controllers (scsi executive processor [sxp]); and a host bus, three-channel, ?rst-party dma controller. the scsi bus controllers and the host bus dma controller operate independently and concurrently under the control of the onboard risc processor for maximum system performance. the ISP1240 risc interface requires external program data memory. the complete i/o subsystem solution using the ISP1240 and associated supporting memory devices is shown in ?gure 2. interfaces the ISP1240 interfaces consist of the 64-bit pci bus interface, two scsi interfaces, and the risc interface. pins that support these interfaces and other chip operations are shown in ?gure 3. ISP1240 scsi 16 scsi targets target target pci i/f scsi i/f risc code/data memory pci host memory iocb data 64 figure 2. i/o subsystem design using the ISP1240 p c i b u s scsi i/f scsi 16 scsi targets target target
83240-580-00 b ISP1240 3 qlogic corporation pci interface the ISP1240 pci interface supports the following: n 64-bit, intelligent bus master, burst dma host interface for fetching i/o control blocks and data transfers n 64-bit host memory addressing (dual address cycle) n backward compatible to 32-bit pci n three-channel dma controller n 512-byte data dma fifo per channel and 128-byte command dma fifo with threshold control n 16-bit slave mode for communication with host n pipelined dma registers for ef?cient scatter/gather operations n 32-bit dma transfer counter for i/o transfer lengths of up to four gigabytes figure 3. ISP1240 functional signal grouping if risc interface vdd vss power and ground misc control bsy cd diffm diffs earb ebsy eig erst scsi interface channel 0 and channel 1 ISP1240 r oe ecs3-0 raddr15-0 iocs a ck a tn io msg esel req rst sd15-0 sdp1-0 sel esd trig tstout etg reset clk riscstb we scsi differential interface channel 0 and channel 1 rdata15-0 testmode2-0 reset nvdati nvcs nvdato nvclk nvram control pod bsyled gpio3-0 rdpar frame pci bus interface st op ad63-0 trd y devsel perr idsel serr ird y breq cbe7-0 par, par64 int a bclk bgnt a ck64 req64 idenb tdo tdi tms tck jtag interface trst flash bios pdata7-0 flashcs flashoe flashwr extint
4 ISP1240 83240-580-00 b qlogic corporation n support for subsystem id n support for ?ash bios prom n support for pci cache commands n 3.3v and 5.0v tolerant pci i/o buffers the ISP1240 is designed to interface directly to the pci bus and operate as a 64-bit, dma bus master. this operation is accomplished through a pci bus interface unit (pbiu) that contains an onboard dma controller. the pbiu generates and samples pci control signals, generates host memory addresses, and facilitates the transfer of data between host memory and the onboard dma fifo. it also allows the host to access the ISP1240 internal registers and communicate with the onboard risc processor through the pci target mode operation. the ISP1240 onboard dma controller consists of three independent dma channels that initiate transactions on the pci bus and transfer data between the host memory and dma fifo. the three dma channels consist of the command dma channel and two data dma channels. the command dma channel is used mainly by the risc processor for small transfers such as fetching commands from and writing status information to the host memory over the pci bus. the data dma channels transfer data between two scsi buses and the pci bus. the pbiu internally arbitrates between the data dma channels and the command dma channel and alternately services them. each dma channel has a set of dma registers that are programmed for transfers by the risc processor. scsi executive processors each ISP1240 sxp supports the following: n 8- or 16-bit data transfers n ultra scsi (fast-20) synchronous data transfer rates up to 40 mbytes/sec n asynchronous scsi data transfer rates up to 12 mbytes/sec n programmable scsi processor r specialized instruction set with 16-bit microword r 384-bit by 16-bit internal ram control store n 32-bit, con?gurable scsi transfer counter n command, status, message in, and message out buffers n device information storage area n on-chip, single-ended scsi transceivers (48-ma drivers) n programmable active negation the sxp provides an autonomous, intelligent scsi interface capable of handling complete scsi operations. the sxp interrupts the risc processor only to handle higher level functions such as threaded operations or error handling. risc processor the ISP1240 risc processor supports the following: n execution of multiple i/o control blocks from the host memory n reduced host intervention and interrupt overhead n one interrupt or less per i/o operation the onboard risc processor enables the ISP1240 to handle complete i/o transactions with no intervention from the host. the ISP1240 risc processor controls the chip interfaces; executes simultaneous, multiple input/output control blocks (iocb) for both scsi channels; and maintains the required thread information for each transfer. packaging the ISP1240 is available in a 352-pin thermally enhanced ball grid array (te bga) package. aix is a trademark of ibm corporation. dos, os/2, windows nt, and windows 95 are trademarks or registered trademarks of microsoft corp. novell and netware are registered trademarks of novell, inc. sco unix is a registered trademark of santa cruz operations. unix is a trademark of at&t bell laboratories. all other brand and product names are trademarks or registered trademarks of their respective holders. ?july 29, 1997 qlogic corporation, 3545 harbor blvd., costa mesa, ca 92626, (800) on-chip-1 or (714) 438-2200 speci?cations are subject to change without notice. qlogic is a trademark of qlogic corporation.
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