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preliminary spread spectrum 3 dimm system frequency synthesizer w/agp W127/W127-a cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-07225 rev. *a revised december 14, 2002 features ? maximized emi suppression using cypress?s spread spectrum technology i 2 c interface four copies of cpu output six copies of pci output two copies of agp output one copy of 48-mhz usb output one copy of 24-mhz sio output twelve copies of sdram output one buffered copy of 14.318-mhz reference input mode input pin selects optional power management in- put control pins (reconfigures pins 29, 30, 31, and 32) smooth frequency transition upon frequency reselection available in 48-pin ssop (300 mils) standard W127 device supports up to 112-mhz opera- tions. high-performance option W127-a supports up to 124-mhz. key specifications supply voltages: .......... v ddq3 = 3.3v, v ddq2 = 3.3v or 2.5v cpu cycle to cycle jitter: ...........................................250 ps cpu to agp skew: ................................................. 0500 ps agp to pci skew: .................................. 1.5 ns (agp leads) cpu output edge rate: ............................................ > 1 v/ns sdram output edge rate:.................................... > 1.5 v/ns note: all skews are optimized @v ddq2 = v ddq3 = 3.3v5%. skews are not guaranteed for v ddq2 = 2.5v. . notes: 1. configuration ? 110 ? is supported by W127-a only (see shaded row of table 1 ). 2. signal names with ? * ? denote pins have internal 250k pull-up resistor, though not relied upon for pulling to v ddq3 . signal names with parenthesis denote function is selectable by mode pin strapping. table 1. pin selectable frequency [1] input address cpu (mhz) agp (mhz) pci (mhz) fs2 fs1 fs0 0 0 0 68.5 68.5 34.25 001 112 74.6 37.3 0 1 0 95.25 63.5 31.75 0 1 1 100 66.6 33.3 1 0 0 83.3 55.53 27.77 1 0 1 75.0 75 37.5 1 1 0 124 82.6 41.3 1 1 1 66.6 66.6 33.3 block diagram pin configuration [2] vddq3 vddq3 ref/sd_sel* gnd x1 x2 vddq3 pci_f/fs2* pci0 gnd pci1 pci2 pci3 pci4 gnd gnd agp_f/mode* agp0 vddq3 sdram11 sdram10 vddq3 sdata vddq3 W127/W127-a 48mhz/fs1* 24mhz/fs0* gnd gnd cpu0 cpu1 vddq2 cpu2 cpu3 gnd sdram0 sdram1 vddq3 sdram2 sdram3 gnd sdram4(agp_stop#)* sdram5(pwr_dwn#)* sdram6(cpu_stop#)* sdram7(pci_stop#)* gnd sdram8 sdram9 sclock 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 vddq3 sdram0:11 agp_f/mode agp0 xtal osc pll ref 1 x2 x1 pci_f/fs2 (pwr_dwn#) power down control 48mhz/fs1 24mhz/fs0 pll2 serial port sclock sdata device (cpu_stop#) control 2 1 i/o i/o vddq3 12 2 i/o ref/sd_sel pll1 freq 1.5 cpu0:3 cpu stop pci0:4 agp stop (agp_stop#) pci stop (pci_stop#) sdram stop i/o i/o / 5 4 vddq3 vddq2
W127/W127-a preliminary document #: 38-07225 rev. *a page 2 of 20 pin definitions pin name pin no. pin type pin description cpu0:3 44, 43, 41, 40 o cpu clock outputs 0 through 3: these four cpu clock outputs are controlled by the cpu_stop# control pin. output voltage swing is controlled by voltage applied to vddq2. pci_f/fs2 8 i/o free-running pci clock output and frequency selection bit 2: as an output, this pin works in conjunction with pci0:4. output voltage swing is controlled by voltage applied to vddq3. when an input, this pin functions as part of the frequency selection address. the value of fs0:2 determines the power-up default frequency of device output clocks as per table 1 , ? pin selectable frequency ? on page 1. pci0:4 9, 11, 12, 13, 14 o pci clock outputs 0 through 4: output voltage swing is controlled by voltage applied to vddq3. outputs are held low if pci_stop# is set low. sdram0:3 sdram8:11 38, 37, 35, 34, 27, 26, 21, 20 o sdram clock outputs: these eight sdram clock outputs run synchronous to the cpu clock outputs or agp clock output as selected using sd_sel per table 2 . sdram4:7 32, 31, 30, 29 i/o sdram clock outputs: these four sdram clock outputs run synchronous to the cpu clock outputs or agp clock output as selected using sd_sel per table 2 . if programmed as inputs, (refer to mode pin description), these pins are used for stop_ cpu, agp, pci, and power-down control. 48mhz/fs1 48 i/o 48-mhz output and frequency selection bit 1: fixed clock output that defaults to 48 mhz following device power-up. when an input, this pin functions as part of the frequency selection address. the value of fs0:2 determines the power-up default frequency of device output clocks as per table 1 , ? pin selectable frequency ? on page 1. 24mhz/fs0 47 i/o 24-mhz output and frequency selection bit 0: fixed clock output that defaults to 24 mhz following device power-up. when an input, this pin functions as part of the frequency selection address. the value of fs0:2 determines the power-up default frequency of device output clocks as per table 1 , ? pin selectable frequency ? on page 1. agp_f/mode 17 i/o free-running agp output and mode control input: as an output, this pin works in conjunction with agp0 and is a free running clock. when an input, it determines the functions for pin 29, 30, 31, and 32. see table 3 . agp0 18 o agp output: this output is controlled by the agp_stop# pin. ref/sd_sel 3 i/o fixed 14.318-mhz and sdram output selection: as an output, this pin is used for various system applications. output voltage swing is controlled by voltage applied to vddq3. when an input, this pin selects the sdram to run synchronous to either cpu or agp. see table 2 . x1 5 i crystal connection or external reference frequency input: this pin has dual functions. it can be used as an external 14.318-mhz crystal connection or as an external reference frequency input. x2 6 i crystal connection: an input connection for an external 14.318-mhz crystal. if using an external reference, this pin must be left unconnected. sdata 23 i serial data input: data input for serial data interface. refer to serial data inter- face section that follows. sclock 25 i serial clock input: clock input for serial data interface. refer to serial data interface section that follows. vddq3 1, 2, 7, 19, 22, 24, 36 p power connection: connected to 3.3v supply. vddq2 42 p power connection: power supply for cpu0:3 clock outputs. (3.3v supply) gnd 4, 10, 15, 16, 28, 33, 39, 45, 46 g ground connection: connect all ground pins to the common system ground plane.
W127/W127-a preliminary document #: 38-07225 rev. *a page 3 of 20 W127/W127-a pin selection tables overview the W127/W127-a was designed specifically to provide all clock signals required for a motherboard designed with the via mvp3 chipset using either a pentium ? or k6 microprocessor. although it can be used with split voltages (3.3/2.5), the skew specifications are guaranteed only for single 3.3v supply. the primary distinguishing feature of the W127/W127-a is the 95.25-mhz cpu frequency option, which supports the k6 333- mhz cpu. twelve sdram outputs are provided for support of up to 3 sdram dimm modules. unused clock outputs can be dis- abled through the i 2 c interface to reduce system power con- sumption and more importantly reduce emi emissions. functional description i/o pin operation pins 3, 8, 17, 47, and 48 are dual-purpose l/o pins. upon power-up these pins act as logic inputs, allowing the determi- nation of assigned device functions. a short time after power- up, the logic state of each pin is latched and the pins then become clock outputs. this feature reduces device pin count by combining clock outputs with input select pins. an external 10-k ? ? strapping ? resistor is connected between each l/o pin and ground or v ddq3 . connection to ground sets a latch to ? 0, ? connection to v ddq3 sets a latch to ? 1. ? figure 1 and figure 2 show two suggested methods for strapping resis- tor connection. upon W127/W127-a power-up, the first 2 ms of operation is used for input logic selection. during this period, the 24-mhz, 48-mhz, ref, pci_f and agp_f clock output buffers are three-stated, allowing the output strapping resistor on each l/o pin to pull the pin and its associated capacitive clock load to either a logic high or logic low state. at the end of the 2-ms period, the established logic 0 or 1 condition of each l/o pin is latched. next the output buffers are enabled, converting all l/o pins into operating clock outputs. the 2-ms timer starts when v ddq3 reaches 2.0v. the input bits can only be reset by turn- ing v ddq3 off and then back on again. it should be noted that the strapping resistors have no signifi- cant effect on clock output signal integrity. the drive imped- ance of the clock output is 40 ? (nominal), which is minimally affected by the 10-k ? strap to ground or v ddq3 . as with the series termination resistor, the output strapping resistor should be placed as close to the l/o pin as possible in order to keep the interconnecting trace short. the trace from the resistor to ground or v ddq3 should be kept less than two inches in length to prevent system noise coupling during input logic sampling. when the clock outputs are enabled following the 2-ms input period, target (normal) output frequency is delivered, assum- ing that v ddq3 has stabilized. if v ddq3 has not yet reached full value, output frequency initially may be below target but will increase to target once v ddq3 voltage has stabilized. in either case, a short output clock cycle may be produced from the cpu clock outputs when the outputs are enabled. table 2. sd_sel function sd_sel sdram0:11 1 running @ cpu frequency 0 running @ agp frequency table 3. mode function pin function mode pin 29 pin 30 pin 31 pin 32 1 sdram7 sdram6 sdram5 sdram4 0 pci_stop# cpu_stop# pwr_dwn# agp_stop# table 4. power management pin function signal =0 =1 cpu_stop# cpu0:3 & sdram0:11 = low active pci_stop# pci0:4 = low active agp_stop# agp0 = low active pwr_dwn# all clock outputs low active
W127/W127-a preliminary document #: 38-07225 rev. *a page 4 of 20 cpu/pci frequency selection cpu output frequency is selected with i/o pins 8, 47, and 48. refer to table 1 for cpu/pci frequency programming informa- tion. alternatively, frequency selections are available through the serial data interface. refer to table 8 , ? additional frequen- cy selections through serial data interface data bytes, ? on page 9. output buffer configuration clock outputs all clock outputs are designed to drive serially terminated clock lines. the W127/W127-a outputs are cmos-type, which pro- vide rail-to-rail output swing. crystal oscillator the W127/W127-a requires one input reference clock to syn- thesize all output frequencies. the reference clock can be ei- ther an externally generated clock signal or the clock generat- ed by the internal crystal oscillator. when using an external clock signal, pin x1 is used as the clock input and pin x2 is left open. the input threshold voltage of pin x1 is (v ddq3 )/2. the internal crystal oscillator is used in conjunction with a quartz crystal connected to device pins x1 and x2. this forms a parallel resonant crystal oscillator circuit. the W127/W127-a incorporates the necessary feedback resistor and crystal load capacitors. including typical stray circuit capacitance, the total load presented to the crystal is approximately 20 pf. for opti- mum frequency accuracy without the addition of external ca- pacitors, a parallel-resonant mode crystal specifying a load of 20 pf should be used. this will typically yield reference fre- quency accuracies within 100 ppm. to achieve similar accu- racies with a crystal calling for a greater load, external capac- itors must be added such that the total load (internal, external, and parasitic capacitors) equals that called for by the crystal. power-on reset timer output three-state data latch hold qd W127/W127-a v ddq3 clock load r 10 k ? output buffer (load option 1) 10 k ? (load option 0) output low output strapping resistor series termination resistor figure 1. input logic selection through resistor load option power-on reset timer output three-state data latch hold qd W127/W127-a v dd clock load r 10 k ? output buffer output low output strapping resistor series termination resistor jumper options figure 2. input logic selection through jumper option
W127/W127-a preliminary document #: 38-07225 rev. *a page 5 of 20 spread spectrum generator the device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. by increasing the bandwidth of the fundamental and its harmonics, the am- plitudes of the radiated electromagnetic emissions are re- duced. this effect is depicted in figure 3 . as shown in figure 3 , a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. the reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. the equation for the reduction is: db = 6.5 + 9*log 10 (p) + 9*log 10 (f) where p is the percentage of deviation and f is the frequency in mhz where the reduction is measured. the output clock is modulated with a waveform depicted in figure 4 . this waveform, as discussed in ? spread spectrum clock generation for the reduction of radiated emissions ? by bush, fessler, and hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. the deviation selected for this chip is 0.5% of the center frequen- cy. figure 4 details the cypress spreading pattern. cypress does offer options with more spread and greater emi reduc- tion. contact your local sales representative for details on these devices. spread spectrum clocking is activated or deactivated by se- lecting the appropriate values for bits 1 ? 0 in data byte 0 of the i 2 c data stream. refer to table 7 for more details. figure 3. clock harmonic with and without sscg modulation frequency domain representation figure 4. typical modulation profile max (+.0.5%) min. ( ? 0.5%) 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% frequency
W127/W127-a preliminary document #: 38-07225 rev. *a page 6 of 20 serial data interface the W127/W127-a features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. upon power-up, the W127/W127-a initializes with default register settings, there- fore the use of this serial data interface is optional. the serial interface is write-only (to the clock chip) and is the dedicated function of device pins sdata and sclock. in motherboard applications, sdata and sclock are typically driven by two logic outputs of the chipset. clock device register changes are normally made upon system initialization, if any are required. the interface can also be used during system operation for power management functions. table 5 summarizes the control functions of the serial data interface. operation data is written to the W127/W127-a in ten bytes of eight bits each. bytes are written in the order shown in table 6 . table 5. serial data interface control functions summary control function description common application clock output disable any individual clock output(s) can be disabled. dis- abled outputs are actively held low. unused outputs are disabled to reduce emi and system power. examples are clock out- puts to unused sdram dimm socket or pci slot. cpu clock frequency selection provides cpu/pci frequency selections. frequen- cy is changed in a smooth and controlled fashion. for alternate cpu devices and power man- agement options. smooth frequency transi- tion allows cpu frequency change under nor- mal system operation. output three-state puts all clock outputs into a high-impedance state. production pcb testing. (reserved) reserved function for future device revision or pro- duction device testing. no user application. register bit must be writ- ten as 0. table 6. byte writing sequence byte sequence byte name bit sequence byte description 1 slave address 11010010 commands the W127/W127-a to accept the bits in data bytes 0 ? 6 for internal register configuration. since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. the slave receiver address for the W127/W127-a is 11010010. register setting will not be made if the slave address is not correct (or is for an alternate slave receiver). 2 command code don ? t care unused by the W127/W127-a, therefore bit values are ignored ( ? don ? t care ? ). this byte must be included in the data write sequence to maintain proper byte allocation. the command code byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. 3 byte count don ? t care unused by the W127/W127-a, therefore bit values are ignored ( ? don ? t care ? ). this byte must be included in the data write sequence to maintain proper byte allocation. the byte count byte is part of the standard serial communication protocol and may be used when writing to another ad- dressed slave receiver on the serial data bus. 4 data byte 0 refer to table 7 the data bits in these bytes set internal W127/W127-a registers that control device operation. the data bits are only accepted when the ad- dress byte bit sequence is 11010010, as noted above. for description of bit control functions, refer to table 7 , data byte serial configuration map. 5data byte 1 6data byte 2 7data byte 3 8data byte 4 9data byte 5 10 data byte 6
W127/W127-a preliminary document #: 38-07225 rev. *a page 7 of 20 writing data bytes each bit in the data bytes controls a particular device function except for the ? reserved ? bits, which must be written as a logic 0. bits are written msb (most significant bit) first, which is bit 7. table 7 gives the bit formats for registers located in data bytes 0 ? 6. table 8 details additional frequency selections that are avail- able through the serial data interface. table 9 details the select functions for byte 0, bits 1 and 0. table 7. data bytes 0 ? 6 serial configuration map bit(s) affected pin control function bit control default pin no. pin name 0 1 data byte 0 7 -- -- (reserved) -- -- 0 6 -- -- sel_2 refer to table 8 0 5 -- -- sel_1 refer to table 8 0 4 -- -- sel_0 refer to table 8 0 3 8, 47, 48 fs0:2 byt0 /fs# frequency controlled by external pins fs0:2 frequency controlled by sel_0:2, above 0 2 (reserved) -- -- 0 1 ? 0 -- -- bit 1 bit 0 function (see table 9 for function details) 0 0 normal operation 0 1 (reserved) 1 0 spread spectrum on 1 1 all outputs three-stated 00 data byte 1 7 -- -- (reserved) -- -- 0 6 -- -- (reserved) -- -- 0 5 -- -- (reserved) -- -- 0 4 -- -- (reserved) -- -- 0 3 40 cpu3 clock output disable low active 1 2 41 cpu2 clock output disable low active 1 1 43 cpu1 clock output disable low active 1 0 44 cpu0 clock output disable low active 1 data byte 2 7 -- -- (reserved) -- -- 0 6 8 pci_f clock output disable low active 1 5 -- -- (reserved) -- -- 0 4 14 pci4 clock output disable low active 1 3 13 pci3 clock output disable low active 1 2 12 pci2 clock output disable low active 1 1 11 pci1 clock output disable low active 1 0 9 pci0 clock output disable low active 1
W127/W127-a preliminary document #: 38-07225 rev. *a page 8 of 20 data byte 3 7 29 sdram7 clock output disable low active 1 6 30 sdram6 clock output disable low active 1 5 31 sdram5 clock output disable low active 1 4 32 sdram4 clock output disable low active 1 3 34 sdram3 clock output disable low active 1 2 35 sdram2 clock output disable low active 1 1 37 sdram1 clock output disable low active 1 0 38 sdram0 clock output disable low active 1 data byte 4 7 -- -- (reserved) -- -- 0 6 -- -- (reserved) -- -- 0 5 17 agp_f clock output disable low active 1 4 18 agp0 clock output disable low active 1 3 20 sdram11 clock output disable low active 1 2 21 sdram10 clock output disable low active 1 1 26 sdram9 clock output disable low active 1 0 27 sdram8 clock output disable low active 1 data byte 5 7 -- -- (reserved) -- -- 0 5 -- -- (reserved) -- -- 0 5 -- -- (reserved) -- -- 0 4 -- -- (reserved) -- -- 0 3 -- -- (reserved) -- -- 0 2 -- -- (reserved) -- -- 0 1 -- -- (reserved) -- -- 0 0 3 ref clock output disable low active 1 data byte 6 7 -- -- (reserved) -- -- 0 6 -- -- (reserved) -- -- 0 5 -- -- (reserved) -- -- 0 4 -- -- (reserved) -- -- 0 3 -- -- (reserved) -- -- 0 2 -- -- (reserved) -- -- 0 1 -- -- (reserved) -- -- 0 0 -- -- (reserved) -- -- 0 table 7. data bytes 0 ? 6 serial configuration map (continued) bit(s) affected pin control function bit control default pin no. pin name 0 1
W127/W127-a preliminary document #: 38-07225 rev. *a page 9 of 20 notes: 3. configuration ? 110 ? is supported by W127-a only (see shaded row of table 8 ). 4. cpu, sdram, and pci frequency selections are listed in table 1 and table 8 . table 8. additional frequency selections through serial data interface data bytes [3] input conditions output frequency data byte 0, bit 3 = 1 cpu clocks (mhz) agp pci clocks (mhz) bit 6 sel_2 bit 5 sel_1 bit 4 sel_0 0 0 0 68.5 68.5 34.25 0 0 1 112 74.6 37.3 0 1 0 95.25 63.5 31.75 0 1 1 100 66.6 33.3 1 0 0 83.3 55.53 27.77 1 0 1 75.07537.5 1 1 0 124 82.6 41.3 1 1 1 66.666.633.3 table 9. select function for data byte 0, bits 0:1 function input conditions output conditions data byte 0 cpu0:3, sram0:11 pci_f, pci0:4 ref 48/24mhz bit 1 bit 0 normal operation 0 0 note 4 note 4 14.318 mhz 48/24 mhz spread spectrum 1 0 0.5% 0.5% 14.318 mhz 48/24 mhz three-state 1 1 hi-z hi-z hi-z hi-z
W127/W127-a preliminary document #: 38-07225 rev. *a page 10 of 20 how to use the serial data interface electrical requirements figure 5 illustrates electrical characteristics for the serial inter- face bus used with the W127/W127-a. devices send data over the bus with an open drain logic output that can (a) pull the bus line low, or (b) let the bus default to logic 1. the pull-up re- sistors on the bus (both clock and data lines) establish a de- fault logic 1. all bus devices generally have logic inputs to re- ceive data. although the W127/W127-a is a receive-only device (no data write-back capability), it does transmit an ? acknowledge ? data pulse after each byte is received. thus, the sdata line can both transmit and receive data. the pull-up resistor should be sized to meet the rise and fall times specified in ac parameters, taking into consideration total bus line capacitance. data in data out n clock in clock out chip set (serial bus master transmitter) sdclk sdata serial bus clock line serial bus data line n data in data out clock in clock device (serial bus slave receiver) sclock sdata n ~ 2k ? ~ 2k ? vdd vdd figure 5. serial interface bus electrical characteristics
W127/W127-a preliminary document #: 38-07225 rev. *a page 11 of 20 signaling requirements as shown in figure 6 , valid data bits are defined as stable logic 0 or 1 condition on the data line during a clock high (logic 1) pulse. a transitioning data line during a clock high pulse may be interpreted as a start or stop pulse (it will be interpreted as a start or stop pulse if the start/stop timing parameters are met). a write sequence is initiated by a ? start bit ? as shown in figure 7 . a ? stop bit ? signifies that a transmission has ended. as stated previously, the W127/W127-a sends an ? acknowl- edge ? pulse after receiving eight data bits in each byte as shown in figure 8 . sdata sclock valid data bit change of data allowed figure 6. serial data bus valid data bit sdata sclock start bit stop bit figure 7. serial data bus start and stop bit
W127/ W127-a preliminary document #: 38-07225 rev. *a page 12 of 20 figure 8. serial data bus write sequence msb 12345678a12345678a 1234 sclock 12345678a 11 01 001 0 lsb msb msb lsb sdata sdata signaling from system core logic start condition msb lsb slave address (first byte) command code (second byte) last data byte (last byte) byte count (third byte) stop condition signaling by clock device acknowledgment bit from clock device figure 9. serial data bus timing diagram t sthd t low t r t high t f t dsu t dhd t sp t spsu t sthd t spsu t spf sdata sclock
W127/ W127-a preliminary document #: 38-07225 rev. *a page 13 of 20 absolute maximum ratings [5.] stresses greater than those listed in this table may cause per- manent damage to the device. these represent a stress rating only. operation of the device at these or any other conditions above those specified in the operating sections of this specifi- cation is not implied. maximum conditions for extended peri- ods may affect reliability. . parameter description rating unit v ddq3 , v in voltage on any pin with respect to gnd ? 0.5 to +7.0 v t stg storage temperature ? 65 to +150 c t b ambient temperature under bias ? 55 to +125 c t a operating temperature 0 to +70 c esd prot input esd protection 2 (min.) kv 3.3v dc electrical characteristics t a = 0 c to +70 c, v ddq3 = v ddq2 = 3.3v5% (3.135 ? 3.465v) parameter description test condition min. typ. max. unit supply current i dd combined 3.3v supply current cpu0:3 = 66.6 mhz outputs loaded [5] 290 ma logic inputs v il input low voltage 0.8 v v ih input high voltage 2.0 v i il input low current [7] 20 a i ih input high current 5a clock outputs v ol output low voltage i ol = 1 ma 50 mv v oh output high voltage i oh = ? 1 ma 3.1 v i ol output low current cpu0:3 v ol = 1.5v 55 75 105 ma sdram0:11, agp_f, agp0 80 110 155 pci_f, pci0:4 55 75 105 ref 607590 48/24mhz 55 75 105 i oh output high current cpu0:3 v oh = 1.5v 55 85 125 ma sdram0:11, agp_f, agp0 80 120 175 pci_f, pci0:4 55 85 125 ref 60 85 110 48/24mhz 55 85 125 crystal oscillator v th x1 input threshold voltage [8] 1.65 v c load load capacitance, imposed on external crystal [9] 20 pf c in,x1 x1 input capacitance [10] pin x2 unconnected 30 pf notes: 5. multiple supplies : the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequencing is not required. 6. all clock outputs loaded with maximum lump capacitance test load specified in ac electrical characteristics section. 7. W127/127-a logic inputs have internal pull-up devices (not full cmos level). 8. x1 input threshold voltage (typical) is v dd /2. 9. the W127/W127-a contains an internal crystal load capacitor between pin x1 and ground and another between pin x2 and ground. total load placed on crystal is 20 pf; this includes typical stray capacitance of short pcb traces to crystal. 10. x1 input capacitance is applicable when driving x1 with an external clock source (x2 is left unconnected).
W127/W127-a preliminary document #: 38-07225 rev. *a page 14 of 20 ac electrical characteristics t a = 0 c to +70 c, v ddq3 = 3.3v5% (3.35 ? 3.465v), f xtl = 14.31818 mhz spread spectrum function turned off ac clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output. pin capacitance/inductance c in input pin capacitance except x1 and x2 5 pf c out output pin capacitance 6 pf l in input pin inductance 7nh serial input port v il input low voltage v ddq3 = 3.3v 0.3v ddq3 v v ih input high voltage v ddq3 = 3.3v 0.7v ddq3 v i il input low current 10 a i ih input high current 10 a i ol sink current into sdata or sclock, open drain n-channel device on i ol = 0.3(v ddq3 )6 ma c in input capacitance of sdata and sclock 10 pf c sdata total capacitance of sdata bus 400 pf c sclock total capacitance of sclock bus 400 pf 3.3v dc electrical characteristics (continued) t a = 0 c to +70 c, v ddq3 = v ddq2 = 3.3v5% (3.135 ? 3.465v) parameter description test condition min. typ. max. unit cpu agp clock outputs, cpu0:3, agp_f, agp0 (lump capacitance test load = 20 pf) parameter description test condition/comments cpu = 66.6 mhz unit min. typ. max. t p period measured on rising edge at 1.5v 15 ns f frequency, actual determined by pll divider ratio 66.6 mhz t h high time duration of clock cycle above 2.4v 5.2 ns t l low time duration of clock cycle below 0.4v 5 ns t r output rise edge rate measured from 0.4v to 2.4v 1 4 v/ns t f output fall edge rate measured from 2.4v to 0.4v 1 4 v/ns t d duty cycle measured on rising and falling edge at 1.5v 45 55 % t jc jitter, cycle-to-cycle measured on rising edge at 1.5v. maximum differ- ence of cycle time between two adjacent cycles. 250 ps t sk output skew measured on rising edge at 1.5v 250 ps f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequen- cy stabilization. 3ms z o ac output impedance average value during switching transition. used for determining series termination value. 10 15 20 ?
W127/W127-a preliminary document #: 38-07225 rev. *a page 15 of 20 ac electrical characteristics (continued) sdram clock outputs, sdram0:11 (lump capacitance test load = 30 pf) parameter description test condition/comments cpu = 66.6 mhz unit min. typ. max. t p period measured on rising edge at 1.5v 15 ns f frequency, actual determined by pll divider ratio 66.6 mhz t r output rise edge rate measured from 0.4v to 2.4v 1 4 v/ns t f output fall edge rate measured from 2.4v to 0.4v 1 4 v/ns t d duty cycle measured on rising and falling edge at 1.5v 45 55 % t jc jitter, cycle-to-cycle measured on rising edge at 1.5v. maximum differ- ence of cycle time between two adjacent cycles. 250 ps t sk output skew measured on rising edge at 1.5v 100 ps t sk cpu to sdram clock skew covers all cpu/sdram outputs. measured on rising edge at 1.5v. 500 ps f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequen- cy stabilization. 3ms z o ac output impedance average value during switching transition. used for determining series termination value. 10 15 20 ? pci clock outputs, pci_f and pci0:4 (lump capacitance test load = 30 pf) parameter description test condition/comments cpu = 66.6 mhz unit min. typ. max. t p period measured on rising edge at 1.5v 30 ns f frequency, actual determined by pll divider ratio 33.3 mhz t h high time duration of clock cycle above 2.4v 12 ns t l low time duration of clock cycle below 0.4v 12 ns t r output rise edge rate measured from 0.4v to 2.4v 1 4 v/ns t f output fall edge rate measured from 2.4v to 0.4v 1 4 v/ns t d duty cycle measured on rising and falling edge at 1.5v 45 55 % t jc jitter, cycle-to-cycle measured on rising edge at 1.5v. maximum differ- ence of cycle time between two adjacent cycles. 250 ps t sk output skew measured on rising edge at 1.5v 250 ps t o agp to pci clock skew covers all cpu/pci outputs. measured on rising edge at 1.5v. cpu leads pci output. 13ns f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequen- cy stabilization. 3ms z o ac output impedance average value during switching transition. used for determining series termination value. 20 ?
W127/W127-a preliminary document #: 38-07225 rev. *a page 16 of 20 ac electrical characteristics (continued) ref clock output (lump capacitance test load = 45 pf) parameter description test condition/comments cpu = 66.6 mhz unit min. typ. max. f frequency, actual frequency generated by crystal oscillator 14.31818 mhz t r output rise edge rate measured from 0.4v to 2.4v 0.5 2 v/ns t f output fall edge rate measured from 2.4v to 0.4v 0.5 2 v/ns t d duty cycle measured on rising and falling edge at 1.5v 40 60 % f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 1.5 ms z o ac output impedance average value during switching transition. used for determining series termination value. 30 ? 48-/24-mhz clock outputs (lump capacitance test load = 20 pf) parameter description test condition/comments cpu = 66.6 mhz unit min. typ. max. f frequency, actual determined by pll divider ratio (see m/n below) 48.008/24.004 mhz f d deviation from 48 mhz (48.008 ? 48)/48 +167 ppm m/n pll ratio (14.31818 mhz x 57/17 = 48.008 mhz) 57/17, 54/34 t r output rise edge rate measured from 0.4v to 2.4v 0.5 2 v/ns t f output fall edge rate measured from 2.4v to 0.4v 0.5 2 v/ns t d duty cycle measured on rising and falling edge at 1.5v 45 55 % f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 3ms z o ac output impedance average value during switching transition. used for determining series termination value. 30 0 ? serial input port parameter description test condition min. typ. max. unit f sclock sclock frequency normal mode 0 100 khz t sthd start hold time 4.0 s t low sclock low time 4.7 s t high sclock high time 4.0 s t dsu data set-up time 250 ns t dhd data hold time (transmitter should provide a 300-ns hold time to ensure proper timing at the receiver.) 0ns t r rise time, sdata and sclock from 0.3v dd to 0.7v dd 1000 ns t f fall time, sdata and sclock from 0.7v dd to 0.3v dd 300 ns t stsu stop set-up time 4.0 s t spf bus free time between stop and start condition 4.7 s t sp allowable noise spike pulse width 50 ns
W127/W127-a preliminary document #: 38-07225 rev. *a page 17 of 20 pentium is a registered trademark of intel corporation. ordering information ordering code package name package type W127 h 48-pin ssop (300 mils) W127-a
W127/W127-a preliminary document #: 38-07225 rev. *a page 18 of 20 package diagram 48-pin small shrink outline package (ssop, 300 mils) summary of nominal dimensions in inches: body width: 0.296 lead pitch: 0.025 body length: 0.625 body height: 0.102
W127/W127-a preliminary document #: 38-07225 rev. *a page 19 of 20 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. addendum: W127/W127-a replaces w48s87-27a the W127/W127-a is a pin-compatible replacement for the w48s87-27a with the following output frequency modifications (refer to table 1 ): 1. the 90-mhz cpu operation is changed to 95.25-mhz to support the k6 333-mhz chipset. 2. the 60-mhz cpu operation is changed to 124-mhz to support new motherboard designs.
W127/W127-a preliminary document #: 38-07225 rev. *a page 20 of 20 document title: W127/W127-a spread spectrum 3 dimm system frequency synthesizer w/agp document number: 38-07225 rev. ecn no. issue date orig. of change description of change ** 110490 02/13/02 szv change from spec number: 38-00893 to 38-07225 *a 122842 12/14/02 rbi power up requirements added to operating conditions information

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