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spread spectrum ftg for 440bx and via apollo pro-133 W204 preliminary cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-07264 rev. *a revised december 22, 2002 features ? maximized emi suppression using cypress?s spread spectrum technology optimized system frequency synthesizer for 440bx and via apollo pro-133 four copies of cpu output eight copies of pci clock (synchronous w/cpu output) two copies of 14.318-mhz ioapic output and three buffered copies of 14.318-mhz reference input one copy of 48-mhz usb output selectable 24-/48-mhz clock-through-resistor strapping power management control input pins programmable clock outputs up to 155 mhz via smbus interface (32 selectable frequencies) key specifications supply voltages: ..................................... vddq3 = 3.3v5% vddq2 = 2.5v5% cpu cycle to cycle jitter: ..........................................250 ps cpu0:3 output skew: ................................................175 ps pci_f, pci1:7 output skew: .......................................500 ps cpu to pci output skew: ............... 1.0 ? 4.0 ns (cpu leads) ref0/sel48#, sclk,sdata:........................... 250k pull-up fs1:...............................................................250k pull-down fs0:...................................................no pull-up or pull-down test mode and output three-state through smbus interface table 1. pin selectable frequency fs1 fs0 cpu(0:3) pci 1 1 133.3 mhz 33.3 mhz 1 0 105 mhz 35 mhz 0 1 100 mhz 33.3 mhz 0 0 66.8 mhz 33.3 mhz pin configuration block diagram vddq3 ref0/sel48# vddq2 apic0 cpu0 cpu1 cpu2 cpu3 pci_f xtal pll ref freq pll 1 fs0:1 x2 x1 ref1 vddq3 stop clock control stop clock control pci1 pwr_dwn# power down control pci2 pci3 pci4 pci5 48mhz 24_48mhz/fs1 pll2 2/ 3 osc ref2 vddq2 pci_stop# cpu_stop# pci6 pci7 gnd gnd vddq3 gnd apic1 gnd gndcore0/1 vddcore0/1 vddq3 gnd gnd gnd vddq2 spread# i 2 c sdata logic sclk ref0/sel48# ref1 gnd x1 x2 gnd pci_f pci1 vddq3 pci2 pci3 gnd pci4 pci5 vddq3 pci6 pci7 gnd vddq3 gnd vddq3 48mhz 24_48mhz/fs1 gnd vddq3 ref2 vddq2 apic0 apic1 gnd nc vddq2 cpu0 cpu1 gnd vddq2 cpu2 cpu3 gnd vddq3 gnd pci_stop# cpu_stop# pwr_dwn# spread# sdata sclk fs0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 note: 1. internal pull-up resistors should not be relied upon for setting i/o pins high. [1]
W204 preliminary document #: 38-07264 rev. *a page 2 of 16 pin definitions pin name pin no. pin type pin description cpu0:3 40, 39, 36, 35 o cpu clock outputs 0 through 3: these four cpu clock outputs are controlled by the cpu_stop# control pin. output voltage swing is controlled by voltage applied to vddq2. pci1:7 8, 10, 11, 13, 14, 16, 17 o pci bus clock outputs 1 through 7: these seven pci clock outputs are controlled by the pci_stop# control pin. output voltage swing is controlled by voltage applied to vddq3. pci_f 7 o fixed pci clock output: unlike pci1:7 outputs, this output is not controlled by the pci_stop# control pin. output voltage swing is controlled by voltage applied to vddq3. cpu_stop# 30 i cpu_stop# input: when brought low, clock outputs cpu0:3 are stopped low after completing a full clock cycle (2-3 cpu clock latency). when brought high, clock outputs cpu0:3 start beginning with a full clock cycle (2-3 cpu clock latency). pci_stop# 31 i pci_stop# input: the pci_stop# input enables the pci 1:7 outputs when high and causes them to remain at logic 0 when low. the pci_stop signal is latched on the rising edge of pci_f. its effect takes place on the next pci_f clock cycle. spread# 28 i spread# input: when brought low this pin activates spread spectrum clocking. apic0:1 45, 44 o i/o apic clock outputs: provides 14.318-mhz fixed frequency. the output voltage swing is controlled by vddq2. 48mhz 22 o 48-mhz output: fixed clock outputs at 48 mhz. output voltage swing is controlled by voltage applied to vddq3. 24_48mhz/fs1 23 o 24-mhz or 48-mhz output/frequency select 1: 24 mhz output when pin 1 is strapped through 10-k ? resistor to vddq3. 48-mhz output when pin 1 is strapped through 10-k ? resistor to gnd. this pin also serves as the select strap to determine device operating frequency as described in table 1 . ref0/sel48# 1 i/o i/o dual-function ref0 and sel48# pin: during power-on, sel48# input will be latched which will set pin 23 to output 24 mhz or 48 mhz. it then reverts to ref0 fixed output. ref1:2 2, 47 o fixed 14.318-mhz outputs 1 through 2: used for various system applications. output voltage swing is controlled by voltage applied to vddq3. fs0 25 i frequency selection 0: selects power-up default cpu clock frequency as shown in table 1 . sclk 26 i clock pin for smbus circuitry. sdata 27 i/o data pin for smbus circuitry. x1 4 i crystal connection or external reference frequency input: this pin has dual functions. it can be used as an external 14.318-mhz crystal connection or as an external reference frequency input. x2 5 i crystal connection: an input connection for an external 14.318-mhz crystal. if using an external reference, this pin must be left unconnected. pwr_dwn# 29 i power-down control: when this input is low, device goes into a low-power stand- by condition. all outputs are actively held low while in power-down. cpu and pci clock outputs are stopped low after completing a full clock cycle (2 ? 3 cpu clock cycle latency). when brought high, cpu, sdram and pci outputs start with a full clock cycle at full operating frequency (3 ms maximum latency). vddq3 9, 15, 19, 21, 33, 48 p power connection: connect to 3.3v supply. vddq2 46, 41, 37 p power connection: power supply for apic0:1 and cpu0:3 output buffers. connect to 2.5v. gnd 3, 6, 12, 18, 20, 24, 32, 34, 38, 43 g ground connections: connect all ground pins to the common system ground plane.
W204 preliminary document #: 38-07264 rev. *a page 3 of 16 overview the W204, a motherboard clock synthesizer, can provide ei- ther a 2.5v or 3.3v cpu clock swing making it suitable for a variety of cpu options. a fixed 48-mhz clock is provided for other system functions. the device W204 supports spread spectrum clocking for reduced emi. functional description i/o pin operation pins 1 and 23 are dual-purpose l/o pins. upon power-up these pins act as a logic input, allowing the determination of as- signed device functions. a short time after power-up, the logic state of the pin is latched and the pin becomes a clock output. this feature reduces device pin count by combining clock out- puts with input select pins. an external 10-k ? ? strapping ? resistor is connected between the l/o pin and ground or v dd . connection to ground sets a latch to ? 0 ? , connection to v dd sets a latch to ? 1 ? . figure 1 and figure 2 show two suggested methods for strapping resistor connections. upon W204 power-up, the first 2 ms of operation is used for input logic selection. during this period, pins 1 and 23 are three-stated, allowing the output strapping resistor on the l/o pin to pull the pin and its associated capacitive clock load to either a logic high or low state. at the end of the 2-ms peri- od, the established logic ? 0 ? or ? 1 ? condition of the l/o pin is then latched. next the output buffer is enabled which converts the l/o pin into an operating clock output. the 2-ms timer is started when v dd reaches 2.0v. the input bits can only be reset by turning v dd off and then back on again. it should be noted that the strapping resistors have no signifi- cant effect on clock output signal integrity. the drive imped- ance of clock output is 40 ? (nominal) which is minimally affect- ed by the 10-k ? strap to ground or v dd . as with the series termination resistor, the output strapping resistor should be placed as close to the l/o pin as possible in order to keep the interconnecting trace short. the trace from the resistor to ground or v dd should be kept less than two inches in length to prevent system noise coupling during input logic sampling. when the clock outputs are enabled following the 2-ms input period, the associated output frequencies are delivered on the pins, assuming that v dd has stabilized. if v dd has not yet reached full value, output frequency initially may be below tar- get but will increase to target once v dd voltage has stabilized. in either case, a short output clock cycle may be produced from the cpu clock outputs when the outputs are enabled. power-on reset timer output three-state data latch hold qd W204 v dd clock load 10 k ? output buffer (load option 1) 10 k ? (load option 0) output low output strapping resistor series termination resistor figure 1. input logic selection through resistor load option power-on reset timer output three-state data latch hold qd W204 v dd clock load r 10 k ? output buffer output low output strapping resistor series termination resistor jumper options resistor value r figure 2. input logic selection through jumper option
W204 preliminary document #: 38-07264 rev. *a page 4 of 16 spread spectrum feature the device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. by increasing the bandwidth of the fundamental and its harmonics, the am- plitudes of the radiated electromagnetic emissions are re- duced. this effect is depicted in figure 3 . as shown in figure 3 , a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. the reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. the equation for the reduction is: db = 6.5 + 9*log 10 (p) + 9*log 10 (f) where p is the percentage of deviation and f is the frequency in mhz where the reduction is measured. the output clock is modulated with a waveform depicted in figure 4 . this waveform, as discussed in ? spread spectrum clock generation for the reduction of radiated emissions ? by bush, fessler, and hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. the deviation selected for this chip is 0.5% of the center frequen- cy. figure 4 details the cypress spreading pattern. cypress does offer options with more spread and greater emi reduc- tion. contact your local sales representative for details on these devices. figure 3. clock harmonic with and without sscg modulation frequency domain representation figure 4. typical modulation profile ssftg typical clock frequency span (mhz) ? 1.0 +1.0 0 ? 0.5% ? ss% +ss% amplitude (db) 5db/div +0.5% max (+0.5%) min ( ? 0.5%) 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% frequency
W204 preliminary document #: 38-07264 rev. *a page 5 of 16 serial data interface the W204 features a two-pin, serial data interface that can be used to configure internal register settings that control partic- ular device functions. upon power-up, the W204 initializes with default register settings. therefore, the use of this serial data interface is optional. the serial interface is write-only (to the clock chip) and is the dedicated function of device pins sdata and sclock. in motherboard applications, sdata and sclock are typically driven by two logic outputs of the chipset. clock device register changes are normally made upon system initialization, if required. the interface can also be used during system operation for power management func- tions. table 2 summarizes the control functions of the serial data interface. operation data is written to the W204 in ten bytes of eight bits each. bytes are written in the order shown in table 3 . table 2. serial data interface control functions summary control function description common application clock output disable any individual clock output(s) can be disabled. disabled outputs are actively held low. unused outputs are disabled to reduce emi and system power. examples are clock outputs to un- used pci slots. cpu clock frequency selection provides cpu/pci frequency selections beyond the 100- and 66.66-mhz selections that are pro- vided by the fs0:1 pins. frequency is changed in a smooth and controlled fashion. for alternate microprocessors and power man- agement options. smooth frequency transition al- lows cpu frequency change under normal system operation. output three-state puts all clock outputs into a high impedance state. production pcb testing. test mode all clock outputs toggle in relation to x1 input, in- ternal pll is bypassed. refer to table 4 . production pcb testing. (reserved) reserved function for future device revision or pro- duction device testing. no user application. register bit must be written as 0. table 3. byte writing sequence byte sequence byte name bit sequence byte description 1 slave address 11010010 commands the W204 to accept the bits in data bytes 3 ? 6 for internal register configuration. since other devices may exist on the same com- mon serial data bus, it is necessary to have a specific slave address for each potential receiver. the slave receiver address for the W204 is 11010010. register setting will not be made if the slave address is not correct (or is for an alternate slave receiver). 2 command code don ? t care unused by the W204, therefore bit values are ignored ( ? don ? t care ? ). this byte must be included in the data write sequence to maintain proper byte allocation. the command code byte is part of the standard serial com- munication protocol and may be used when writing to another addressed slave receiver on the serial data bus. 3 byte count don ? t care unused by the W204, therefore bit values are ignored ( ? don ? t care ? ). this byte must be included in the data write sequence to maintain proper byte allocation. the byte count byte is part of the standard serial communi- cation protocol and may be used when writing to another addressed slave receiver on the serial data bus. 4 data byte 0 don ? t care refer to cypress sdram drivers. 5 data byte 1 6 data byte 2 7 data byte 3 refer to table 4 the data bits in these bytes set internal W204 registers that control device operation. the data bits are only accepted when the address byte bit sequence is 11010010, as noted above. for description of bit control functions, refer to table 4 , data byte serial configuration map. 8 data byte 4 9 data byte 5 10 data byte 6
W204 preliminary document #: 38-07264 rev. *a page 6 of 16 writing data bytes each bit in the data bytes control a particular device function except for the ? reserved ? bits which must be written as a logic 0. bits are written msb (most significant bit) first, which is bit 7. table 4 gives the bit formats for registers located in data bytes 3 ? 6. table 5 details additional frequency selections that are avail- able through the serial data interface. table 6 details the select functions for byte 3, bits 1 and 0. table 4. data bytes 3 ? 6 serial configuration map bit(s) affected pin control function bit control default pin no. pin name 0 1 data byte 3 7 -- -- sel_3 refer to table 5 0 6 -- -- sel_2 refer to table 5 0 5 -- -- sel_1 refer to table 5 0 4 -- -- sel_0 refer to table 5 0 3 -- -- byt3_fs# frequency controlled by external fs0:1 pins frequency controlled by byt3 sel_(3:0) 0 2 -- -- (reserved) -- -- 0 1 ? 0 -- -- bit 1 bit 0 function (see table 6 for function details) 0 0 spread spectrum off 0 1 test mode 1 0 spread spectrum on (default) 1 1 all outputs three-stated 10 data byte 4 7 -- -- (reserved) -- -- 0 6 23 24_48mhz clock output disable low active 1 5 -- -- (reserved) -- -- 0 4 -- -- (reserved) -- -- 0 3 35 cpu3 clock output disable low active 1 2 36 cpu2 clock output disable low active 1 1 39 cpu1 clock output disable low active 1 0 40 cpu0 clock output disable low active 1 data byte 5 7 7 pci_f clock output disable low active 1 6 17 pci7 clock output disable low active 1 5 16 pci6 clock output disable low active 1 4 14 pci5 clock output disable low active 1 3 13 pci4 clock output disable low active 1 2 11 pci3 clock output disable low active 1 1 10 pci2 clock output disable low active 1 0 8 pci1 clock output disable low active 1 data byte 6 7 -- -- (reserved) -- -- 0 6 -- -- (reserved) -- -- 0 5 44 apic1 clock output disable low active 1 4 45 apic0 clock output disable low active 1 3 -- -- (reserved) -- -- 0 2 47 ref2 clock output disable low active 1 1 2 ref1 clock output disable low active 1 0 1 ref0 clock output disable low active 1
W204 preliminary document #: 38-07264 rev. *a page 7 of 16 note: 2. cpu and pci frequency selections are listed in ta ble 1 and tab le 5 . table 5. additional frequency selections through serial data interface data bytes input conditions data byte 3, bit [7:4, 1:0] output frequency if spread is on bit [1:0] bit 7 sel_3 bit 6 sel_2 bit 5 sel_1 bit 4 sel_0 cpu, sdram clocks (mhz) pci clocks (mhz) spread percentage 00 0 0 0 0 78 39 off 00 0 0 0 1 81 40.5 off 00 0 0 1 0 113.5 37.8 off 00 0 0 1 1 66.8 33.4 off 00 0 1 0 0 117 39 off 00 0 1 0 1 118.5 39.5 off 00 0 1 1 0 122 37.3 off 00 0 1 1 1 100 33.3 off 00 1 0 0 0 126 31.5 off 00 1 0 0 1 135 33.75 off 00 1 0 1 0 137 34.25 off 00 1 0 1 1 138.5 34.62 off 00 1 1 0 0 142 35.5 off 00 1 1 0 1 144 36 off 00 1 1 1 0 155 38.75 off 00 1 1 1 1 133.3 33.3 off 10 0 0 0 0 124 41.3 0.5% center 10 0 0 0 1 75 37.5 0.5% center 10 0 0 1 0 83.3 41.65 0.5% center 10 0 0 1 1 66.8 33.4 0.5% center 10 0 1 0 0 90 30 0.5% center 10 0 1 0 1 112 37.3 0.5% center 10 0 1 1 0 95 31.67 0.5% center 10 0 1 1 1 100 33.3 0.5% center 10 1 0 0 0 120 40 0.5% center 10 1 0 0 1 115 38.3 0.5% center 10 1 0 1 0 110 36.67 0.5% center 10 1 0 1 1 105 35 0.5% center 10 1 1 0 0 140 35 0.5% center 10 1 1 0 1 150 37.5 0.5% center 10 1 1 1 0 124 31 0.5% center 10 1 1 1 1 133.3 33.3 0.5% center table 6. select function for data byte 3, bits 0:1 function input conditions output conditions data byte 3 cpu0:3 pci_f, pci1:7 ref0:2, ioapic0:1 48mhz 24mhz bit 1 bit 0 spread spectrum off 0 0 note 2 note 2 14.318 mhz 48 mhz 24 mhz test mode 0 1 x1/2 cpu/2 or 3 x1 x1/2 x1/4 spread spectrum on (default) 1 0 note 2 ss%=0.5 note 2 ss%=0.5 14.318 mhz 48 mhz 24 mhz three-state 1 1 hi-z hi-z hi-z hi-z hi-z
W204 preliminary document #: 38-07264 rev. *a page 8 of 16 how to use the serial data interface electrical requirements figure 5 illustrates electrical characteristics for the serial inter- face bus used with the W204. devices send data over the bus with an open drain logic output that can (a) pull the bus line low, or (b) let the bus default to logic 1. the pull-up resistors on the bus (both clock and data lines) establish a default logic 1. all bus devices generally have logic inputs to receive data. although the W204 is a receive-only device (no data write-back capability), it does transmit an ? acknowledge ? data pulse after each byte is received. thus, the sdata line can both transmit and receive data. the pull-up resistor should be sized to meet the rise and fall times specified in ac parameters, taking into consideration total bus line capacitance. figure 5. serial interface bus electrical characteristics data in data out n clock in clock out chip set (serial bus master transmitter) sdclk sdata serial bus clock line serial bus data line n data in data out clock in clock device (serial bus slave receiver) sclock sdata n ~ 2k ? ~ 2k ? vdd vdd
W204 preliminary document #: 38-07264 rev. *a page 9 of 16 signaling requirements as shown in figure 6 , valid data bits are defined as stable logic 0 or 1 condition on the data line during a clock high (logic 1) pulse. a transitioning data line during a clock high pulse may be interpreted as a start or stop pulse (it will be interpreted as a start or stop pulse if the start/stop timing parameters are met). a write sequence is initiated by a ? start bit ? as shown in figure 7 . a ? stop bit ? signifies that a transmission has ended. as stated previously, the W204 sends an ? acknowledge ? pulse after receiving eight data bits in each byte as shown in figure 8 . sending data to the W204 the device accepts data once it has detected a valid start bit and address byte sequence. device functionality is changed upon the receipt of each data bit (registers are not double buff- ered). partial transmission is allowed meaning that a transmis- sion can be truncated as soon as the desired data bits are transmitted (remaining registers will be unmodified). trans- mission is truncated with either a stop bit or new start bit (re- start condition). figure 6. serial data bus valid data bit figure 7. serial data bus start and stop bit sdata sclock valid data bit change of data allowed sdata sclock start bit stop bit
W204 preliminary document #: 38-07264 rev. *a page 10 of 16 figure 8. serial data bus write sequence figure 9. serial data bus timing diagram msb 12345678a12345678a 1234 sclock 12345678a 11 01 001 0 lsb msb msb lsb sdata sdata signaling from system core logic start condition msb lsb slave address (first byte) command code (second byte) last data byte (last byte) byte count (third byte) stop condition signaling by clock device acknowledgment bit from clock device t sthd t low t r t high t f t dsu t dhd t sp t spsu t sthd t spsu t spf sdata sclock
W204 preliminary document #: 38-07264 rev. *a page 11 of 16 absolute maximum ratings [3] stresses greater than those listed in this table may cause per- manent damage to the device. these represent a stress rating only. operation of the device at these or any other conditions above those specified in the operating sections of this specifi- cation is not implied. maximum conditions for extended peri- ods may affect reliability. parameter description rating unit v dd , v in voltage on any pin with respect to gnd ? 0.5 to +7.0 v t stg storage temperature ? 65 to +150 c t b ambient temperature under bias ? 55 to +125 c t a operating temperature 0 to +70 c esd prot input esd protection 2 (min.) kv dc electrical characteristics: t a = 0 c to +70 c, v ddq3 = 3.3v5%, v ddq2 = 2.5v5% parameter description test condition min. typ. max. unit supply current i ddq3 3.3v supply current cpu0:3 =100 mhz outputs loaded [4] 120 ma i ddq2 2.5v supply current 60 ma logic inputs v il input low voltage gnd ? 0.3 0.8 v v ih input high voltage 2.0 v dd + 0.3 v i il input low current [5] ? 25 a i ih input high current [5] 10 a input low current (fs0) ? 5a input high current (fs0) +5 a clock outputs v ol output low voltage i ol = 1 ma 50 mv v oh output high voltage i oh = ? 1 ma 3.1 v v oh output high voltage (cpu, apic) i oh = ? 1 ma 2.2 v i ol output low current cpu0:3 v ol = 1.25v 27 57 97 ma pci_f, pci1:7 v ol = 1.5v 20.5 53 139 ma apic0:1 v ol = 1.25v 40 85 140 ma ref0:2 v ol = 1.5v 25 37 76 ma 48mhz 0:1 v ol = 1.5v 25 37 76 ma i oh output high current cpu0:3 v ol = 1.25v 25 55 97 ma pci_f, pci1:7 v ol = 1.5v 31 55 189 ma apic0:1 v ol = 1.25v 40 87 155 ma ref0:2 v ol = 1.5v 27 44 94 ma 48mhz 0:1 v ol = 1.5v 27 44 94 ma crystal oscillator v th x1 input threshold voltage [6] v ddq3 = 3.3v 1.65 v c load load capacitance, as seen by external crystal [7] 14 pf c in,x1 x1 input capacitance [8] pin x2 unconnected 28 pf notes: 3. multiple supplies: the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequencing is not required. 4. all clock outputs loaded with 6 ? 60 ? transmission lines with 20-pf capacitors. 5. W204 logic inputs have internal pull-up resistors, except fs0 (pull-ups not full cmos level). 6. x1 input threshold voltage (typical) is v dd /2. 7. the W204 contains an internal crystal load capacitor between pin x1 and ground and another between pin x2 and ground. total l oad placed on crystal is 14 pf; this includes typical stray capacitance of short pcb traces to crystal. 8. x1 input capacitance is applicable when driving x1 with an external clock source (x2 is left unconnected).
W204 preliminary document #: 38-07264 rev. *a page 12 of 16 ac electrical characteristics t a = 0 c to +70 c, v ddq3 = 3.3v5%,v ddq2 = 2.5v 5%, f xtl = 14.31818 mhz ac clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output; spread spectrum clocking is disabled. pin capacitance/inductance c in input pin capacitance except x1 and x2 5 pf c out output pin capacitance 6pf l in input pin inductance 7nh dc electrical characteristics: t a = 0 c to +70 c, v ddq3 = 3.3v5%, v ddq2 = 2.5v5% (continued) parameter description test condition min. typ. max. unit cpu clock outputs, cpu0:3 (lump capacitance test load = 20 pf) parameter description test condition/comments cpu = 66.8 mhz cpu = 100 mhz unit min. typ. max. min. typ. max. t p period measured on rising edge at 1.25v 15 15.5 10 10.5 ns t h high time duration of clock cycle above 2.0v 5.2 3.0 ns t l low time duration of clock cycle below 0.4v 5.0 2.8 ns t r output rise edge rate measured from 0.4v to 2.0v 1 4 1 4 v/ns t f output fall edge rate measured from 2.0v to 0.4v 1 4 1 4 v/ns t d duty cycle measured on rising and falling edge at 1.25v 45 55 45 55 % t jc jitter, cycle-to-cycle measured on rising edge at 1.25v. max- imum difference of cycle time between two adjacent cycles. 200 200 ps t sk output skew measured on rising edge at 1.25v 250 250 ps f st frequency stabiliza- tion from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 33ms z o ac output impedance average value during switching transi- tion. used for determining series termi- nation value. 20 20 ?
W204 preliminary document #: 38-07264 rev. *a page 13 of 16 pci clock outputs, pci1:7 and pci_f (lump capacitance test load = 30 pf parameter description test condition/comments cpu = 66.8/100 mhz unit min. typ. max. t p period measured on rising edge at 1.5v 30 ns t h high time duration of clock cycle above 2.4v 12 ns t l low time duration of clock cycle below 0.4v 12 ns t r output rise edge rate measured from 0.4v to 2.4v 1 4 v/ns t f output fall edge rate measured from 2.4v to 0.4v 1 4 v/ns t d duty cycle measured on rising and falling edge at 1.5v 45 55 % t jc jitter, cycle-to-cycle measured on rising edge at 1.5v. maximum difference of cycle time between two adjacent cycles. 250 ps t sk output skew measured on rising edge at 1.5v 500 ps t o cpu to pci clock skew covers all cpu/pci outputs. measured on rising edge at 1.5v. cpu leads pci output. 14ns f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 3ms z o ac output impedance average value during switching transition. used for determining series termination value. 30 ? apic0:1 clock output (lump capacitance test load = 20 pf) parameter description test condition/comments cpu = 66.8/100 mhz unit min. typ. max. f frequency, actual frequency generated by crystal oscillator 14.31818 mhz t r output rise edge rate measured from 0.4v to 2.0v 1 4 v/ns t f output fall edge rate measured from 2.0v to 0.4v 1 4 v/ns t d duty cycle measured on rising and falling edge at 1.25v 45 55 % f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 1.5 ms z o ac output impedance average value during switching transition. used for determining series termination value. 15 ? ref0:2 clock output (lump capacitance test load = 20 pf) parameter description test condition/comments cpu = 66.8/100 mhz unit min. typ. max. f frequency, actual frequency generated by crystal oscillator 14.318 mhz t r output rise edge rate measured from 0.4v to 2.4v 0.5 2 v/ns t f output fall edge rate measured from 2.4v to 0.4v 0.5 2 v/ns t d duty cycle measured on rising and falling edge at 1.5v 45 55 % f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 3ms z o ac output impedance average value during switching transition. used for determining series termination value. 40 ?
W204 preliminary document #: 38-07264 rev. *a page 14 of 16 48-mhz0:1 clock output (lump capacitance test load = 20 pf = 66.6/100 mhz) parameter description test condition/comments cpu = 66.8/100 mhz unit min. typ. max. f frequency, actual determined by pll divider ratio (see m/n below) 48.008 mhz f d deviation from 48 mhz (48.008 ? 48)/48 +167 ppm m/n pll ratio (14.31818 mhz x 57/17 = 48.008 mhz) 57/17 t r output rise edge rate measured from 0.4v to 2.4v 0.5 2 v/ns t f output fall edge rate measured from 2.4v to 0.4v 0.5 2 v/ns t d duty cycle measured on rising and falling edge at 1.5v 45 55 % f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to fre- quency stabilization. 3ms z o ac output impedance average value during switching transition. used for determining series termination value. 40 ? ordering information ordering code package name package type W204 h 48-pin ssop (300 mils)
W204 preliminary document #: 38-07264 rev. *a page 15 of 16 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagram summary of nominal dimensions in inches: body width: 0.296 lead pitch: 0.025 body length: 0.625 body height: 0.102
W204 preliminary document #: 38-07264 rev. *a page 16 of 16 document title: W204 spread spectrum ftg for 440bx and via apollo pro-133 (preliminary) document number: 38-07264 rev. ecn no. issue date orig. of change description of change ** 110529 01/31/02 szv change from spec number: 38-01103 to 38-07264 *a 122862 12/22/02 rbi added power up requirements to maximum ratings.

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