spice device model si1305dl vishay siliconix p-channel 1.8-v (g-s) mosfet characteristics ? p-channel vertical dmos ? macro model (subcircuit model) ? level 3 mos ? apply for both linear and sw itching application ? accurate over the ? 55 to 125 c temperature range ? model the gate charge, transient, and diode reverse recovery characteristics description the attached spice model descri bes the ty pical electrical characteristics of the p-channel ve rtical dmos. the subcircuit model schematic is extrac ted and optimized over the ? 55 to 125 c temperature ranges under the pulsed 0 to ? 5v gate drive. the saturated output impedance is best fit at the gate bias near the threshold voltage. a novel gate-to-drain feedback capac itance netw o rk is used to model the gate charge characteristics w h ile avoiding convergence difficulties of the sw itched c gd model. all model parameter values are optimized to provide a best fit to the m easured electrical data and are not intended as an exact phy sical interpretation of the device. subcircuit model schematic this document is intended as a spice modeling guideline and does not constitute a commercial product data sheet. designers sho uld refer to the appropriate data sheet of the same number fo r guaranteed specific ation limits. document number : 71476 www. vi s h a y . c o m 24-apr-04 1
spice device model si1305dl vishay siliconix specificat ions (t j = 2 5 c unless ot herwise not e d) pa ra me te r s y m b o l te s t c o n d i t i o n ty pic a l u n i t static gate threshold voltage v gs(t h ) v ds = v gs , i d = ? 250 a 0 . 8 5 v on-state drain current a i d ( on) v ds = ? 5 v, v gs = ? 4.5 v 1 4 a v gs = ? 4.5 v, i d = ? 1 a 0.250 v gs = ? 2.5 v, i d = ? 0.5 a 0.318 drain-source on-state resistance a r ds(o n ) v gs = ? 1.8 v, i d = ? 0.3 a 0.420 ? forw ard transconductance a g fs v ds = ? 5 v, i d = ? 1 a 2 . 7 s diode forw ard voltage a v sd i s = ? 1 a, v gs = 0 v ? 0.79 v dy namic b t o tal gate c harge b q g 2 . 2 gate-source charge b q gs 0 . 6 gate-drain charge b q gd v ds = ? 4 v, v gs = ? 4.5 v, i d = ? 1 a 0.5 nc turn-on delay time b t d(on) 8 ris e time b t r 1 6 turn-off delay time b t d(off) 2 7 fall time b t f v dd = ? 4 v, r l = 4 ? i d ? ? 1 a, v gen = ? 4.5 v, r g = 6 ? 8 source-drain rev e rse recov e ry time t rr i f = ? 1 a, di/dt = 100 a/ s 26 ns not e s a. pulse test; pulse w i dth 300 s, duty cy cle 2%. b. guaranteed by design, not s ubject to production testing. www . v is ha y . c o m document number: 71476 2 24-apr-04
spice device model si1305dl vishay siliconix comparison of model wit h measured dat a (t j =2 5 document number : 71476 www. vi s h a y . c o m 24-apr-04 3
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