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bj8p508/153 otp rom bj8p508/153 8-bit micro-controller v ersion 2.0 www..net
bj8p508/153 otp rom application note a n-001 q & a on ice53s a n-002 the set-u p timin g and pin chan g e wake-u p function a pp lication a n-003 internal rc oscillator mode this s p ecification is sub j ect to chan g e without p rior notice. 2 6. 17 .2007 ( v2.0 )
bj8p508/153 otp rom 1. general description bj8p508/153 is an 8-bit microproces sor with low-power and high-speed cmos t echnology. it is equipped with a 1024*13-bits electrical one time programmable read only memory (otp-rom) with it. it provides a protection bit to prevent intrusion of user?s code in the otp memory well as 15 option bits to match user?s r q uirements. with its otp-rom feature, the bj8p508/153 offers users a convenient way of developing and verifying their programs. moreover, user developed code c an be easily programmed with the emc writer. this s p ecification is sub j ect to chan g e without p rior notice. 3 6.17.2007 (v2.0)
bj8p508/153 otp rom 2. features ? 8-lead packages : bj8p508; 14-lead packages:bj8p153 ? operating voltage range : 2.3v~5.5v ? available in temperature range: 0 c~70 c ? operating frequency range (base on 2 clocks): * crystal mode: dc~20mhz at 5v, dc~8mhz at 3v, dc~4mhz at 2.3v. * erc mode: dc~4mhz at 5v, dc~4 mhz at 3v, dc~4mhz at 2.3v. ? low power consumption: * less then 1.5 ma at 5v/4mhz * typical of 15 a, at 3v/32khz * typical of 1 a, during the sleep mode ? 1024 ? 13 bits on chip rom ? built-in calibrated irc oscillators (8mhz, 4mhz, 1mhz, 455khz ) ? programmable prescaler of oscillator set-up time ? one security register to prevent the code in the otp memory from intruding ? one configuration register to match the user?s requirements ? 32 ? 8 bits on chip registers (sra m, general purpose register) ? 2 bi-directional i/o ports ? 5 level stacks for subroutine nesting ? 8-bit real time clock/counter (tcc) with selective signal sources and trigger edges, and with overflow interrupt ? power down mode (sleep mode) ? three available interruptions * tcc overflow interrupt * input-port status changed interrupt (wake up from the sleep mode) * external interrupt ? pro g rammable free runnin g wa t chdo g timer ? 7 programmable pull-high i/o pins ? 7 programmable open-drain i/o pins ? 6 programmable pull-down i/o pins ? two clocks per instruction cycle ? package type: 8 pins sop, pdip * 8 pin dip 300mil: bj8p508apj this s p ecification is sub j ect to chan g e without p rior notice. 4 6.17.2007 ( v2.0 )
bj8p508/153 otp rom * 8 pin sop 150mil: 8p508anj 14 pins sop, pdip * 14 pin dip 300mil: bj8p153apj, * 14 pin sop 150mil: bj8p153snj the names in bjx?s erp are bj8p508apj,8 p508anj,bj8p153apj/78p153spj,bj8p153snj. ? the transient point of system freq uency between hxt and lxt is around 400khz. this s p ecification is sub j ect to chan g e without p rior notice. 5 6.17.2007 (v2.0)
bj8p508/153 otp rom 3. pin assignments this s p ecification is sub j ect to chan g e without p rior notice. 6 6.17.2007 ( v2.0 ) fig1.pin assignments table 1. pin description symbol type function vdd - power supply p65/osci i/o *general purpose i/o pin. *external clock signal input. *input pin of xt oscillator. *pull-high/open-drain *wake up from sleep mode when the status of the pin changes. p64/osco i/o *general purpose i/o pin. *external clock signal input. *input pin of xt oscillator *pull-high/open-drain *wake up from sleep mode when the status of the pin changes. p63//reset i *if set as /reset and remain at logic low,the device will be uder reset. *wake up from sleep mode when the status of the pin changes. *voltage on/reset must not exceed vdd during the normal mode. *internal pull-high is on if defined as /reset. *p63 is input pin only. p62/tcc i/o *general purpose i/o pin. *pull-high/open-drain/pull-down. *wake up from sleep mode when the status of the pin changes. *schmitt trigger input during the programming mode. p61 i/o *general purpose i/o pin. *pull-high/open-drain/pull-down. *wake up from sleep mode when the status of the pin changes. *schmitt trigger input during the programming mode. p60//int i/o *general purpose i/o pin. *pull-high/open-drain/pull-down. *wake up from sleep mode when the status of the pin changes. *schmitt trigger input during the programming mode. *external interrupt pin triggered by falling edge.
bj8p508/153 otp rom this s p ecification is sub j ect to chan g e without p rior notice. 7 6.17.2007 (v2.0) p66,p67 i/o *general purpose i/o pin. *pull-high/open-drain *wake up from sleep mode when the status of the pin changes. p50~p53 i/o *general purpose i/o pin. *pull-down. p53 i/o *general purpose i/o pin. vss - *ground.
bj8p508/153 otp rom 4. function description o s c o osci oscillator/timing control / re s e t wdt t i m e r prescaler t c c / i n t rom r2 s t ack buil t -in osc ram interrup t controlle r ins t r u c t ion register a l u r4 r1(tcc) ins t r uc t ion decoder r3 a cc d a t a & c o ntr o l bu s ioc6 r6 i/o port 6 p60 p61 p62/tcc p63//rest p64/osco p65/osci p66 p67 ioc5 r6 i/o port 5 p50 p51 p52 p53 fig. 2 functional block diagram 4.1 o p erational re g isters 1. r0 ( indirect addressin g re g ister ) r0 is not a physically implemented regis t er. its majo r function is to be an indi r ect add r essing pointer. a ny instruction using r0 as a pointer, actually accesses data pointed by the ram select register (r4). 2. r1 ( time clock / counter ) ? increased by an external signal edge, which is defined by te bit (cont-4) th r ough the tcc pin, o r by the instruction cycle clock. ? writable and readable as any other registers. ? defined by resetting pab (cont-3). ? the prescaler is assigned to tcc if the pab bit (cont-3) is reset. ? the contents of the prescaler counter is cleared only when a value is written to tcc register. this s p ecification is sub j ect to chan g e w ithout p rior notice. 8 6.17.2007 ( v2.0 )
bj8p508/153 otp rom 3. r2 ( pro g ram counter ) & stack ? depending on the device type, r2 and hardware stac k are 10-bit wide. the structure is depicted in fig.3. ?1024 ? 13 bits on-chip otp rom addresses to the relative programming instruction codes. one program page is 1024 words long. ? r2 is set as all "0"s when at reset condition. ? "jmp" instruction allows direct loading of the lo wer 10 program counter bits. thus, "jmp" allows pc to go to any location within a page. ? "call" instruction loads the lower 10 bits of the pc, and then pc+1 is pushed into the stack. thus, the subroutine entry address can be located anywhere within a page. ? "ret" ("retl k", "reti") instruction loads the pr ogram counter with the contents of the top-level stack. ? "add r2,a" allows the contents of ?a? to be added to the current pc , and the ninth and tenth bits of the pc are cleared. ? "mov r2,a" allows to load an address from the "a" register to the lower 8 bits of the pc, and the ninth and tenth bits of the pc are cleared. ? any instruction that is written to r2 (e.g. "add r2,a", "mov r2,a", "bc r2,6", ) will cause th e ninth and tenth bits (a8,a9) of the pc to be cleare d. thus, the computed jump is limited to the first 256 locations of a page. ? all instructions are single instruction cycle (fclk/ 2 or fclk/4), except for the instruction that would chan g e the contents of r2. this instruc t ion will need one more instruction c y cle. pc ( a 9 ~ a0 ) reset vecto r interrupt vector ) ) stack level 1 stack level 2 stack level 3 stack level 4 stack level 5 on-chip p r og r am memory '') fig. 3 program counter organization this s p ecification is sub j ect to chan g e without p rior notice. 9 6.17.2007 ( v2.0 )
bj8p508/153 otp rom add r ess r page re g iste r sioc p a ge r e g iste r s 00 r0 reserve 01 r1 (tcc) cont (control registe r 02 r2 ( pc ) reserve 03 r3 ( s t atus ) reserve 04 r4 ( rsr ) reserve 05 r5 (port5) ioc5 (i/o port control register) 06 r6 (port6) ioc6 (i/o port control register) 07 reserve reserve 08 reserve reserve 09 reserve reserve 0 a reserve reserve 0b reserve iocb (pull-down regist e 0c reserve iocc (open-drain con t r o 0d reserve iocd (pull-high control registe 0e res 0f rf (interrupt s t atus) iocf (interrupt mask regist e 10 m general re g isters 2f fig. 4 data memo r y configu r ation this s p ecification is sub j ect to chan g e without p rior notice. 10 6.17.2007 ( v2.0 )
bj8p508/153 otp rom 4. r3 (status register) 7 6 5 4 3 2 1 0 rst gp1 gp0 t p z dc c ? bit 7 (rst) bit for reset type. set to 1 if wake-up from sleep mode on pin change set to 0 if wake up from other reset types ? bit6 ~ 5 (gp1 ~ 0) general purpose read/write bits. ? bit 4 (t) time-out bit. set to 1 with the "slep" and "wdtc" command, or during power up and reset to by wdt time-out. ? bit 3 (p) power down bit. set to 1 during power on or by a "wdtc" command and reset to 0 by a "slep" command. ? bit 2 (z) zero flag. set to "1" if the result of an arithmetic or logic operation is zero. ? bit 1 (dc) auxiliary carry flag ? bit 0 (c) carry flag 5. r4 (ram select register) ? bits 7 ~ 6 are general-purpose read / write bits. see the configuration of t he data memory in fig. 4. ? bits 5 ~ 0 are used to select registers (address: 00~06, 0f~2f) in the indirect addressing mode. 6. r5 ~ r6 (port 5 ~ port 6) ? r5 and r6 are i/o regis t ers. ? only the lower 4 bits of r5 are available. ? the upper 4 bits of r5 are fixed to 0. ? p63 is input only. 7. rf (interrupt status register) 7 6 5 4 3 2 1 0 - - - - - exif icif tcif ?1? means interrupt request, and ?0? means no interrupt occurs. ? bits 7 ~ 3 not used. ? bit 2 (exif) external interrupt flag. set by falling edge on /int pin, reset by software. ? bit 1 (icif) port 6 input status changed interrupt flag. set when port 6 input changes, reset by software. ? bit 0 ( tcif ) tcc overflowin g interru pt fla g . set when tcc overflows, reset b y software. this s p ecification is sub j ect to chan g e without p rior notice. 11 6.17.2007 ( v2.0 )
bj8p508/153 otp rom ? rf can be cleared by ins t ruction but cannot be set. ? iocf is the interrupt mask register. ? note that the result of reading rf is the "logic and" of rf and iocf. 8. r10 ~ r2f ? all of these are the 8-bit general-purpose registers. 4.2 special purpose re g isters 1. a ( accumulator ) ? internal da t a transfer, or instruction operand holding ? it cannot be addressed. 2. cont (control register) 7 6 5 4 3 2 1 0 - int ts te pab psr2 psr1 psr0 ? bit 7 not used. ? bit 6 (int) interrupt enable flag 0: masked by disi or hardware interrupt 1: enabled by eni/reti instructions ? bit 5 (ts) tcc signal source 0: internal instruction cycle clock, p62 is a bi-directional i/o pin. 1: transition on tcc pin ? bit 4 (te) tcc signal edge 0: increment if the transition from low to high takes place on tcc pin 1: increment if the transition from high to low takes place on tcc pin ? bit 3 (pab) prescaler assignment bit. 0: tcc 1: wdt ? bit 2 (psr2) ~ 0 (psr0) tcc/wdt prescaler bits. psr2 psr1 psr0 tcc rate wdt rate 0 0 0 1:2 1:1 0 0 1 1:4 1:2 0 1 0 1:8 1:4 0 1 1 1:16 1:8 1 0 0 1:32 1:16 1 0 1 1:64 1:32 1 1 0 1:128 1:64 1 1 1 1:256 1:128 this s p ecification is sub j ect to chan g e without p rior notice. 12 6.17.2007 ( v2.0 )
bj8p508/153 otp rom ? cont register is both readable and writable. 3. ioc5 ~ ioc6 (i/o port control register) ? "1" put the relative i/o pin into high impedance, w hile "0" defines the relative i/o pin as output. ? only the lower 4 bits of ioc5 are available to be defined. ? ioc5 and ioc6 registers are both readable and writable. 4. iocb (pull-down control register) 7 6 5 4 3 2 1 0 - /pd6 /pd5 /pd4 - /pd2 /pd1 /pd0 ? bit 7 not used. 0: enable internal pull-down 1: disable internal pull-down ? bit 6 (/pd6) control bit used to enable the pull-down of p62 pin. ? bit 5 (/pd5) control bit is used to enable the pull-down of p61 pin. ? bit 4 (/pd4) control bit is used to enable the pull-down of p60 pin. ? bit 3 not used ? bit 2 (/pd2) control bit is used to enable the pull-down of p52 pin. ? bit 1 (/pd1) control bit is used to enable the pull-down of p51 pin. ? bit 0 (/pd0) control bit is used to enable the pull-down of p50 pin. ? iocb register is both readable and writable. 5. iocc (open-drain control register) 7 6 5 4 3 2 1 0 od7 od6 od5 od4 - od2 od1 od0 ? bit 7 (od7) control bit is used to enable the open-drain of p67 pin. 0: disable open-drain output 1: enable open-drain output ? bit 6 (od6) control bit is used to enable the open-drain of p66 pin. ? bit 5 (od5) control bit is used to enable the open-drain of p65 pin. ? bit 4 (od4) control bit is used to enable the open-drain of p64 pin. ? bit 3 not used. ? bit 2 (od2) control bit is used to enable the open-drain of p62 pin. ? bit 1 (od1) control bit is used to enable the open-drain of p61 pin. ? bit 0 (od0) control bit is used to enable the open-drain of p60 pin. ? iocc register is both readable and writable. 6. iocd (pull-high control register) this s p ecification is sub j ect to chan g e without p rior notice. 13 6.17.2007 ( v2.0 )
bj8p508/153 otp rom 7 65 4321 0 /ph7 /ph6 /ph5 /ph4 - /ph2 /ph1 /ph0 ? bit 7 (/ph7) control bit is used to enable the pull-high of p67 pin. 0: enable internal pull-high 1: disable internal pull-high ? bit 6 (/ph6) control bit is used to enable the pull-high of p66 pin. ? bit 5 (/ph5) control bit is used to enable the pull-high of p65 pin. ? bit 4 (/ph4) control bit is used to enable the pull-high of p64 pin. ? bit 3 not used. ? bit 2 (/ph2) control bit is used to enable the pull-high of p62 pin. ? bit 1 (/ph1) control bit is used to enable the pull-high of p61 pin. ? bit 0 (/ph0) control bit used to enable the pull-high of p60 pin. ? iocd register is both readable and writable. 7. ioce (wdt control register) 7 6 5 4 3 2 1 0 wdte eis - - - - - - ? bit 7 (wdte) control bit used to enable watchdog timer. 0: disable wdt. 1: enable wdt. wdte is both readable and writable. ? bit 6 (eis) control bit is used to define t he function of p60(/int) pin. 0: p60, bi-directional i/o pin. 1: /int, external interrupt pin. in th is case, the i/o control bit of p60 (bit 0 of ioc6) must be set to "1". when eis is "0", the path of /int is masked. when eis is "1", the status of /int pin can also be read by way of reading port 6 (r6). refer to fig. 7. eis is both readable and writable. ? bit 5 ~ 0 not used. 8. iocf (interrupt mask register) 7 6 5 4 3 2 1 0 - - - - - exie icie tcie ? bit 7 ~ 3 not used. ? individual interrupt is enabled by setting its associated control bit in the iocf to "1". ? global interrupt is enabled by the eni instruction and is disabled by the disi instruction. refer to fig. 9. ? bit 2 ( exie ) exif interru p t enable bit. this s p ecification is sub j ect to chan g e without p rior notice. 14 6.17.2007 ( v2.0 )
bj8p153ap otp rom 0: disable exif interrupt 1: enable exif interrupt ? bit 1 (icie) icif interrupt enable bit. 0: disable icif interrupt 1: enable icif interrupt ? bit 0 (tcie) tcif interrupt enable bit. 0: disable tcif interrupt 1: enable tcif interrupt ? iocf register is both readable and writable. 4.3 tcc/wdt & prescaler there is an 8-bit counter available as prescaler for the tcc or wdt. the prescaler is available for the tcc only or the wdt only at the same time and the p ab bit of the cont register is used to determin e the prescaler assignment. the psr0~psr2 bits determi ne the ratio. the prescaler is cleared each tim e the instruction is written to tcc under tcc mo de. the wdt and prescaler, when assigned to wd t mode, are cleared by the ?wdtc? or ?slep? instructions. fig. 5 depicts the circui t dia g ram . ? r1(tcc) is an 8-bit timer/counter. the clock source of tcc can be internal or external clock input (edge selectable from tcc pin). if tcc signal source is from internal clock, tcc will increase by 1 at every instruction cycle (without prescaler). refe rring to fig. 5, clk=fosc/2 or clk=fosc/4, depends on the code option bit clk. clk=fosc/2 is used if cl k bit is "0", and clk=fosc/4 is used if clk bit is "1". if tcc signal source is from external clock input, tcc is increased by 1 at every falling edge or risin g ed g e of tcc p in. ? the watchdog timer is a free running on-chip rc o scillator. the wdt will keep running even when the oscillator driver has been turned off (i.e. in sleep mode). during normal operation or sleep mode, a wdt time-out (if enabled) will cause the device to reset. the wdt can be enabled or disabled an y time during normal mode by software programming . refer to wdte bit of ioce register. withou t prescaler, the wdt time-out period is approximately 18 ms 1 (default). 4.4 i/o ports the i/o re g isters, both port 5 and port 6, are bi -directional tri-state i/o ports. por t 6 can be pulled-hi g h 1 : vdd = 5v, set up time period = 16.5ms 30 % vdd = 3v, set up time period = 18ms 30% this s p ecification is sub j ect to chan g e without p rior notice. 15 6.17.2007 ( v2.0 )
bj8p508/153 otp rom internally by software except p63. in addition , port 6 can also have open-drain output by software except p63. input status changed interrupt (or wake-up) function is available from port 6. p50 ~ p52 and p60 ~ p62 pins can be pulled-down by software. each i/o pin can be defined as "input" or "output" pin by the i/o control register (ioc5 ~ ioc6) except p63. the i/o registers and i/o control registers are both readable and writable. the i/o interfac e circuits for port 5 and port 6 are shown in fig 6,fig.7 and fig. 8 respectively. $-, 'ptd p s 'ptd
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.69 1"# 8%5 5jnf 0vu fig. 5 block diagram of tcc and wdt this s p ecification is sub j ect to chan g e without p rior notice. 16 6.17.2007 v2.0
bj8p508/153 otp rom pcrd q p r d _ q cl k c l pcwr port q p r d iod _ q cl k c l pdwr 0 1 m u x pdrd *pull-down is not shown in the figu r e. fi g . 6 the circuit of i/o port and i/o control re g ister for port 5 p crd q _ q p r d cl k c l pc w r po r t q p r d io d bi t 6 o f i o c e 0 _ q cl k c l pd w r d r q m cl k c l _ q 1 u x p drd t1 0 d p r q cl k c l _ q *pull-high (down), open-drain are not shown in t he figure. fig. 7 the circuit of i/o port and i/o control register for p60(/int) this s p ecification is sub j ect to chan g e without p rior notice. 17 6.17.2007 v2.0
bj8p508/153 otp rom q p r d _ q cl k c l pcw r port q p r d io d 0 1 m u x _ q cl k c l pdw r pdrd tin d p r q cl k c l _ q *pull-high (down), open-drain are not shown in t he figure. fig. 8 the circuit of i/o port and i/o control register for p61~p67 icie d p r q clk c l _ q icif interru p t 1 d p r q eni instruction 1 1 1 clk c _ q p r d 1 1 1 1 l q _ q clk c l disi instruction /slep interru p t (w ake-up from sleep) next instruction (w ake-up from sleep) fi g . 9 block dia g ram of i/o port 6 with in p ut chan g e interru p t / wake-u p this s p ecification is sub j ect to chan g e without p rior notice. 18 6.17.2007 v2.0
bj8p508/153 otp rom table 2 usage of port 6 input change wake-up/interrupt function usage of port 6 input status change wake-up/interrupt (i) wake-up from port 6 input status change (ii) port 6 input status change interrupt (a) before sleep 1. read i/o port 6 (mov r6,r6) 1. disable wdt 2. execute "eni" 2. read i/o port 6 (mov r6,r6) 3. enable interrupt (set iocf.1) 3. execute "eni" or "disi" 4. if port 6 change (interrupt) 4. enable interrupt (set iocf.1) interrupt vector (008h) 5. execute "slep" instruction (b) after wake-up 1. if "eni" interrupt vector (008h) 2. if "disi" next instruction 4.5 reset and wake-up 1. reset in p ut status chan g e (1) power on reset. (2) /reset pin input "low", or (3) wdt time-out (if enabled). the device is kept in a reset condition for a period of approx. 18ms 1 (one oscillator start-up time r period) after the reset is detected. once the r eset occurs, the following functions are performed. refer to fig10.. ? the oscilla t or is running, or will be started. ? the program counter (r2) is set to all "0". ? all i/o port pins are configured as input mode (high-impedance state). ? the watchdog timer and prescaler are cleared. ? when power is switched on, the upper 3 bits of r3 are cleared. ? the bits of the cont register are set to all "1" except for the bit 6 (int flag). ? the bits of the iocb register are set to all "1". ? the iocc register is cleared. ? the bits of the iocd register are set to all "1". ? bit 7 of the ioce register is set to "1", and bits 4 and 6 are cleared. ? bits 0~2 of rf and bits 0~2 of iocf register are cleared. 1 vdd = 5v, set up time period = 16.5ms 30 % vdd = 3v, set up time period = 18ms 30% this s p ecification is sub j ect to chan g e without p rior notice. 19 6.17.2007 v2.0
bj8p508 / 153 otp rom the sleep (power down) mode is attained by exec uting the ?slep? instruction. while entering sleep mode, wdt (if enabled) is cleared but keeps on running. the controller can be awakened by (1) external reset input on /reset pin, (2) wdt time-out (if enabled), or (3) port 6 input status changes (if enabled). the first two cases will cause the bj8p508/153 to reset. the t and p flags of r3 can be used t o determine the source of the reset (wake-up). the la st case is considered the continuation of progra m execution and the global interrupt ("eni" or "disi" being executed) decides whethe r or not the controller branches to the interr upt vector following wake-up. if eni is execute d before slep, the instruction will begin to execut e from the address 008h after wake-up. if dis i is execu t ed before onl y one of the cases 2 and 3 can be enabled before enterin g the sleep mode. that is, [a] if port 6 input status changed interrupt is enabled before slep , wdt must be disabled. by software. however, the wdt bit in the option register remains enabled. hence, the bj8p508/153 can be awakened only by case 1 or 3. [b] if wdt is enabled before slep, port 6 input sta t us change interrupt must be disabled. hence, the bj8p508/153 can be awakened only by case 1 or 2. refer to the section on interrupt. if port 6 input status changed interrupt is used to wake-up the bj8p508/153 (case [a] above), th e following instructions must be executed before slep: mov a, @xxxx1110b ; select wdt prescaler, presca ler must set over 1:1 contw wdtc ; clear wdt and prescaler mov a, @0xxxxxxxb ; disable wdt iow re mov r6, r6 ; read port 6 mov a, @00000x1xb ; enable port 6 input change interrupt iow rf eni (or disi) ; enable (or disable) global interrupt slep ; sleep note : 1. a fter waking up from the sleep mode, wdt is automatically enabled. the wdt enabled/disabl e operation after waking up from sleep mode should be appropriately defined in the software. 2. to avoid a reset from occurring when the port 6 input status changed interrupt enters into interrupt vector or is used to wake-up the mcu, the wdt prescaler must be set abov e the 1:1 ratio. this s p ecification is sub j ect to chan g e without p rior notice. 20 6.17.2007 v2.0
bj8p508/153 otp rom table 3 the summa r y of the initialized register v alues address name reset type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit name x x x x c53 c52 c51 c50 n/a ioc5 n/a ioc6 0x05 p5 0x06 p6 n/a cont 0x00 r0(iar) 0x01 r1(tcc) 0x02 r2(pc) 0x03 r3(sr) 0x04 r4(rsr) 0x0f rf(isr) 0x0b iocb po w e r -on 00 001 1 11 /reset and wdt 0 0 0 0 1 1 1 1 wake-up from pin change 0 0 0 0 p p p p bit name c67 c66 c65 c64 c63 c62 c61 c60 power-on 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 wake-up from pin change p p p p p p p p bit name x x x x p53 p52 p51 p50 power-on 1 1 1 1 1 1 1 1 /reset and wdt p p p p p p p p wake-up from pin change p p p p p p p p bit name p67 p66 p65 p64 p63 p62 p61 p60 power-on 1 1 1 1 1 1 1 1 /reset and wdt p p p p p p p p wake-up from pin change p p p p p p p p bit name x int ts te pab psr2 psr1 psr0 power-on 1 0 1 1 1 1 1 1 /reset and wdt 1 0 1 1 1 1 1 1 wake-up from pin change p 0 p p p p p p bit name - - - - - - - - power-on u u u u u u u u /reset and wdt p p p p p p p p wake-up from pin change p p p p p p p p bit name - - - - - - - - power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 wake-up from pin change p p p p p p p p bit name - - - - - - - - power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 wake-up from pin change p p p p n p p p bit name rst gp1 gp0 t p z dc c power-on 0 0 0 1 1 u u u /reset and wdt 0 0 0 t t p p p wake-up from pin change 1 p p t t p p p bit name gp1 gp0 - - - - - - power-on u u u u u u u u /reset and wdt p p p p p p p p wake-up from pin change p p p p p p p p bit name x x x x x exif icif tcif power-on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 wake-up from pin change 0 0 0 0 0 p n p bit name x /pd6 /pd5 /pd4 /pd3 /pd2 /pd1 /pd0 power-on 1 1 1 1 1 1 1 1 this s p ecification is sub j ect to chan g e without p rior notice. 21 6.17.2007 v2.0
bj8p508/153 otp rom a ddress name reset t y pe bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wake-up from pin change p p p p p p p p bit name od7 od6 od5 od4 x od2 od1 od0 0x0c iocc 0x0d iocd 0x0e ioce 0x0f iocf 0x10~0x2f r10~r2f po w e r -on 00 000 0 00 /reset and wdt 0 0 0 0 0 0 0 0 wake-up from pin change p p p p p p p p bit name /ph7 /ph6 /ph5 /ph4 x /ph2 /ph1 /ph0 power-on 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 wake-up from pin change p p p p p p p p bit name wdte eis x x x x x x power-on 1 0 1 1 1 1 1 1 /reset and wdt 1 0 1 1 1 1 1 1 wake-up from pin change 1 p 1 1 1 1 1 1 bit name x x x x x exie icie tcie power-on 1 1 1 1 1 0 0 0 /reset and wdt 1 1 1 1 1 0 0 0 wake-up from pin change 1 1 1 1 1 p p p bit name - - - - - - - - power-on u u u u u u u u /reset and wdt p p p p p p p p wake-up from pin change p p p p p p p p x: not used. u: unknown or don?t care. -: not def ined p: previous value before reset. t: check table 4 n: monitors interrupt operation status; 1 = running; p = not running 2. /reset configure refer to fig. 10 when the r eset bit in the option word is progr ammed to 0, the external / reset is enabled. when programmed to 1, the internal /re set is enabled, tied to the internal vdd and the pin is defined as p63. 3. the status o f rst, t, and p o f status re g iste r a reset condition is initiated b y the followin g even t s: 1. a power-on condition, 2. a high-low-high pulse on /reset pin, and 3. watchdog timer time-out. the values of rst, t and p, listed in table 4 are used to check hoe the p rocessor wakes u p . table 5 shows the events which ma y affect the status of rst, t and p. this s p ecification is sub j ect to chan g e without p rior notice. 22 6.17.2007 v2.0
bj8p508/153 otp rom table 4 the values of rst, t and p after reset reset type rst t p power on 0 1 1 /reset during operating mode 0 *p *p /reset wake-up during sleep mode 0 1 0 wdt during operating mode 0 0 p wdt wake-up during sleep mode 0 0 0 wake-up on pin change during sleep mode 1 1 0 *p: previous status before reset table 5 the status of rst, t and p being affected by e v ents event rst t p power on 0 1 1 wdtc instruction *p 1 1 wdt time-out 0 0 *p slep instruction *p 1 0 wake-up on pin change during sleep mode 1 1 0 *p: previous value before reset vdd oscillator d q clk clr cl k power-on reset voltage detector wdte wdt wdt timeout setu p time reset /reset fi g . 10 block dia g ram of cont r oller res e this s p ecification is sub j ect to chan g e without p rior notice. 23 6.17.2007 v2.0
bj8p508/153 otp rom 4.6 interru p t the bj8p508/153 has three falling-edge interru pts as listed below: (1) tcc overflow interrup t (2) port 6 input status change interrupt (3) external interrupt [(p60, /int) pin]. before the port 6 input status changed interru pt is enabled, reading port 6 (e.g. "mov r6,r6") is necessary. each pin of port 6 will have this feature if its status ch anges. any pin conf igured as output o r p60 pin configured as /int, is excluded from this function. the port 6 input status changed interrup t can wake up the bj8p508/153 from sleep mode if port 6 is enabled prior to going into the sleep mod e by executing slep instruction. when the ch ip wakes-up, the controller will continue t o execute the program in-line if the global interrupt is disabled. if the global interrupt is enabled, it wil l branch to the rf is the interrupt status register that records the interrupt requests in the relative flags/bi t s. iocf is an interrupt mask register. the global interrupt is enabl ed by the eni instruction and is disabled by the dis i instruction. when one of the interrupts (enabled) occurs, the next instruction will b e fetched from address 008h. once in the interrupt service routine, the source of an interrupt can b e determined by polling the flag bits in rf. the interrupt flag bit must be cleared b y instructions before leaving the interrupt se rvice routine before interrupts are enabled to avoi d recursive interrupts. the flag (except icif bit) in the interrupt status regis t er (rf) is set regardless of the status of its mask bit or the execution of eni. note that the outcome of rf will be the logic and of rf and iocf (refer to fig. 11). the reti instruction ends the interrupt routine and enables the global interrupt ( the execution of eni). when an interrupt is generated by the int instruction (enabled), the ne x t instruction will be fetched from address 001h. this s p ecification is sub j ect to chan g e without p rior notice. 24 6.17.2007 v2.0
bj8p508/153 otp rom vcc /irqn d clk rf p r c l q _ q rfrd irqn irqm int eni/disi q p r d iod iocf _ q cl k c l iocfwr /reset iocfrd rfwr 4.7 oscillator fi g . 11 interrupt input 1. oscillator modes the bj8p508/153 can be operated in four different oscillator mod es, such as internal rc oscillat o mode (irc), external rc oscillator mode(erc), high xtal oscillator mode(hxt), and low xtal oscillator mode(lxt). user can sele ct one of them by programming ocs1 and osc2 in the code option register. table 6 depicts how these four modes are defined. the up-limited operation frequenc y of cr y stal/resonator on the different vdds is listed in table 7. table 6 oscillator modes defined by osc1 and osc2 mode osc1 osc2 irc(internal rc oscillator mode) 1 1 erc(external rc oscillator mode) 1 0 hxt(high xtal oscillator mode) 0 1 lxt(low xtal oscillator mode) 0 0 the transient point of system fr equency between hxt and lxy is around 400 khz. this s p ecification is sub j ect to chan g e without p rior notice. 25 6.17.2007 v2.0
bj8p508/153 otp rom table 7 the summa r y of maximum ope r ating speeds conditions vdd fxt max.(mhz) 2.3 4.0 two c y cles with two clocks 3.0 8.0 5.0 20.0 2. cr y stal oscillator/ceramic resonators ( xtal ) bj8p508/153 can be driven b y an external clock si g nal throu g h the osci p in as shown in fi g . 1 2 osci ext. clock osco bj8p508/153 fi g . 12 circuit for exte r nal clock inp u in most applications, pin osci and pin osco can be connected with a crystal or ceramic resonator to generate oscillation. fig. 13 depicts such circuit. the same thing applies whether it is in the hx t mode or in the lxt mode. table 8 provides the recommended values of c1 and c2. since eac h resonator has its own attribute, user should refer to its specification for appropriate values of c1 and c2. rs, a serial resistor, ma y be necessar y for a t stri p cut cr y stal or low fre q uenc y mode osci c1 bj8p508/153 xtal osco rs c2 fi g . 13 circuit for c r y stal/resonat o table 8 capacitor selection guide for c r y stal oscillator or ceramic resonators this s p ecification is sub j ect to chan g e without p rior notice. 26 6.17.2007 v2.0
bj8p508/153 otp rom oscillator type frequency m ode frequency c1(pf) c2(pf) 455 khz 100~150 100~150 ceramic resonators hxt lxt crystal oscillator hxt 2.0 mhz 20~40 20~40 4.0 mhz 10~30 10~30 32.768khz 25 15 100khz 25 25 200khz 25 25 455khz 20~40 20~150 1.0mhz 15~30 15~30 2.0mhz 15 15 4.0mhz 15 15 1. the value of capacitors ( c1, c2 ) is for reference. 3. external rc oscillator mode for some applications that do not need t o have its timing to be calculated precisely, the rc oscillator (fig. 16) offers a lot of cost savings. nevertheles s, it should be noted that the frequency of the r c oscillator is influenced by the supply voltage, the va lues of the resistor (r ext), the capacitor (cext) , and even the operation temperature. moreover, the fr equency also changes slightly from one chip to another due to the manufacturin g p rocess variation. in order to maintain a stable system frequency, the values of the cext should not be less than 20pf, and that the value of rext should not be greater than 1 m ohm. if they cannot be kept in this range, the frequency is easily affected by noise, humidity, and leakage. the smaller the rext in the rc oscillator, the faster its frequency will be. on the contrary, for very low rext values, for instance, 1 k & , the oscillator becomes unstable because the nmos cannot discharge the current of the capacitance correctly. based on the reasons above, it must be kept in mind that all of the supply voltage, the operation temperature, the components of the rc oscillator, the package types, the way the pcb is layout, will affect the system frequency. this s p ecification is sub j ect to chan g e without p rior notice. 27 6.17.2007 v2.0
bj8p508/153 otp rom v cc rext osci cext bj8p508/15 3 fi g .14 circuit for external rc oscillator mod e table 9 rc oscillator frequencies cext rext average fosc 5v,25 c average fosc 3v,25 c 3.3k 3.92 mhz 3.63mhz 20 pf 100 pf 300 pf 5.1k 2.67 mhz 2.6 mhz 10k 1.4 mhz 1.4 mhz 100k 150 khz 156 khz 3.3k 1.4 mhz 1.33 mhz 5.1k 940 khz 917 khz 10k 476 khz 480 khz 100k 50 khz 52 khz 3.3k 595 khz 570 khz 5.1k 400 khz 384 khz 10k 200 khz 203 khz 100k 20.9 khz 20 khz 1. measured on dip packages. 2. design reference only 3. the frequency drift is about ? 30% 4. internal rc oscillator mode bj8p508/153 offer a versa t ile internal rc mode wi t h default frequency value of 4mhz.internal r c oscillator mode still has other frequencies 8mhz, 1mhz, and 455khz and can be set by option bits , rcm1 and rcm0. all these four main frequencies can be calibration by programming the optio n bits, cal0~cal2. table 10 describes the bj8p508/153 nternal rc drift with the variation o f volta g e, this s p ecification is sub j ect to chan g e without p rior notice. 28 6.17.2007 v2.0
bj8p508/153 otp rom table 10 internal rc drift rate (ta=25 c , vdd=5 v 5%, vss=0v) drift rate internal rc temperature (0 c~70 c) voltage process total ( 2.3v~5.5v ) 8mhz 3% 5% 10% 18% 4mhz 3% 5% 5% 13% 1mhz 3% 5% 10% 18% 455khz 3% 5% 10% 18% 4.8 code option re g ister the bj8p508/153 has one code option word that is not a part of the normal program memory. the option bits cannot be accessed during normal program execution. code option re g ister and customer id re g ister arran g ement distribution: word 0 word1 word 2 bit12~bit0 bit1~bit0 bit12~bit0 code option register (word 0) word 0 bit12 bit11 bit10 bi t9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 /reset /enwdt clks osc1 ocs0 cs sut1 sut0 type rcout c2 c1 c0 ? bit 12 (/reset ): define pin7 as a reset pin. 0: /reset enable 1: /reset disable ? bit 11 ( /enwtd ) : watchdo g timer enable bit. 0: enable 1: disable this bit must enable and the wdte reg. (ioce reg. bit 6) must disable when port 6 pin change wake up function is used. ? bit 10 (clks) : instruction period option bit. 0: two oscillator periods. 1: four oscillator periods. refer to the section of instruction set. ? bit 9 and bit 8 ( osc1 and osc0 ) : oscillator modes selection bits. table 11 oscillator modes defined by osc1 and osc 0 mode osc1 osc0 irc(internal rc oscillator mode) 1 1 erc(external rc oscillator mode) 1 0 hxt(high xtal oscillator mode) 0 1 this s p ecification is sub j ect to chan g e without p rior notice. 29 6.17.2007 v2.0
bj8p508/153 otp rom lxt(low xt a l oscillator mode) 0 0 : the transient point of system fr equency between hxt and lxy is around 400 khz. ? bit 7 (cs) : code security bit 0: security on 1: security off ? bit6 and bit5 ( sut1 and sut0 ) : set-up time of device bits. table 12 set-up time of de v ice prog r ammin g sut1 sut0 *set-up time 1 1 18 ms 1 0 4.5 ms 0 1 288 ms 0 0 72 ms * theoretical values, for reference only ? bit 4 (t y pe) : type selection for bj8p156ap type series 0 bj8p508/153 1 x ? bit 3 (rcout) : a selecting bit of oscillator output or i/o port. rcout pin function 0 p64 1 osco ? bit 2, bit 1, and bit 0 ( c2, c1, c 0 ) : calibrator of internal rc mode bit 3 c2,c1,c0 must be set to ?1? only. code option register (word 1) word1 bit1 bit0 rcm1 rcm0 bit 1, and bit 0 ( rcm1, rcm0): rc mode selection bits rcm 1 rcm 0 *frequency(mhz) 1 1 4 1 0 8 0 1 1 0 0 455khz customer id register (word 2) bit 12~bit 0 xxxxxxxxxxxxx bit 12~ 0 : customer?s id code this s p ecification is sub j ect to chan g e without p rior notice. 30 6.17.2007 v2.0
bj8p508/153 otp rom 4.9 power on considerations a ny microcontroller is not guaranteed to start to ope rate properly before the power supply stabilizes at its steady state. under customer application, when power is off, vdd must drop to below 1.8v an d remains off for 10us before power can be switched on again. this way, th e bj8p508/153 will reset a nd work normally. the extra external reset circuit will work well if vdd ca n rise at very fast speed (50 ms or less). however, under most cases where cr itical applications are involved, extra devices are re q uired to assist in solvin g the p ower-u p p roblems. 4.10 pro g rammable oscillator set-up time the option word contains sut0 and sut1 which can be used to define the oscillator se t up time. theorically, the range is from 4.5 ms to 72 ms. for most of crystal or ceramic resonators, the lower the operation frequency is, the longer the set-up time may be required. table 12 describes the values of oscillator set-u p time. 4.11 external power on reset circuit the circuit shown in fig 17 implements an external rc to produce the reset pulse. the pulse width (time constant) should be kept long enough for vdd to reach minimum operation voltage. this circuit is used when the power supply has slow rise time. becaus e the current leak age from the /reset pin is about 5 a, it is recommended that r should not be great than 40 k. in this way, the voltage in pin /rese t will be held below 0.2v. the diode (d) acts as a short circuit at the moment of powe r down. the capacitor c, will discharged rapidly and fu lly. rl, the current-limited resistor, will prevent hi g h current v dd / reset r d bj8p508/153 rin c fig. 15 external powe r -up reset ci r cui t 4.12 residue-voltage protection when batter y is replaced, device powe r ( vdd ) is taken off but r esidue-volta g e this s p ecification is sub j ect to chan g e w ithout p rior notice. 31 6.17.2007 v2.0
bj8p508/153 otp rom residue-voltage may trips below vdd minimum, but not to zero. this condition may cause a poor power on reset. fig.18 and fig. 19 show how to build a residue-voltage protection circuit. v dd vdd bj8p508/153 q1 10k 33k / reset 100k 1n4684 fig. 16 circuit 1 for the residue v oltage protection v d d vd d bj8p508/153 q1 r1 / r eset r3 r2 fi g .17 circuit 2 for the residue v olta g e p rotection 4.13 instruction set each instruction in the instruction set is a 13-bit word divided into an op code and one or more operands. normally, all instructions are executed within one single instruction cycle (one instruction consists of 2 osc illator periods), unless the program counter is change d by instructi o "mov r2 , a" this s p ecification is sub j ect to chan g e without p rior notice. 32 6.17.2007 v2.0
bj8p508/153 otp rom "add r2,a", or by instructions of arithmetic or logic operation on r 2 (e.g. "sub r2,a", "bs(c) r2,6", "clr r2", ) . in this case, the execution takes two instruction c y cles. if for some reasons, the specification of the instru ction cycle is not suitable for certain applications, try modifying the instruction as follows: (a) modify one instruction cycle to consist of 4 oscillator periods. (b) execute within two instruction cycles the "j mp", "call", "ret", "retl", "reti" commands, o r the conditional skip ("jbs", "jbc", "jz", "jza", "djz", "djza") which were tested to be true . the instructions that are written to the prog ram counter, should also take two instructio n c y cles. the case (a) is selected by the code option bit, called clks. one instruction cycle will consist of two oscillator clocks if clks is low, and four oscillator clocks if clks is high. note that once the 4 oscillator periods within one instruction c y cle is selected under case (a), t h internal clock source to tcc sh ould be clk=fosc/4 ,instead of fo sc/ 2 as illustrated in fig. 5. in addition, the instruction set has the followin g features: (1) every bit of any register can be set, cleared, or tested directly. (2) the i/o register can be regarded as general regi ster. that is, the same instruction can operate on i/o re g ister. the symbol "r" represen t s a register designator that specifies which one of the registers (including operational registers and general purpos e registers) is to be utilized by t he instruction. "b" represents a bit field designator that selects the value for the bit which is located in the register "r", and affects the operation. "k" represents an 8 or 10-bit constant or literal value. instruction binary hex mnemonic operation status affected 0 0000 0000 0000 0000 nop no operation none 0 0000 0000 0001 0001 daa decimal adjust a c 0 0000 0000 0010 0002 contw a cont none 0 0000 0000 0011 0003 slep 0 wdt, stop oscillator t,p 0 0000 0000 0100 0004 wdtc 0 wdt t,p 0 0000 0000 rrrr 000r iow r a iocr none 0 0000 0001 0000 0010 eni enable interrupt none 0 0000 0001 0001 0011 disi disable interrupt none 0 0000 0001 0010 0012 ret [top of stack] pc none 0 0000 0001 0011 0013 reti [top of stack] pc, enable interrupt none 0 0000 0001 0100 0014 contr cont a none 0 0000 0001 rrrr 001r ior r iocr a none 0 0000 01rr rrrr 00rr mov r,a a r none 0 0000 1000 0000 0080 clra 0 a z 0 0000 11rr rrrr 00rr clr r 0
bj8p508/153 otp rom 0 0001 00rr rrr r 01r r sub a,r r-a r z,c,dc 0 0001 10rr rrrr 01rr deca r r-1 a z 0 0001 11rr rrrr 01rr dec r r-1 r z 0 0010 00rr rrrr 02rr or a,r a ( vr a z 0 0010 01rr rrrr 02rr or r,a a ( vr r z 0 0010 10rr rrrr 02rr and a,r a & r a z 0 0010 11rr rrrr 02rr and r,a a & r r z 0 0011 00rr rrrr 03rr xor a,r a r a z 0 0011 01rr rrrr 03rr xor r,a a r r z 0 0011 10rr rrrr 03rr add a,r a + r a z,c,dc 0 0011 11rr rrrr 03rr add r,a a + r r z,c,dc 0 0100 00rr rrrr 04rr mov a,r r a z 0 0100 01rr rrrr 04rr mov r,r r r z 0 0100 10rr rrrr 04rr coma r /r a z 0 0100 11rr rrrr 04rr com r /r r z 0 0101 00rr rrrr 05rr inca r r+1 a z 0 0101 01rr rrrr 05rr inc r r+1 r z 0 0101 10rr rrrr 05rr djza r r-1 a, skip if zero none 0 0101 11rr rrrr 05rr djz r r-1 r, skip if zero none 0 0110 00rr rrrr 06rr rrca r r(n) a(n-1),r(0) c, c a(7) c 0 0110 01rr rrrr 06rr rrc r r(n) r(n-1),r(0) c, c r(7) c 0 0110 10rr rrrr 06rr rlca r r(n) a(n+1),r(7) c, c a(0) c 0 0110 11rr rrrr 06rr rlc r r(n) r(n+1),r(7) c, c r(0) c 0 0111 00rr rrrr 07rr swapa r r(0-3) a(4-7),r(4-7) a(0-3) none 0 0111 01rr rrrr 07rr swap r r(0-3) r(4-7) none 0 0111 10rr rrrr 07rr jza r r+1 a, skip if zero none 0 0111 11rr rrrr 07rr jz r r+1 r, skip if zero none 0 100b bbrr rrrr 0xxx bc r,b 0 r(b) none 0 101b bbrr rrrr 0xxx bs r,b 1 r(b) none 0 110b bbrr rrrr 0xxx jbc r,b if r(b)=0, skip none 0 111b bbrr rrrr 0xxx jbs r,b if r(b)=1, skip none 1 00kk kkkk kkkk 1kkk call k pc+1 [sp],(page, k) pc none 1 01kk kkkk kkkk 1kkk jmp k (page, k) pc none 1 1000 kkkk kkkk 18kk mov a,k k a none 1 1001 kkkk kkkk 19kk or a,k a ( k a z 1 1010 kkkk kkkk 1akk and a,k a & k a z 1 1011 kkkk kkkk 1bkk xor a,k a k a z 1 1100 kkkk kkkk 1ckk retl k k a,[top of stack] pc none 1 1101 kkkk kkkk 1dkk sub a,k k-a a z,c,dc 1 1110 0000 0001 1e01 int pc+1 [sp],001h pc none 1 1111 kkkk kkkk 1fkk add a,k k+a a z,c,dc this instruction is applicab le to ioc5~ioc6, iocb~iocf only. this instruction is not recommended for rf operation. this ins t ruction cannot o p erate under r f . this s p ecification is sub j ect to chan g e without p rior notice. 34 6.17.2007 v2.0
bj8p508/153 otp rom 4.14 timin g dia g rams a c test input/output wa v eform 2.4 0.4 2.0 0.8 test points 2.0 0.8 a c testing : input is driven at 2.4 v fo r logic "1",and 0.4 v f o r logic "0".timing measurements are made at 2.0v for logic "1",and 0.8v for logic "0". reset timing (cl k ="0") nop instruction 1 executed cl k / r eset td r h tcc input timing (clks="0") tins cl k tcc ttcc this s p ecification is sub j ect to chan g e without p rior notice. 35 6.17.2007 v2.0
bj8p508/153 otp rom 5. absolute maximunm rating s items rating temperature under bias 0 c to 70 c storage temperature -65 c to 150 c input voltage -0.3v to +6.0v output voltage -0.3v to +6.0v this s p ecification is sub j ect to chan g e without p rior notice. 36 6.17.2007 v2
bj8p508/153 otp rom 6. electrical characteristic 6.1 dc electrical characteristic ( ta= 0 c ~ 70 c, vdd= 5.0v 5%, vss= 0v ) symbol parameter cond ition min typ max unit fxt xtal: vdd to 2.3v two cycle with two clocks dc 4.0 mhz fxt xtal: vdd to 3v two cycle with two clocks dc 8.0 mhz fxt xtal: vdd to 5v two cycle with two clocks dc 20.0 mhz erc rc: vdd to 5v r: 5k & % 1500 f+30 % 1 a ipd pull-down current pull-down active, input pin at vdd 20 50 120 a isb1 power down current all input and i/o pins at vdd, output pin floating, wdt disabled isb2 power down current all input and i/o pins at vdd, output pin floating, wdt enabled /res et =' high ' fosc = 32khz icc1 operating supply current(vdd=3v) at two clocks icc2 operating supply current (vdd=3v) at two clocks icc3 operating supply current(vdd=5.0v) at two clocks icc4 operating supply current(vdd=5.0v) at t w o clocks (c r y stal t y pe,clks="0"), output pin floating, wdt disabled /reset= 'high', fosc=32khz (crystal type,clks="0"), output pin floating, wdt enabled /reset= 'high', fosc=4mhz (crystal type, clks="0"), output pin floating /reset= 'high', fosc=10mhz (crystal type, clks="0"), out p ut p in floatin g 15 15 30 a 2.0 ma 4.0 ma * these parameters are characterizes and tested. * data in the minimum, typical, maximum(?min?,?typ?, ?max?) column are based on characterization results at 25
. this data is for design guidance and is tested. this s p ecification is sub j ect to chan g e without p rior notice. 37 6.17.2007 v2.0
bj8p508/153 otp rom 6.2 ac electrical characteristic ( ta=0 c ~ 70 c, vdd=5 v 5%, v ss=0 v) s y mbol paramete r conditions min t y p max unit dclk input clk duty cycle 45 50 55 % crystal type 100 dc ns tins instruction c y cle time (clks="0") rc type 500 dc ns ttcc tcc input period (tins+20)/n* ns ta = 25 c tdrh device r eset hold time t x al,sut1,sut0=1,1 17.6-30% 17.6 17.6+30% ms t r st /reset pulse w idth ta = 25 c 2000 ns twdt1* watchdog timer period ta = 25 c sut1,sut0=1,1 twdt2* watchdog timer period ta = 25 c sut1,sut0=1,0 twdt3* watchdog timer period ta = 25 c sut1,sut0=0,1 t w dt4* watchdo g timer p eriod ta = 25 c 17.6-30% 17.6 17.6+30% ms 4.5-30% 4.5 4.5+30% ms 288-30% 288 288+30% ms 72-30% 72 72+30% ms tset input pin setup time 0 ns thold input pin hold time 20 ns tdelay output pin delay time cload=20pf 50 ns * twdt1: the option word (sut1,sut0) is used to defi ne the oscillator set-up time. in crystal mode the wdt timeout length is the same as set-up time(18ms). * twdt2: the option word (sut1,sut0) is used to defi ne the oscillator set-up time. in crystal mode the wdt timeout length is the same as set-up time(4.5ms). * twdt3: the option word (sut1,sut0) is used to defi ne the oscillator set-up time. in crystal mode the wdt timeout length is the same as set-up time(288ms). * twdt4: the option word (sut1,sut0) is used to defi ne the oscillator set-up time. in crystal mode the wdt timeout length is the same as set-up time(72ms). * these parameters are characterizes but not tested. * data in the minimum, typical, maximum(?min?,?typ?, ?max?) column are based on characterization results at 25
. this data is for design guidance and is not tested. * n= selected prescaler ratio. * the duration of watch do g timer is de t ermined b y o p tion code ( bit6 , bit5 ) this s p ecification is sub j ect to chan g e without p rior notice. 38 6.17.2007 v2.0
bj8p508/153 otp rom 6.3 device characteristic the graphs provided in the following pages were der ived based on a limited number of samples and are shown here for reference only. the device char acteristic illustrated herein are not guaranteed for it accuracy. in some graphs, the data maybe out of the specified warranted operating range. 7ji7jm *o q vu q jot xjui tdinjuu jowfsufs
vih max (-40
to 85
) vih typ 25
vih min (-40
to 85
) vil max (-40
to 85
) vil typ 25
vil min (-40
to 85
) 7ee 7pmu
fi g . 18 vih , v il of p60~p63 , p66 , p67 v s. vdd this s p ecification is sub j ect to chan g e without p rior notice. 39 6.17.2007 v2.0
bj8p508/153 otp rom 7u i * o q vu u i f s ti pm e wpm u b h f
p g * 0 max (-40
to 85
) t yp 25
min(-40
to 85
) 7%% 7pmu
fi g . 19 vth ( th r eshold v olta g e ) of p50~p53, p64~p65 v s. vdd 7p i *p i 7%% 7p i * p i 7%% 7
max 70
min 70
t yp 25
t yp 25
min 0
min 0
7pi 7pmu
7pi 7pmu
fi g . 20 port5 and port6 v oh v s. ioh, vdd=5 v fi g . 21 port5 and port6 v oh v s. ioh, vdd=3 v this s p ecification is sub j ect to chan g e without p rior notice. 40 6.17.2007 v2.0
bj8p508/153 otp rom 7pm*pm 7%%7
max 0
7p m *p m 7%% 7
max 0
t y p 25
t yp 25
min 70
min 70
7pm 7pmu
fig. 22 port5, port6.0~port6.3 and port6.6~port6.7 vol vs. iol, v dd=5 v fig. 23 port5, port6.0~po r t6.3 and port6.6~port6.7 vol vs. iol, vdd=3 v this s p ecification is sub j ect to chan g e without p rior notice. 41 6.17.2007 v2.0
bj8p508/153 otp rom vol/iol (vdd=5v) max 0
t yp 25
min 70
7p m *p m 7%% 7
max 0
t yp 25
min 70
vol (volt ) 7pm 7pmu
fi g . 24 port6.4 and port6.5 vol v s. iol, v dd=5 v fi g . 25 port6.4 and port6.5 vol v s. iol, v dd=3 v this s p ecification is sub j ect to chan g e without p rior notice. 42 6.17.2007 v2.0
bj8p508/153 otp rom 8%5 5j nf @ p v u max 70
t yp 25
min 0
7%% 7pmu
fig. 26 wdt time out period v s. vdd, perscaler set to 1:1 this s p ecification is sub j ect to chan g e without p rior notice. 43 6.17.2007 v2.0
bj8p508/153 otp rom $ f yu q' 5zqj d b m 3 $ 04 $ ' sf rv f r = 3.3 k r = 5.1 k r = 10k r = 100k 7 % % 7 pmu
fig. 27 t y pical rc osc frequency v s. vdd (cext=100pf, temperature at 25
) fi g . 28 t y pical rc osc frequenc y v s. tempe r atu r e ( r and c are ideal components ) this s p ecification is sub j ect to chan g e without p rior notice. 44 6.17.2007 v2.0
bj8p508/153 otp rom *3 $ 04$ 'sf r v f o d z 7%% 7
o s c = 8m hz o s c = 4m hz o s c = 1m hz osc = 455k hz 5fnqfsbuvsf

fi g . 29 internal rc osc frequenc y vs. tempe r ature, vdd=5 v irc osc f r e qu e n c y ( v dd=3 v ) o s c = 8m hz osc = 4m hz osc = 1m hz osc = 455k hz te m pe r a tu r e(
) fi g . 30 internal rc osc frequenc y vs. tempe r ature, vdd=3 v this s p ecification is sub j ect to chan g e without p rior notice. 45 6.17.2007 v2.0
bj8p508/153 otp rom four conditions exist with t he operating current icc1 to icc4. these conditions are as follows: icc1: vdd=3v, fosc=32k hz, 2 clocks, wdt disable icc2: vdd=3v, fosc=32k hz, 2 clocks, wdt enable icc3: vdd=5v, fosc=4m hz, 2 clocks, wdt enable icc4: vdd=5v, fosc=10m hz, 2 clocks, wdt enable typic a l icc1 a nd icc2 vs . te m pe r a tu r e t yp icc2 t yp icc1 temperature (
) fi g . 31 t y pical operatin g current ( icc1 and icc2 ) v s. temperature maxim u m icc1 a n d icc2 vs. t em p e r at u r e max icc2 max icc1 5fn q f s b u v s f

this s p ecification is sub j ect to chan g e without p rior notice. 46 6.17.2007 v2.0
bj8p508/153 otp rom fi g . 32 maximum operatin g current ( icc1 and icc2 ) v s. temperatu r e t y p ical icc3 a n d icc4 vs. t em p e r at u r e t yp icc4 t yp icc3 5fn q f s b u vsf

fi g . 33 t y pical operatin g current ( icc3 and icc4 ) v s. temperature maxim u m icc3 a n d icc4 vs. t em p e r at u r e max icc4 max icc3 t e m p e r a t u r e (
) fi g . 34 maximum operatin g current ( icc3 and icc4 ) v s. temperatu r e this s p ecification is sub j ect to chan g e without p rior notice. 47 6.17.2007 v2.0
bj8p508/153 otp rom two conditions exist with t he standby current isb1 and isb2. these conditions are as follow s isb1: vdd=5v, wdt disable isb2: vdd=5v, wdt enable t y p ical isb1 a n d isb2 vs. t em p e r at u r e t yp i s b2 t yp i s b1 t e m p e r a t u r e (
) fi g . 35 t y pical standb y current ( isb1 and isb2 ) v s. temperatu r e maxim u m isb1 a n d isb2 vs. t em p e r at u r e t yp i s b2 t yp i s b1 t e m p e r a t u r e (
) fi g . 36 maximum standb y current ( isb1 and isb2 ) v s. temperatu r e this s p ecification is sub j ect to chan g e without p rior notice. 48 6.17.2007 v2.0
bj8p508/153 otp rom fi g . 37 ope r atin g v olta g e under tempe r ature r an g e of 0
to 70
osc = 4m h z osc = , )[ max min max min v fig. 38 v-i curve in operating mode, operating frequency is 4m hz 7 7pmu
fig. 39 v-i curve in operating mode, operating fre q uenc y is 32k hz this s p ecification is sub j ect to chan g e without p rior notice. 49 6.17.2007 v2.0
bj8p508/153 otp rom this s p ecification is sub j ect to chan g e without p rior notice. 50 6.17.2007 v2.0 appendix package types: otp mcu package type pin count package size bj8p508apj pdip 8 300 mil bj8p508anj sop 8 150 mil bj8p153apj pdip 14 300 mil bj8p153snj sop 14 150 mil
bj8p508/153 otp rom this s p ecification is sub j ect to chan g e without p rior notice. 51 6.17.2007 v2.0 package information 14-lead plastic dual in line (pdip) { 300 mil
bj8p508/153 otp rom 14-lead plastic small outline (sop) { 150 mil this s p ecification is sub j ect to chan g e without p rior notice. 52 6.17.2007 v2.0
bj8p508/153 otp rom this s p ecification is sub j ect to chan g e without p rior notice. 53 6.17.2007 v2.0 s y mbols dimension in inches min nom max a - - 0.210 a 1 0.015 - - a 2 0.125 0.130 0.135 d 0.367 0.375 0.388 e 0.300 bsc. e1 0.245 0.250 0.255 l 0.115 0.130 0.150 eb 0.335 0.355 0.375 o 0 o 7 o 15 o 8-lead plastic dual in line (pdip) { 300 mil
bj8p508/153 otp rom s y mbols a 0.058 0.064 0.068 a 1 0.004 - 0.010 b 0.013 0.016 0.020 c 0.0075 0.008 0.0098 d 0.191 0.193 0.195 e 0.150 0.154 0.157 e - 0.050 - h 0.228 0.236 0.244 l 0.015 0.025 0.050 o 0 o - 8 o dimension in inches min nom max this s p ecification is sub j ect to chan g e without p rior notice. 6.17.2007 v2.0 54 8-lead plastic small outline (sop) { 150 mil

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