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?2008 silicon storage technology, inc. s71107-06-eol 6/08 1 the sst logo and superflash are registered trademarks of silicon storage technology, inc. combomemory is a trademark of silicon storage technology, inc. these specifications are subject to change without notice. eol preliminary specifications features: ? monolithic flash + sram combomemory ? sst31lf041/041a: 512k x8 flash + 128k x8 sram ? single 3.0-3.6v read and write operations ? concurrent operation ? read from or write to sram while erase/program flash ? superior reliability ? endurance: 100,000 cycles (typical) ? greater than 100 years data retention ? low power consumption: ? active current: 10 ma (typical) for flash and 20 ma (typical) for sram read ? standby current: 10 a (typical) ? flash sector-erase capability ? uniform 4 kbyte sectors ? latched address and data for flash ? fast read access times: ? sst31lf041/041a flash: 70 ns sram: 70 ns ? sst31lf041a flash: 300 ns sram: 300 ns ? flash fast erase and byte-program: ? sector-erase time: 18 ms (typical) ? bank-erase time: 70 ms (typical) ? byte-program time: 14 s (typical) ? bank rewrite time: 8 seconds (typical) ? flash automatic erase and program timing ? internal v pp generation ? flash end-of-write detection ? toggle bit ? data# polling ? cmos i/o compatibility ? jedec standard command set ? packages available ? 32-lead tsop (8mm x 14mm) sst31lf041a ? 40-lead tsop (10mm x 14mm) sst31lf041 product description the sst31lf041/041a devices are a 512k x8 cmos flash memory bank combined with a 128k x8 cmos sram memory bank manufactured with sst?s proprietary, high performance superflash technology. the sst31lf041/041a devices write (sram or flash) with a 3.0-3.6v power supply. the monolithic sst31lf041/041a devices conform to software data protect (sdp) com- mands for x8 eeproms. featuring high performance byte-program, the flash mem- ory bank provides a maximum byte-program time of 20 sec. the entire flash memory bank can be erased and programmed byte-by-byte in typically 8 seconds, when using interface features such as toggle bit or data# polling to indicate the completion of program operation. to protect against inadvertent flash write, the sst31lf041/041a devices have on-chip hardware and software data protec- tion schemes. designed, manufactured, and tested for a wide spectrum of applications, the sst31lf041/041a devices are offered with a guaranteed endurance of 10,000 cycles. data retention is rated at greater than 100 years. the sst31lf041/041a operate as two independent mem- ory banks with respective bank enable signals. the sram and flash memory banks are superimposed in the same memory address space. both memory banks share com- mon address lines, data lines, we# and oe#. the memory bank selection is done by memory bank enable signals. the sram bank enable signal, bes# selects the sram bank and the flash memory bank enable signal, bef# selects the flash memory bank. the we# signal has to be used with software data protection (sdp) command sequence when controlling the erase and program opera- tions in the flash memory bank. the sdp command sequence protects the data stored in the flash memory bank from accidental alteration. the sst31lf041/041a provide the added functionality of being able to simultaneously read from or write to the sram bank while erasing or programming in the flash memory bank. the sram memory bank can be read or written while the flash memory bank performs sector- erase, bank-erase, or byte-pro gram concurrently. all flash memory erase and program operations will automatically latch the input address and data signals and complete the operation in background without further input stimulus requirement. once the internally controlled erase or pro- gram cycle in the flash bank has commenced, the sram bank can be accessed for read or write. the sst31lf041/041a devices are suited for applications that use both nonvolatile flash memory and volatile sram memory to store code or data. for all system applications, the sst31lf041/041a devices significantly improve per- formance and reliability, while lowering power consumption, when compared with multiple chip solutions. the 4 mbit flash + 1 mbit sram combomemory sst31lf041 / sst31lf041a sst31lf041 / 041a4mb flash (x8) + 1mb sram (x8) monolithic combomemory
2 preliminary specifications 4 mbit flash + 1 mbit sram combomemory sst31lf041 / sst31lf041a ?2008 silicon storage technology, inc. s71107-06-eol 6/08 sst31lf041/041a inherently use less energy during erase and program than alternative flash technologies. when programming a flash device, the total energy con- sumed is a function of the applied voltage, current, and time of application. since for any given voltage range, the superflash technology uses less current to program and has a shorter erase time, the total energy consumed dur- ing any erase or program operation is less than alternative flash technologies. the monolithic combomemory elimi- nates redundant functions when using two separate mem- ories of similar architecture; therefore, reducing the total power consumption. the superflash technology provides fixed erase and pro- gram times, independent of the number of erase/program cycles that have occurred. therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose erase and program times increase with accumulated erase/pro- gram cycles. the sst31lf041/041a devices also improve flexibility by using a single package and a common set of signals to perform functions previously requiring two separate devices. to meet high density, surface mount requirements, the sst31lf041 device is offered in 40-lead tsop pack- age and the sst31lf041a device is offered in 32-lead tsop package. see figures 1 and 2 for the pinouts. device operation the combomemory uses bes# and bef# to control oper- ation of either the sram or the flash memory bank. bus contention is eliminated as the monolithic device will not recognize both bank enables as being simultaneously active. if both bank enables are asserted (i.e., bef# and bes# are both low), the bef# will dominate while the bes# is ignored and the appropriate operation will be exe- cuted in the flash memory bank. sst does not recommend that both bank enables be simultaneously asserted. all other address, data, and control lines are shared which minimizes power consumption and area. the device goes into standby when both bank enables are raised to v ihc . see table 3 for sram operation mode selection. for sst31lf041a only: bes# and oe# share pin 32. during sram operation, pin 32 will function as bes#. dur- ing flash operation, pin 32 will function as oe#. when pin 32 (oe#/bes#) is high, the data bu s is in high impedance state. sram operation with bes# low and bef# high, the sst31lf041/041a operate as a 128k x8 cmos sram with fully static opera- tion requiring no external clocks or timing strobes. the sram is mapped into the fi rst 128 kbyte address space of the device for 041/041a. read and write cycle times are equal. sram read the sram read operation of the sst31lf041/041a are controlled by oe# and bes#, both have to be low with we# high, for the system to ob tain data from the outputs. bes# is used for sram bank selection. when bes# and bef# are high, both memory banks are deselected. oe# is the output control and is used to gate data from the out- put pins. the data bus is in high impedance state when oe# is high. see figure 3 for the read cycle timing dia- gram. sram write the sram write operation of the sst31lf041/041a is controlled by we# and bes#; bot h have to be low for the system to write to the sram. bes# is used for sram bank selection. during the byte-write operation, the addresses and data are referenced to the rising edge of either bes# or we#, whichever occurs first. the write time is measured from the last falling edge to the first rising edge of bes# and we#. oe# can be v il or v ih , but no other value, for sram write operations. see figure 4 for the sram write cycle timing diagram. flash operation with bef# active, the sst31lf041/041a operate as a 512k x8 flash memory. the flash memory bank is read using the common address lines, data lines, we# and oe#. erase and program operations are initiated with the jedec standard sdp command sequences. address and data are latched during the sdp commands and internally timed erase and program operations. see table 3 for flash operation mode selection.
eol preliminary specifications 4 mbit flash + 1 mbit sram combomemory sst31lf041 / sst31lf041a 3 ?2008 silicon storage technology, inc. s71107-06-eol 6/08 flash read the read operation of the sst31lf041/041a devices are controlled by bef# and oe#; both have to be low, with we# high, for the system to obtain data from the outputs. bef# is used for flash memory bank selection. when bef# and bes# are high, both banks are deselected and only standby power is consumed. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when oe# is high. see figure 5 for the read cycle timing diagram. flash erase/program operation sdp commands are used to initiate the flash memory bank program and erase operations of the sst31lf041/041a. sdp commands are loaded to the flash memory bank using standard microprocessor write sequences. a com- mand is loaded by asserting we# low while keeping bef# low and oe# high. the address is latched on the falling edge of we# or bef#, whichever occurs last. the data is latched on the rising edge of we# or bef#, whichever occurs first. flash byte-program operation the flash memory bank of the sst31lf041/041a devices are programmed on a byte-by-byte basis. before the pro- gram operations, the memory must be erased first. the program operation consists of three steps. the first step is the three-byte load sequence for software data protection. the second step is to load byte address and byte data. dur- ing the byte-program operation, the addresses are latched on the falling edge of either bef# or we#, whichever occurs last. the data is latched on the rising edge of either bef# or we#, whichever occurs first. the third step is the internal program operation which is initiated after the rising edge of the fourth we# or bef#, whichever occurs first. the program operation, once initiated, will be completed, within 20 s. see figures 6 and 7 for we# and bef# con- trolled program operation timing diagrams and figure 17 for flowcharts. during the program operation, the only valid flash read operations are data# polling and toggle bit. during the internal program operation, the host is free to perform additional tasks. any sdp commands loaded dur- ing the internal program operation will be ignored. flash sector-erase operation the sector-erase operation allows the system to erase the flash memory bank on a sector-by-sector basis. the sector architecture is based on uniform sector size of 4 kbyte. the sector-erase operation is initiated by execut- ing a six-byte command load sequence for software data protection with sector-erase command (30h) and sector address (sa) in the last bus cycle. the address lines a 18 -a 12 will be used to determine the sector address. the sector address is latched on the falling edge of the sixth we# pulse, while the command (30h) is latched on the rising edge of the sixth we# pulse. the internal erase operation begins after the sixth we# pulse. the end-of-erase can be determined using either data# polling or toggle bit methods. see figure 10 for timing waveforms. any sdp commands loaded during the sector-erase oper ation will be ignored. flash bank-erase operation the sst31lf041/041a flash memory bank provides a bank-erase operation, which allows the user to erase the entire flash memory bank array to the ?1?s state. this is use- ful when the entire bank must be quickly erased. the bank- erase operation is initiated by executing a six-byte software data protection command sequence with bank-erase com- mand (10h) with address 5555h in the last byte sequence. the internal erase operation begins with the rising edge of the sixth we# or bef# pulse, whichever occurs first. during the internal erase operation, the only valid flash read oper- ations are toggle bit and data# polling. see table 4 for the command sequence, figure 11 for timing diagram, and fig- ure 20 for the flowchart. any sdp commands loaded during the bank-erase operation will be ignored. flash write operati on status detection the sst31lf041/041a flash memory bank provides two software means to detect the completion of a flash memory bank write (program or erase) cycle, in order to optimize the system write cycle time. the software detection includes two status bits: data# polling (dq 7 ) and toggle bit (dq 6 ). the end-of-write detection mode is enabled after the rising edge of we#, which initiates the internal program or erase operation. the actual completion of the nonvola- tile write is asynchronous with the system; therefore, either a data# polling or toggle bit read may be simultaneous with the completion of the write cycle. if this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either dq 7 or dq 6 . in order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid.
4 preliminary specifications 4 mbit flash + 1 mbit sram combomemory sst31lf041 / sst31lf041a ?2008 silicon storage technology, inc. s71107-06-eol 6/08 flash data# polling (dq 7 ) when the sst31lf041/041a flash memory bank is in the internal program operation, any attempt to read dq 7 will produce the complement of the true data. once the pro- gram operation is completed, dq 7 will produce true data. note that even though dq 7 may have valid data immedi- ately following the completion of an internal write opera- tion, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent suc- cessive read cycles after an interval of 1 s. during inter- nal erase operation, any attempt to read dq 7 will produce a ?0?. once the internal erase operation is completed, dq 7 will produce a ?1?. the data# polling is valid after the rising edge of the fourth we# (or bef#) pulse for program opera- tion. for sector or bank-erase, the data# polling is valid after the rising edge of the sixth we# (or bef#) pulse. see figure 8 for data# polling timing diagram and figure 18 for a flowchart. flash toggle bit (dq 6 ) during the internal program or erase operation, any con- secutive attempts to read dq 6 will produce alternating 0s and 1s, i.e., toggling between 0 and 1. when the internal program or erase operation is completed, the toggling will stop. the flash memory bank is then ready for the next operation. the toggle bit is valid after the rising edge of the fourth we# (or be#) pulse for program operation. for sec- tor or bank-erase, the toggle bit is valid after the rising edge of the sixth we# (or bef#) pulse. see figure 9 for toggle bit timing diagram and figure 18 for a flowchart. flash memory data protection the sst31lf041/041a flash memory bank provides both hardware and software features to protect nonvolatile data from inadvertent writes. flash hardware data protection noise/glitch protection: a we# or bef# pulse of less than 5 ns will not initiate a write cycle. v dd power up/down detection: the write operation is inhibited when is less than 1.5v. write inhibit mode: forcing oe# low, bef# high, or we# high will inhibit the flash write operation. this prevents inadvertent writes during power-up or power-down. flash software data protection (sdp) the sst31lf041/041a provide the jedec approved software data protection scheme for all flash memory bank data alteration operations, i.e., program and erase. any program operation requires the inclusion of a series of three-byte sequence. the three-byte load sequence is used to initiate the program operation, providing optimal protection from inadvertent write operations, e.g., during the system power-up or power-down. any erase operation requires the inclusion of six-byte load sequence. the sst31lf041/041a devices are shipped with the software data protection permanently enabled. see table 4 for the specific software command codes. during sdp command sequence, invalid sdp commands will abort the device to the read mode, within t rc. concurrent read and write operations the sst31lf041/041a provide the unique benefit of being able to read from or write to sram, while simulta- neously erasing or programming the flash. the device will ignore all sdp commands when an erase or program operation is in progress. this allows data alteration code to be executed from sram, while altering the data in flash. the following table lists all valid states. sst does not rec- ommend that both bank enables, bef# and bes#, be simultaneously asserted. note that product identification commands use sdp; therefore, these commands will also be ignored while an erase or program operation is in progress. c oncurrent r ead /w rite s tate t able flash sram program/erase read program/erase write
eol preliminary specifications 4 mbit flash + 1 mbit sram combomemory sst31lf041 / sst31lf041a 5 ?2008 silicon storage technology, inc. s71107-06-eol 6/08 product identification the product identification mode identifies the devices as either sst31lf041 or sst31lf041a and the manufac- turer as sst. this mode may be accessed by hardware or software operations. the hardware device id read opera- tion is typically used by a programmer to identify the correct algorithm for the sst31lf041/041a flash memory banks. users may wish to use the software product identification operation to identify the part (i.e., using the device id) when using multiple manufacturers in the same socket. for details, see table 3 for hardware operation or table 4 for software operation, figure 12 for the software id entry and read timing diagram and figure 19 for the id entry com- mand sequence flowchart. product identificatio n mode exit/reset in order to return to the standard read mode, the software product identification mode must be exited. exiting is accomplished by issuing the exit id command sequence, which returns the device to the read operation. please note that the software reset command is ignored during an internal program or erase operation. see table 4 for soft- ware command codes, figure 13 for timing waveform and figure 19 for a flowchart. design considerations sst recommends a high frequency 0.1 f ceramic capac- itor to be placed as close as possible between v dd and v ss , e.g., less than 1 cm away from the v dd pin of the device. additionally, a low frequency 4.7 f electrolytic capacitor from v dd to v ss should be placed within 1 cm of the v dd pin. table 1: p roduct i dentification address data manufacturer?s id 0000h bfh device id sst31lf041 0001h 17h sst31lf041a 0001h 16h t1.2 1107 i/o buffers 1107 b1.6 address buffers dq 7 - dq 0 oe# bef# we# superflash memory sram control logic bes# a ms - a 0 a ms = most significant address address buffers & latches f unctional b lock d iagram
6 preliminary specifications 4 mbit flash + 1 mbit sram combomemory sst31lf041 / sst31lf041a ?2008 silicon storage technology, inc. s71107-06-eol 6/08 figure 1: p in a ssignments for 40- lead tsop (10 mm x 14 mm ) - sstlf041 figure 2: p in a ssignments for 32- lead tsop (8 mm x 14 mm ) - sstlf041a a16 a15 a14 a13 a12 a11 a9 a8 we# nc bes# nc a18 a7 a6 a5 a4 a3 a2 a1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a17 v ss nc nc a10 dq7 dq6 dq5 dq4 v dd v dd nc dq3 dq2 dq1 dq0 oe# v ss bef# a0 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1107 40-tsop p1.2 standard pinout top view die up a11 a9 a8 a13 a14 a17 we# v dd a18 a16 a15 a12 a7 a6 a5 a4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 oe#/bes# a10 bef# dq7 dq6 dq5 dq4 dq3 v ss dq2 dq1 dq0 a0 a1 a2 a3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1107 32-tsop p2.1 standard pinout top view die up
eol preliminary specifications 4 mbit flash + 1 mbit sram combomemory sst31lf041 / sst31lf041a 7 ?2008 silicon storage technology, inc. s71107-06-eol 6/08 table 2: p in d escription symbol pin name functions a ms 1 -a 0 address inputs to provide memory addresses. a 18 -a 0 to provide flash address a 16 -a 0 to provide sram addresses for sst32lf041/041a during flash sector-erase, a 18 -a 12 address lines will select the sector. dq 7 -dq 0 data input/output to output data during read cycles and receive input data during write cycles. data is internally latched dur ing a flash erase/program cycle. the outputs are in tri-state when oe# or bes# and bef# are high. bes# sram memory bank enable to activate t he sram memory bank when bes# is low. note: for sst31lf041a, bes# and oe# share pin 32. bef# flash memory bank enable to activate the flash memory bank when bef# is low. oe# output enable to gate the data output buffers. note: for sst31lf041a, bes# and oe# share pin 32. we# write enable to control the write operations. v dd power supply 3.0-3.6v power supply v ss ground t2.11 1107 1. a ms = most significant address
8 preliminary specifications 4 mbit flash + 1 mbit sram combomemory sst31lf041 / sst31lf041a ?2008 silicon storage technology, inc. s71107-06-eol 6/08 table 3: o peration m odes s election mode bes# 1 bef# 1 oe# we# a 9 dq address flash read x 2 v il v il v ih a in d out a in program x v il v ih v il a in d in a in erase x v il v ih v il x x sector address, xxh for bank-erase sram read v il v ih v il v ih a in d out a in write v il v ih xv il a in d in a in standby v ihc v ihc x x x high z x flash write inhibit x x v il x x high z / d out x xxxv ih x high z / d out x xv ih x x x high z / d out x product identification hardware mode x v il v il v ih v h manufacturer?s id (bfh) device id 3 a 18 -a 1 =v il , a 0 =v il a 18 -a 1 =v il , a 0 =v ih software mode x v il v il v ih a in id code see table 4 t3.9 1107 1. bes# and bef# cannot be asserted simultaneously. for sst31lf041a bes# and oe# share pin 32. when flash is active, pin 32 becomes oe#. when flash is inactive, pin 32 becomes bes#. 2. x can be v il or v ih , but no other value. 3. device id 17h for sst31lf041 and 16h for sst31lf041a. table 4: s oftware c ommand s equence command sequence 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle addr 1 1. address format a 14 -a 0 (hex), address a 18 -a 15 can be v il or v ih , but no other value, for the command sequence. data addr 1 data addr 1 data addr 1 data addr 1 data addr 1 data byte-program 5555h aah 2aaah 55h 5555h a0h ba 2 2. ba = program byte address data sector-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h sa x 3 3. sa x for sector-erase; uses a 18 -a 12 address lines 30h bank-erase 5555h aah 2aaah 55h 555 5h 80h 5555h aah 2aaah 55h 5555h 10h software id entry 4,5 4. the device does not remain in software product id mode if powered down. 5. with a 18 -a 1 = 0; sst manufacturer?s id = bfh, is read with a 0 = 0, sst31lf041 device id = 17h, is read with a 0 = 1, sst31lf041a device id = 16h, is read with a 0 = 1 5555h aah 2aaah 55h 5555h 90h software id exit 5555h aah 2aaah 55h 5555h f0h t4.7 1107
eol preliminary specifications 4 mbit flash + 1 mbit sram combomemory sst31lf041 / sst31lf041a 9 ?2008 silicon storage technology, inc. s71107-06-eol 6/08 absolute maximum stress ratings (applied conditions greater than t hose listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater t han those defined in the operational sections of this data sheet is not implied. exposu re to absolute maximum stress rating co nditions may affect device reliability.) operating temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20c to +85c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0. 5v to v dd +0.5v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0v to v dd +1.0v voltage on a 9 pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 13.2v package power dissipation capability (ta = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount lead soldering temperature (3 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240c output short circuit current 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 1. outputs shorted for no more than one second. no more than one output shorted at a time. o perating r ange range ambient temp v dd commercial 0c to +70c 3.0-3.6v extended -20c to +85c 3.0-3.6v ac c onditions of t est input rise/fall time . . . . . . . . . . . . . . . 5 ns output load . . . . . . . . . . . . . . . . . . . . . c l = 30 pf see figures 15 and 16
10 preliminary specifications 4 mbit flash + 1 mbit sram combomemory sst31lf041 / sst31lf041a ?2008 silicon storage technology, inc. s71107-06-eol 6/08 table 5: dc o perating c haracteristics (v dd = 3.0-3.6v) symbol parameter limits test conditions min max units i dd power supply current address input = v ilt /v iht, at f=1/t rc min, v dd =v dd max, all dqs open read oe#=v il , we#=v ih flash 12 ma bef#=v il , bes#=v ih sram 40 ma bef#=v ih , bes#=v il concurrent operation 55 ma bef#=v ih , bes#=v il write oe#=v ih , we#=v il flash (program) 15 ma bef#=v il , bes#=v ih sram 40 ma bef#=v ih , bes#=v il i sb 1 standby v dd current 30 a bef#=bes#=v ihc , v dd =v dd max i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 1 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.4 v v dd =v dd min v ih input high voltage 0.7v dd vv dd =v dd max v ihc input high voltage (cmos) v dd -0.3 v v dd =v dd max v ol output low voltage 0.2 v i ol =100 a, v dd =v dd min v oh output high voltage v dd -0.2 v i oh =-100 a, v dd =v dd min v h supervoltage for a 9 pin 11.4 12.6 v bef#=oe#=v il , we#=v ih i h supervoltage current for a 9 pin 200 a bef#=oe#=v il , we#=v ih, a 9 =v h max t5.15 1107 1. specification applies to commercial te mperature devices only. this parame ter may be higher for extended devices. table 6: r ecommended s ystem p ower - up t imings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. power-up to read operation 100 s t pu-write 1 power-up to write operation 100 s t6.2 1107 table 7: c apacitance (ta = 25c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. i/o pin capacitance v i/o = 0v 12 pf c in 1 input capacitance v in = 0v 6 pf t7.2 1107 table 8: r eliability c haracteristics symbol parameter minimum spec ification units test method n end 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t8.4 1107
eol preliminary specifications 4 mbit flash + 1 mbit sram combomemory sst31lf041 / sst31lf041a 11 ?2008 silicon storage technology, inc. s71107-06-eol 6/08 ac characteristics table 9: sram m emory b ank c ycle t iming p arameters (v dd = 3.0-3.6v) symbol parameter sst31lf041/041a-70 sst31lf041a-300 units min max min max t rcs read cycle time 70 300 ns t bes bank enable access time 70 300 ns t aas address access time 70 300 ns t oes 1 1. no t oes value for sst31lf041a output enable access time 35 150 ns t blzs 2 2. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. bes# to active output 0 0 ns t olzs 1 output enable to active output 0 0 ns t bhzs 1 bes# to high-z output 25 30 ns t ohzs 1 output disable to high-z output 25 30 ns t ohs output hold from address change 0 10 ns t9.8 1107 table 10: sram m emory b ank w rite c ycle t iming p arameters (v dd = 3.0-3.6v) symbol parameter sst31lf041/041a-70 sst31lf041a-300 unit min max min max t wcs write cycle time 70 300 ns t bws bank enable to end-of-write 60 230 ns t aws address valid to end-of-write 60 230 ns t asts address set-up time 0 0 ns t wps write pulse width 60 200 ns t wrs write recovery time 0 0 ns t dss data set-up time 30 150 ns t dhs data hold from write time 0 0 ns t10.5 1107 table 11: f lash r ead c ycle t iming p arameters (v dd = 3.0-3.6v) symbol parameter sst31lf041/041a-70 sst31lf041a-300 units min max min max t rc read cycle time 70 300 ns t be bank enable access time 70 300 ns t aa address access time 70 300 ns t oe output enable access time 40 150 ns t blz 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. bef# low to active output 0 0 ns t olz 1 oe# low to active output 0 0 ns t bhz 1 bef# high to high-z output 15 60 ns t ohz 1 oe# high to high-z output 15 60 ns t oh 1 output hold from address change 0 0 ns t11.5 1107
12 preliminary specifications 4 mbit flash + 1 mbit sram combomemory sst31lf041 / sst31lf041a ?2008 silicon storage technology, inc. s71107-06-eol 6/08 table 12: f lash p rogram /e rase c ycle t iming p arameters (v dd = 3.0-3.6v) symbol parameter sst31lf041/041a-7 0 sst31lf041a-300 units min max min max t bp byte-program time 20 20 s t as address setup time 0 0 ns t ah address hold time 30 50 ns t bs we# and bef# setup time 0 0 ns t bh we# and bef# hold time 0 0 ns t oes oe# high setup time 0 0 ns t oeh oe# high hold time 10 10 ns t bp bef# pulse width 40 100 ns t wp we# pulse width 40 100 ns t wph we# pulse width high 30 50 ns t bph bef# pulse width high 30 50 ns t ds data setup time 40 50 ns t dh data hold time 0 0 ns t ida software id access and exit time 150 150 ns t se sector-erase 25 25 ms t sbe bank-erase 100 100 ms t bs bank enable setup time for concurrent operation 00ns t12.4 1107
eol preliminary specifications 4 mbit flash + 1 mbit sram combomemory sst31lf041 / sst31lf041a 13 ?2008 silicon storage technology, inc. s71107-06-eol 6/08 figure 3: sram r ead c ycle t iming d iagram figure 4: sram w rite c ycle t iming d iagram 1107 f02.10 address a 16-0 dq 7-0 we# oe# 1 bes# 1 t bes t rcs t aas t oes t olzs v ih high-z t blzs t ohs t bhzs high-z data valid data valid t ohzs bef# note 1: for sst31lf041a. bes# and oe# share pin 32. during sram operation, pin 32 functions as bes#. 1107 f03.11 address a 16-0 address dq 7-0 oe# 1 we# bes# 1 t bws t wcs t aws t asts t wps t wrs t dss t dhs data valid bef# note 1: for sst31lf041a. bes# and oe# share pin 32. during sram operation, pin 32 functions as bes#.
14 preliminary specifications 4 mbit flash + 1 mbit sram combomemory sst31lf041 / sst31lf041a ?2008 silicon storage technology, inc. s71107-06-eol 6/08 figure 5: f lash r ead c ycle t iming d iagram figure 6: f lash we# c ontrolled p rogram c ycle t iming d iagram 1107 f18.6 address a 18-0 dq 7-0 we# oe# 1 bef# bes# 1 t be t rc t aa t oe t olz v ih high-z t blz t oh t bhz high-z data valid data valid t ohz note 1. for sst31lf041a, bes# and oe# share pin 32. during flash operation, pin 32 functions as oe#. 1107 f04.7 address a 18-0 dq 7-0 t dh t wph t ds t wp t ah t as t ch t cs bef# bes# 1 sw0 sw1 sw2 5555 2aaa 5555 addr aa 55 a0 data internal program operation starts byte (addr/data) oe# 1 we# t bp note 1. for sst31lf041a, bes# and oe# share pin 32. during flash operation, pin 32 functions as oe#.
eol preliminary specifications 4 mbit flash + 1 mbit sram combomemory sst31lf041 / sst31lf041a 15 ?2008 silicon storage technology, inc. s71107-06-eol 6/08 figure 7: bef# c ontrolled f lash p rogram c ycle t iming d iagram figure 8: f lash d ata # p olling t iming d iagram 1107 f05.7 address a 18-0 dq 7-0 t dh t cph t ds t cp t ah t as t ch t cs we# sw0 sw1 sw2 5555 2aaa 5555 addr aa 55 a0 data internal program operation starts byte (addr/data) oe# 1 bef# t bp bes# 1 note 1. for sst31lf041a, bes# and oe# share pin 32. during flash operation, pin 32 functions as oe#. 1107 f06.7 address a 18-0 dq 7 dd# d# d we# oe# 1 bef# t oeh t oe t ce t oes bes# 1 note 1. for sst31lf041a, bes# and oe# share pin 32. during flash operation, pin 32 functions as oe#.
16 preliminary specifications 4 mbit flash + 1 mbit sram combomemory sst31lf041 / sst31lf041a ?2008 silicon storage technology, inc. s71107-06-eol 6/08 figure 9: f lash t oggle bit t iming d iagram figure 10: we# c ontrolled f lash s ector -e rase t iming d iagram 1107 f07.7 address a 18-0 dq 6 we# oe# 1 bef# t oe t oeh t be t oes two read cycles with same outputs bes# 1 note 1. for sst31lf041a, bes# and oe# share pin 32. during flash operation, pin 32 functions as oe#. 1107 f08.9 address a 18-0 dq 7-0 we# sw0 note: the device also supports bef# controlled sector-erase operation. the we# and bef# signals are interchangeable as long as minimum timings are met. (see table 12) sa x = sector address sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 55 30 55 aa 80 aa sa x bef# six-byte code for sector-erase t se t wp oe# 1 bes# 1 note 1. for sst31lf041a, bes# and oe# share pin 32. during flash operation, pin 32 functions as oe#.
eol preliminary specifications 4 mbit flash + 1 mbit sram combomemory sst31lf041 / sst31lf041a 17 ?2008 silicon storage technology, inc. s71107-06-eol 6/08 figure 11: we# c ontrolled f lash b ank -e rase t iming d iagram figure 12: f lash s oftware id e ntry and r ead 1107 f17.9 address a 18-0 dq 7-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 55 10 55 aa 80 aa 5555 bef# six-byte code for bank-erase t sbe t wp note: the device also supports bef# controlled bank-erase operation. the we# and bef# signals are interchangeable as long as minimum timings are met. (see table 12) oe# 1 bes# 1 note 1. for sst31lf041a, bes# and oe# share pin 32. during flash operation, pin 32 functions as oe#. 1107 f09.8 address a 14-0 t ida dq 7-0 we# sw0 sw1 sw2 5555 2aaa 5555 0000 0001 bef# three-byte sequence for software id entry t wp t wph t aa bf device id 55 aa 90 oe# 1 bes# 1 note 1. for sst31lf041a, bes# and oe# share pin 32. during flash operation, pin 32 functions as oe#. note: device id = 16h for sst31lf041a and 17h for sst31lf041.
18 preliminary specifications 4 mbit flash + 1 mbit sram combomemory sst31lf041 / sst31lf041a ?2008 silicon storage technology, inc. s71107-06-eol 6/08 figure 13: f lash s oftware id e xit and r eset figure 14: t iming d iagram for a lternating between f lash /sram and sram/f lash 1107 f10.8 address a 14-0 dq 7-0 t ida t wp t whp we# sw0 sw1 sw2 5555 2aaa 5555 three-byte sequence for software id exit and reset bef# aa 55 f0 oe# 1 bes# 1 note 1. for sst31lf041a, bes# and oe# share pin 32. during flash operation, pin 32 functions as oe#. 1107 f22.0 address a 18-0 t bs dq 7-0 bej# bej1# we# oe# note: j = f or s j1 = s or f
eol preliminary specifications 4 mbit flash + 1 mbit sram combomemory sst31lf041 / sst31lf041a 19 ?2008 silicon storage technology, inc. s71107-06-eol 6/08 figure 15: ac i nput /o utput r eference w aveforms figure 16: a t est l oad e xample 1107 f11.1 reference points output input v it v iht v ilt v ot ac test inputs are driven at v iht (0.9 v dd ) for a logic ?1? and v ilt (0.1 v dd ) for a logic ?0?. measurement reference points for inputs and outputs are v it (0.5 v dd ) and v ot (0.5 v dd ). input rise and fall times (10% ? 90%) are <5 ns. note: v it - v input te s t v ot - v output te s t v iht - v input high test v ilt - v input low test 1107 f12.2 to tester to dut c l
20 preliminary specifications 4 mbit flash + 1 mbit sram combomemory sst31lf041 / sst31lf041a ?2008 silicon storage technology, inc. s71107-06-eol 6/08 figure 17: b yte -p rogram a lgorithm 1107 f13.2 start load data: aah address: 5555h load data: 55h address: 2aaah load data: a0h address: 5555h load byte address/byte data wait for end of program (t bp , data# polling bit, or toggle bit operation) program completed
eol preliminary specifications 4 mbit flash + 1 mbit sram combomemory sst31lf041 / sst31lf041a 21 ?2008 silicon storage technology, inc. s71107-06-eol 6/08 figure 18: w ait o ptions 1107 f14.0 wait t bp , t sbe, or t se byte program/erase initiated internal timer toggle bit ye s ye s no no program/erase completed does dq 6 match? read same byte data# polling program/erase completed program/erase completed read byte is dq 7 = true data? read dq 7 byte program/erase initiated byte program/erase initiated
22 preliminary specifications 4 mbit flash + 1 mbit sram combomemory sst31lf041 / sst31lf041a ?2008 silicon storage technology, inc. s71107-06-eol 6/08 figure 19: s oftware p roduct c ommand f lowcharts 1107 f15.2 load data: aah address: 5555h software product id entry command sequence load data: 55h address: 2aaah load data: 90h address: 5555h wait t ida read software id load data: aah address: 5555h software product id exit & reset command sequence load data: 55h address: 2aaah load data: f0h address: 5555h load data: f0h address: xxh return to normal operation wait t ida wait t ida return to normal operation
eol preliminary specifications 4 mbit flash + 1 mbit sram combomemory sst31lf041 / sst31lf041a 23 ?2008 silicon storage technology, inc. s71107-06-eol 6/08 figure 20: e rase c ommand s equence 1107 f16.2 load data: aah address: 5555h chip-erase command sequence load data: 55h address: 2aaah load data: 80h address: 5555h load data: 55h address: 2aaah load data: 10h address: 5555h load data: aah address: 5555h wait t sbe chip erased to ffh load data: aah address: 5555h sector-erase command sequence load data: 55h address: 2aaah load data: 80h address: 5555h load data: 55h address: 2aaah load data: 30h address: sa x load data: aah address: 5555h wait t se sector erased to ffh
24 preliminary specifications 4 mbit flash + 1 mbit sram combomemory sst31lf041 / sst31lf041a ?2008 silicon storage technology, inc. s71107-06-eol 6/08 product ordering information valid combinations for sst31lf041 sst31lf041-70-4c-wi SST31LF041-70-4E-WI valid combinations for sst31lf041a sst31lf041a-70-4c-wh sst31lf041a-300-4c-wh sst31lf041a-70-4e-wh sst31lf041a-300-4e-wh note: valid combinations are those products in mass production or will be in mass production. consult your sst sales representative to confirm av ailability of valid combinations and to det ermine availability of new combinations. device speed suffix1 suffix2 sst31 l f04x x - xxx -x x -x x package modifier h = 32 leads i = 40 leads package type w = tsop (type 1, die up, 8mm x 14mm) (type 1, die up, 10mm x 14mm) temperature range c = commercial = 0c to +70c e = extended = -20c to +85c minimum endurance 4 = 10,000 cycles read access speed 70 = 70 ns 300 = 300 ns version a = 32-lead tsop package density 041 = 4 mbit flash + 1 mbit sram voltag e l = 3.0-3.6v product series 31 = monolithic combomemory
eol preliminary specifications 4 mbit flash + 1 mbit sram combomemory sst31lf041 / sst31lf041a 25 ?2008 silicon storage technology, inc. s71107-06-eol 6/08 packaging diagrams 32- lead t hin s mall o utline p ackage (tsop) 8 mm x 14 mm sst p ackage c ode : wh 32-tsop-wh-7 note: 1. complies with jedec publication 95 mo-142 ba dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (max/min). 3. coplanarity: 0.1 mm 4. maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 1.20 max. 1mm pin # 1 identifier 12.50 12.30 14.20 13.80 0.70 0.50 8.10 7.90 0.27 0.17 0. 50 bsc 1.05 0.95 0.15 0.05 0.70 0.50 0?- 5? detail
26 preliminary specifications 4 mbit flash + 1 mbit sram combomemory sst31lf041 / sst31lf041a ?2008 silicon storage technology, inc. s71107-06-eol 6/08 40- lead t hin s mall o utline p ackage (tsop) 10 mm x 14 mm sst p ackage c ode : wi table 13: r evision h istory number description date 03 ? 2002 data book feb 2002 04 ? removed the 256 sram parts (sst31lf043/043a) and associated mpns ? corrected the test conditions for i dd in table 5 on page 10 ? added revision history sep 2003 05 ? 2004 data book dec 2003 06 ? end of life for all valid combinations jun 2008 12.50 12.30 14.20 13.80 0.70 0.50 10.10 9.90 0.27 0.17 1.05 0.95 0.15 0.05 0.70 0.50 40-tsop-wi-7 note: 1. complies with jedec publication 95 mo-142 ca dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (max/min). 3. coplanarity: 0.1 mm 4. maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. pin # 1 identifier 0. 50 bsc 1.20 max. 1mm 0?- 5? detail silicon storage technology, inc. ? 1171 sonora court ? sunnyvale, ca 94086 ? telephone 408-735-9110 ? fax 408-735-9036 www.superflash.com or www.sst.com

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