application note AN69 AN69-1 the x24c44 novram teams up with 8051 microcontrollers by rick orlando, january 1990 introduction the x24c44 is a 256-bit serial novram internally con- figured as sixteen 16-bit words of ram overlaid bit for bit with a nonvolatile e 2 prom. the x24c44. has the standard hardware recall and store inputs plus the ability to perform these same operations under soft- ware control, thereby freeing two microcontroller port pins for other tasks. the serial interface allows the x24c44 to be packaged in a low cost space saving 8- pin mini dip. when teamed with the 8051 family of microcontrollers (figure 1), the x24c44s small physi- cal size, software instruction set, and serial interface make it an ideal parameter storage and scratch pad memory, while maintaining full use of the 8051 serial port as a uart. scope this application note describes interfacing the x24c44 with the 8051 family of microcontrollers. emphasis will be placed on the timing considerations of the interface and explaining the modifications to the instruction words for normal device operation. this note assumes the reader has access to a xicor data book and an intel microcontroller handbook. serial port operation port 3 on the 8051 provides a serial port that can be used in two basic configurations, full duplex and half duplex. this note examines the half duplex (mode 0) operation when interfacing to the x24c44. port 3 pin 1 (p3.1) is the clock output for both transmit and receive modes and port 3 pin 0 (p3.0) is used for bidirectional data transfers. the clock output frequency is 1/12 of the xtal oscillator input frequency. to simplify timing calculations, this note will assume an input frequency of 12mhz resulting in a symmetrical 1mhz output on p3.1. AN69_f01.eps 8051 8052 host serial interface x24c44 74hc367 px.x p3.1 p3.0 15 11 12 g 1 2 3 11 10 4 8 +5v 7 6 5 14 13 ce sk di do v cc store recall v ss fi g ure 1. 8051 and x24c44 interface adds scratch pad ram and nonvolatile parameter stora g e via the 8051 microcontroller serial port and still maintain full use of the serial port as a u art .
xicor application note AN69-2 AN69 the p3.1 and p3.0 pins, when inactive (neither trans- mittin g nor receivin g ) are always a lo g ic 1 (high). when a data transfer commences, p3.1 will be low durin g machine cycle states s3, s4, and s5 and w ill be high durin g states s6, s1, and s2. when transmittin g , data is shifted out on p3.0 durin g s6p2 (state 6 phase 2) lsb first. when receivin g , data is sampled durin g s5p2. refer to fi g ure 3 for the basic 8051 serial port timin g . hardware connections the x24c44 directly interfaces with the 8051 with no external circuitry required. di and do of the x24c44 are both tied to p3.0, sk is tied to p3.1, ce is tied to any free port pin confi g ured as an output, and store and recall are tied to v cc (see fi g ure 2). figure 2. basic configuration x24c44 operations review the x24c44 is a serial device and in this application, all chip functions are handled via the software instructions. the 8051 transmits data lsb first, but the instruction format for the x24c44 shows the instruction to be transmitted msb first. this requires a simple transposi- tion of the instruction, msb for lsb. the memory is effectively a fifo, so the data to be stored need not be transposed. internally the x24c44 increments a bit (clock) counter. this is used to indicate the end of an instruction and, if a read or write instruction is received, to increment a bit position pointer. this pointer enables individual ram cells for writin g and readin g . the counter for the pointer increments from zero to fifteen. if ce remains high and sk continues to clock, the counter will rollover from fifteen to zero. the word address does not increment, therefore durin g a write operation, if sk continues to clock and ce is high, a 25th risin g clock ed g e (8 ed g es for instruction + 16 ed g es for the data word + 1) would cause bit position zero to be overwritten. system characteristics under normal operatin g conditions, the x24c44 expects ce to transition low to high when sk is low in order that the first bit of data can be clocked into the x24c44 on the first risin g ed g e of sk. the data is sampled to see if it is "0" (a don't care state) or a "1" which is reco g nized as an instruction start. the 8051, however, places both p3.1 and p3.0 in the high state when not actively transmittin g . this is ok! the x24c44 internally g ates ce and sk; therefore, to gg lin g the port pin controllin g ce to a high effectively g ener- ates the first risin g ed g e of sk, and also clocks in the high present at p3.0 (di). AN69_f03.eps 8051 8052 x24c44 px.x p3.1 p3.0 1 2 3 11 10 4 8 +5v 7 6 5 ce sk di do v cc store recall v ss
AN69-3 xicor application note AN69 figure 3. 12mhz 8051 serial port mode 0 and x24c44 timing AN69_f02.eps xtal2 p3.1/sk p3.0/di p3.0/do s6 s1 s2 s3 s4 s5 s6 s1 s2 s3 1/f sk (1?) t skl (500ns) t skh (500ns) t os (916ns) t dh (84ns) s5p2 data taken what this does is clock a "1" into the x24c44 indicatin g the start of an instruction prior to an y shiftin g operation b y the 8051 serial port. this will require droppin g the leadin g 1" from the instruction. see table 1 for the was/is conditions for the equivalent instructions to be used b y the 8051. the 8051 will still g enerate ei g ht risin g clock ed g es on p3.1 for each b y te loaded into the shift re g ister (sbuf), effectivel y providin g the x24c44 with nine clocks for the first b y te. for the sin g le b y te instructions, the ninth clock and data are i g nored b y the x24c44. refer to fi g ure 4 for the sin g le b y te instruction timin g . writing writin g to the ram arra y is strai g htforward. the write instruction is issued b y the 8051 in the same manner as the sin g le b y te instructions. the msb (ei g hth bit) of the instruction b y te is clocked in on the equivalent ninth clock risin g ed g e. this bit is reco g nized as the first data bit of the transfer and is initiall y written into the addressed word's bit position zero. the 8051 will con- tinue to transmit two more b y tes of actual data. the lsb (bit zero) of the first b y te will be ph y sicall y located in bit position one and all subsequent bits will also be offset b y one. the msb (sixteenth data bit) of the word will be written into bit position zero, overwritin g the last bit of the instruction b y te. refer to fi g ure 5 for the sequence of operations. reading readin g data back from the ram arra y is quite similar. the x24c44 be g ins to shift data out durin g the instruc- tion c y cle (more on this later). after the instruction is shifted out, the 8051 must turn around p3.0 and confi g - ure it as an input. ce and sk are static durin g this period and the do output will remain unchan g ed until after the risin g ed g e of the first 8051 receive data clock. therefore, the first data shifted into the 8051 will be from bit position one, equivalent to the lsb ori g inall y written. refer to fi g ure 5 for the sequence of opera- tions. bus contention there will not be an y bus contention for sin g le b y te instructions or the write command. however, for the read command there could be contention. while the 8051 is still shiftin g out the instruction b y te, the x24c44 be g ins to output data on the same line. refer to fi g ure 5, just aftre the fallin g ed g e of clock ei g ht. the 8051 shifts out data at s6p2. if the data chan g es state from "0" to "1" a hi g h current enhancement fet is turned on for two 8051 s y stem clock c y cles. this is used to provide a fast rise time. at the end of this two c y cle period, the enhancement fet is turned off and the output is held high b y a depletion mode fet that essentiall y looks like a resistor pull-up (refer to intel's microcontroller handbook [1984] pa g es 6-6 and 6-7).
xicor application note AN69-4 AN69 note that the hi g h drive circuit is enabled only for data state chan g es from "0" to "1"; therefore, if the output is already a "1" and another "1" is shifted out on p3.0, the hi g h drive will not be turned on. this depletion fet can source a maximum of 250 m a if the port pin is g rounded. the instruction table indicates that bit seven for the read instruction should be a "1". the reason for this is to g uarantee that the hi g h drive period is off before the x24c44 be g ins to output data. if bit seven were a "0", the 8051 would turn on the hi g h drive circuit to return p3.0 to the inactive state, possibly g eneratin g a hi g h current contention problem with the do output of the x24c44. fi g ure 6 illustrates the timin g involved durin g clock ei g ht. the hi g h drive period of the 8051 is turned off well before the x24c44 be g ins to output data. versatility the do output of the x24c44 is always in the hi g h impedance state unless it is outputtin g data in response to a read command. therefore, the serial port of the 8051 need not be dedicated solely to a serial memory interface. fi g ure 1 illustrates the versatility that this affords. this fi g ure depicts the basic system components required in a remote location controller. notice that the 8051 serial port has access to both the x24c44 and throu g h the use of the ce control line maintains full use of the serial port as a uart. therefore, it can receive downloaded parameters from a host, re-enable the serial port for x24c44 communication, then store the data either tem- porarily in the x24c44 ram array or permanently in the x24c44 e 2 prom array. conclusion this application note has shown that with no extra hard- ware, the x24c44 interfaces directly with the 8051 fam- ily of microcontrollers, providin g a nonvolatile memory stora g e and scratch pad memory, while maintainin g full 8051 uart capabilities. it is the ideal solution for appli- cations where extra memory is required but few port pins are available for implementation. table 1. reconfigured instruction format *note: bit 7 of the read command should be a "1" to avoid bus contention. instruction was is 7654321 0 76543210 wrds 1xxxx0 0 0 x0 0 0xxxx sto 1xxxx0 0 1 x1 0 0xxxx reserved 1 xxxx0 1 0 x0 1 0xxxx write 1aaaa0 1 1 x1 1 0aaaa wren 1xxxx1 0 0 x0 0 1xxxx rcl 1xxxx1 0 1 x1 0 1xxxx read 1a aaa1 1x 1x 1 1aaaa
AN69-5 xicor application note AN69 figure 6. worst case bus contention AN69_f04.eps p3.0/di p3.1/sk i/o n /ce d1 3 2 456789 d2 d0 d3 d4 d5 d6 d7 effective data xfer xx xxi 2 i 1 i 0 x ignored by x24c44 clk1 instruction start AN69_f05.eps p3.0/di p3.1/sk px.x/ce a 3 2 456789 11121314151617 10 19 20 21 22 23 24 25 18 a aa d1 d0 d2 d3 d4 d5 d6 d7 d9 d8 d10 d11 d12 d13 d14 d15 2 1 3 4 5 6 7 8 10 9 11 12 13 14 15 0 effective write instruction instruction start clk1 first data shifting edge bit address for word n bit address rollover AN69_f06.eps p3.0/di p3.1/sk px.x/ce a 3 2 456789 11121314151617 10 19 20 21 22 23 24 25 18 a a a high z clk1 instruction start first data shifting edge p3.0/do d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d0 not recognized throw away figure 4. single byte instructions figure 5. read cycle sequence cks high drive period 8051 depletion mode fet pull-up only p3.0 change from output to inpout worst case contention p3.1 / sk p3.0 0 /d1 p3.0 / do high z high z AN69f06.bm p
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