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ST3020 audio decoder/ encoder datasheet note: sitronix technology corp. reserves the right to change the contents in this document without prior notice. this is not a final specification. some parameters are subject to change version 0.1 2007/06/20 preliminary
ST3020 preliminary ver 0.1 page 2/13 2007/06/20 1 features n dsp based voice/audio processor n operation voltage C core logic: 2.25v~2.7v C i/o pads: 3.0v~3.6v n voltage regulator for core logic n low voltage reset (lvr) _ 2.5v low voltage reset n one pll to generate high system frequency from a 3mhz source _ 12m~30mhz pll output n triple clock sources _ crystal......................................3mhz _ external input... ......3mhz n low power down current _typical current: 3ua n one 16-bit programmable timer n one clocking output n one external interrupt _ edge/level trigger supported n one 14-bit direct-drive dac C maximum current: 145ma n mcu interfaces _ parallel mode n two serial port interfaces(sp) _ programmable data length from 8-bit to 16-bit _ i2s, left/right justified interfaces to external dac/adc n speech playback/recorder _ low bit rate compression (lbrc) _ 1.2k/1.6k/2.4kbps@8khz playback _ 1.6k/2.2k/3.3kbps@11.025khz playback _ ab-repeat _ time stretch (speed up x 2, speed down x 2) _ combine syllable _ encryption _ audio playback (cbr, vbr C all bit rates) _ forward/backward play, ab-repeat _ spectrum gain _ time stretch (speed up x 1.5, speed down x 1.5) _ combine syllable _ encryption _ wav playback _ forward/backward play, ab-repeat _ wav record {(ms-adpcm(3.8:1)} _ software agc _ motion-jpeg playback _ jpeg-baseline decoder 2 general description the ST3020 is a highly integrated and cost-effective dsp based audio processor for various consumer applications. it consists of one powerful dsp for advanced voice decoder and encoder algorithms of natural speech with less memory. it provides low bit rate compression (lbrc) for voice playback, audio playback, motion-jpeg playback, and jpeg-baseline decoder. system clock comes from 3mhz crystal or external input. ST3020 has 32 i/os and these can be either gpio or functional pins. each pin can be programmed to input or output. one external interrupt pin can be requested by external devices. one internal 16-bit dac can provide significant volume equipping with internal amplifier. for particular application or recorder, two general audio interfaces are supported to interface with external dac/adc. audio interface can be configured to i2s or left/right justified compatible mode. there are parallel interface to connect with different mcus.
ST3020 preliminary ver 0.1 page 3/13 2007/06/20 2.1 block diagram reset mcu interface oscxi oscxo dsp core clock generator 16-bit dac sp0 dpa0/tf0 vdd33 dpa1/rf0 dpa2/tx0 dpa3/rx0 dpa4/sclk0 sp1 dpa8/tf1 dpa9/rf1 dpa10/tx1 dpa11/rx1 dpa12/sclk1 lvr power down controller pwd pwda power external interrupt xreq/dpa5 daco d[3:7] wr rd req cmd cs so0/dpa7 so1/dpa15 clko/dpa6 clock out generator special i/o rom timer p/s pmode 2.5v regulator dacovdd33a ram parallel daco general io dpa[14:13] dpb[15:0] rdy cmode[1:0] vccout dacvdd33a dacvss33a vcm pll pllvdd25 pllvss25 pllvdd25a pllvss25a test mode circuit test[2:0] eclk regvdd33 regvss33 vref dacob dacob dacovdd33a dacovss33a dacovss33a vss33 vdd33 vss33 vdd25 vss25 vdd25 vss25 figure 2-1 ST3020 block diagram
ST3020 preliminary ver 0.1 page 4/13 2007/06/20 3 signal descriptions table 3-1 signal function description function group pin name pin # i/o description reset 1 i system reset, low active pwd 1 i power down, low active pwda 1 o power down acknowledge, high active oscxi 1 i crystal input or r-oscillator input. if not used, it connects to gnd osxo 1 o crystal output. if not used, it connects to gnd eclk 1 i external clock input. if not used, it connects to gnd cmode[1:0] 2 i clock source select 01=crystal. eclk connects to gnd 1x=eclk. oscxi and osxo connect to gnd system control test[2:0] 3 i test mode. test[2:0] connect to gnd so[1:0]/ dpa[7,15] 2 o so0/dpa[7], so1/dpa[15] special i/o clko/ dpa[6] 1 o clock output/dpa[6] gpio dap[13,14], dpb[0:15] 18 i/o general i/o external interrupt xreq/dpa[5] 1 i external interrupt/dpa[5] tf0/dpa[0] 1 o transmit frame synchronization/dpa[0] rf0/dpa[1] 1 i receive frame synchronization/dpa[1] tx0/dpa[2] 1 o serial data transmit/dpa[2] rx0/dpa[3] 1 i serial data receive/dpa[3] serial port0/ dpa[4:0] sclk0/dpa[4] 1 o serial clock/dpa[4] tf1/dpa[8] 1 o transmit frame synchronization/dpa[8] rf1/dpa[9] 1 i receive frame synchronization/dpa[9] tx1/dpa[10] 1 o serial data transmit/dpa[10] rx1/dpa[11] 1 i serial data receive/dpa[11] serial port1/ dpa[12:8] sclk1/dpa[12] 1 o serial clock/dpa[12] d[0]/scl 1 i/o parallel : data bus d[1]/sdi 1 i/o parallel : data bus d[2]/sdo 1 i/o parallel : data bus d[3:7] 5 i/o parallel : data bus wr 1 i parallel : write enable, low active rd 1 i parallel : read enable, low active cs 1 i parallel : chip select, low active cmd 1 i parallel : command/data select h : data l : command req 1 o dsp wants to sent command to mcu, low active rdy 1 o dsp permit mcu access data, low active, not used mcu interface pmode 1 i parallel interface select 0: parallel (default). connecting to gnd 1: not used
ST3020 preliminary ver 0.1 page 5/13 2007/06/20 p/s 1 i parallel/serial interface select 0: not used 1: parallel. connect to vdd33. vdd25 2 i 2.5v power vss25 2 i 2.5v power ground vdd33 2 i 3.3v power vss33 2 i 3.3v power ground regvdd33 1 i digital power input of regulator regvss33 1 i digital power ground of regulator pllvdd25 1 i digital power input of pll pllvss25 1 i digital power ground of pll pllvdd25a 1 i analog power input of pll pllvss25a 1 i analog power ground of pll dacvdd33a 1 i analog power input of dac dacvss33a 1 i analog power ground of dac dacovdd33a 2 i analog power input of dac output stage power dacovss33a 2 i analog power ground of dac output stage vccout 1 o 2.5v output of regulator regulator vref 1 o voltage reference daco 2 o dac direct drive pin(+) dacob 2 o dac direct drive pin(-) dac vcm 1 o common mode voltage reference
ST3020 preliminary ver 0.1 page 6/13 2007/06/20 4 electrical characteristics 4.1 absolute maximum rations dc supply voltage: vdd33 ----------- -0.3v to +4.5v operating ambient temperature ---- -10 c to +60 c storage temperature ------------------- -10 c to +125 c 4.2 dc electrical characteristics table 4-1 dc electrical characteristics standard operation conditions: vdd33 = 3.3v, gnd = 0v, t a = 25 c, unless otherwise specified parameter symbol min. typ. max. unit condition operating voltage vdd33 3.0 3.6 v operating voltage vdd25 2.25 2.5 2.7 v operating current i op 1 30 ma run at 24mhz without speaker power down current i pd 3 4.5 m a output driving i od 16 ma output sinking i os 26 ma input low voltage v il 0.6 v input high voltage v ih 1.3 v pull-up resistor r pu 54 k C C CC pd 50 k C C CCCC lvr 2.4 2.5 2.6 v *note: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. all the ranges are stress ratings only. functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. exposed to the absolute maximum rating conditions for extended periods may affect device reliability.
ST3020 preliminary ver 0.1 page 7/13 2007/06/20 4.3 ac electrical characteristics figure 4-1 parallel interface timing diagram table 4-2 timing parameters for figure 4-1 standard operation conditions: vdd33 = 3.3v, gnd = 0v, t a = 25 c remark: d = time of one dsp system clock rating symbol characteristic min. typ. max. unit t ch cmd pin hold time 5 ns t cs cmd pin setup time 5 ns t cyc system cycle time 3.5d ns t cclw write pulse width 0.5d ns t cchw enable h write width 3d ns t cclr read pulse width 0.5d ns t cchr enable h read width 3d ns t ds write data setup time 0.5d ns t dh write data hold time 5 ns t acc read access time 25 ns t oh read data disable time 4 ns
ST3020 preliminary ver 0.1 page 8/13 2007/06/20 5 pad diagram
ST3020 preliminary ver 0.1 page 9/13 2007/06/20 6 device information substrate: gnd pad no. symbol x y 1 tf0 1616.23 62.5 2 rf0 1716 .23 62.5 3 tx0 1816.23 62.5 4 rx0 1916.23 62.5 5 sclk0 2016.23 62.5 6 xreq 2116.23 62.5 7 clko 2216.23 62.5 8 so0 2316.23 62.5 9 tf1 2416.23 62.5 10 rf1 2516.23 62.5 11 tx1 2616.23 62.5 12 rx1 2716.23 62.5 13 sclk1 2826.23 62.5 14 dpa13 2936.23 62.5 15 dpa14 2977.5 406.55 16 so1 2977.5 516.55 17 vdd25 2977.5 626.55 18 vss25 2977.5 736.55 19 test2 2977.5 836.55 20 test1 2977.5 936.55 21 test0 2977.5 1036.55 22 vss33 2977.5 1136.55 23 vdd33 2977.5 1236.55 24 dpb0 2977.5 1336.55 25 dpb1 2977.5 1436.55 26 dpb2 2977.5 1536.55 27 dpb3 2977.5 1636.55 28 dpb4 2977.5 1736.55 29 dpb5 2977.5 1836.55 30 dpb6 2977.5 1936.55 pad no. symbol x y 31 dpb7 2977.5 2036.55 32 dpb8 2977.5 2136.55 33 dpb9 2977.5 2236.55 34 dpb10 2977.5 2 336.55 35 dpb11 2977.5 2436.55 36 dpb12 2977.5 2546.55 37 dpb13 2977.5 2656.55 38 dpb14 2977.5 2766.55 39 dpb15 2940 3107.5 40 vss33 2830 3107.5 41 vdd33 2720 3107.5 42 pwda 2620 3107.5 43 pwd 2520 3107.5 44 d7 2420 3107.5 45 d6 2320 3107.5 46 d5 2220 3107.5 47 d4 2120 3107.5 48 d3 2020 3107.5 49 sdo 1920 3107.5 50 sdi 1820 3107.5 51 scl 1720 3107.5 52 vdd25 1620 3107.5 53 vss25 1520 3107.5 54 cmd 1420 3107.5 55 pmode 1320 3107.5 56 req 1220 3107.5 57 rdy 1120 3107.5 58 wr 1020 3107. 5 59 rd 920 3107.5 60 cs 820 3107.5 pad no. symbol x y 61 p/s 720 3107.5 62 reset 620 3107.5 63 cmode0 520 3107.5 64 cmode1 420 3107.5 65 oscxi 320 3107.5 66 osxo 210 3107.5 67 eclk 100 3107.5 68 vref 62.5 2753.0 69 vccout 62.5 2643 .0 70 regvdd33 62.5 2533.0 71 regvss33 62.5 2433.0 72 pllvss25 62.5 2257.0 73 pllvdd25 62.5 2157.0 74 pllvss25a 62.5 2057.0 75 pllvdd25a 62.5 1957.0 76 dacvss33 62.5 1781.0 77 dacvdd33 62.5 1681.0 78 vcm 62.5 1581.0 79 dacob 62.5 1481 .0 80 dacob 62.5 1381.0 81 dac o vss3 62.5 1281.0 82 dac o vss3 62.5 1181.0 83 dac o vdd3 62.5 1081.0 84 dac o vdd3 62.5 981.04 85 daco 62.5 881.04 86 daco 62.5 781.04
ST3020 preliminary ver 0.1 page 10/13 2007/06/20 7 application circuit 7.1 ST3020 r e q r e s e t p / s c s p w d w r r d d 7 ~ 0 o s c x i o s x o w r d 0 ~ 7 g p i o r d c s n g p i o s o 1 p w d a e c l k p m o d e 2 2 0 c m o d e [ 1 : 0 ] 2 2 0 o s c n c m d a 0 / g p i o 2 2 0 2 2 0 figure 7-1 application circuit diagram note: 1. if any of oscxi, osxo, and eclk is not used, it needs to connect to gnd. 2. the cascade resistor and parallel capacitor on cmd, rd, wr, and cs pins can reduce noise interference. in general, resistor is short and capacitor is open. please preserve the options on pcb.
ST3020 preliminary ver 0.1 page 11/13 2007/06/20 7.2 adc 2 k 1 . 2 k 1 . 5 k 1 0 k 1 0 k figure 7-2 adc application circuit diagram
ST3020 preliminary ver 0.1 page 12/13 2007/06/20 7.3 dac figure 7-3 dac application circuit diagram
ST3020 the above information is the exclusive intellectual property of sitronix technology corp. and shall not be disclosed, distributed or reproduced without permission from sitronix. sitronix technology corp. reserves the right to change this document without prior notice and makes no warranty for any errors which may appear in this document. sitronix products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where products failure could result in injury, or loss of life, or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. preliminary ver 0.1 page 13/13 2007/06/20 8 revision revision description page date 0.1 first release 2007/06/20

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