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publication# 20381 rev: a amendment/ 0 issue date: march 1996 this document contains information on a product under development at advanced micro devices. the information is intended to help you evaluate this product. amd reserves the right to change or discontinue work on this proposed product without notice. magic packet technology application in hardware and software application note abstract this application note addresses the use of the magic packet technology in conjunction with green pc hardware and system-level software. its objective is to assist individuals in using this new tech- nology in their own environments. introduction over the last few years, two technologies have evolved that seem to be competing rather than complementing each other at the pc desktop. these technologies are network technology and green pc technology. the connectivity rate in large companies using network technology has been increasing exponentially. this trend has resulted in an on-going need for network management and for network managers to have access to pcs on their networks. at the same time, the concept of green pcs has gained momentum because the environmental protection agency (epa) began encouraging the use of low-power computers to conserve energy. network administrators and information systems (is) personnel in large companies are required to perform tasks, such as backups or installation of software up- grades, at remote sites at night when system downtime does not impact the users. however, these tasks per- formed after hours require the users to leave their ma- chines on overnight, resulting in twice as much electricity consumed as daytime usage (16 hrs. vs. 8 hrs.). green pcs, however, are not network friendly. that is, if the machine is asleep (in a low-powered state), it cannot be addressed from the network, thus hindering the network administrators from doing their nightly tasks. working together, amd and hewlett packard (hp) came up with a solution to this problem. since power is generally on inside a green machine, the network side of the machine could be left in a state, whereby it would continue to scan every packet coming in from the net- work, this time looking for the special data sequence that would serve to wake up the sleeping machine. the value that separates one machine from another on an ethernet network is its unique ieee address. this unique address repeated 16 times in a row anywhere within a valid network frames data ?ld was chosen to serve as the wake-up call. this frame has now been called a magic packet frame. in the interest of making magic packet technology an industry standard, amd is licensing this technology to network vendors at minimal cost, royalty free, so that all vendors can enjoy its bene?s. although magic packet technology is not limited to any particular type of ethernet connection, the only connection that makes sense from a low-power standpoint is a 10base-t connection. the green computer hardware implementation and the software interface now stand in opposition to the ?al solution. this application note is meant to pull the solu- tion together in a concise format providing a way for pc vendors and embedded system users to implement amds magic packet technology. divided into two sec- tions, this application note addresses (1) the hardware interface for three different hardware models and (2) how the dos-level magic packet software driver inter- faces both with the operating system and the hardware to bring a complete solution to the marketplace. currently, amd has designed magic packet technology into two of its network controllers, the pcnet-isa ii (79c961a) and the pcnet-pci ii (79c970a). both of these controllers are available and in production today. for further information, refer to the following amd data sheets: am79c961a data sheet (pid 19364) and am79c970a data sheet (pid 19436). hardware in the competitive pc environment, green has become the byword for the next new standard system feature. the original targets by the department of energy (doe) in its green recommendations were 30 watts (w) for the system box and 30 w for the monitor in a low power state. since these values were relatively easy to obtain in current technology, the market shifted to ask- ing the question, ?ow deep a shade of green is your system? there now stands at least three different so- lutions to obtaining green status in the market. the fol- lowing solutions are ordered from most power used to least power used:
2 ma gic p ac ket t ec hnology application in har d ware and software 1. simply lo w er the cloc k speed on the motherboard to a slo w speed, usually 8 mhz. shut do wn all disks and stop all synchs at the video controller . 2. stop the processor cloc k, putting the dram in slo w refresh, in addition to solution 1. 3. suspend to disk all dram and control registers , and then po w er off the entire system, lea ving a small auxiliar y po w er supply to some circuits to allo w them to a w ak en the sleeping machine . in e xamining each option belo w , an increasing le v el of comple xity will be f ound in the hardw are solutions to implement the magic p ac k et technology . in time , some system v endors ma y use each of these le v els in the or- der ly shutdo wn of the bo x to meet the needs of the g reen pc mar k et. har d ware model 1 hardw are model 1 requires no hardw are , softw are , or e v en magic p ac k et technology f or implementation, be- cause nothing in the system bo x, e xcept the disks , is shut do wn. all netw or k activity is fully aliv e and the speed of the cpu can be v ar ied with the interr upt r ate being handled. the cpu is not stopped and the net- w or k controller is not required to do an ything diff erently . har d ware model 2 hardw are model 2 requires some le v el of interf ace . since cloc ks are stopped in this implementation, some- thing m ust be used to retur n the system to nor mal op- er ating mode . without the netw or k card installed in the system bo x, either a k e ystrok e or mouse mo v ement could repo w er the system to full po w er . in reality , either of these actions could cause an interr upt on the bac k- plane . this model contains a circuit added b y chipset v endors to monitor speci cally designated interr upts f or activity and then retur n the cloc k to the cpu , signal- ing this e v ent through a technique kno wn as system management interr upt (smi). since amd controllers already use an interr upt line to signal that the dr iv er s ser vice is needed f or netw or k-re- lated activities , this same interr upt line can be used to w ak e the system as w ell. this w aking interr upt can be added to the designated interr upt list in the main sys- tem board setup men u. ho w e v er , with the pci cloc k stopped, neither direct memor y access (dma) activity nor magic p ac k et interr upt gener ation b y the controller on the pci b us can tak e place . since nor mal oper ation of amd s netw or k controllers requires dma activity , the y m ust be placed in magic p ac k et mode . currently , pcnet-isa ii and pcnet-pci ii suppor t this . in this mode , the amd controller will not initiate an y dma activity . all incoming data is scanned b y the address recognition logic until a magic p ac k et is receiv ed. when this occurs , mpint is set in csr 5 (bit 4) and will be repor ted through the interr upt pin if mpinte is set in csr 5 (bit 3). the use of these tw o bits will be discussed later in the softw are section. the le v el of compliance required (f or both g reen and netw or k ) can be done on an y current card or mother- board implementation on the open mar k et, using either pcnet-isa ii or pcnet-pci ii as the netw or k controller solution, without need f or an y hardw are addition or modi cation. ho w e v er , there is one issue that m ust be considered. that is , if the pcnet-pci ii par t is used and the pci cloc k is stopped when in standb y mode , a pci interr upt cannot be gener ated and an led pin m ust be used to perf or m the interr upt oper ation. har d ware model 3 t o mak e hardw are model 3 w or k, se v er al issues need to be solv ed in the hardw are implementation. current technology f or the complete system po w er do wn and w ak e up calls f or a modem r ing detect input to w ak e up the sleeping unit. when the modem is called the rst time , the r ing detector pulses a logic input to the sys- tem bo x. because the ser ial por t does not ha v e the data set ready (dsr) tr ue , the modem does not an- s w er . ho w e v er , the system star ts its po w er up . the call- ing par ty times out and calls again, and b y this time , the system is po w ered up and ready . this is the model to be em ulated in the netw or k adapter card using magic p ac k et technology . since the netw or k card is plugged into the bac kplane , which will be po w ered do wn, the po w er f or the netw or k card m ust come from an alter nate source . this po w er is usually supplied b y an auxiliar y po w er supply connection, and the nor mal +5 v olt (v) connec- tion to the isa or pci b us connector is an open circuit. this auxiliar y supply w ould ha v e to be ab le to supply an additional 100 milliamperes (ma). a z ero ohm ( w ) jumper could be used here to mak e the card a man u- f actur ing con gur ab le unit f or use with or without auxil- iar y po w er supplies . if the pcnet controller w as cer ti ed f or +5/-10% vcc toler ance , then a lo w resistance p channel field eff ect t r ansistor (fet) could be utiliz ed to pro vide a direct no jumper suppor t of the pr inted circuit board (pcb) be- tw een bac kplane v oltage and auxiliar y v oltage as the system w as con gured. the gate of the fet w ould be dr iv en with the auxiliar y v oltage connector and w ould isolate the po w er planes from the bac kplane if the aux- iliar y po w er supply w ere present. ho w e v er , this w ould add to the cost and comple xity of the pcb design. f or f eder al comm unications commission (fcc) pur poses , a set of chok es or pref er ab ly a balun should be added with b ypass capacitors to pre v ent f alse g round loops from r adiating noise on the auxiliar y po w er connector . the ne xt issue that m ust be addressed is that of reset. since the po w er on the bac kplane will be cycling, a
ma gic p ac ket t ec hnology application in har d ware and software 3 reset on the rst po w er up and then on the po w er do wn will occur , and y et a third reset on the subsequent po w er up . since a reset to an amd controller w ould tak e the magic p ac k et detection logic off line , at least the second reset has to be b loc k ed, or the media ac- cess controller (ma c) will be tak en off line and the magic p ac k et fr ame will not be seen. in order f or the netw or k card to be used together with the modem r ing detection logic , there m ust be an e xter- nal signal that comes from the controller on the card that tells the modem logic to w ak e up the system. amd designers f oresa w this need and pro vided that the de- tection of a magic p ac k et fr ame be indicated on an y of the led pins . this is enab led b y setting mpse (bit 9) in an y of the respectiv e led control registers . ho w e v er , some of the led registers do ha v e po w er-up def ault v alues that ma y be the wrong polar ity f or the modem logic. only led3 has a def ault v alue to tr ansmit activity that on po w er up or reset can be guar anteed to pro vide a signal to the modem logic with the correct polar ity . theref ore , the led3 pin has to be the e xter nal connec- tion f or magic p ac k et indication. figures 1 and 2 sho w the schematic and gener al timing diag r am f or a correct led3 implementation using either pcnet-isa ii or pcnet-pci ii. magic p ac k et mode is enab led b y perf or ming three steps . first, the pcnet-isa ii or pcnet-pci ii controller m ust be put into suspend mode , allo wing an y current netw or k activity to nish. ne xt mpmode (csr 5, bit1) m ust be set to one if it has not been set already . fi- nally , either sleepl m ust be asser ted (hardw are con- trol) or mpen (csr 5. bit 2) m ust be set to one (softw are control). of the tw o w a ys , the softw are w a y is pref er ab le because the only w a y on an adapter card to detect po w er going do wn is to monitor the bac kplane vcc or reset to set the sleep pin. this could cause magic p ac k et mode to happen in the middle of a dma cycle resulting in a dma prob lem (as po w er is going do wn) that ma y result in loss of data. the only w a y to coordinate going into magic p ac k et mode with the op- er ating system is b y using the softw are-enab led magic p ac k et mode . ho w the softw are w or ks will be dis- cussed in the ne xt section. p al equation discussion since amd s current controllers do not ha v e all the nec- essar y interf ace circuitr y b uilt into them, an e xter nal p alce16v8 is used in this application to pro vide the necessar y interf ace to the system b us reset and to pro vide the proper polar ity f or the led3 pin to interf ace to the modem r ing detect. in the case of the system v endor used f or demonstr ation pur poses , modem r ing detect w as positiv e tr ue , while the led3 pin is negativ e tr ue on po w er up def ault. appendix a contains the p alasm equations f or the p alce16v8 used. this p al s function is mainly to condition the reset pin of the pcnet controller and to interf ace the led3 pin to the system v endor s po w er control circuitr y . most of the p al is used to b uild an asynchronous state machine used to decide when to b loc k the second reset (the one gener ated when po w er is going do wn). depending on whether the system sim- ply reloads the memor y image and tak es off , or the system is restar ted from g round up , will deter mine whether subsequent repo w er-up resets need to be b loc k ed also . in system oper ation, the rst po w er supply to reach its nal oper ating v oltage le v el is the auxiliar y po w er sup- ply . this usually happens when the machine is simply plugged into the w all. the auxiliar y po w er supply po w- ers the p alce16v8 and the pcnet controller . it will be some time later when the po w er s witch is tur ned on f or the main system po w er , and the interf ace reset be- comes activ e f or the rst time while main po w er is r ising to its nal v oltage le v el. f rom initial auxiliar y po w er supply tur n on to the end of the system reset , the reset pin of the pcnet control- ler m ust be held activ e to ensure the pcnet controller state . theref ore , the equations f or s_r_reset deter- mine the initial time when auxiliar y po w er has come on f or the rst time and the main po w er supply has not come on y et. this is accomplished b y using an e xclu- siv e or in the rst tw o ter ms of the equation using pullup and nc2, which gener ates a 2 tpd pulse , set- ting s_r_reset tr ue . this is then reinf orced b y the third ter m in a positiv e f eedbac k loop . s_r_reset will then be held tr ue until the rst system reset (reset_in) becomes tr ue . once s_r_reset goes f alse , it will ne v er come tr ue again until the auxiliar y po w er supply goes off and comes bac k on again. the equation reset_t o_chip is used to condition the reset pin on the pcnet controller . the rst ter m s_r_reset will pro vide reset until the main po w er supply comes on. then reset_in will reset s_r_reset , b ut because first_time is f alse , it will also pro vide reset to the pcnet controller . the third ter m in this equation is only used if the system being po w ered bac k up reestab lishes the netw or k dr iv er . if the system only reloads the dram image and does not e x ecute config.sys and autoexec.bat , then this line should be commented out in the p alasm compile . the equation first_time is used to sense when the pcnet controller has estab lished its def ault eepr om v alues , b y using the eepr om cloc k to cloc k a ip- op whose d input is the f alse of s_r_reset . the amp alce16v8 has an inter nal po w er-on reset circuit f or all ip- ops; theref ore , it can be guar anteed that this ip- op will alw a ys come up in the reset condition. this ip- op is then used to qualify what is done with reset_in and the f act that vcc at the bac kplane in- terf ace has gone a w a y (vcc_gone on pin 3 is simply
4 ma gic p ac ket t ec hnology application in har d ware and software tied to one of the bac kplane vcc pins and pro vides a sense condition f or the bac kplane po w er). the equation sec_reset_ok is used to pro vide a state of indication betw een the po w er do wn and the re- po w er up due to the presence of a magic p ac k et fr ame . the rst and the third ter ms are used in the e v ent that someone uses the po w er s witch on the front panel, r ather than at the arr iv al of a magic p ac k et fr ame . the second ter m is used if a magic p ac k et arr iv es and is in- dicated b y led3. led3 will go a w a y on a magic p ac k et arr iv al condition after po w er comes up and the reset_in is allo w ed to go the reset_t o_chip through the third ter m of reset_t o_chip . the equation led3_out is used to both in v er t the po- lar ity of the led output dr iv er as w ell as and the indi- cation of a magic p ac k et fr ame s presence with the state of bac kplane vcc . the polar ity is dictated b y the system v endor and the spare output ma y also be used to gener ate the negativ e tr ue output f or those systems that w ould pref er that condition. appendix a giv es the equations f or an implementation using the pcnet-isa ii controller . the pcnet-pci ii controller is similar b ut has some diff erences . because of the architecture of the pcnet-pci ii par t, the led pins are m ultiple x ed with the eepr om pins . the equa- tions applicab le to pcnet-pci ii are giv en in appendix b . the timing f or the pci v ersion is sho wn in figure 3. pcnet issues after these p al discussions , the issue of ha ving the pcnet controller s i/o pins dr iving the bac kplane b us while po w er is do wn on the motherboard m ust be ad- dressed. the pcnet-isa ii controller only has one ac- tiv ely dr iv en high non-tr istated output on the dreq pin selected. since the current f or this pin is limited, the only issue will be the small amount of e xtr a current dr a wn on the auxiliar y po w er supply . the pcnet-pci ii does not ha v e the same issues as the pcnet-isa. when the ma c is put into magic p ac k et mode , all b us interf ace output pins are placed into high z. the e xpansion r om pins are not tr istated so an e x- pansion r om m ust also be po w ered off the auxiliar y po w er supply . ho w e v er , the pcnet-pci ii does ha v e one other consider ation. that is , this controller has tw o sets of po w er pins , one f or the core and the other f or the i/o b uff ers . this w as done to suppor t both 5-v pci b us interf ace and 3.3-v pci interf ace b y connecting the vio pins of the pci b us interf ace to the vb uff er pins on the pcnet-pci ii controller . these po w er pins w ere de- signed to ne v er ha v e to go belo w 3.0 v in a w or king system. ho w e v er , when a motherboard po w ers do wn, these pins will go to 0 v . this can cause inter nal break- do wn on the chip , so the v oltage (vb uff er) pins m ust be connected to the auxiliar y po w er supply . this implies that this card design will not suppor t a 3.3-v pci b us . softw are the softw are issues of interf acing the netw or k dr iv ers and magic p ac k et code with the oper ating system will be discussed in this section. the only demonstr ab le code w or king toda y is in the dos and windo ws 3.1/ windo ws f or w or kg roups 3.11 en vironment. os2 and other en vironments , probab ly with similar implementa- tion schemes , will not be discussed here . the po w er management standard in a dos system w as estab lished b y microsoft and intel b y w a y of the adv anced p o w er management (apm) speci cation. in the apm speci cation, some system interr upts w ere estab lished to inf or m the necessar y dr iv ers needing the inf or mation that the system is prepar ing f or po w er do wn or going to resume from a po w er do wn state . un- f or tunately , b y the time the apm speci cation w as cre- ated, all the interr upts dos w as using w ere already tak en. theref ore , interr upt 2f w as chosen to be the apm interr upt. interr upt 2f had been the catchall f or miscellaneous interr upts , so that an y dr iv er associating with this interr upt has to chec k to see if this interr upt is e v en a v ailab le f or its use . theref ore , it is this interr upt that will be used in the dos-based t er minate sta y resident (tsr) dr iv er . appendix c sho ws the dos tsr de v eloped to do the interf ace betw een dos and the pcnet controller and the netw or k dr iv er . in the w a y the oper ating system and the netw or k dr iv- ers w or k, the apm is unkno wn to the netw or k stac k. this ma y change in the future , b ut f or no w the real in- terf ace will be betw een the oper ating system and the hardw are itself . once loaded, the netw or k dr iv er oper- ates str ictly off interr upts , so that if there are no inter- r upts it simply is asleep and w aiting. the hardw are is set up b y the dr iv er to gener ate interr upts only f or the receiv e activity . the tr ansmit activity is initiated b y a system call to the disk redirector , which e v entually l- ters do wn to a call to the tr ansmit routine . theref ore , if the system goes to sleep , there will be no redirection eff or t, because no prog r ams will be r unning. if the pcnet hardw are is put in the suspend mode bef ore being put into magic p ac k et mode , then an y receiv e ac- tivity will be used f or magic p ac k et detection only . because of this independence betw een the magic p ac k et tsr dr iv er and the netw or k dr iv er , it w as de- cided to treat them as separ ate entities . the adv an- tage is that both prog r ams can be independently re vised as needed. in addition, the tsr is wr itten so that it can be loaded in an y order with respect to the netw or k dr iv er , and both can coe xist. if the tsr is loaded without the netw or k dr iv er , then the magic p ac k et functionality will not w or k, because the ma c is ne v er initializ ed and enab led, and there is no damage done to the oper ating system or the oper ation of the base system.
ma gic p ac ket t ec hnology application in har d ware and software 5 (see the flo wchar ts section f or a step-b y-step illustr a- tion of the magic p ac k et tsr dr iv er softw are .) if the magic p ac k et tsr did w ant to initializ e the pcnet par t because a 2f interr upt w as receiv ed, the stop bit could be chec k ed in the tsr. if the controller w as f ound stopped, the f ollo wing could be a minim um procedure to place the ma c on line: 1. wr ite the ieee address of the node directly to the p adr. 2. wr ite the mode register (csr 15) with drx and dtx set to 1. 3. set csr 4 and csr 5 as the y should be f or magic p ac k et mode . 4. set st ar t bit in csr 0 to 1. the tsr prog r am listing in appendix c is basically di- vided into tw o par ts . the rst par t of the code is located in the last par t of the listing. this is the initialization par t of the code . after the code r uns f or the rst time , this code drops off and the second par t of the code , the tsr itself , sta ys behind to do the interf ace job . the initialization is responsib le f or tw o tasks . first, the controller m ust be searched out on the bac kplane . since the pcnet-isa ii and the pcnet-pci ii are on tw o diff erent b usses , the method of emplo ying the search is diff erent. the isa controller is f ound b y looking f or the char acter istic ?7 (ascii w ) at location xxf in the reg- ister space . this search is star ted at the base address of 200h and incremented b y 20h until f ound. if there is no isa controller f ound, then the search is made on the pci b us . the search on the pci b us is accomplished b y using a call to the pci bios and asking the pci bios to nd the v endor id of 1022h. if no controller is f ound, the softw are dr iv er retur ns to dos outputting a message to that f act and does not lea v e the tsr stub . if a controller is f ound, the controller is e xamined to ensure that it suppor ts magic p ac k et mode . if the controller f ound is not magic p ac k et capab le , then the softw are dr iv er re- tur ns to dos outputting that f act and does not lea v e the tsr stub . if the controller f ound is magic p ac k et capab le , then the address of the controller is stored f or later use b y the tsr itself . this v alue is sa v ed within a data area of the tsr itself . bef ore hook- ing the 2f v ector , the tsr prog r ams magic p ac k et mode in csr 5 and sets dpoll in csr 4 (bit 12) to disab le polling. after sa ving the address and the initial- ization routine , the tsr then prepares f or the hooking of the 2f v ector . this is done b y rst getting the current cs:ip of the rst routine in the stac k in the v ector tab le and sa ving it in a data str ucture of the tsr. then the address of the tsr (cs:ip) is put in place of that v ector entr y in the tab le and a retur n is done to dos , b ut this time the softw are dr iv er lea v es the tsr par t of the code activ e and w aiting. the tsr is a simple procedure in that it is no w hook ed at the top of the 2f chain. once a 2f interr upt is re- quested, the softw are dr iv er will be called and rst in- terrogates the call b y looking at the ax register f or a v alue of 530bh, which is f or an apm function. if it is not 530bh, then the softw are dr iv er simply restores the ag register and calls the routine belo w . if it is a 530bh, then the softw are dr iv er looks at bl f or a v alue of 2 or 3. if bl is a 2, then the softw are dr iv er is requested to prepare f or a suspend (not the amd controller sus- pend), and if it is a 3, the softw are dr iv er is being re- quested to do a po w er up resume . if it is an y other v alue , the softw are dr iv er simply restores the ag reg- ister and calls the routine belo w . f or a suspend , the routine does tw o things . it uses the stored controller address that w as f ound in the initial- ization of the tsr to prepare the led3 control register to output the indication of a magic p ac k et fr ame f ound on this pin. this is done b y setting mpse (bit 9) in the bcr7 register to suppor t hardw are model 3. if the in- terr upt method is used, then this step could be skipped. a consider ation might also be to disab le all other led pin dr iv ers b y setting bit leddis (bit 13) to 0 (f alse) to conser v e po w er on the auxiliar y po w er supply . then csr 5 is prog r ammed to enab le magic p ac k et mode . it is dur ing the wr ite to csr 5 that the magic p ac k et in- terr upt method can be controlled b y setting the appro- pr iate enab le bit. this corresponds to hardw are model 2. after that, the ax, dx, and ag registers are x ed and control is passed to the ne xt tsr in the 2f chain. if a bl of 3 is f ound, the softw are dr iv er will do a po w er up resume . here the prog r am simply does a wr ite of the csr 5 register to clear the magic p ac k et enab le and suspend bits , and then x es the ax, dx, and ag reg- isters and passes control to the ne xt routine . if the in- terr upt method w ere emplo y ed, then the interr upt bit w ould ha v e to be reset as necessar y . conclusions the magic p ac k et technology enab les better w or king netw or ks within the cor por ate en vironment and can easily be added to a g reen enab led computer at little or no cost abo v e the standard system cost, as indicated b y this application note . this represents a strong v alue proposition f or the magic p ac k et technology to become the standard in the mar k et place , allo wing ear ly imple- mentors to be on the leading edge of a ne w standard with a small in v estment.
6 ma gic p ac ket t ec hnology application in har d ware and software figures figure 1. p al and pcnet contr oller sc hematic figure 2. isa v er sion timing dia gram pcnet controller reset jumper out for power managed bus interface pal 16v8 reset_to_controller modem ring detect eeprom_clk auxiliary power supply led3 *positive true for isa, negative true for pci +5 v +5 v *reset a/d/control l 3 l 4 l 1 l 2 +5 v v cc _gone (l 1 to l 4 = 10 m h) pin 1 led3_out +5 volt aux +5 volt main eeprom_clk first_time s_r_reset reset_in reset_to_chip led3 led3_out timing diagram for isa version
ma gic p ac ket t ec hnology application in har d ware and software 7 figure 3. pci timing dia gram +5 volt aux +5 volt main eeprom_clk reset_in reset_to_chip led3 led3_out timing diagram for pci
8 ma gic p ac ket t ec hnology application in har d ware and software flo wc har ts magic tsr enter power tsr enter install is ?f?inter. 530b? no yes is bl = 2 ? yes no normal_resume suspend_req is bl = 3 ? yes no jump to hooked routine indirect old_2f_vector jump to hooked routine indirect old_2f_vector suspend_req set up ds and save dx set led3 req (bcr7) with 0200 set csr4 for disable polling set csr5 for magic packet enable 0006 restore ax and ds and dx and flags jump to hooked routine indirect old_2f_vector
ma gic p ac ket t ec hnology application in har d ware and software 9 save ds and dx set up ds set csr5 to 0002 restore ds, dx ax and flags normal_resume jump to hooked routine indirect old_2f_vector install look for isa card at 20f using ?7 increment search address by 20 card found ? no found all address used 3ef? yes exit_to_dos exit_to_dos no is machine pci bios? no yes yes is pci type ?? no yes a
10 ma gic p ac ket t ec hnology application in har d ware and software scan for amd device using pci bios get address of card through pci bios remove extra 1 exit_to_dos exit_to_dos found card ? no yes if isa card is it isa ii? no yes b a found set csr5 to 2 for magic packet sleep enable save ax in found_address save entry point of power_tsr in 2f vector get the old 2f vector and save (cs:if) in old_2f_vector exit_to_dos return to dos but keep power_tsr in int 27 if pci card is it pci ii? no yes b int 25a output fail message (return to dos) int 21 exit_to_dos
ma gic p ac ket t ec hnology application in har d ware and software 11 appendix a p al equations ; palasm design description ;---------declaration segment----------- title magic packet converter pattern mag_pkt.pds revision a author david stoenner company amd date 02/02/95 chip _mag_pkt palce16v8 ---------------pin declarations--------- pin 1 eeprom_clk pin 2 reset_in pin 3 /vcc_gone pin 4 /led3 pin 5 /pullup pin 10 gnd pin 11 /oe pin 12 reset_to_chip pin 13 /first_time pin 14 spare pin 15 led3_out pin 16 sec_reset_ok pin 17 /s_r_reset pin 18 /nc1 pin 19 /nc2 pin 20 vcc ;-------- boolean equation segment ----- - equations led3_out = led3 * vcc_gone nc1 = pullup nc2 = nc1 s_r_reset = pullup * /nc2 * /reset_in + /pullup * nc2 * / reset_in + s_r_reset * /reset_in sec_reset_ok = first_time * vcc_gone + sec_reset_ok * led3 + sec_reset_ok * reset_in first_time := /s_r_reset reset_to_chip = s_r_reset + /first_time * reset_in + first_time * sec_reset_ok * reset_in
12 ma gic p ac ket t ec hnology application in har d ware and software appendix b p alasm design description ;palasm design description ;---------- declaration segment -------- - title magic packet convertor pattern mag_pci.pds revision a author david stoenner company amd date 08/28/95 chip _mag_pkt palce16v8 ;------------- pin declarations -------- - pin 1 eeprom_clk pin 2 /reset_in pin 3 /vcc_gone pin 4 /led3 pin 10 gnd pin 11 /oe pin 12 /reset_to_chip pin 13 /first_time pin 15 led3_out pin 19 /sleep pin 20 vcc ;-------- boolean equation segment ----- - equations led3_out = led3 * vcc_gone * first_time + led3_out * vcc_gone first_time := vcc reset_to_chip = /first_time * reset_in + first_time * led3_out * vcc_gone sleep = vcc_gone ;--------- simulation segment ---------- -
ma gic p ac ket t ec hnology application in har d ware and software 13 appendix c ;---------------------------------------------------------------------- ; this program is used with the pcnet family of parts to hook into the power interrupt ;so magic packet can be utilized. for now we can use pcntnw or the pcntnd (ndis 2.0) ;drivers to initialize and run the pcnet_isa ii or the pcnet_pci ii controllers. this ;tsr could be made to initialize the controller and deal with the receive interrupt ;but that would require a foot print in memory that would contain at least a 2k buffer ;hence making the tsr 2k larger than needed to demonstrate the magic packet capability. ;this tsr works only if power.exe is activated. ;----------------------------------------------------------------------- .286 .model tiny .stack 256 ;--------------- rev history --------------- ;3.0 reworked adding pci scan support ;2.0 reworked the 2f interrupt section by moving some of the initialization code from ;the original startup to the 2f interrupt itself. this was for the setting of csr4 ;for the polling disabled and the setting of led3 for the magic packet interrupt. ;this now made the driver work with both novell odi and windows for workgroups ndis ;2.0 drivers both in dos and windows environment. i removed the requirement to have ;the mac running before loading the 2f interrupt vector so, therefore, made the loading ;of this tsr independent of load order. ; ;1.0 initial working model for pcnet_isa ii only. ; ;--------- end of rev history ----------- ; ; pci bios equates ; pci_function_id_1 equ 0b0h ;pci bios spec version 1 pci_function_id_2 equ 0b1h ;pci bios spec version 2 pci_bios_present equ 01h ;pci bios present find_pci_device equ 02h ;pci device search
14 ma gic p ac ket t ec hnology application in har d ware and software read_config_byte equ 08h ;pci configuration space byte read read_config_word equ 09h ;pci configuration space word read read_config_dword equ 0ah ;pci configuration space dword read ;-------------------------------------------------------------------- ; ; amd pci devices equates ; amd_id equ 1022h ;vendor id pci_pcnet equ 2000h ;golden gate pcnet max_pci_dev_num equ 0ffh ;maximum pci device number ;------------------------------------------------------------------------- ; this data segment will be appended by the loader after the .code section. ; however we will need some storage for the stacks and variables we need to retain ;after we have returned to dos. therefore, we will put some data storage in the code ;section. the following will be a list of the variables. since we need some stack for ;operations we will set the ss=cs=ds and use a sp=00ffh ; ; old_2f_vector dd ; ; found_address dw ; ; our_code_segment dw ; ; incomming_stack_segment dw ; ; incomming_stack_pointer dw ; ; .data message1 db "pcnet_isa ii controller was not found.",0dh,0ah l_message1 equ $ - message1 message2 db "pcnet controller was not found and tsr was not installed.",0dh,0ah, "please check setup.",0dh,0ah l_message2 equ $ - message2 message3 db "pcnet controller that was found is not capable of magic packet.",
ma gic p ac ket t ec hnology application in har d ware and software 15 0dh,0ah l_message3 equ $ - message3 message4 db "pcnet controller is now ready for magic packet.",0dh,0ah l_message4 equ $ - message4 message5 db "this machine does not have a pci bios.",0dh,0ah l_message5 equ $ - message5 message6 db "this machine has a pci bios type 1.",0dh,0ah l_message6 equ $ - message6 message7 db "this machine has a pci bios type 2.",0dh,0ah l_message7 equ $ - message7 message8 db "pcnet_isa ii controller was found.",0dh,0ah l_message8 equ $ - message8 message9 db "pcnet_pci ii controller was found.",0dh,0ah l_message9 equ $ - message9 message10 db "pcnet_pci ii controller was not found.",0dh,0ah l_message10 equ $ - message10 message11 db "pci bios read failure.",0dh,0ah l_message11 equ $ - message11 pci_bios db 0 ; pci bios version number pci_device_num db max_pci_dev_num ; maximum number of pci devices pci_device_fnd db 0 ; used to decide whether isa or pci ;--------------------------------------------------------------------------- .code main proc far .startup
16 ma gic p ac ket t ec hnology application in har d ware and software ;we jump over the code we want and only install the encloser code and leave jmp install ; the data section needed in the code space goes in here. old_2f_vector dd 0h found_address dw 0h our_code_segment dw 0h incoming_dx dw 0h incoming_ds dw 0h incomming_stack_segment dw 0h incomming_stack_pointer dw 0h main endp ;----------------------------------------------------------------------- ; here is the main power interrupt routine ;----------------------------------------------------------------------- power proc pushf cmp ax, 0530bh jne not_mine cmp bl, 2 je suspend_req cmp bl, 3 je normal_resume ; we get here because we got a 2f vector but not a shut down or power up so we ; will pass it on to the other linked routines of 2f.
ma gic p ac ket t ec hnology application in har d ware and software 17 not_mine: popf jmp dword ptr cs:old_2f_vector ; we got here because the computer is going to go to sleep. we need to set ; the pcnet controller into sleep mode. this is done by putting a 6 in the ; csr5 register. suspend_req: mov incoming_dx,dx ; save off ds, dx and ds mov ax,ds mov incoming_ds,ax mov ax, cs ; fix up the data segment pointer mov ds, ax ; first we will program the led3 register for magic packet indication and ; then we will set the part for magic packet detection mode. mov dx, found_address ; point the rap to the register wanted add dx, 012h mov ax, 0007h out dx, ax ; db9 of iscar7 controls the use of magic packet detection for led3 add dx, 04h mov ax, 0200h out dx, ax sub dx, 04h ; realign dx to the rap mov ax, 5 out dx, ax sub dx, 2 ; point the dx to rdp mov ax, 026h ; put into magic packet suspend mode and
18 ma gic p ac ket t ec hnology application in har d ware and software ; broadcast accept out dx, ax mov ax,incoming_ds ; restore ds, ax and dx mov ds,ax mov dx,incoming_dx mov ax,0530bh ; repair the ax register popf jmp dword ptr cs: old_2f_vector ; we got here because the computer is going to wake up. we need to clear the ; magic packet look for bit. we will set csr5 back to 2 normal_resume: mov incoming_dx,dx ; save off ds, dx and ds mov ax,ds mov incoming_ds,ax mov ax, cs ; fix up the data segment pointer mov ds, ax mov dx, found_address ; point the rap to the register wanted add dx, 012h mov ax, 5 out dx, ax sub dx, 2 ; point the dx to rdp mov ax, 02h ; take out of magic packet mode out dx, ax mov ax,incoming_ds ; restore ds, ax and dx mov ds,ax mov dx,incoming_dx mov ax, 0530bh ; repair the ax register
ma gic p ac ket t ec hnology application in har d ware and software 19 popf jmp dword ptr cs: old_2f_vector power endp end_of_program: install: push cs ; just in case pop ds ; ds is now set to the cs for com file ; we will now save the current cs for later use mov ax,cs mov our_code_segment, ax ; now we will look for a pcnet isa. the first location can be 0x200 base mov dx, 020fh look_again: in al, dx cmp al, 057h jz isa_found add dx, 020h cmp dx, 040fh jz check_for_pci jmp look_again ; we did not find an isa device so now we will look for a pci device. this ; will involve first seeing if we have a pci machine. then if a pci bios is ; present we will then scan the pci backplane for an amd device and save the ; address at configuration space + 10h as the card address.
20 ma gic p ac ket t ec hnology application in har d ware and software ; ; now we will put out a message about finding no isa adapter. check_for_pci: mov bx, 0001h ; output message no isa ii card lea dx, message1 mov cx, l_message1 mov ah, 40h int 21h ;-------------------------------- ; test pci bios spec version 2 interface ;-------------------------------- xor bx,bx ;clear bx xor cx,cx ;clear cx xor dx,dx ;clear dx mov ah,pci_function_id_2 ;assume pci bios spec version 2 mov al,pci_bios_present ;request for pci bios support int 1ah ;pci bios interface ;-------------------------------- ; check return value from pci bios spec version 2 ;-------------------------------- jc check_pci_bios_ver1 ;jump, if carry set ; cmp dx,"cp" ;check for pci signature jne check_pci_bios_ver1 ;jump, if pci bios version is not 2 ; or ah,ah ;check present status jnz no_pci_bios ;jump, if no pci bios present ; mov pci_bios,2 ;set pci bios version = 2 mov pci_device_num,cl ;save cl = # of last pci bus in system mov bx, 0001h ; output message about bios type lea dx, message7 mov cx, l_message7 mov ah, 40h int 21h
ma gic p ac ket t ec hnology application in har d ware and software 21 jmp scan_for_card ;jump, get hardware mechanism ;-------------------------------- ; if not version 2 then test pci bios spec version 1 interface ;-------------------------------- check_pci_bios_ver1: xor cx,cx ;clear cx xor dx,dx ;clear dx mov ah,pci_function_id_1 ;assume pci bios spec version 2 mov al,pci_bios_present ;request for pci bios support int 1ah ;pci bios interface ;-------------------------------- ; check return value from pci bios spec version 1 ;-------------------------------- jc no_pci_bios ;jump, if carry set ; cmp dx,"cp" ;check for pci signature jne no_pci_bios ;jump, if no pci bios present cmp cx," i" ;check for pci signature jne no_pci_bios ;jump, if no pci bios present ; mov pci_bios,1 ;set pci bios version = 1 mov pci_device_num,max_pci_dev_num;maximun pci device number ;assume mechanism 2 for pci bios ver1 mov bx, 0001h ; output message about bios type lea dx, message6 mov cx, l_message6 mov ah, 40h int 21h jmp scan_for_card ;jump, get hardware mechanism
22 ma gic p ac ket t ec hnology application in har d ware and software ;-------------------------------- ; no pci bios exists ;-------------------------------- no_pci_bios: mov bx, 0001h ; output message no pci bios lea dx, message5 mov cx, l_message5 mov ah, 40h int 21h jmp not_here ;exit ;-------------------------------- ; search amd pci pcnet devices ;-------------------------------- scan_for_card: xor si,si ;si = 0 (index initialize) ; mov dx,amd_id ;dx = amd vender id ; mov cx,pci_pcnet ;assume cx = pci pcnet device id mov ah,pci_function_id_1 ;assume bh = pci bios spec version 1 cmp pci_bios,1 ;check pci bios version = 1 je pci_bios_version_set ;jump, if pci bios version determined mov ah,pci_function_id_2 ;bh = pci bios spec version 2 pci_bios_version_set: ;-------------------------------- ; find amd pci device through bios api ;-------------------------------- mov al,find_pci_device ;request for amd pci device int 1ah ; pci bios interface
ma gic p ac ket t ec hnology application in har d ware and software 23 ; this function will return in the bx register the bus number in bh and the ; device number in bl. ; test for error carry = 1 jnc find_pci_device_success ;find pci device success search_fail: mov bx, 0001h ;output message no pci ii card lea dx, message10 mov cx, l_message10 mov ah, 40h int 21h jmp not_here ; find_pci_device_success: or ah,ah check search successful jnz search_fail jump, if search failed ; we have now found a pcnet_pci device. now we will get its address at ; configuration space + 10h. bx is being maintained here from the previous ; call with the bus number and the device number mov ah,pci_function_id_1; assume ah = pci bios spec version 1 cmp pci_bios,1 ;check pci bios version = 1 je pci_bios_ver_set ;jump, if pci bios version determined mov ah,pci_function_id_2 ;ah = pci bios spec version 2 pci_bios_ver_set: ; mov di,010h ;di = pci config space data bytes ;-------------------------------- ; read pci configuration space ;--------------------------------
24 ma gic p ac ket t ec hnology application in har d ware and software mov al,read_config_dword ; request for amd pci device int 1ah ; pci bios interface ; jc read_fail ; exit, if error ; or ah,ah ; check return code jnz read_fail ; jump, if error happened ; cx now contains the address of the card but the address has its lower bit ; set in pci config register to indicate it is i/o not memory. therefore we ; will have to mask off that bit. ; mov ax,cx ; save config byte and ax,0fffeh ; mask off the lower bit to 0 mov found_address, ax ; save off the found_address mov ax,1 ; 1 = pci device found mov pci_device_fnd, al mov bx, 0001h ; output message pci card found lea dx, message9 mov cx, l_message9 mov ah, 40h int 21h jmp found read_fail: mov bx, 0001h ; output message read address fail lea dx, message11 mov cx, l_message11 mov ah, 40h int 21h jmp not_here
ma gic p ac ket t ec hnology application in har d ware and software 25 isa_found: sub dx, 0fh mov ax, dx mov found_address, ax ; save off the found_address mov ax,0 ; 0 = isa device found mov pci_device_fnd, al mov bx, 0001h ; output message isa card found lea dx, message8 mov cx, l_message8 mov ah, 40h int 21h ; we get here if we found the card at an address. now dx contains the address ; of the found card but with an offset of 0xf so we need to adjust. found: ; now that we have found the controller we must check to see if the pcnet ; controller can handle the magic packet. only pcnet isa ii and pcnet_pci ii ; can handle a magic packet. pcnet isa ii can be identified with a 01h ; in the address space + 9h register. while a pcnet_pci ii controller can ; be found by a 1x in the rev register of the pci configuration register. mov ah, 0 mov al,pci_device_fnd jnz use_pci_check ; this is the isa check mov dx, found_address ; point the rap to the register wanted add dx, 09h in al, dx cmp al, 01h jz interrupt_link
26 ma gic p ac ket t ec hnology application in har d ware and software ; this is the pci check use_pci_check: mov dx, found_address ; point the rap to the register wanted add dx, 09h in al, dx cmp al, 11h jz interrupt_link mov bx, 0001h lea dx, message3 mov cx, l_message3 mov ah, 40h int 21h jmp return_to_dos interrupt_link: mov dx, found_address add dx, 012h ; now we will program the csr5 register turn on magic packet mode. mov ax, 05h ; point the rdp to csr 5 out dx, ax sub dx, 02h mov ax, 02h out dx, ax ; now we will program the csr4 register to disable polling just in case a ; motherboard has a timer on the breq/dreq activity of the controller. add dx,02h ; realign dx to the rap mov ax, 04h ; point the rdp to csr 4
ma gic p ac ket t ec hnology application in har d ware and software 27 out dx, ax sub dx, 02h in ax, dx or ax, 01000h ; set the disable polling bit out dx, ax add dx, 02h ; now reset the address pointer back to 0 mov ax, 00h out dx, ax ; we now need to hook the 2f interrupt (power management). since this ; interrupt is cascaded with other programs we need to get the old 2f ; interrupt vector and save it in old_2f_vector and then put our pointer ; in 2f. xor ax, ax mov es, ax pushf cli mov ax, es:[2fh * 4 ] ; get the old vector mov word ptr old_2f_vector, ax mov ax, es:[2fh * 4 + 2] mov word ptr old_2f_vector + 2 , ax lea ax, power mov es:[02fh * 4], ax mov ax, cs mov es:[02fh * 4 + 2], ax popf ; this re-enables the interrupts ; now we display the message that we are magic packet ready mov bx, 0001h lea dx, message4
28 ma gic p ac ket t ec hnology application in har d ware and software mov cx, l_message4 mov ah, 40h int 21h ; now we return to dos but we leave the tsr for power mov al, 0 lea dx, end_of_program mov ah, 31h int 27h not_here: ; now we display the message that the pcnet was not found and tsr was not ; installed. mov bx, 0001h lea dx, message2 mov cx, l_message2 mov ah, 40h int 21h return_to_dos: mov ah,4ch int 21h end .
trademarks copyright ?1998 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are trademarks of advanced micro devices, inc. am186, am386, am486, am29000, b imr, eimr, eimr+, gigaphy, himib, ilacc, imr, imr+, imr2, isa-hub, mace, magic packet, pcnet, pcnet- fast , pcnet- fast +, pcnet-mobile, qfex, qfexr, quasi , quest, quiet, taxichip, tpex, and tpex plus are trademarks of advanced micro devices, inc. microsoft is a registered trademark of microsoft corporation. product names used in this publication are for identi?ation purposes only and may be trademarks of their respective companies.

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