15 semiconductor, inc. ei82c684 EI68C684 quad uart features ? full duplex, four channel asynchronous receiver and transmitter ? quadruple-buffered receiver and transmitter ? internal bit rate generator with 23 industry standard bit rates operating from either of two standard crystal clocks ? independent bit rate selection for each receiver and transmitter ? maximum bit rate: 1 x clock - 2 mb/sec., 16 x clock- 250 kb/sec. ? normal, auto-echo, local loop-back and remote loop-back modes ? multi-function 16-bit counter/timer ? programmable interrupt daisy chain ? up to 32 i/o pins (depending on package and version) ? change of state detectors on inputs ? multidrop mode compatible with 8051 nine- bit mode ? stop bits programmable in 1/16-bit increments ? pin selectable 88xxx/68xxx interface ? debounced reset pin (20 nsec. min) ? on-chip oscillator for crystal ? programmable internal clock:x1/clk or x1/clk divided by 2 ? buffered system clock output pin ? stand-by mode to reduce operating power ? advanced cmos low power technology description the epic EI68C684/ei88c684 quad universal asynchronous receiver and transmitter (quart) is a data communication device that provides four fully independent full duplex asynchronous communication channels in a single package. the quart is designed for use in microprocessor based systems and may be used in a polled or interrupt driven environment. two basic versions of the quart are pin selectable with sel pin and each is optimized for use with various microprocessor families: the ei88c684 for 8080/5, 8086/88, z80, z8000, 68xx and 65xx family based systems., and the 68c681 for 68000 family based sys- tems.and the EI68C684 for 68000family based systems a programmable mode of the ei88c684 versions pro- vides an interrupt daisy chain for use in z80 and z8000 based systems. the bus interfaces are however gener- al enough to allow interfacing with other microprocessors and microcontrollers. the ei88c684 and EI68C684 are high integrated versions of epic semiconductors ei88c681 and ei66c681 duarts respectively, and are function compatible with those devices. 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 op5 op6 op7 d0 d1 d2 d3 d4 d5 d6 d7 wr? ce? op15 op14 op13 op12 ip5 ip4? rd? ip3 ip2 ip1(ctsb?) ip0(ctsa?) a1 a2 a3 a4 a5 ip8(ctsc?) ip9(ctsd?) ip10 ip11 iei rxdd txdd (ieo) iack? intr? clkbuf+op11 gnd gnd op10 op9(rtsd?) op8(rtsc?) txdc rxdc ip15 ip14 ip13 ip12 op4 x2 x1/clk rxdb txdb op3 op2 sel vcc0 vcc1 reset op1(rtsb?) op0(rtsa?) txda rxda ip7 ip6 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 ei82c684 x2 x1/clk rxdb txdb op3 sel vcc reset op1(rtsb) op0(rtsa) txda rxda rdn ip1(ctsb) ip0(ctsa) a1 a2 a3 a4 a5 ip8(ctsc) ip9(ctsd) d0 d1 d2 d3 d4 d5 d6 d7 r/wn cen rxdd txdd (ieo) iackn intrn op11 gnd op9(rtsd) op8(rtsb) txdc rxdc iei 1 ei82c684 68-pin plcc 44-pin plcc
16 semiconductor, inc. EI68C684 ei88c684 quad uart block diagram channel x transmit and receive shift register transmit holding register receive fifo (3) mr1x mr2x srx input port a change of state detectors (4) acra ipcra input port b change of state detectors (4) acrb ipcrb output port a function select logic opra opcra output port b oprb opcrb function select logic internal data bus txdx( ? ) rxdx bus buffer operation control address decode command decode cra cra cra cra interrupt control ivra ivrb imra imrb isra ivrb timing clock selectors counter timer a counter timer b bit rate generator crystal oscillator csra csrc acra ctura ctlra csrb acrb cturb ctlrb csrd ? ? ? ? ? ? ? ? ? ? ? reset/reset? intr? ce? rd? wr?/r/w? iack? d0-d7 iei ieo/dtack? x1/clk x2 a0-a4/a1/a5
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