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12/19/2002 - 1 - 9656 - sil - dc1 - p0 - . 96 pci 9656 blue book revision 0.90b corrections this document details several corrections to the pci 9656 blue book, revision 0.90b. please review these corrections before proceeding with your design. 1. toggling iddqen# at power on time when using the pci 9656 ad, external logic is required on the iddqen# pin to configure the pci buffers for proper operation. this external logic is not required when using the pci 9656ba. the requirement for this logic is not included in the blue book. pci 9656ad iddqen# to put t he pci 9656ad into its iddq state, hold the iddqen# input signal (ball a10) in its asserted state. to configure the pci 9656ad for normal operation, during initialization the iddqen# input signal must transition from its asserted state to its de - asserted s tate prior to pci rst# de - assertion. this causes the silicon to configure its pci i/o buffers for proper bus operation. after this transition completes, hold iddqen# in its de - asserted state. note. for compactpci hot swap applications, iddqen# must be held in its de - asserted state during pre - charge. as a result, compactpci hot swap applications require that iddqen# transition from its de - asserted state to its asserted state after pre - charge completes, and then transition back to its de - asserted state prior to local pci rst# de - assertion. pci 9656ba iddqen# to put the pci 9656ba into its iddq state, hold the iddqen# input signal (ball a10) in its asserted state. to configure the pci 9656ba for normal operation, hold iddqen# in its de - asserted state. note. for applications that use the pci 9656ba?s pci power management d3cold pme generation feature, de - assert iddqen# by tying it directly to the 2.5v power source for vcore. the pci 9656ba uses iddqen# to sense both when vcore is going away to prepare to enter th e d3cold state and when vcore is coming back to prepare to leave the d3cold state. do not tie iddqen# to the 2.5v power source for 2.5vaux, and do not tie it to the 3.3v power source for either vring or card_vaux. even though the pci 9656ba does not requir e any transitioning of its iddqen# input signal for proper pci bus operation, transitioning the pci 9656ba?s iddqen# in accordance with the pci 9656ad iddqen# requirements, above, will have no effect on pci 9656ba operation. as a result, the pci 9656ba can be substituted for the pci 9656ad in existing designs without needing to remove the external iddqen# transitioning logic. sample circuit designs supporting all silicon versions the following circuit diagrams come directly from the schematics of two plx ha rdware reference design boards that have been validated empirically. the first is an example circuit for designs that
12/19/2002 - 2 - 9656 - sil - dc1 - p0 - . 96 do not need to support compactpci hot swap. the second is an example for designs that do need to support compactpci hot swap. note. these circuit diagrams are provided as examples only. it is the designer?s responsibility to create circuitry that meets the above stated iddqen# toggling requirements for their particular design. figure 1 . iddqen# toggling circuitry e xample for non - compactpci hot swap designs figure 2 . iddqen# toggling circuitry example for compactpci hot swap designs 2. useri pull - up/pull - down at power up time when using the pci 9656, an external pull - up or pull - down resistor is required on the useri pin to configure the chip for the desired pci bus behavior during chip initialization. a pull - up resistor configures the chip to issue pci retries during initialization [high = retry], and a pull - down resistor configures the chip to do nothing on the pci bus during initialization. this is true for both the pci 9656ad and the pci 9656ba. the description in the blue book regarding this is incorrect for these chip revisions.
12/19/2002 - 3 - 9656 - sil - dc1 - p0 - . 96 the following text replaces sections 2.4.1.2 and 4.4.1.2 of the blue book. note that these sections of the blue book look very similar to what is below. the key difference is that the polarity of useri is incorrectly reversed in the blue book descriptions. follow the polarity in the description below. changes from the blue book are underlined. 2.4.1.2/4.4.1.2 local initialization as stated in pci r2. 2, section 3.5.1.1: ?if the target is accessed during initialization - time, it is allowed to do any of the following: 1. ignore the request (except if it is a boot device ). this results in a master abort. 2. claim the access and hold in wait sates until it can complete the request, not to exceed the end of initialization - time. 3. claim the access and terminate with [pci] retry.? the pci 9656 supports option 1 ( initially no t respond ), and option 3 ( initially retry ), above. for compactpci hot swap live insertion systems, the preferred method for the silicon is usually not to respond to pci configuration accesses during initialization. for legacy systems, retries are usually p referred for compatibility reasons. however, it is ultimately the designer?s choice of which option to use. the pci 9656 determines the option to use as follows: the useri pin is sampled at the rising edge rst# to determine the selected pci bus response mo de during local initialization. if useri is low (through an external 1k ohm pull - down resistor), the pci 9656 does not respond to pci activity until the device?s local bus initialization is complete. this results in a master abort (the preferred method for compactpci hot swap systems). if useri is high (through an external 1k ? 4.7k ohm pull - up resistor), the pci 9656 responds to pci accesses with pci retry cycles until the device?s local bus initialization is complete. local bus initialization is complete wh en the local init status bit is set (lmisc1[2]=1). the lmisc1[2] bit can be programmed in one of three ways: 1. by a local bus master writing a 1 directly to lmisc1[2]. 2. by the serial eeprom specifying a value of 1 for lmisc1[2] during a serial eeprom lo ad. 3. if a local bus master is not present and either a serial eeprom is not present or a blank serial eeprom is present, the pci 9656 reverts to its power on/reset default register values and sets this bit. (refer to table 2 - 18 on page 2 - 9.) during run t ime, useri can be used as a general purpose input as described in the tables 12 - 10, 12 - 11, and 12 - 12, for the m, c, and j mode local bus pins. refer to section 9, ?compactpci hot swap? for specifics on using this feature in picmg 2.1, r2.0 systems.
12/19/2002 - 4 - 9656 - sil - dc1 - p0 - . 96 3. eedi/ee do pull - up when local processor present but eeprom not present when using the pci 9656, if initialization is to be performed by a local bus master and no serial eeprom is present, the eedi/eedo pin must not be pulled down. this is true for both the pci 965 6ad and the pci 9656ba. the description in the blue book regarding this is vague. tables 2 - 18 and 4 - 18 of the blue book make no mention of a pull - up or pull - down resistor on the eedi/eedo pin when a local processor is present but an eeprom is not present. the correct requirement is that the eedi/eedo pin must be either be left floating or pulled up with a 1k - ohm or greater value resistor when an eeprom is not present. in any case, the pin must not be pulled down. the following shows the corrected entry of t ables 2 - 18 and 4 - 18: table 1 . serial eeprom guidelines local processor serial eeprom system boot condition ? present none the local processor programs the pci 9656 registers, then sets the local init status bit (lmisc1[2] = 1). a 1k ohm or greater pull - up resistor on eedi/eedo is recommended, but not required. the eedi/eedo pin already has an internal pull - up (ref. table 12 - 1). note: some systems may avoid configuring devices that do not complete configuration accesses within 2 25 pci clocks after rst# has been de - asserted. in addition, some systems may hang if direct slave reads and writes are immediately retried. the value of the direct slave retry delay clocks (lbrd0[31:28]) may resolve the hang by delaying assertion of the st op# signal by the pci 9656. ? 4. updated electrical specifications the following table updates blue book table 13 - 5 for both the pci 9656ad and the pci 9656ba. changes from the blue book are underlined.
12/19/2002 - 5 - 9656 - sil - dc1 - p0 - . 96 table 2 . electrical characte ristics over operating range parameter description test conditions min max units v oh 1 output high voltage i oh = - 12.0 ma 2.4 - v v ol 1 output low voltage v dd = min v in = v ih or v il i ol = 12.0 ma - 0.4 v v oh 2 output high voltage i oh = - 24.0 ma 2.4 - v v ol 2 output low voltage v dd = min v in = v ih or v il i ol = 24.0 ma - 0.4 v v ih input high level - - 2.0 5.5 v v il input low level - - - 0.5 0.8 v v oh3 pci 3.3v output high voltage i oh = - 500 a 0.9 v dd - v v ol3 pci 3.3v output low voltage v dd = min v in = v ih or v il i ol = 1500 a - 0.1 v dd v v ih3 pci 3.3v input high level - - 0.5 v dd v dd +0.5 v v il3 pci 3.3v input low level - - - 0.5 0.3 v dd v i il input leakage current v ss = v in = v dd , v dd = max - 10 +10 a i lpc 3 dc c urrent per pin during pre - charge v p = 0.8 to 1.2v - 1.0 ma i oz three - state output leakage current v dd = max - 10 +10 a i dd 4 (i/o ring) power supply current for i/o ring i/o ring v dd = 3.6v pclk = 66mhz, lclk = 66mhz - 95 ma i dd (core) power supply curre nt for core core v dd = 2.63v pclk = 66mhz, lclk = 66mhz - 185 ma i ccl i cch i ccz quiescent power supply current v cc = max v in = gnd or v cc - 50 a notes: 1. for 12 ma i/o or output cells (local bus side). 2. for 24 ma i/o or output cells (local bus side). 3. i lpc is the dc current flowing from vdd to ground during pre - charge, as both pmos and nmos devices remain on during pre - charge. it is not the leakage current flowing into or out of the pin under pre - charge. 4. 40 local bus side i/os switching simultaneously and 76 pci side i/os switching simultaneously.
12/19/2002 - 6 - 9656 - sil - dc1 - p0 - . 96 5. pci arbiter enable/disable when using the pci 9656, the configuration register bit that is used to enable or disable the pci 9656?s pci arbiter can only be written by the eeprom or a local bus master. a pci master c annot be write this bit. this is true for both the pci 9656ad and the pci 9656ba. the description in the blue book regarding this is incorrect. register 11 - 57 of the blue book incorrectly states that the pci arbiter enable bit (pciarb[0]) can be written by a pci master. in fact, a pci master cannot write the pci arbiter enable bit. the following shows the corrected entry of register 11 - 57: table 3 . (pciarb; pci:100h, loc:1a0h) pci arbiter control bit description read write value aft er reset 0 pci arbiter enable. value of 0 indicates the pci arbiter is disabled and req0# and gnt0# are used by the pci 9656 to acquire pci bus use. value of 1 indicates the pci arbiter is enabled. yes local/ serial eeprom 0 ? 6. pci bar?s 4 & 5 unused for direct slave data transfers, the pci 9656 supports mapping two pci address spaces to the local bus using pci base address registers (bar?s) 2 and 3. this is true for both the pci 9656ad and the pci 9656ba. the blue book pci configuration register table re garding this is potentially confusing. table 11 - 2 of the blue book could be interpreted to indicate that the pci 9656 supports mapping four pci address spaces to the local bus for direct slave data transfers. the pci 9656 in fact only supports mapping two pci address spaces. the following shows the corrected entries of table 11 - 2. table 4 . pci configuration registers pci configuration register address local access (offset from chip select address) to ensure software compatibility w ith other versions of the pci 9656 family and to ensure compatibility with future enhancements, write 0 to all unused bits. 31 0 pci/ local writeable serial eeprom writeable ? 20h 20h pci base address 4; unused y n 24h 24h pci base address 5; unused y n ? 7. big endian/little endian/byte lane mode the blue book descriptions of big endian and little endian conversion are potentially confusing. pci 9656 big endian and little endian conversion are detailed in blue book sections 2.3 and 4.3. the following ta bles provide further clarification by detailing precisely pci 9656 signal mappings between the pci bus and the local bus during big endian and little endian conversion.
12/19/2002 - 7 - 9656 - sil - dc1 - p0 - . 96 table 5 . c mode endian mapping for byte lane mode 0 c mode local bus pin byte lane mode = 0 (bigend[4] = 0) little endian big endian pci pins mapped 2 nd (64 - bit transfers only) pci pins mapped 1 st 32 - bit 16 - bit 8 - bit 32 - bit 16 - bit 8 - bit ad32 ad0 1 - ld0 1 - ld0 1 - ld0 1 - ld24 1 - ld8 1 - ld0 ad33 ad1 1 - ld1 1 - ld1 1 - l d1 1 - ld25 1 - ld9 1 - ld1 ad34 ad2 1 - ld2 1 - ld2 1 - ld2 1 - ld26 1 - ld10 1 - ld2 ad35 ad3 1 - ld3 1 - ld3 1 - ld3 1 - ld27 1 - ld11 1 - ld3 ad36 ad4 1 - ld4 1 - ld4 1 - ld4 1 - ld28 1 - ld12 1 - ld4 ad37 ad5 1 - ld5 1 - ld5 1 - ld5 1 - ld29 1 - ld13 1 - ld5 ad38 ad6 1 - ld6 1 - ld6 1 - ld6 1 - ld30 1 - ld14 1 - ld6 ad39 ad7 1 - ld7 1 - ld7 1 - ld7 1 - ld31 1 - ld15 1 - ld7 ad40 ad8 1 - ld8 1 - ld8 2 - ld0 1 - ld16 1 - ld0 2 - ld0 ad41 ad9 1 - ld9 1 - ld9 2 - ld1 1 - ld17 1 - ld1 2 - ld1 ad42 ad10 1 - ld10 1 - ld10 2 - ld2 1 - ld18 1 - ld2 2 - ld2 ad43 ad11 1 - ld11 1 - ld11 2 - ld3 1 - ld19 1 - ld3 2 - ld3 ad44 ad 12 1 - ld12 1 - ld12 2 - ld4 1 - ld20 1 - ld4 2 - ld4 ad45 ad13 1 - ld13 1 - ld13 2 - ld5 1 - ld21 1 - ld5 2 - ld5 ad46 ad14 1 - ld14 1 - ld14 2 - ld6 1 - ld22 1 - ld6 2 - ld6 ad47 ad15 1 - ld15 1 - ld15 2 - ld7 1 - ld23 1 - ld7 2 - ld7 ad48 ad16 1 - ld16 2 - ld0 3 - ld0 1 - ld8 2 - ld8 3 - ld0 ad48 ad17 1 - ld1 7 2 - ld1 3 - ld1 1 - ld9 2 - ld9 3 - ld1 ad50 ad18 1 - ld18 2 - ld2 3 - ld2 1 - ld10 2 - ld10 3 - ld2 ad51 ad19 1 - ld19 2 - ld3 3 - ld3 1 - ld11 2 - ld11 3 - ld3 ad52 ad20 1 - ld20 2 - ld4 3 - ld4 1 - ld12 2 - ld12 3 - ld4 ad53 ad21 1 - ld21 2 - ld5 3 - ld5 1 - ld13 2 - ld13 3 - ld5 ad54 ad22 1 - ld22 2 - ld6 3 - ld6 1 - ld14 2 - ld14 3 - ld6 ad55 ad23 1 - ld23 2 - ld7 3 - ld7 1 - ld15 2 - ld15 3 - ld7 ad56 ad24 1 - ld24 2 - ld8 4 - ld0 1 - ld0 2 - ld0 4 - ld0 ad57 ad25 1 - ld25 2 - ld9 4 - ld1 1 - ld1 2 - ld1 4 - ld1 ad58 ad26 1 - ld26 2 - ld10 4 - ld2 1 - ld2 2 - ld2 4 - ld2 ad59 ad27 1 - ld27 2 - ld11 4 - ld3 1 - ld 3 2 - ld3 4 - ld3 ad60 ad28 1 - ld28 2 - ld12 4 - ld4 1 - ld4 2 - ld4 4 - ld4 ad61 ad29 1 - ld29 2 - ld13 4 - ld5 1 - ld5 2 - ld5 4 - ld5 ad62 ad30 1 - ld30 2 - ld14 4 - ld6 1 - ld6 2 - ld6 4 - ld6 ad63 ad31 1 - ld31 2 - ld15 4 - ld7 1 - ld7 2 - ld7 4 - ld7 notes 1. during 64 - bit pci transfers, the lower 32 bits of the pci bus (ad[31:0]) are always mapped first. 2. for each local bus pin table entry, n - m means that row?s pci pin maps to local bus pin m during local bus cycle n that either results from the pci cycle (pci - to - local bus transfers) or results in the pci cycle (local bus - to - pci transfers). for example, a local bus pin of ?2 - ld5? for pci pin ad21 during 16 ? bit little endian local bus transfers (ref. the darkest shaded entry) means that during a pci - to - local bus transfer, the value of pci pin ad21 du ring each 32 - bit pci transfer will occur on local bus pin ld5 of the second resulting 16 - bit local bus transfer. during a local bus - to - pci transfer, this means that the value of pci pin ad21 will result from the value of local bus pin ld5 during the second 16 - bit local bus transfer. 3. the mappings in the table only occur during data phases. addresses always map to/from pci ad[31:0] as indicated in the 32 - bit little endian column after the address translation specified in the configuration registers is perform ed. 4. little and big endian modes are selected by both register bits and pin signals, depending on the data phase type: direct master read/write, direct slave read/write, dma pci - to - local bus / local bus - to - pci, and configuration register read/write. see the bigend register description in table 11 - 41 and the bigend# pin description in table 12 - 11 for details.
12/19/2002 - 8 - 9656 - sil - dc1 - p0 - . 96 table 6 . c mode endian mapping for byte lane mode 1 c mode local bus pin byte lane mode = 1 (bigend[4] = 1) little endian big endian pci pins mapped 2 nd (64 - bit transfers only) pci pins mapped 1 st 32 - bit 16 - bit 8 - bit 32 - bit 16 - bit 8 - bit ad32 ad0 1 - ld0 1 - ld16 1 - ld24 1 - ld24 1 - ld24 1 - ld24 ad33 ad1 1 - ld1 1 - ld17 1 - ld25 1 - ld25 1 - ld25 1 - ld25 ad34 ad2 1 - ld2 1 - ld18 1 - ld26 1 - ld 26 1 - ld26 1 - ld26 ad35 ad3 1 - ld3 1 - ld19 1 - ld27 1 - ld27 1 - ld27 1 - ld27 ad36 ad4 1 - ld4 1 - ld20 1 - ld28 1 - ld28 1 - ld28 1 - ld28 ad37 ad5 1 - ld5 1 - ld21 1 - ld29 1 - ld29 1 - ld29 1 - ld29 ad38 ad6 1 - ld6 1 - ld22 1 - ld30 1 - ld30 1 - ld30 1 - ld30 ad39 ad7 1 - ld7 1 - ld23 1 - ld31 1 - ld3 1 1 - ld31 1 - ld31 ad40 ad8 1 - ld8 1 - ld24 2 - ld24 1 - ld16 1 - ld16 2 - ld24 ad41 ad9 1 - ld9 1 - ld25 2 - ld25 1 - ld17 1 - ld17 2 - ld25 ad42 ad10 1 - ld10 1 - ld26 2 - ld26 1 - ld18 1 - ld18 2 - ld26 ad43 ad11 1 - ld11 1 - ld27 2 - ld27 1 - ld19 1 - ld19 2 - ld27 ad44 ad12 1 - ld12 1 - ld28 2 - ld28 1 - ld20 1 - ld20 2 - ld28 ad45 ad13 1 - ld13 1 - ld29 2 - ld29 1 - ld21 1 - ld21 2 - ld29 ad46 ad14 1 - ld14 1 - ld30 2 - ld30 1 - ld22 1 - ld22 2 - ld30 ad47 ad15 1 - ld15 1 - ld31 2 - ld31 1 - ld23 1 - ld23 2 - ld31 ad48 ad16 1 - ld16 2 - ld16 3 - ld24 1 - ld8 2 - ld24 3 - ld24 ad48 ad17 1 - ld17 2 - ld17 3 - ld25 1 - ld9 2 - ld25 3 - ld25 ad50 ad18 1 - ld18 2 - ld18 3 - ld26 1 - ld10 2 - ld26 3 - ld26 ad51 ad19 1 - ld19 2 - ld19 3 - ld27 1 - ld11 2 - ld27 3 - ld27 ad52 ad20 1 - ld20 2 - ld20 3 - ld28 1 - ld12 2 - ld28 3 - ld28 ad53 ad21 1 - ld21 2 - ld21 3 - ld29 1 - ld13 2 - ld29 3 - ld29 ad54 ad22 1 - ld2 2 2 - ld22 3 - ld30 1 - ld14 2 - ld30 3 - ld30 ad55 ad23 1 - ld23 2 - ld23 3 - ld31 1 - ld15 2 - ld31 3 - ld31 ad56 ad24 1 - ld24 2 - ld24 4 - ld24 1 - ld0 2 - ld16 4 - ld24 ad57 ad25 1 - ld25 2 - ld25 4 - ld25 1 - ld1 2 - ld17 4 - ld25 ad58 ad26 1 - ld26 2 - ld26 4 - ld26 1 - ld2 2 - ld18 4 - ld26 ad59 ad27 1 - ld27 2 - ld27 4 - ld27 1 - ld3 2 - ld19 4 - ld27 ad60 ad28 1 - ld28 2 - ld28 4 - ld28 1 - ld4 2 - ld20 4 - ld28 ad61 ad29 1 - ld29 2 - ld29 4 - ld29 1 - ld5 2 - ld21 4 - ld29 ad62 ad30 1 - ld30 2 - ld30 4 - ld30 1 - ld6 2 - ld22 4 - ld30 ad63 ad31 1 - ld31 2 - ld31 4 - ld31 1 - ld7 2 - ld23 4 - ld31 note s 1. during 64 - bit pci transfers, the lower 32 bits of the pci bus (ad[31:0]) are always mapped first. 2. for each local bus pin table entry, n - m means that row?s pci pin maps to local bus pin m during local bus cycle n that either results from the pci cycle (pc i - to - local bus transfers) or results in the pci cycle (local bus - to - pci transfers). for example, a local bus pin of ?2 - ld21? for pci pin ad21 during 16 ? bit little endian local bus transfers (ref. the darkest shaded entry) means that during a pci - to - local b us transfer, the value of pci pin ad21 during each 32 - bit pci transfer will occur on local bus pin ld21 of the second resulting 16 - bit local bus transfer. during a local bus - to - pci transfer, this means that the value of pci pin ad21 will result from the va lue of local bus pin ld21 during the second 16 - bit local bus transfer. 3. the mappings in the table only occur during data phases. addresses always map to/from pci ad[31:0] as indicated in the 32 - bit little endian column after the address translation specifie d in the configuration registers is performed. 4. little and big endian modes are selected by both register bits and pin signals, depending on the data phase type: direct master read/write, direct slave read/write, dma pci - to - local bus / local bus - to - pci, and configuration register read/write. see the bigend register description in table 11 - 41 and the bigend# pin description in table 12 - 11 for details.
12/19/2002 - 9 - 9656 - sil - dc1 - p0 - . 96 table 7 . j mode endian mapping for byte lane mode 0 j mode local bus pin byte lane mode = 0 (bigend[4] = 0) little endian big endian pci pins mapped 2 nd (64 - bit tr ansfers only) pci pins mapped 1 st 32 - bit 16 - bit 8 - bit 32 - bit 16 - bit 8 - bit ad32 ad0 1 - lad0 1 - lad0 1 - lad0 1 - lad24 1 - lad8 1 - lad0 ad33 ad1 1 - lad1 1 - lad1 1 - lad1 1 - lad25 1 - l ad9 1 - lad1 ad34 ad2 1 - lad2 1 - lad2 1 - lad2 1 - lad26 1 - lad10 1 - lad2 ad35 ad3 1 - lad3 1 - lad3 1 - lad3 1 - lad27 1 - lad11 1 - lad3 ad36 ad4 1 - lad4 1 - lad4 1 - lad4 1 - lad28 1 - lad12 1 - lad4 ad37 ad5 1 - lad5 1 - lad5 1 - lad5 1 - lad29 1 - lad13 1 - lad5 ad38 ad6 1 - lad6 1 - lad6 1 - lad 6 1 - lad30 1 - lad14 1 - lad6 ad39 ad7 1 - lad7 1 - lad7 1 - lad7 1 - lad31 1 - lad15 1 - lad7 ad40 ad8 1 - lad8 1 - lad8 2 - lad0 1 - lad16 1 - lad0 2 - lad0 ad41 ad9 1 - lad9 1 - lad9 2 - lad1 1 - lad17 1 - lad1 2 - lad1 ad42 ad10 1 - lad10 1 - lad10 2 - lad2 1 - lad18 1 - lad2 2 - lad2 ad43 ad11 1 - la d11 1 - lad11 2 - lad3 1 - lad19 1 - lad3 2 - lad3 ad44 ad12 1 - lad12 1 - lad12 2 - lad4 1 - lad20 1 - lad4 2 - lad4 ad45 ad13 1 - lad13 1 - lad13 2 - lad5 1 - lad21 1 - lad5 2 - lad5 ad46 ad14 1 - lad14 1 - lad14 2 - lad6 1 - lad22 1 - lad6 2 - lad6 ad47 ad15 1 - lad15 1 - lad15 2 - lad7 1 - lad23 1 - lad 7 2 - lad7 ad48 ad16 1 - lad16 2 - lad0 3 - lad0 1 - lad8 2 - lad8 3 - lad0 ad48 ad17 1 - lad17 2 - lad1 3 - lad1 1 - lad9 2 - lad9 3 - lad1 ad50 ad18 1 - lad18 2 - lad2 3 - lad2 1 - lad10 2 - lad10 3 - lad2 ad51 ad19 1 - lad19 2 - lad3 3 - lad3 1 - lad11 2 - lad11 3 - lad3 ad52 ad20 1 - lad20 2 - lad4 3 - lad4 1 - lad12 2 - lad12 3 - lad4 ad53 ad21 1 - lad21 2 - lad5 3 - lad5 1 - lad13 2 - lad13 3 - lad5 ad54 ad22 1 - lad22 2 - lad6 3 - lad6 1 - lad14 2 - lad14 3 - lad6 ad55 ad23 1 - lad23 2 - lad7 3 - lad7 1 - lad15 2 - lad15 3 - lad7 ad56 ad24 1 - lad24 2 - lad8 4 - lad0 1 - lad0 2 - lad0 4 - lad0 ad57 ad25 1 - lad25 2 - lad9 4 - lad1 1 - lad1 2 - lad1 4 - lad1 ad58 ad26 1 - lad26 2 - lad10 4 - lad2 1 - lad2 2 - lad2 4 - lad2 ad59 ad27 1 - lad27 2 - lad11 4 - lad3 1 - lad3 2 - lad3 4 - lad3 ad60 ad28 1 - lad28 2 - lad12 4 - lad4 1 - lad4 2 - lad4 4 - lad4 ad61 ad29 1 - lad29 2 - lad13 4 - lad5 1 - lad5 2 - lad5 4 - lad5 ad62 ad30 1 - lad30 2 - lad14 4 - lad6 1 - lad6 2 - lad6 4 - lad6 ad63 ad31 1 - lad31 2 - lad15 4 - lad7 1 - lad7 2 - lad7 4 - lad7 notes 1. during 64 - bit pci transfers, the lower 32 bits of the pci bus (ad[31:0]) are always mapped first. 2. for each local bus pin tabl e entry, n - m means that row?s pci pin maps to local bus pin m during local bus cycle n that either results from the pci cycle (pci - to - local bus transfers) or results in the pci cycle (local bus - to - pci transfers). for example, a local bus pin of ?2 - lad5? fo r pci pin ad21 during 16 ? bit little endian local bus transfers (ref. the darkest shaded entry) means that during a pci - to - local bus transfer, the value of pci pin ad21 during each 32 - bit pci transfer will occur on local bus pin lad5 of the second resulting 16 - bit local bus transfer. during a local bus - to - pci transfer, this means that the value of pci pin ad21 will result from the value of local bus pin lad5 during the second 16 - bit local bus transfer. 3. the mappings in the table only occur during data phases. addresses always map to/from pci ad[31:0] as indicated in the 32 - bit little endian column after the address translation specified in the configuration registers is performed. 4. little and big endian modes are selected by both register bits and pin signals, depending on the data phase type: direct master read/write, direct slave read/write, dma pci - to - local bus / local bus - to - pci, and configuration register read/write. see the bigend register description in table 11 - 41 and the bigend# pin description in table 12 - 11 for details.
12/19/2002 - 10 - 9656 - sil - dc1 - p0 - . 96 table 8 . j mode endian mapping for byte lane mode 1 j mode local bus pin byte lane mode = 1 (bigend[4] = 1) little endian big endian pci pins mapped 2 nd (64 - bit transfers only) pci pins mapped 1 st 32 - bit 16 - bit 8 - bit 32 - bit 16 - bit 8 - bit ad32 ad0 1 - lad0 1 - lad16 1 - lad24 1 - lad24 1 - lad24 1 - lad24 ad33 ad1 1 - lad1 1 - lad17 1 - lad25 1 - lad25 1 - lad25 1 - lad25 ad34 ad2 1 - lad2 1 - lad18 1 - lad26 1 - lad26 1 - lad26 1 - lad26 ad35 ad3 1 - lad3 1 - lad19 1 - lad27 1 - lad27 1 - lad27 1 - lad27 ad36 ad4 1 - lad4 1 - lad20 1 - lad28 1 - lad28 1 - lad28 1 - lad28 ad37 ad5 1 - lad5 1 - lad21 1 - lad29 1 - lad29 1 - lad29 1 - lad29 ad38 ad6 1 - lad6 1 - lad22 1 - lad30 1 - lad30 1 - lad30 1 - lad30 ad39 ad7 1 - lad7 1 - lad23 1 - lad31 1 - lad31 1 - lad31 1 - lad31 ad40 ad8 1 - lad8 1 - lad 24 2 - lad24 1 - lad16 1 - lad16 2 - lad24 ad41 ad9 1 - lad9 1 - lad25 2 - lad25 1 - lad17 1 - lad17 2 - lad25 ad42 ad10 1 - lad10 1 - lad26 2 - lad26 1 - lad18 1 - lad18 2 - lad26 ad43 ad11 1 - lad11 1 - lad27 2 - lad27 1 - lad19 1 - lad19 2 - lad27 ad44 ad12 1 - lad12 1 - lad28 2 - lad28 1 - lad20 1 - l ad20 2 - lad28 ad45 ad13 1 - lad13 1 - lad29 2 - lad29 1 - lad21 1 - lad21 2 - lad29 ad46 ad14 1 - lad14 1 - lad30 2 - lad30 1 - lad22 1 - lad22 2 - lad30 ad47 ad15 1 - lad15 1 - lad31 2 - lad31 1 - lad23 1 - lad23 2 - lad31 ad48 ad16 1 - lad16 2 - lad16 3 - lad24 1 - lad8 2 - lad24 3 - lad24 ad48 ad 17 1 - lad17 2 - lad17 3 - lad25 1 - lad9 2 - lad25 3 - lad25 ad50 ad18 1 - lad18 2 - lad18 3 - lad26 1 - lad10 2 - lad26 3 - lad26 ad51 ad19 1 - lad19 2 - lad19 3 - lad27 1 - lad11 2 - lad27 3 - lad27 ad52 ad20 1 - lad20 2 - lad20 3 - lad28 1 - lad12 2 - lad28 3 - lad28 ad53 ad21 1 - lad21 2 - lad21 3 - lad29 1 - lad13 2 - lad29 3 - lad29 ad54 ad22 1 - lad22 2 - lad22 3 - lad30 1 - lad14 2 - lad30 3 - lad30 ad55 ad23 1 - lad23 2 - lad23 3 - lad31 1 - lad15 2 - lad31 3 - lad31 ad56 ad24 1 - lad24 2 - lad24 4 - lad24 1 - lad0 2 - lad16 4 - lad24 ad57 ad25 1 - lad25 2 - lad25 4 - lad25 1 - lad1 2 - lad17 4 - lad25 ad58 ad26 1 - lad26 2 - lad26 4 - lad26 1 - lad2 2 - lad18 4 - lad26 ad59 ad27 1 - lad27 2 - lad27 4 - lad27 1 - lad3 2 - lad19 4 - lad27 ad60 ad28 1 - lad28 2 - lad28 4 - lad28 1 - lad4 2 - lad20 4 - lad28 ad61 ad29 1 - lad29 2 - lad29 4 - lad29 1 - lad5 2 - lad21 4 - lad29 ad62 ad30 1 - lad 30 2 - lad30 4 - lad30 1 - lad6 2 - lad22 4 - lad30 ad63 ad31 1 - lad31 2 - lad31 4 - lad31 1 - lad7 2 - lad23 4 - lad31 notes 1. during 64 - bit pci transfers, the lower 32 bits of the pci bus (ad[31:0]) are always mapped first. 2. for each local bus pin table entry, n - m means that row?s pci pin maps to local bus pin m during local bus cycle n that either results from the pci cycle (pci - to - local bus transfers) or results in the pci cycle (local bus - to - pci transfers). for example, a local bus pin of ?2 - lad21? for pci pin ad21 during 16 ? bit little endian local bus transfers (ref. the darkest shaded entry) means that during a pci - to - local bus transfer, the value of pci pin ad21 during each 32 - bit pci transfer will occur on local bus pin lad21 of the second resulting 16 - bit local bus tra nsfer. during a local bus - to - pci transfer, this means that the value of pci pin ad21 will result from the value of local bus pin lad21 during the second 16 - bit local bus transfer. 3. the mappings in the table only occur during data phases. addresses always ma p to/from pci ad[31:0] as indicated in the 32 - bit little endian column after the address translation specified in the configuration registers is performed. 4. little and big endian modes are selected by both register bits and pin signals, depending on the dat a phase type: direct master read/write, direct slave read/write, dma pci - to - local bus / local bus - to - pci, and configuration register read/write. see the bigend register description in table 11 - 41 and the bigend# pin description in table 12 - 11 for details.
12/19/2002 - 11 - 9656 - sil - dc1 - p0 - . 96 table 9 . m mode endian mapping for byte lane mode 0 m mode local bus pin byte lane mode = 0 (bigend[4] = 0) little endian big endian pci pins mapped 2 nd (64 - bit transfers only) pci pins mapped 1 st 32 - bit 16 - bit 8 - bit 32 - bit 16 - bit 8 - bit ad32 ad0 1 - ld31 1 - ld31 1 - ld31 1 - ld7 1 - ld23 1 - ld31 ad33 ad1 1 - ld30 1 - ld30 1 - ld30 1 - ld6 1 - ld22 1 - ld30 ad34 ad2 1 - ld29 1 - ld29 1 - ld29 1 - ld5 1 - ld21 1 - ld29 ad35 ad3 1 - ld28 1 - ld28 1 - ld28 1 - ld4 1 - ld20 1 - ld28 ad36 ad4 1 - ld27 1 - ld27 1 - ld27 1 - ld3 1 - ld19 1 - ld27 ad37 ad5 1 - ld26 1 - ld26 1 - ld26 1 - ld2 1 - ld18 1 - ld26 ad38 ad6 1 - ld25 1 - ld25 1 - ld25 1 - ld1 1 - ld17 1 - ld25 ad39 ad7 1 - ld24 1 - ld24 1 - ld24 1 - ld0 1 - ld16 1 - ld24 ad40 ad8 1 - ld23 1 - ld23 2 - ld31 1 - ld15 1 - ld31 2 - ld31 ad41 ad9 1 - ld22 1 - ld22 2 - ld30 1 - ld14 1 - ld30 2 - ld30 ad42 ad10 1 - ld21 1 - ld21 2 - ld29 1 - ld13 1 - ld29 2 - ld29 ad43 ad11 1 - ld20 1 - ld20 2 - ld28 1 - ld12 1 - ld28 2 - ld28 ad44 ad12 1 - ld19 1 - ld19 2 - ld27 1 - ld11 1 - ld27 2 - ld27 ad45 ad13 1 - ld18 1 - ld18 2 - ld26 1 - ld10 1 - ld26 2 - ld26 ad46 ad14 1 - ld17 1 - ld17 2 - ld2 5 1 - ld9 1 - ld25 2 - ld25 ad47 ad15 1 - ld16 1 - ld16 2 - ld24 1 - ld8 1 - ld24 2 - ld24 ad48 ad16 1 - ld15 2 - ld31 3 - ld31 1 - ld23 2 - ld23 3 - ld31 ad48 ad17 1 - ld14 2 - ld30 3 - ld30 1 - ld22 2 - ld22 3 - ld30 ad50 ad18 1 - ld13 2 - ld29 3 - ld29 1 - ld21 2 - ld21 3 - ld29 ad51 ad19 1 - ld12 2 - ld2 8 3 - ld28 1 - ld20 2 - ld20 3 - ld28 ad52 ad20 1 - ld11 2 - ld27 3 - ld27 1 - ld19 2 - ld19 3 - ld27 ad53 ad21 1 - ld10 2 - ld26 3 - ld26 1 - ld18 2 - ld18 3 - ld26 ad54 ad22 1 - ld9 2 - ld25 3 - ld25 1 - ld17 2 - ld17 3 - ld25 ad55 ad23 1 - ld8 2 - ld24 3 - ld24 1 - ld16 2 - ld16 3 - ld24 ad56 ad24 1 - ld7 2 - ld23 4 - ld31 1 - ld31 2 - ld31 4 - ld31 ad57 ad25 1 - ld6 2 - ld22 4 - ld30 1 - ld30 2 - ld30 4 - ld30 ad58 ad26 1 - ld5 2 - ld21 4 - ld29 1 - ld29 2 - ld29 4 - ld29 ad59 ad27 1 - ld4 2 - ld20 4 - ld28 1 - ld28 2 - ld28 4 - ld28 ad60 ad28 1 - ld3 2 - ld19 4 - ld27 1 - ld27 2 - ld27 4 - ld27 ad61 ad29 1 - ld2 2 - ld18 4 - ld26 1 - ld26 2 - ld26 4 - ld26 ad62 ad30 1 - ld1 2 - ld17 4 - ld25 1 - ld25 2 - ld25 4 - ld25 ad63 ad31 1 - ld0 2 - ld16 4 - ld24 1 - ld24 2 - ld24 4 - ld24 notes 1. during 64 - bit pci transfers, the lower 32 bits of the pci bus (ad[31:0]) are always mapped first. 2. for ea ch local bus pin table entry, n - m means that row?s pci pin maps to local bus pin m during local bus cycle n that either results from the pci cycle (pci - to - local bus transfers) or results in the pci cycle (local bus - to - pci transfers). for example, a local b us pin of ?2 - ld26? for pci pin ad21 during 16 ? bit little endian local bus transfers (ref. the darkest shaded entry) means that during a pci - to - local bus transfer, the value of pci pin ad21 during each 32 - bit pci transfer will occur on local bus pin ld26 of the second resulting 16 - bit local bus transfer. during a local bus - to - pci transfer, this means that the value of pci pin ad21 will result from the value of local bus pin ld26 during the second 16 - bit local bus transfer. 3. the mappings in the table only occu r during data phases. addresses always map to/from pci ad[31:0] as indicated in the 32 - bit little endian column after the address translation specified in the configuration registers is performed. 4. little and big endian modes are selected by both register b its and pin signals, depending on the data phase type: direct master read/write, direct slave read/write, dma pci - to - local bus / local bus - to - pci, and configuration register read/write. see the bigend register description in table 11 - 41 and the bigend# pin description in table 12 - 11 for details.
12/19/2002 - 12 - 9656 - sil - dc1 - p0 - . 96 table 10 . m mode endian mapping for byte lane mode 1 m mode local bus pin byte lane mode = 1 (bigend[4] = 1) little endia n big endian pci pins mapped 2 nd (64 - bit transfers only) pci pins mapped 1 st 32 - bit 16 - bit 8 - bit 32 - bit 16 - bit 8 - bit ad32 ad0 1 - ld31 1 - ld15 1 - ld7 1 - ld7 1 - ld7 1 - ld7 ad33 ad1 1 - ld30 1 - ld14 1 - ld6 1 - ld6 1 - ld6 1 - ld6 ad34 ad2 1 - ld29 1 - ld13 1 - ld5 1 - ld5 1 - ld5 1 - ld5 ad35 ad3 1 - ld28 1 - ld12 1 - ld4 1 - ld4 1 - ld4 1 - ld4 ad36 ad 4 1 - ld27 1 - ld11 1 - ld3 1 - ld3 1 - ld3 1 - ld3 ad37 ad5 1 - ld26 1 - ld10 1 - ld2 1 - ld2 1 - ld2 1 - ld2 ad38 ad6 1 - ld25 1 - ld9 1 - ld1 1 - ld1 1 - ld1 1 - ld1 ad39 ad7 1 - ld24 1 - ld8 1 - ld0 1 - ld0 1 - ld0 1 - ld0 ad40 ad8 1 - ld23 1 - ld7 2 - ld7 1 - ld15 1 - ld15 2 - ld7 ad41 ad9 1 - ld22 1 - ld6 2 - ld6 1 - ld14 1 - ld14 2 - ld6 ad42 ad10 1 - ld21 1 - ld5 2 - ld5 1 - ld13 1 - ld13 2 - ld5 ad43 ad11 1 - ld20 1 - ld4 2 - ld4 1 - ld12 1 - ld12 2 - ld4 ad44 ad12 1 - ld19 1 - ld3 2 - ld3 1 - ld11 1 - ld11 2 - ld3 ad45 ad13 1 - ld18 1 - ld2 2 - ld2 1 - ld10 1 - ld10 2 - ld2 ad46 ad14 1 - ld17 1 - ld1 2 - ld1 1 - ld9 1 - ld9 2 - ld1 ad47 ad15 1 - ld16 1 - ld0 2 - ld0 1 - ld8 1 - ld8 2 - ld0 ad48 ad16 1 - ld15 2 - ld15 3 - ld7 1 - ld23 2 - ld7 3 - ld7 ad48 ad17 1 - ld14 2 - ld14 3 - ld6 1 - ld22 2 - ld6 3 - ld6 ad50 ad18 1 - ld13 2 - ld13 3 - ld5 1 - ld21 2 - ld5 3 - ld5 ad51 ad19 1 - ld12 2 - ld12 3 - ld4 1 - ld20 2 - ld 4 3 - ld4 ad52 ad20 1 - ld11 2 - ld11 3 - ld3 1 - ld19 2 - ld3 3 - ld3 ad53 ad21 1 - ld10 2 - ld10 3 - ld2 1 - ld18 2 - ld2 3 - ld2 ad54 ad22 1 - ld9 2 - ld9 3 - ld1 1 - ld17 2 - ld1 3 - ld1 ad55 ad23 1 - ld8 2 - ld8 3 - ld0 1 - ld16 2 - ld0 3 - ld0 ad56 ad24 1 - ld7 2 - ld7 4 - ld7 1 - ld31 2 - ld15 4 - ld7 ad 57 ad25 1 - ld6 2 - ld6 4 - ld6 1 - ld30 2 - ld14 4 - ld6 ad58 ad26 1 - ld5 2 - ld5 4 - ld5 1 - ld29 2 - ld13 4 - ld5 ad59 ad27 1 - ld4 2 - ld4 4 - ld4 1 - ld28 2 - ld12 4 - ld4 ad60 ad28 1 - ld3 2 - ld3 4 - ld3 1 - ld27 2 - ld11 4 - ld3 ad61 ad29 1 - ld2 2 - ld2 4 - ld2 1 - ld26 2 - ld10 4 - ld2 ad62 ad30 1 - l d1 2 - ld1 4 - ld1 1 - ld25 2 - ld9 4 - ld1 ad63 ad31 1 - ld0 2 - ld0 4 - ld0 1 - ld24 2 - ld8 4 - ld0 notes 1. during 64 - bit pci transfers, the lower 32 bits of the pci bus (ad[31:0]) are always mapped first. 2. for each local bus pin table entry, n - m means that row?s pci pin map s to local bus pin m during local bus cycle n that either results from the pci cycle (pci - to - local bus transfers) or results in the pci cycle (local bus - to - pci transfers). for example, a local bus pin of ?2 - ld10? for pci pin ad21 during 16 ? bit little endia n local bus transfers (ref. the darkest shaded entry) means that during a pci - to - local bus transfer, the value of pci pin ad21 during each 32 - bit pci transfer will occur on local bus pin ld10 of the second resulting 16 - bit local bus transfer. during a loca l bus - to - pci transfer, this means that the value of pci pin ad21 will result from the value of local bus pin ld10 during the second 16 - bit local bus transfer. 3. the mappings in the table only occur during data phases. addresses always map to/from pci ad[31:0 ] as indicated in the 32 - bit little endian column after the address translation specified in the configuration registers is performed. 4. little and big endian modes are selected by both register bits and pin signals, depending on the data phase type: direct master read/write, direct slave read/write, dma pci - to - local bus / local bus - to - pci, and configuration register read/write. see the bigend register description in table 11 - 41 and the bigend# pin description in table 12 - 11 for details.
12/19/2002 - 13 - 9656 - sil - dc1 - p0 - . 96 8. local bus pause time r count must be even (marbr[8] = 0) the blue book includes a description of the local bus pause timer in the marbr register (register description 11 - 40). for the pci 9656ad, the local bus pause timer count must be even (marbr[8] = 0). this restriction is n ot included in the blue book description. for the pci 9056ba, this count may be odd or even (marbr[8] = 0 or 1). the pci 9656 includes a local bus pause timer (marbr[15:8]) for specifying how long to stay off of the local bus between transfers to/from the local bus during dma. for the pci 9656ad, this count must be even (marbr[8] = 0). note that this counter is 0 after reset, so the only time this correction is of concern is if the local bus pause timer count is ever changed from its reset value. for the pc i 9056ba, this count may be odd or even (marbr[8] = 0 or 1). 9. ale output delay timing for any local bus clock rate the blue book includes figure 13 - 3 that shows the ale output delay timing to the processor/local bus clock for a clock rate of 33mhz. it does not show the output delay timing for other clock rates. the following figure shows the pci 9656ad ale output delay timing for any processor/local bus clock rate. it replaces figure 13 - 3 in the blue book for the pci 9656ad silicon. lc high is the time in ns that the processor/local bus clock is high. ( note. when two times are given like x/y ns, x ns is the minimum value and y ns is the maximum value.) ale local clock address bus 1.5v lc high lc high +15.1/15.4 ns (33 mhz) lc high +7.6/7.9 ns (66 mhz) 3.1/6.9 ns 2.9/6.5 ns 2.9/7.8 ns 2.9/7.8 ns 1.5v figure 3 . pci 9656ad ale output delay to the local clock
12/19/2002 - 14 - 9656 - sil - dc1 - p0 - . 96 the following figure shows the pci 9656ba ale output delay timing for any processor/local bus clock rate. it replaces figure 13 - 3 in the blue book for the pci 9656ba silicon. lc high is the time in ns that the processor/local bus clock is high. ( note. when two times are given like x/y ns, x ns is the minimum value and y ns is the maximum value.) ale local clock 1.5v lc high lc high +14.8/14.9 ns (33 mhz) lc high +6.8/6.9 ns (66 mhz) 3.4/6.9 ns 3.6/7.0 ns 3.0/6.4 ns 3.0/6.4 ns 1.5v address bus figure 4 . pci 9656ba ale output delay to the local clock 10. m mode la30 & la 31 pin outs description: the blue bo ok table 14 - 3 pin outs for pins p19 and p20 are indicated incorrectly. the m mode la31 and la30 signals are swapped. this is true for both the pci 9656ad and the pci 9656ba. blue book table 14 - 3 indicates that pin p19 is ?la31 (m), lbe1# (c, j)? and pin p2 0 is ?la30 (m), lbe0# (c, j)?. this is incorrect. for the pci 9656ad and pci 9656ba, pin p19 is ?la30 (m), lbe1# (c, j)? and pin p20 is ?la31 (m), lbe0# (c, j)?. note that in table 12 - 10 the pin numbers for la30 and la31 are indicated correctly. 11. ac timing description: plx had conducted exhaustive static timing analysis (sta) of the pci 9656ad and pci 9656ba silicon. the following six tables contain the results of that analysis and replace tables 13 - 6, 13 - 7, 13 - 8, and 13 - 9 in the blue book.
12/19/2002 - 15 - 9656 - sil - dc1 - p0 - . 96 table 11 . c mode local bus input ac timing specifications signals (synchronous inputs) t setup (v cc = 3.0v, t a = 85c) t hold (v cc = 3.0v, t a = 85c) blue book ad sta ba sta blue book ad sta ba sta ads# 4.5 ns 4.8 ns 2.1 n s 1 ns 1 ns 1 ns bigend# 4.5 ns 4.8 ns 4.0 ns 1 ns 1 ns 1 ns blast# 4.5 ns 4.0 ns 3.4 ns 1 ns 1 ns 1 ns breqi 4.5 ns 1.7 ns 0.3 ns 1 ns 1 ns 1 ns bterm# 4.5 ns 4.8 ns 4.0 ns 1 ns 1 ns 1 ns ccs# 4.5 ns 1.7 ns 2.9 ns 1 ns 1 ns 1 ns dmpaf/ eot# 4.5 ns 4.7 ns 4.2 ns 1 ns 1 ns 1 ns dp[3:0] 4.5 ns 2.0 ns 2.9 ns 1 ns 1 ns 1 ns dreq[1:0]# 4.5 ns 4.4 ns 3.3 ns 1 ns 1 ns 1 ns la[31:2] 4.5 ns 4.0 ns 3.4 ns 1 ns 1 ns 1 ns lbe[3:0]# 4.5 ns 4.6 ns 3.6 ns 1 ns 1 ns 1 ns ld[31:0] 4.5 ns 4.9 ns 3.1 ns 1 ns 1 ns 1 ns lh olda 4.5 ns 4.2 ns 2.5 ns 1 ns 1 ns 1 ns lw/r# 4.5 ns 5.0 ns 3.5 ns 1 ns 1 ns 1 ns ready# 4.5 ns 4.7 ns 4.0 ns 1 ns 1 ns 1 ns useri/llocki# 4.5 ns 2.4 ns 2.9 ns 1 ns 1 ns 1 ns wait# 4.5 ns 4.7 ns 4.0 ns 1 ns 1 ns 1 ns input clocks min max local clock input frequency 0 mhz 66 mhz pci clock input frequency 0 mhz 66 mhz table 12 . c mode local bus output ac timing specifications signals (synchronous outputs) output t valid (c l = 50pf, v cc = 3.0v, t a = 85c) blue book ad 1 sta ba 2 sta ads# 9ns 7.6 ns 6.3 ns blast# 9ns 7.6 ns 6.3 ns breqo 9ns 9.5 ns 6.8 ns bterm# 9ns 8.3 ns 6.8 ns dack[1:0]# 9ns 7.6 ns 6.3 ns dmpaf /eot# 9ns 8.5 ns 6.6 ns dp[3:0] 9ns 7.9 ns 6. 8 ns la[31:2] 9ns 8.0 ns 6.8 ns lbe[3:0]# 9ns 7.6 ns 6.3 ns ld[31:0] 9ns 7.8 ns 6.4 ns lhold 9ns 7.5 ns 6.8 ns lserr# 9ns 10.2 ns 7.5 ns lw/r# 9ns 7.6 ns 6.3 ns ready# 9ns 9.0 ns 7.2 ns usero/llocko# 9ns 7.6 ns 6.3 ns wait# 9ns 7.6 ns 6.4 ns 1. on high - to - low transitions, output t valid values increase/decrease by 23 ps for each increase/decrease of 1pf. on low - to - high transitions, output t valid values increase/decrease by 20 ps for each increase/decrease of 1pf. 2. on high - to - low transitions, output t valid va lues increase/decrease by 16 ps for each increase/decrease of 1pf. on low - to - high transitions, output t valid values increase/decrease by 20 ps for each increase/decrease of 1pf. on high - to - low transitions, the slew rate at 50 pf loading is 1.93 v/ns typic al; .94 v/ns worst case. on low - to - high transitions, the slew rate at 50 pf loading is 1.15 v/ns typical; .70 v/ns worst case.
12/19/2002 - 16 - 9656 - sil - dc1 - p0 - . 96 table 13 . j mode local bus input ac timing specifications signals (synchronous inputs) t setup (v cc = 3.0v, t a = 85c) t hold (v cc = 3.0v, t a = 85c) blue book ad sta ba sta blue book ad sta ba sta ads# 4.5 ns 4.9 ns 2.1 ns 1 ns 1 ns 1 ns ale 4.5 ns 4.5 ns 1.7 ns 1 ns 1 ns 1 ns bigend# 4.5 ns 4.8 ns 4. 0 ns 1 ns 1 ns 1 ns blast# 4.5 ns 4.0 ns 3.4 ns 1 ns 1 ns 1 ns breqi 4.5 ns 1.7 ns 0.3 ns 1 ns 1 ns 1 ns bterm# 4.5 ns 4.8 ns 4.2 ns 1 ns 1 ns 1 ns ccs# 4.5 ns 1.7 ns 2.9 ns 1 ns 1 ns 1 ns dmpaf/ eot# 4.5 ns 4.7 ns 4.2 ns 1 ns 1 ns 1 ns dp[3:0] 4.5 ns 2.0 ns 2.9 ns 1 ns 1 ns 1 ns dreq[1:0]# 4.5 ns 4.4 ns 3.3 ns 1 ns 1 ns 1 ns la [28:2] 4.5 ns 4.0 ns 3.4 ns 1 ns 1 ns 1 ns lad[31:0] 4.5 ns 4.9 ns 3.1 ns 1 ns 1 ns 1 ns lbe[3:0]# 4.5 ns 4.6 ns 3.6 ns 1 ns 1 ns 1 ns lholda 4.5 ns 4.2 ns 2.5 ns 1 ns 1 ns 1 ns lw/r# 4.5 ns 5.0 ns 3.5 ns 1 ns 1 ns 1 ns ready# 4.5 ns 4.7 ns 4.2 ns 1 ns 1 ns 1 ns useri/llocki# 4.5 ns 2.4 ns 2.9 ns 1 ns 1 ns 1 ns wait# 4.5 ns 4.7 ns 4.0 ns 1 ns 1 ns 1 ns input clocks min max local clock input frequency 0 mhz 66 mhz pci clock input frequency 0 mhz 66 mhz table 14 . j mode local bus output ac timing specifications signals (synchronous output s) output t valid (c l = 50pf, v cc = 3.0v, t a = 85c) blue book ad 1 sta ba 2 sta ads# 9 ns 7.6 ns 6.3 ns ale 9 ns 8.0 ns see item 9 , above. blast# 9 ns 7.6 ns 6.3 ns breqo 9 ns 9.5 ns 6.8 ns bterm# 9 ns 8.3 ns 6.8 ns dack[1:0]# 9 ns 7.6 ns 6.3 ns den# 9 ns 7.9 ns 6.4 ns dmpaf /eot# 9 ns 8.5 ns 6.6 ns dp[3:0] 9 ns 7.9 ns 6.8 ns dt/r# 9 ns 7.9 ns 6.3 ns la[28:2] 9 ns 8.0 ns 6.4 ns lad[31:0] 9 ns 7.8 ns 6.4 ns lbe[3:0]# 9 ns 7.6 ns 6.3 ns lhold 9 ns 7.5 ns 6.8 ns lserr# 9 ns 10.2 ns 7.5 ns lw/r# 9 ns 7.6 ns 6.3 ns ready# 9 ns 9.0 ns 7.2 ns usero/llocko# 9 ns 7.6 ns 6.3 ns wait# 9 ns 7.6 ns 6.4 ns 1 on high - to - low transitions, output t valid values increase/decrease by 23 ps for each increase/decrease of 1pf. on low - to - high transitions, output t valid values inc rease/decrease by 20 ps for each increase/decrease of 1pf. 2 on high - to - low transitions, output t valid values increase/decrease by 16 ps for each increase/decrease of 1pf. on low - to - high transitions, output t valid values increase/decrease by 20 ps for each i ncrease/decrease of 1pf. on high - to - low transitions, the slew rate at 50 pf loading is 1.93 v/ns typical; .94 v/ns worst case. on low - to - high transitions, the slew rate at 50 pf loading is 1.15 v/ns typical; .70 v/ns worst case.
12/19/2002 - 17 - 9656 - sil - dc1 - p0 - . 96 table 15 . m mode local bus input ac timing specifications signals (synchronous inputs) t setup (v cc = 3.0v, t a = 85c) t hold blue book ad sta ba sta blue book ad sta ba sta bb# 4.5 ns 4.9 ns 2.7 ns 1 ns 1 ns 1 ns bdip# 4.5 ns 4.5 ns 3.8 ns 1 ns 1 ns 1 ns bg# 4.5 ns 4.4 ns 2.9 ns 1 ns 1 ns 1 ns bi# 4.5 ns 5.3 ns 4.0 ns 1 ns 1 ns 1 ns bigend#/wait# 4.5 ns 4.8 ns 3.8 ns 1 ns 1 ns 1 ns burst# 4.5 ns 4.8 ns 4.1 ns 1 ns 1 ns 1 ns ccs# 4.5 ns 1.7 ns 2.9 ns 1 ns 1 ns 1 ns dp[0:3] 4.5 ns 2.0 ns 2.9 ns 1 ns 1 ns 1 ns dreq[1:0]# 4.5 ns 4.4 ns 3.3 ns 1 ns 1 ns 1 ns la[0:31] 4.5 ns 5.2 ns 3.6 ns 1 ns 1 ns 1 ns ld[0:31] 4.5 ns 4.9 ns 3.1 ns 1 ns 1 ns 1 ns mdreq#/dmpaf/ eot# 4.5 ns 4.7 ns 4.2 ns 1 ns 1 ns 1 ns rd/wr# 4.5 ns 5.3 ns 3.5 ns 1 ns 1 ns 1 n s ta# 4.5 ns 5.3 ns 4.1 ns 1 ns 1 ns 1 ns tea# 4.5 ns 5.2 ns 4.4 ns 1 ns 1 ns 1 ns ts# 4.5 ns 4.8 ns 2.1 ns 1 ns 1 ns 1 ns tsiz[0:1]# 4.5 ns 5.0 ns 3.6 ns 1 ns 1 ns 1 ns useri/llock# 4.5 ns 1.9 ns 3.2 ns 1 ns 1 ns 1 ns input clocks min max local clock input frequency 0 mhz 66 mhz pci clock input frequency 0 mhz 66 mhz table 16 . m mode local bus output ac timing specifications signals (synchronous outputs) output t valid (c l = 50pf, v cc = 3.0v, t a = 85c) blue book ad 1 sta ba 2 sta bb# 9 ns 9.4 ns 6.8 ns bdip# 9 ns 7.7 ns 6.4 ns bigend#/ wait# 9 ns 7.6 ns 6.3 ns br# 9 ns 7.5 ns 6.8 ns burst# 9 ns 7.6 ns 6.3 ns dack[1:0]# 9 ns 7.6 ns 6.3 ns dp[0:3] 9 ns 7.9 ns 6.8 ns la[0:31] 9 ns 8.0 ns 6.8 ns ld[0:31] 9 ns 7.8 ns 6.3 ns mdreq#/dmpaf/ eot# 9 ns 8.5 ns 6.6 ns rd/wr# 9 ns 7.6 ns 6.3 ns retry# 9 ns 9.5 ns 6.8 ns ta# 9 ns 9.0 ns 7 .2 ns tea# 9 ns 9.6 ns 7.5 ns ts# 9 ns 7.6 ns 6.3 ns tsiz[0:1]# 9 ns 7.6 ns 6.3 ns usero/llocko# 9 ns 7.6 ns 6.3 ns 1 on high - to - lo w transitions, output t valid values increase/decrease by 23 ps for each increase/decrease of 1pf. on low - to - high transitions, output t valid values increase/decrease by 20 ps for each increase/decrease of 1pf. 2 on high - to - low transitions, output t valid value s increase/decrease by 16 ps for each increase/decrease of 1pf. on low - to - high transitions, output t valid values increase/decrease by 20 ps for each increase/decrease of 1pf. on high - to - low transitions, the slew rate at 50 pf loading is 1.93 v/ns typical; .94 v/ns worst case. on low - to - high transitions, the slew rate at 50 pf loading is 1.15 v/ns typical; .70 v/ns worst case.
12/19/2002 - 18 - 9656 - sil - dc1 - p0 - . 96 12. pin types description: the following tables detail the pin types of the pci 9656ad and pci 9656ba silicon. the information in these tables is intended to replace the pin type columns of blue book tables 12 - 4 through 12 - 12. each table includes 5 columns for each pin: 1. each entry in the leftmost column contains the name of the signal (or signals, in the case of multiplexed pins) connecte d to that pin. 2. each entry in the next column contains the pin number (or pin numbers in the case of address buses, data buses, etc. that share the same pin type). 3. each entry in the next column contains the pin type in the blue book. 4. each entry in the next column contains the actual pin type for the ad silicon revision. shaded entries in this column indicate where the actual pin type of the ad silicon differs from the pin type given in the blue book. while these changes should not effect designs that follow the blue book pin types, for designs that use the ad version of silicon, the designers should look carefully at the shaded entries in this column. 5. each entry in the rightmost column contains the actual pin type for the ba silicon revision. shaded entries i n this column indicate where the actual pin type of the ba silicon differs from the actual pin type of the ad silicon. while these changes should not effect designs intended to use both ad and ba silicon revisions, for ad designs that are intended to use t he ba as a drop - in replacement for the ad, the designers should look carefully at the shaded entries in this column.
12/19/2002 - 19 - 9656 - sil - dc1 - p0 - . 96 table 17 . pci 9656ad/pci 9656ba pci pin types symbol pin number blue book r.90b pin type true ad pin type true b a pin type ack64# n1 i/o sts pci i/o sts pci i/o sts pci ad[63:0] t4, u3, w1, v3, y2, w4, v4, u5, y3, y4, v5, w5, y5, v6, u7, w6, y6, v7, w7, y7, v8, w8, y8, v9, w9, y9, w10, v10, y10, y11, w11, v11, a5, d7, c6, b5, a4, c5, b4, a3, b3, b2, a2, c3, b1, c2 , d2, d3, h3, h2, h1, j4, j3, j2, j1, k2, k1, l2, l3, l4, m1, m2, m3, m4 i/o ts pci i/o ts pci i/o ts pci c/be[7:0]# t2, u1, t3, u2, d5, e4, g1, k3 i/o ts pci i/o ts pci i/o ts pci devsel# e1 i/o sts pci i/o sts pci i/o sts pci frame# c1 i/o sts pci i/o sts pci i/o sts pci gnt0# req# c7 gnt0# o req# o sts pci o tp pci note: if ((rst# asserted) or (bd_sel# not asserted)) pin goes hi - z. o tp pci note: if ((rst# asserted) or (bd_sel# not asserted)) pin goes hi - z. gnt[6:1]# w12, u11, p4, r2, r1, n3 o t p o tp pci note: if ((rst# asserted) or (bd_sel# not asserted) or pcarb[0]=0)) pins go hi - z. o tp pci note: if ((rst# asserted) or (bd_sel# not asserted) or pcarb[0]=0)) pins go hi - z. idsel c4 i i i inta# b7 i/o oc pci i/o oc pci i/o oc pci irdy# d1 i /o sts pci i/o sts pci i/o sts pci lock# g4 i/o sts pci i/o sts pci i/o sts pci par g2 i/o ts pci i/o ts pci i/o ts pci par64 v1 i/o ts pci i/o ts pci i/o ts pci pclk l1 i i i perr# f2 i/o sts pci i/o sts pci i/o sts pci
12/19/2002 - 20 - 9656 - sil - dc1 - p0 - . 96 table 17 . pci 9656ad/pci 9656ba pci pin types symbol pin number blue book r.90b pin type true ad pin type true b a pin type pme# b9 o oc pci o oc pci o o c pci req0# gnt# b6 req0# i gnt# i i i req[6:1]# v12, y12, r3, t1, p2, p1 i i i req64# n2 i/o sts pci i/o sts pci i/o sts pci rst# a6 i/o if (hosten# asserted) o tp pci else i if (hosten# asserted) o tp pci else i serr# g3 i/o oc pci i/o oc pc i i/o oc pci stop# f3 i/o sts pci i/o sts pci i/o sts pci trdy# e3 i/o sts pci i/o sts pci i/o sts pci
12/19/2002 - 21 - 9656 - sil - dc1 - p0 - . 96 table 18 . pci 9656ad/pci 9656ba c mode pin types symbol pin number blue book r.90b pin type true ad pin type true ba pin ty pe ads# c17 i/o ts 24 ma i/o ts 24 ma i/o ts 24 ma bigend# c12 i i i blast# a18 i/o ts 24 ma i/o ts 24 ma i/o ts 24 ma breqi c16 i i i breqo a17 o oc 24 ma o dts 24 ma o dts 24 ma bterm# c20 i/o dts 24 ma i/o dts 24 ma i/o dts 24 ma ccs# d12 i i i dack[1:0]# c13, a13 o tp 24 ma o tp 24 ma note: if ((hosten# not asserted & rst# asserted) or (hosten# asserted & lreset# asserted) or (bd_sel# not asserted)) pins go hi - z. o tp 24 ma note: if ((hosten# not asserted & rst# asserted) or (hosten# asserted & lreset# asserted) or (bd_sel# not asserted)) pins go hi - z. dmpaf eot# d14 dmpaf o ts 24 ma eot# i if ((dmamode0[14]=1) or (dmamode1[14]=1)) i else o tp 24 ma if ((dmamode0[14]=1) or (dmamode1[14]=1)) i else o tp 24 ma note for 2nd case: if ((ho sten# not asserted & rst# asserted or (hosten# asserted & lreset# asserted) or (bd_sel# not asserted)) pin goes hi - z. dp[3:0] d18, b20, c18, b19 i/o ts 24 ma i/o ts 24 ma i/o ts 24 ma dreq[1:0]# a14, b13 i i i la[31:2] w14, y15, v14, w15, y16, u14, v15, w16, y17, v16, w17, y18, u16, v17, w18, y19, v18, w19, y20, w20, v19, u18, t17, v20, u20, t18, t19, t20, r18, p17 i/o ts 24 ma i/o ts 24 ma i/o ts 24 ma lbe[3:0]# r20, p18, p19, p20 i/o ts 24 ma i/o ts 24 ma i/o ts 24 ma lclk d20 i i i
12/19/2002 - 22 - 9656 - sil - dc1 - p0 - . 96 table 18 . pci 9656ad/pci 9656ba c mode pin types symbol pin number blue book r.90b pin type true ad pin type true ba pin ty pe ld[31:0] n18, n1 9, n20, m17, m18, m19, m20, l19, l18, l20, k20, k19, k18, k17, j20, j19, j18, j17, h20, h19, h18, g20, g19, f20, g18, f19, e20, g17, f18, e19, e18, d19 i/o ts 24 ma i/o ts 24 ma i/o ts 24 ma lhold b18 o tp 24 ma o tp 24 ma o tp 24 ma note: if ((hosten# n ot asserted & rst# asserted) or (hosten# asserted & lreset# asserted) or (bd_sel# not asserted)) pin goes hi - z. lholda b17 i i i linti# b15 i i i linto# a15 o oc 24 ma o oc 24 ma o oc 24 ma lreset# a16 i/o tp 24 ma if (hosten# asserted) i else o tp 24 ma if (hosten# asserted) i else o tp 24 ma lserr# d16 o oc 24 ma o oc 24 ma o oc 24 ma lw/r# r19 i/o ts 24 ma i/o ts 24 ma i/o ts 24 ma pmereq# b10 i i i ready# e17 i/o dts 24 ma i/o dts 24 ma i/o dts 24 ma useri llocki# b14 useri i llocki# i i i usero llocko# c14 usero o ts 24 ma llocko# o o tp 24 ma note: if ((hosten# not asserted & rst# asserted) or (hosten# asserted & lreset# asserted) or (bd_sel# not asserted)) pin goes hi - z. o tp 24 ma note: if ((hosten# not asserted & rst# asserted) or (hosten# asserted & lreset# asserted) or (bd_sel# not asserted)) pin goes hi - z. wait# b16 i/o ts 24 ma i/o ts 24 ma i/o ts 24 ma
12/19/2002 - 23 - 9656 - sil - dc1 - p0 - . 96 table 19 . pci 9656ad/pci 9656ba j mode pin types symbol pin number blue book r.90b pin type tr ue ad pin type true ba pin type ads# c17 i/o ts 24 ma i/o ts 24 ma i/o ts 24 ma ale v14 i/o ts 24 ma i/o ts 24 ma i/o ts 24 ma bigend# c12 i i i blast# a18 i/o ts 24 ma i/o ts 24 ma i/o ts 24 ma breqi c16 i i i breqo a17 o oc 24 ma o dts 24 ma o dts 24 ma bterm# c20 i/o dts 24 ma i/o dts 24 ma i/o dts 24 ma ccs# d12 i i i dack[1:0]# c13, a13 o tp 24 ma o tp 24 ma note: if ((hosten# not asserted & rst# asserted) or (hosten# asserted & lreset# asserted) or (bd_sel# not asserted)) pins go hi - z. o tp 24 ma note: if ((hosten# not asserted & rst# asserted) or (hosten# asserted & lreset# asserted) or (bd_sel# not asserted)) pins go hi - z. den# y15 o ts 24 ma o ts 24 ma o ts 24 ma dmpaf eot# d14 dmpaf o ts 24 ma eot# i if ((dmamode0[14]=1) or (dmamode1 [14]=1)) i else o tp 24 ma if ((dmamode0[14]=1) or (dmamode1[14]=1)) i else o tp 24 ma note for 2nd case: if ((hosten# not asserted & rst# asserted or (hosten# asserted & lreset# asserted) or (bd_sel# not asserted)) pin goes hi - z. dp[3:0] d18, b20, c18, b19 i/o ts 24 ma i/o ts 24 ma i/o ts 24 ma dreq[1:0]# a14, b13 i i i dt/r# w1 4 o ts 24 ma o ts 24 ma o ts 24 ma la[28:2] w15, y16, u14, v15, w16, y17, v16, w17, y18, u16, v17, w18, y19, v18, w19, y20, w20, v19, u18, t17, v20, u20, t18, t19, t20, r 18, p17 i/o ts 24 ma i/o ts 24 ma i/o ts 24 ma
12/19/2002 - 24 - 9656 - sil - dc1 - p0 - . 96 table 19 . pci 9656ad/pci 9656ba j mode pin types symbol pin number blue book r.90b pin type tr ue ad pin type true ba pin type lad[31:0] n18, n19, n20, m17, m18, m19, m20, l19, l18, l20, k20, k19, k18, k17, j20, j19, j18, j17, h20, h19, h18, g20, g19, f20, g18, f19, e20, g17, f18, e19, e18, d19 i/o ts 24 ma i/o ts 24 ma i/o ts 24 ma lbe[3:0]# r20, p18, p19, p20 i/o ts 24 ma i/o ts 24 ma i/o ts 24 ma lclk d20 i i i lhold b18 o tp 24 ma o tp 24 ma o tp 24 ma note: if ((hosten# not asserted & rst# asserted) or (hosten# asserted & lreset# asserted) or (bd_sel# not asserted)) pin goes hi - z. lholda b17 i i i linti# b15 i i i linto# a15 o oc 24 ma o oc 24 ma o oc 24 ma lreset# a16 i/o tp 24 ma if (hosten# asserted) i else o tp 24 ma if (hosten# asserted) i else o tp 24 ma lserr# d16 o oc 24 ma o oc 24 ma o oc 24 ma lw/r# r19 i /o ts 24 ma i/o ts 24 ma i/o ts 24 ma pmereq# b10 i i i ready# e17 i/o dts 24 ma i/o dts 24 ma i/o dts 24 ma useri llocki# b14 useri i llocki# i i i usero llocko# c14 usero o ts 24 ma llocko# o o tp 24 ma note: if ((hosten# not asserted & rst# ass erted) or (hosten# asserted & lreset# asserted) or (bd_sel# not asserted)) pin goes hi - z. o tp 24 ma note: if ((hosten# not asserted & rst# asserted) or (hosten# asserted & lreset# asserted) or (bd_sel# not asserted)) pin goes hi - z. wait# b16 i/o ts 24 m a i/o ts 24 ma i/o ts 24 ma
12/19/2002 - 25 - 9656 - sil - dc1 - p0 - . 96 table 20 . pci 9656ad/pci 9656ba m mode pin types symbol pin number blue book r.90b pin type true ad pin type true ba pin type bb# c16 i/o oc 24 ma i/o dts 24 ma i/o dts 24 ma bdip# b16 i/o ts 24 ma i/o ts 24 ma i/o ts 24 ma bg# b17 i i i bi# c20 i i i bigend# wait# c12 bigend# i wait# i/o ts 24 ma if(marbr(31)=0) i else i/o ts 24 ma if(marbr(31)=0) i else i/o ts 24 ma br# b18 o tp 24 ma o tp 24 ma o tp 24 ma note: if ((hosten# not assert ed & rst# asserted) or (hosten# asserted & lreset# asserted) or (bd_sel# not asserted)) pin goes hi - z. burst# a18 i/o ts 24 ma i/o ts 24 ma i/o ts 24 ma ccs# d12 i i i dack[1:0]# c13, a13 o tp 24 ma o tp 24 ma note: if ((hosten# not asserted & rst# ass erted) or (hosten# asserted & lreset# asserted) or (bd_sel# not asserted)) pins go hi - z. o tp 24 ma note: if ((hosten# not asserted & rst# asserted) or (hosten# asserted & lreset# asserted) or (bd_sel# not asserted)) pins go hi - z. dp[0:3] d18, b20, c18, b19 i/o ts 24 ma i/o ts 24 ma i/o ts 24 ma dreq[1:0]# a14, b13 i i i la[0:31] w14, y15, v14, w15, y16, u14, v15, w16, y17, v16, w17, y18, u16, v17, w18, y19, v18, w19, y20, w20, v19, u18, t17, v20, u20, t18, t19, t20, r18, p17, p19, p20 i/o ts 24 ma i/o ts 24 ma i/o ts 24 ma lclk d20 i i i ld[0:31] n18, n19, n20, m17, m18, m19, m20, l19, l18, l20, k20, k19, k18, k17, j20, j19, j18, j17, h20, h19, h18, g20, g19, f20, g18, f19, e20, g17, f18, e19, e18, d19 i/o ts 24 ma i/o ts 24 ma i/o ts 24 ma linti# b1 5 i i i
12/19/2002 - 26 - 9656 - sil - dc1 - p0 - . 96 table 20 . pci 9656ad/pci 9656ba m mode pin types symbol pin number blue book r.90b pin type true ad pin type true ba pin type linto# a15 o oc 24 ma o oc 24 ma o oc 24 ma lreset# a16 i/o tp 24 ma if (hosten# asserted) i else o tp 24 ma if (hosten# asserted) i else o tp 24 ma mdreq# dmpaf eot# d14 mdreq# o ts 24 ma dmpaf o ts 24 ma eot# i if ((dmamode0[14]=1) o r (dmamode1[14]=1)) i else o tp 24 ma if ((dmamode0[14]=1) or (dmamode1[14]=1)) i else o tp 24 ma note for 2nd case: if ((hosten# not asserted & rst# asserted or (hosten# asserted & lreset# asserted) or (bd_sel# not asserted)) pin goes hi - z. pmereq # b10 i i i rd/wr# r19 i/o ts 24 ma i/o ts 24 ma i/o ts 24 ma retry# a17 o oc 24 ma o dts 24 ma o dts 24 ma ta# e17 i/o dts 24 ma i/o dts 24 ma i/o dts 24 ma tea# d16 i/o oc 24 ma i/o oc 24 ma i/o oc 24 ma ts# c17 i/o ts 24 ma i/o ts 24 ma i/o ts 24 m a tsiz[0:1] r20, p18 i/o ts 24 ma i/o ts 24 ma i/o ts 24 ma useri llocki# b14 useri i llocki# i i i usero llocko# c14 usero o ts 24 ma llocko# o o tp 24 ma note: if ((hosten# not asserted & rst# asserted) or (hosten# asserted & lreset# asserted) or (bd_sel# not asserted)) pin goes hi - z. o tp 24 ma note: if ((hosten# not asserted & rst# asserted) or (hosten# asserted & lreset# asserted) or (bd_sel# not asserted)) pin goes hi - z.
12/19/2002 - 27 - 9656 - sil - dc1 - p0 - . 96 table 21 . pci 9656ad/pci 9656ba jtag pin type s symbol pin number blue book r.90b pin type true ad pin type true ba pin type tck a8 i i i tdi a7 i i i tdo c8 o ts pci o ts pci o ts pci tms b8 i i i trst# d9 i i i table 22 . pci 9656ad/pci 9656ba hot swap pin types symbo l pin number blue book r.90b pin type true ad pin type true ba pin type 64en# u12 i i i bd_sel# c9 i i i cpcisw y14 i i i enum# y13 o oc pci o oc pci o oc pci ledon# v13 o tp 24 ma o oc 24 ma o oc 24 ma table 23 . pci 9656ad/p ci 9656ba system pin types symbol pin number blue book r.90b pin type true ad pin type true ba pin type iddqen# a10 i i i mode[1:0] a19, a20 i i i hosten# c15 i i i table 24 . pci 9656ad/pci 9656ba eeprom pin types symbol pin number blue book r.90b pin type true ad pin type true ba pin type eecs b12 o tp 12 ma o tp 12 ma note: if (bd_sel# not asserted) pin goes hi - z. o tp 12 ma note: if (bd_sel# not asserted) pin goes hi - z. eedi/eedo b11 i/o tp 12 ma i/o ts 12 ma note: if (cntrl[31]=1) pin goes hi - z. i/o ts 12 ma note: if (cntrl[31]=1) pin goes hi - z. eesk a12 o tp 12 ma o tp 12 ma note: if (bd_sel# not asserted) pin goes hi - z. o tp 12 ma note: if (bd_sel# not asserted) pin goes hi - z.
12/19/2002 - 28 - 9656 - sil - dc1 - p0 - . 96 table 25 . pci 9656ad/pci 9656ba power & ground pin types symbol pin number blue book r.90b pin type true ad pin type true ba pin type 2.5v aux d10 i i i card_v aux c10 i i i present_det a11 i i i v bb w3 i i i note: changes from v bb to v ss . v core c11, c19, e2, p3, u9, u19 i i i v dda w2 i i i note: changes from v dda to v ring . v io a9, f1, v2, w13 i i i v ring a1, d4, d6, d8, d11, d13, d15, d17, f4, f17, h4, h17, k4, l17, n4, n17, r4, r17, u4, u6, u8, u10, u13, u15, u17 i i i v ss j9 - j12, k9 - k12, l9 - l12, m9 - m12 i i i v ssa y1 i i i note: changes from v ssa to v ss .

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