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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 1999 mos integrated circuit m m m m pd444012a-x 4m-bit cmos static ram 256k-word by 16-bit extended temperature operation preliminary data sheet document no. m14464ej1v0ds00 (1st edition) date published september 1999 ns cp (k) printed in japan the mark h h h h shows major revised points. description the m pd444012a-x is a high speed, low power, 4,194,304 bits (262,144 words by 16 bits) cmos static ram. the m pd444012a-x has two chip enable pins (/ce1, ce2) to extend the capacity. the m pd444012a-x is packed in 48-pin plastic tsop (i). features 262,144 words by 16 bits organization fast access time: 55, 70, 85, 100, 120, 150 ns (max.) byte data control: /lb (i/o1 - i/o8), /ub (i/o9 - i/o16) low voltage operation (b version: v cc = 2.7 to 3.6 v, c version: v cc = 2.2 to 3.6 v, d version: v cc = 1.8 to 3.6 v) operating ambient temperature: t a = C25 to +85 c output enable input for easy application two chip enable inputs: /ce1, ce2 part number access time operating supply operating ambient supply current ns (max.) voltage v temperature c at operating ma (max.) at standby m a (max.) at data retention m a (max.) m pd444012a-bxxx 55, 70, 85, 100 2.7 to 3.6 - 25 to +85 40 note 7tbd m pd444012a-cxxx 70, 85, 100, 120 2.2 to 3.6 40 m pd444012a-dxxx 100, 120, 150 1.8 to 3.6 note cycle time 3 70 ns. m pd444012a-b55x : tbd
preliminary data sheet m14464ej1v0ds00 2 m m m m pd444012a-x ordering information part number package access time ns (max.) operating supply voltage v operating temperature c remark m pd444012agy-b55x-mjh 48-pin plastic tsop (i) (12 18 mm) (normal bent) 55 2.7 to 3.6 - 25 to +85 b version m pd444012agy-b55x-mkh 48-pin plastic tsop (i) (12 18 mm) (reverse bent) m pd444012agy-b70x-mjh 48-pin plastic tsop (i) (12 18 mm) (normal bent) 70 m pd444012agy-b70x-mkh 48-pin plastic tsop (i) (12 18 mm) (reverse bent) m pd444012agy-b85x-mjh 48-pin plastic tsop (i) (12 18 mm) (normal bent) 85 m pd444012agy-b85x-mkh 48-pin plastic tsop (i) (12 18 mm) (reverse bent) m pd444012agy-b10x-mjh 48-pin plastic tsop (i) (12 18 mm) (normal bent) 100 m pd444012agy-b10x-mkh 48-pin plastic tsop (i) (12 18 mm) (reverse bent) m pd444012agy-c70x-mjh 48-pin plastic tsop (i) (12 18 mm) (normal bent) 70 2.2 to 3.6 c version m pd444012agy-c70x-mkh 48-pin plastic tsop (i) (12 18 mm) (reverse bent) m pd444012agy-c85x-mjh 48-pin plastic tsop (i) (12 18 mm) (normal bent) 85 m pd444012agy-c85x-mkh 48-pin plastic tsop (i) (12 18 mm) (reverse bent) m pd444012agy-c10x-mjh 48-pin plastic tsop (i) (12 18 mm) (normal bent) 100 m pd444012agy-c10x-mkh 48-pin plastic tsop (i) (12 18 mm) (reverse bent) m pd444012agy-c12x-mjh 48-pin plastic tsop (i) (12 18 mm) (normal bent) 120 m pd444012agy-c12x-mkh 48-pin plastic tsop (i) (12 18 mm) (reverse bent) m pd444012agy-d10x-mjh 48-pin plastic tsop (i) (12 18 mm) (normal bent) 100 1.8 to 3.6 d version m pd444012agy-d10x-mkh 48-pin plastic tsop (i) (12 18 mm) (reverse bent) m pd444012agy-d12x-mjh 48-pin plastic tsop (i) (12 18 mm) (normal bent) 120 m pd444012agy-d12x-mkh 48-pin plastic tsop (i) (12 18 mm) (reverse bent) m pd444012agy-d15x-mjh 48-pin plastic tsop (i) (12 18 mm) (normal bent) 150 m pd444012agy-d15x-mkh 48-pin plastic tsop (i) (12 18 mm) (reverse bent)
preliminary data sheet m14464ej1v0ds00 3 m m m m pd444012a-x pin configurations (marking side) /xxx indicates active low signal. 48-pin plastic tsop (i) (12 18 mm) (normal bent) [ m m m m pd444012agy-bxxx-mjh ] [ m m m m pd444012agy-cxxx-mjh ] [ m m m m pd444012agy-dxxx-mjh ] a15 a14 a13 a12 a11 a10 a9 a8 nc nc /we ce2 nc /ub /lb nc a17 a7 a6 a5 a4 a3 a2 a1 a16 nc gnd i/o16 i/o8 i/o15 i/o7 i/o14 i/o6 i/o13 i/o5 v cc i/o12 i/o4 i/o11 i/o3 i/o10 i/o2 i/o9 i/o1 /oe gnd /ce1 a0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a0 - a17 : address inputs i/o1 - i/o16 : data inputs / outputs /ce1, ce2 : chip enable 1, 2 /we : write enable /oe : output enable /lb, /ub : byte data select v cc : power supply gnd : ground nc : no connection
preliminary data sheet m14464ej1v0ds00 4 m m m m pd444012a-x 48-pin plastic tsop (i) (12 18 mm) (reverse bent) [ m m m m pd444012agy-bxxx-mkh ] [ m m m m pd444012agy-cxxx-mkh ] [ m m m m pd444012agy-dxxx-mkh ] a15 a14 a13 a12 a11 a10 a9 a8 nc nc /we ce2 nc /ub /lb nc a17 a7 a6 a5 a4 a3 a2 a1 a16 nc gnd i/o16 i/o8 i/o15 i/o7 i/o14 i/o6 i/o13 i/o5 v cc i/o12 i/o4 i/o11 i/o3 i/o10 i/o2 i/o9 i/o1 /oe gnd /ce1 a0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a0 - a17 : address inputs i/o1 - i/o16 : data inputs / outputs /ce1, ce2 : chip enable 1, 2 /we : write enable /oe : output enable /lb, /ub : byte data select v cc : power supply gnd : ground nc : no connection
preliminary data sheet m14464ej1v0ds00 5 m m m m pd444012a-x block diagram address buffer address buffer row decoder memory cell array 4,194,304 bits input data controller a0 a17 i/o9 - i/o16 sense / switch column decoder /ce1 /we /oe ce2 /ub /lb output data controller i/o1 - i/o8 v cc gnd
preliminary data sheet m14464ej1v0ds00 6 m m m m pd444012a-x truth table /ce1 ce2 /oe /we /lb /ub mode i/o supply current i/o1 - i/o8 i/o9 - i/o16 h not selected high impedance high impedance i sb l lhhh output disable high impedance high impedance i cca l h l l word read d out d out l h lower byte read d out high impedance h l upper byte read high impedance d out l l l word write d in d in l h lower byte write d in high impedance h l upper byte write high impedance d in h h not selected high impedance high impedance i sb note note /ce1, ce2 = v ih or v il remark : dont care
preliminary data sheet m14464ej1v0ds00 7 m m m m pd444012a-x electrical specifications absolute maximum ratings parameter symbol condition rating unit supply voltage v cc C0.5 note to +4.0 v input / output voltage v t C0.5 note to v cc + 0.4 (4.0 v max.) v operating ambient temperature t a C25 to +85 c storage temperature t stg C55 to +125 c note C3.0 v (min.) (pulse width : 30 ns) caution exposing the device to stress above those listed in absolute maximum rating could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol condition m pd444012a-bxxx m pd444012a-cxxx m pd444012a-dxxx unit min. max. min. max. min. max. supply voltage v cc 2.7 3.6 2.2 3.6 1.8 3.6 v high level input voltage v ih 2.7 v v cc 3.6 v 2.4 v cc +0.4 2.4 v cc +0.4 2.4 v cc +0.4 v 2.2 v v cc < 2.7 v C C 2.0 v cc +0.3 2.0 v cc +0.3 1.8 v v cc < 2.2 vCCCC1.6v cc +0.2 low level input voltage v il C0.3 note +0.5 C0.3 note +0.3 C0.3 note +0.2 v operating ambient temperature t a C25 +85 C25 +85 C25 +85 c note C1.5 v (min.) (pulse width: 30 ns) capacitance (t a = 25 c, f = 1 mhz) parameter symbol test condition min. typ. max. unit input capacitance c in v in = 0 v 8 pf input / output capacitance c i/o v i/o = 0 v 10 pf remarks 1. v in : input voltage 2. these parameters are periodically sampled and not 100% tested.
preliminary data sheet m14464ej1v0ds00 8 m m m m pd444012a-x dc characteristics (recommended operating conditions unless otherwise noted) parameter symbol test condition v cc 3 2.7 v v cc 3 2.2 v v cc 3 1.8 v unit m pd444012a-bxxx m pd444012a-cxxx m pd444012a-dxxx min. typ. max. min. typ. max. min. typ. max. input leakage i li v in = 0 v to v cc C1.0 +1.0 C1.0 +1.0 C1.0 +1.0 m a current i/o leakage i lo v i/o = 0 v to v cc , /ce1 = v ih or C1.0 +1.0 C1.0 +1.0 C1.0 +1.0 m a current ce2 = v il or /we = v il or /oe = v ih operating i cca1 /ce1 = v il , ce2 = v ih ,C40 note C40 C40ma supply current minimum cycle time, v cc 2.7 v C C C 38 C 38 i i/o = 0 ma v cc 2.2 v C C C C C 35 i cca2 /ce1 = v il , ce2 = v ih , C 10 C 10 C 10 i i/o = 0 ma v cc 2.7 v C C C 8 C 8 v cc 2.2 v C C C C C 6 i cca3 /ce1 0.2 v, ce2 3 v cc C 0.2 v, C 8 C 8 C 8 cycle = 1 mhz, i i/o = 0 ma, v il 0.2 v, v cc 2.7 v C C C 6 C 6 v ih 3 v cc C 0.2 v v cc 2.2 v C C C C C 6 standby i sb /ce1 = v ih or ce2 = v il or C 1.2 C 1.2 C 1.2 ma supply current /lb = /ub = v ih ,v cc 2.7 v C C C 1.2 C 1.2 /ce1, ce2 = v ih or v il v cc 2.2 v C C C C C 1.2 i sb1 /ce1 3 v cc - 0.2 v, 0.5 7 0.5 7 0.5 7 m a ce2 3 v cc - 0.2 v v cc 2.7 v C C 0.4 6 0.4 6 v cc 2.2 v C C C C 0.3 5 i sb2 ce2 0.2 v 0.5 7 0.5 7 0.5 7 v cc 2.7 v C C 0.4 6 0.4 6 v cc 2.2 v C C C C 0.3 5 i sb3 /lb = /ub 3 v cc - 0.2 v, 0.5 7 0.5 7 0.5 7 /ce1 0.2 v, v cc 2.7 v C C 0.4 6 0.4 6 ce2 3 v cc - 0.2 v v cc 2.2 v C C C C 0.3 5 high level v oh i oh = C0.5 ma 2.4 2.4 2.4 v output voltage v cc 2.7 v C 1.8 1.8 v cc 2.2 v C C 1.5 low level v ol i ol = 1.0 ma 0.4 0.4 0.4 v output voltage note cycle time 3 70 ns. m pd444012a-b55x : tbd remarks 1. v in : input voltage 2. these dc characteristics are in common regardless of package types and access time.
preliminary data sheet m14464ej1v0ds00 9 m m m m pd444012a-x ac characteristics (recommended operating conditions unless otherwise noted) ac test conditions [ m m m m pd444012a-b55x, m m m m pd444012a-b70x, m m m m pd444012a-b85x, m m m m pd444012a-b10x ] input waveform (rise and fall time 5 ns) test points 0.5 v 2.4 v 1.5 v 1.5 v output waveform test points 1.5 v 1.5 v output load 1ttl + 50 pf [ m m m m pd444012a-c70x, m m m m pd444012a-c85x, m m m m pd444012a-c10x, m m m m pd444012a-c12x ] input waveform (rise and fall time 5 ns) test points 0.3 v 2.0 v 1.1 v 1.1 v output waveform test points 1.1 v 1.1 v output load 1ttl + 30 pf [ m m m m pd444012a-d10x, m m m m pd444012a-d12x, m m m m pd444012a-d15x ] input waveform (rise and fall time 5 ns) test points 0.2 v 1.6 v 0.9 v 0.9 v output waveform test points 0.9 v 0.9 v output load 1ttl + 30 pf
preliminary data sheet m14464ej1v0ds00 10 m m m m pd444012a-x read cycle (1/3) (b version) parameter symbol v cc 3 2.7 v unit condition m pd444012a m pd444012a m pd444012a m pd444012a -b55x -b70x -b85x -b10x min. max. min. max. min. max. min. max. read cycle time t rc 55 70 85 100 ns address access time t aa 55 70 85 100 ns note 1 /ce1 access time t co1 55 70 85 100 ns ce2 access time t co2 55 70 85 100 ns /oe to output valid t oe 30 35 40 50 ns /lb, /ub to output valid t ba 55 70 85 100 ns output hold from address change t oh 10 10 10 10 ns /ce1 to output in low impedance t lz1 10 10 10 10 ns note 2 ce2 to output in low impedance t lz2 10 10 10 10 ns /oe to output in low impedance t olz 5555ns /lb, /ub to output in low impedance t blz 10 10 10 10 ns /ce1 to output in high impedance t hz1 20 25 30 35 ns ce2 to output in high impedance t hz2 20 25 30 35 ns /oe to output in high impedance t ohz 20 25 30 35 ns /lb, /ub to output in high impedance t bhz 20 25 30 35 ns notes 1. the output load is 1ttl + 50 pf. 2. the output load is 1ttl + 5 pf. remark these ac characteristics are in common regardless of package types. read cycle (2/3) (c version) parameter symbol v cc 3 2.2 v unit condition m pd444012a m pd444012a m pd444012a m pd444012a -c70x -c85x -c10x -c12x min. max. min. max. min. max. min. max. read cycle time t rc 70 85 100 120 ns address access time t aa 70 85 100 120 ns note 1 /ce1 access time t co1 70 85 100 120 ns ce2 access time t co2 70 85 100 120 ns /oe to output valid t oe 35 40 50 60 ns /lb, /ub to output valid t ba 70 85 100 120 ns output hold from address change t oh 10 10 10 10 ns /ce1 to output in low impedance t lz1 10 10 10 10 ns note 2 ce2 to output in low impedance t lz2 10 10 10 10 ns /oe to output in low impedance t olz 5555ns /lb, /ub to output in low impedance t blz 10 10 10 10 ns /ce1 to output in high impedance t hz1 25 30 35 40 ns ce2 to output in high impedance t hz2 25 30 35 40 ns /oe to output in high impedance t ohz 25 30 35 40 ns /lb, /ub to output in high impedance t bhz 25 30 35 40 ns notes 1. the output load is 1ttl + 30 pf. 2. the output load is 1ttl + 5 pf. remark these ac characteristics are in common regardless of package types.
preliminary data sheet m14464ej1v0ds00 11 m m m m pd444012a-x read cycle (3/3) (d version) parameter symbol v cc 3 1.8 v unit condition m pd444012a m pd444012a m pd444012a -d10x -d12x -d15x min. max. min. max. min. max. read cycle time t rc 100 120 150 ns address access time t aa 100 120 150 ns note 1 /ce1 access time t co1 100 120 150 ns ce2 access time t co2 100 120 150 ns /oe to output valid t oe 50 60 70 ns /lb, /ub to output valid t ba 100 120 150 ns output hold from address change t oh 10 10 10 ns /ce1 to output in low impedance t lz1 10 10 10 ns note 2 ce2 to output in low impedance t lz2 10 10 10 ns /oe to output in low impedance t olz 555ns /lb, /ub to output in low impedance t blz 10 10 10 ns /ce1 to output in high impedance t hz1 35 40 50 ns ce2 to output in high impedance t hz2 35 40 50 ns /oe to output in high impedance t ohz 35 40 50 ns /lb, /ub to output in high impedance t bhz 35 40 50 ns notes 1. the output load is 1ttl + 30 pf. 2. the output load is 1ttl + 5 pf. remark these ac characteristics are in common regardless of package types. read cycle timing chart t hz2 t rc t oh t hz1 t blz t ba t lz2 t co2 t lz1 t co1 t bhz t aa high impedance data out /lb, /ub (input) ce2 (input) /ce1 (input) address (input) i/o (output) t olz t oe t ohz /oe (input) remark in read cycle, /we should be fixed to high level.
preliminary data sheet m14464ej1v0ds00 12 m m m m pd444012a-x write cycle (1/3) (b version) parameter symbol v cc 3 2.7 v unit condition m pd444012a m pd444012a m pd444012a m pd444012a -b55x -b70x -b85x -b10x min. max. min. max. min. max. min. max. write cycle time t wc 55 70 85 100 ns /ce1 to end of write t cw1 50 55 70 80 ns ce2 to end of write t cw2 50 55 70 80 ns /lb, /ub to end of write t bw 50 55 70 80 ns address valid to end of write t aw 50 55 70 80 ns address setup time t as 0000ns write pulse width t wp 45 50 55 60 ns write recovery time t wr 0000ns data valid to end of write t dw 25 30 35 40 ns data hold time t dh 0000ns /we to output in high impedance t whz 20 25 30 35 ns note output active from end of write t ow 5555ns note the output load is 1ttl + 5 pf. remark these ac characteristics are in common regardless of package types. write cycle (2/3) (c version) parameter symbol v cc 3 2.2 v unit condition m pd444012a m pd444012a m pd444012a m pd444012a -c70x -c85x -c10x -c12x min. max. min. max. min. max. min. max. write cycle time t wc 70 85 100 120 ns /ce1 to end of write t cw1 55 70 80 100 ns ce2 to end of write t cw2 55 70 80 100 ns /lb, /ub to end of write t bw 55 70 80 100 ns address valid to end of write t aw 55 70 80 100 ns address setup time t as 0000ns write pulse width t wp 50 55 60 85 ns write recovery time t wr 0000ns data valid to end of write t dw 30 35 40 60 ns data hold time t dh 0000ns /we to output in high impedance t whz 25 30 35 40 ns note output active from end of write t ow 5555ns note the output load is 1ttl + 5 pf. remark these ac characteristics are in common regardless of package types.
preliminary data sheet m14464ej1v0ds00 13 m m m m pd444012a-x write cycle (3/3) (d version) parameter symbol v cc 3 1.8 v unit condition m pd444012a m pd444012a m pd444012a -d10x -d12x -d15x min. max. min. max. min. max. write cycle time t wc 100 120 150 ns /ce1 to end of write t cw1 80 100 120 ns ce2 to end of write t cw2 80 100 120 ns /lb, /ub to end of write t bw 80 100 120 ns address valid to end of write t aw 80 100 120 ns address setup time t as 000ns write pulse width t wp 60 85 100 ns write recovery time t wr 000ns data valid to end of write t dw 40 60 80 ns data hold time t dh 000ns /we to output in high impedance t whz 35 40 50 ns note output active from end of write t ow 555ns note the output load is 1ttl + 5 pf. remark these ac characteristics are in common regardless of package types.
preliminary data sheet m14464ej1v0ds00 14 m m m m pd444012a-x write cycle timing chart 1 (/we controlled) t wc t cw1 t bw t whz t dw t dh t ow indefinite data out high impe- dance high impe- dance data in indefinite data out address (input) /ce1 (input) /lb, /ub (input) i/o (input / output) ce2 (input) t cw2 t aw t wp t as t wr /we (input) cautions 1. during address transition, at least one of pins /ce1, ce2, /we should be inactivated. 2. when i/o pins are in the output state, do not apply to the i/o pins signals that are opposite in phase with output signals. remarks 1. write operation is done during the overlap time of a low level /ce1, /we, /lb and/or /ub, and a high level ce2. 2. if /ce1 changes to low level at the same time or after the change of /we to low level, or if ce2 changes to high level at the same time or after the change of /we to low level, the i/o pins will remain high impedance state. 3. when /we is at low level, the i/o pins are always high impedance. when /we is at high level, read operation is executed. therefore /oe should be at high level to make the i/o pins high impedance.
preliminary data sheet m14464ej1v0ds00 15 m m m m pd444012a-x write cycle timing chart 2 (/ce1 controlled) t wc t as t cw1 t dw t dh data in high impedance address (input) /ce1 (input) /lb, /ub (input) i/o (input) high impedance ce2 (input) t cw2 t aw t wp t wr /we (input) t bw cautions 1. during address transition, at least one of pins /ce1, ce2, /we should be inactivated. 2. when i/o pins are in the output state, do not apply to the i/o pins signals that are opposite in phase with output signals. remark write operation is done during the overlap time of a low level /ce1, /we, /lb and/or /ub, and a high level ce2.
preliminary data sheet m14464ej1v0ds00 16 m m m m pd444012a-x write cycle timing chart 3 (ce2 controlled) t wc t as t cw2 t bw t dw t dh data in high impedance address (input) ce2 (input) /lb, /ub (input) i/o (input) high impedance /ce1 (input) t cw1 t aw t wp t wr /we (input) cautions 1. during address transition, at least one of pins /ce1, ce2, /we should be inactivated. 2. when i/o pins are in the output state, do not apply to the i/o pins signals that are opposite in phase with output signals. remark write operation is done during the overlap time of a low level /ce1, /we, /lb and/or /ub, and a high level ce2.
preliminary data sheet m14464ej1v0ds00 17 m m m m pd444012a-x write cycle timing chart 4 (/lb, /ub controlled) t wc t dw t dh data in high impedance address (input) /lb, /ub (input) i/o (input) high impedance ce2 (input) t cw2 t aw t wp t wr /we (input) t as t bw /ce1 (input) t cw1 cautions 1. during address transition, at least one of pins /ce1, ce2, /we should be inactivated. 2. when i/o pins are in the output state, do not apply to the i/o pins signals that are opposite in phase with output signals. remark write operation is done during the overlap time of a low level /ce1, /we, /lb and/or /ub, and a high level ce2.
preliminary data sheet m14464ej1v0ds00 18 m m m m pd444012a-x low v cc data retention characteristics (t a = C25 to +85 c) parameter symbol test condition v cc 3 2.7 v v cc 3 2.2 v v cc 3 1.8 v unit m pd444012a -b x m pd444012a -c x m pd444012a -d x min. typ. max. min. typ. max. min. typ. max. data retention supply voltage v ccdr1 /ce1 3 v cc - 0.2 v, ce2 3 v cc - 0.2 v 1.0 3.6 1.0 3.6 1.0 3.6 v v ccdr2 ce2 0.2 v 1.0 3.6 1.0 3.6 1.0 3.6 v ccdr3 /lb = /ub 3 v cc - 0.2 v, /ce1 0.2 v, ce2 3 v cc - 0.2 v 1.0 3.6 1.0 3.6 1.0 3.6 data retention supply current i ccdr1 v cc = 1.0 v, /ce1 3 v cc - 0.2 v, ce2 3 v cc - 0.2 v or ce2 0.2 v tbd tbd tbd tbd tbd tbd m a i ccdr2 v cc = 1.0 v, ce2 0.2 v tbd tbd tbd tbd tbd tbd i ccdr3 v cc = 1.0 v, /lb = /ub 3 v cc - 0.2 v, /ce1 0.2 v, ce2 3 v cc - 0.2 v tbd tbd tbd tbd tbd tbd chip deselection to data retention mode t cdr 000ns operation recovery time t r t rc note t rc note t rc note ns note t rc : read cycle time
preliminary data sheet m14464ej1v0ds00 19 m m m m pd444012a-x data retention timing chart (1) /ce1 controlled v ih (min.) v ccdr (min.) v il (max.) v cc /ce1 /ce1 3 v cc C 0.2 v gnd 3.0 v v cc (min.) note t cdr data retention mode t r note b version : 2.7 v, c version : 2.2 v, d version : 1.8 v remark on the data retention mode by controlling /ce1, the input level of ce2 must be 3 v cc - 0.2 v or 0.2 v. the other pins (address, i/o, /we, /oe, /lb, /ub) can be in high impedance state. (2) ce2 controlled 3.0 v v ih (min.) v ccdr (min.) v il (max.) v cc ce2 ce2 0.2 v gnd v cc (min.) note t cdr data retention mode t r note b version : 2.7 v, c version : 2.2 v, d version : 1.8 v remark the other pins (/ce1, address, i/o, /we, /oe, /lb, /ub) can be in high impedance state.
preliminary data sheet m14464ej1v0ds00 20 m m m m pd444012a-x (3) /lb, /ub controlled t cdr data retention mode v ih (min.) v ccdr (min.) v il (max.) t r v cc /lb, /ub /lb, /ub 3 v cc C 0.2 v gnd 3.0 v v cc (min.) note note b version : 2.7 v, c version : 2.2 v, d version : 1.8 v remark on the data retention mode by controlling /lb and /ub, the input level of /ce1 and ce2 must be 3 v cc - 0.2 v or 0.2 v. the other pins (address, i/o, /we, /oe) can be in high impedance state.
preliminary data sheet m14464ej1v0ds00 21 m m m m pd444012a-x package drawings notes 48-pin plastic tsop( i ) (12x18) item millimeters a b c e i 12.0 0.1 0.5 (t.p.) 0.1 0.05 0.45 max. k 1.2 max. 16.4 0.1 0.145 0.05 f 0.10 m d 0.22 0.05 1. each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition. 2. "a" excludes mold flash. (includes mold flash : 12.4 mm max.) r k l 1.0 0.05 g l 0.5 0.10 n p 18.0 0.2 q3 + 5 - 3 0.25 r s48gy-50-mjh1-1 s 0.60 0.15 j 0.8 0.2 s q s n e g f j detail of lead end c d m m b a i p 1 24 48 25 s
preliminary data sheet m14464ej1v0ds00 22 m m m m pd444012a-x 0.145 0.05 notes 48-pin plastic tsop( i ) (12x18) item millimeters a b c e i 12.0 0.1 0.5 (t.p.) 0.1 0.05 0.45 max. k 1.2 max. 16.4 0.1 f 0.10 m d 0.22 0.05 1. each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition. 2. "a" excludes mold flash. (includes mold flash : 12.4 mm max.) c b r k d m m 1.0 0.05 g l 0.5 0.10 n p 18.0 0.2 q3 + 5 - 3 0.25 r s48gy-50-mkh1-1 s 0.60 0.15 j 0.8 0.2 s n j g f l s q e detail of lead end 1 24 48 25 s a i p
preliminary data sheet m14464ej1v0ds00 23 m m m m pd444012a-x recommended soldering conditions please consult with our sales offices for soldering conditions of the m pd444012a-x. types of surface mount device m pd444012agy-bxxx-mjh: 48-pin plastic tsop (i) (12 18 mm) (normal bent) m pd444012agy-bxxx-mkh: 48-pin plastic tsop (i) (12 18 mm) (reverse bent) m pd444012agy-cxxx-mjh: 48-pin plastic tsop (i) (12 18 mm) (normal bent) m pd444012agy-cxxx-mkh: 48-pin plastic tsop (i) (12 18 mm) (reverse bent) m pd444012agy-dxxx-mjh: 48-pin plastic tsop (i) (12 18 mm) (normal bent) m pd444012agy-dxxx-mkh: 48-pin plastic tsop (i) (12 18 mm) (reverse bent)
preliminary data sheet m14464ej1v0ds00 24 m m m m pd444012a-x [ memo ]
preliminary data sheet m14464ej1v0ds00 25 m m m m pd444012a-x [ memo ]
preliminary data sheet m14464ej1v0ds00 26 m m m m pd444012a-x [ memo ]
preliminary data sheet m14464ej1v0ds00 27 m m m m pd444012a-x notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
m m m m pd444012a-x the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7 98. 8

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