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linkswitch design guide application note AN-35 april 2003 introduction integrated switching power supply technology, offering small size, low weight and universal ac input voltage operation, has finally evolved to cost-effectively replace linear transformer- based power supplies for low power applications. linkswitch reduces the cost of switching battery chargers and ac adapters to the level of linear transformer power supplies. linkswitch also easily meets standby and no-load energy consumption guidelines specified by worldwide regulatory programs such as the usa s presidential 1 w standby executive order and the european commission s 2005 requirement for 300 mw no-load consumption. the feature set of linkswitch offers the following advantages over other solutions: ? lowest cost and component count for a constant voltage, constant current (cv/cc) solution ? extremely simple circuit only 14 components required for a production-worthy design ? primary based cv/cc solution eliminates 10 to 20 components for low system cost ? up to 75% lighter power supply reduces shipping costs ? fully integrated auto-restart for short circuit and open loop fault protection ? 42 khz operation simplifies emi filter design ? 3 w output with ee13 core for low cost and small size linkswitch is designed to produce an approximate cv/cc output characteristic as shown in figure 2. in charger applications, a discharged battery operates on the cc portion of the curve until almost fully charged and then naturally transitions to the cv portion of the curve. below an output voltage of approximately 2 v (consistent with a failed battery pack), the supply enters auto-restart, reducing the average output current to approximately 8% of nominal. in an ac adapter, normal operation occurs only on the cv portion of the curve, the cc portion providing overload protection and auto-restart short circuit protection. linkswitch is a fixed frequency pwm controlled device, designed to operate with flyback converters in discontinuous mode. in the cv portion of the curve, the device operates using voltage mode control and changes to a current limit mode during the cc portion of the curve. total system cv accuracy is typically 10% at the peak power point, including all device tolerances and line input voltage variations. with transformer primary inductance variations within 10%, the total system cc accuracy is typically 20% (lnk501) or 25% (lnk500) compared to nominal values. during cv operation, the reflected output voltage (v or ) controls the duty cycle. linkswitch is placed in the high side rail, as shown in figure 1, such that v or can be sensed directly, requiring no additional subtraction of the input voltage component. figure 1. key parameters for an initial linkswitch design. pi-2957-081602 linkswitch v rcable v dout v rsec r sec 0.15 ? r cable 0.3 ? d out 0.7 v/ 1.1 v s d c i o load v o v sec c out n p :n s v or v leak r lf 100 ? d clamp 1n4937 i sec(rms) 2 x i o i sec(peak) 4 x i o v fb c clamp 0.1 f, 100 v c cp 0.22 f/1 f, 10 v u1 i dct r fb ac input + + + + c1+c2 3 f/w or 1 f/w rf1 10 ? fusible d1-d4 in4005 1 a, 600 v l1 680 h - 2.2 mh, 80 ma rms + + + + ~ ~ ~ ~ l p
AN-35 2 b 4/03 during cc operation, duty cycle is controlled by the peak drain current limit (i lim ). the device current limit is designed to be a function of reflected voltage such that the load current remains approximately constant as the load impedance is reduced. when the output voltage falls to approximately 30% of nominal value (normally associated with a failed battery), linkswitch enters the auto-restart mode of operation to safely limit average fault current (typically 8% of i o ). with discontinuous mode design, maximum output power is independent of input voltage and is a simple function of primary inductance, peak primary current squared and switching frequency (equation 6). linkswitch controls and cancels out variations normally associated with frequency and peak current by specifying a device i 2 f term. this allows users to easily design for a specific corner point where cv mode transitions to cc mode. scope this application note is for engineers designing an ac-dc power supply using the linkswitch lnk500 or lnk501 devices in a discontinuous mode flyback converter. since linkswitch is designed to replace linear transformer based power supplies, the output characteristic provides an approximate cv characteristic, offering much better line and load regulation than an equivalent linear transformer. the very simple nature of the linkswitch circuit allows an initial paper design to be completed quickly using simple design equations. it is then recommended that the circuit performance be tuned with a prototype power supply to finalize external component choices. this document therefore highlights the key design parameters and provides expressions to calculate the transformer turns ratio, primary inductance and clamp/feedback component values. this enables designers to build an operating prototype and iterate to reach the final design. for readers who want to generate a design as quickly as possible, the quick start section provides enough information to generate an initial prototype. this document does not address transformer construction. please see linkswitch dak engineering prototype report for examples showing typical transformer construction techniques. further details of support tools and updates to this document can be found at www.powerint.com . cv/cc circuit design the linkswitch circuit shown in figure 3 serves as a cv/cc charger example to illustrate design techniques. nominal output voltage is 5.5 v and nominal cc output current is 500 ma. linkswitch design methodology is very simple. transformer turns ratios and bias component values are selected at the figure 1 shows the key parameters and components needed to generate an initial linkswitch design. where initial estimates can be used, they are shown below the parameter they refer to. 1) let v or equal 50 v. 2) define the transformer turns ratio according to equation 5. if no better estimates or measure- ments are available, then let v dout equal 0.7 v for a schottky or 1.1 v for a pn diode, r cable equal 0.3 ? , r sec equal 0.15 ? , i sec(rms) equal 2 x i o , and i sec(peak) equal 4 x i o , where i o is the desired cc output current and v o is the desired output voltage at the cv/cc transition point. 3) calculate p o(eff) according to equation 13. as an initial estimate for p core use 0.1 w. 4) calculate l p according to equation 14 and other transformer parameters from equations 15, 16, 17, 18 and 19. 5) calculate value for feedback resistor r fb accord- ing to equations 20, 21, 22, 23 and 24. this should be a 1/4 w, 1% part. 6) set clamp capacitor c clamp as a 0.1 f, 100 v metalized plastic film type. 7) set clamp resistor r lf as 100 ? , 1/4 w. 8) set control pin capacitor c cp to be 0.22 f, 10 v for battery loads or 1 f, 10 v for resistive loads. 9) select input and output components. see figure 3 and relevant sections. 10) construct prototype. 11) iterate design (see hints and tips section). quick start nominal peak power point output voltage v o , while transformer primary inductance is calculated from the total output power. few components require computations, while the balance are selected from the included recommendations. design and selection criteria for each component are described starting with the transformer. once set, transformer parameters and behavior are used to design clamp, bias and feedback components for proper supply operation. output capacitors and the input circuitry can then be determined.
AN-35 3 b 4/03 the value for i pri(peak) is equal to the typical value of the linkswitch data sheet parameter i lim . as an initial estimate the i sec(peak) can be approximated as 4 x i o . once the first prototype has been built this can be refined as the final turns ratio is known or alternatively, the peak diode forward voltage can be measured directly using an oscilloscope. the transformer turns ratio is given by: if no better estimates or measurements are available, use 0.15 ? as an initial value for the transformer secondary winding resistance r sec , 0.7 v for the forward voltage (v dout ) of a schottky diode or 1.1 v for a pn diode and 0.3 ? for the cable resistance r cable . figure 2. typical output characteristic for linkswitch based 5.5 v, 0.5 a charger with specification limits. transformer t1 transformer design begins by selecting the reflected output voltage (v or ). for most linkswitch designs, v or should be between 40 v and 60 v. a good starting point is 50 v allowing for optimization later. v or values over 60 v are recommended only for those applications allowed to consume over 300 mw at no-load. to calculate the transformer turns ratio, the voltage required across the secondary winding v sec is first calculated. this is a function of output cable voltage drop v rcable , nominal output voltage v o , the secondary winding voltage drop v rsec , and output diode forward voltage drop v dout . figure 1 shows the sources of secondary side voltage drops. since c clamp charges to the peak value of v or plus an error due to leakage inductance, the value of v rsec and v dout are defined at the peak secondary current. the output cable drop v rcable is defined at the nominal cc output current i o . curves of v dout versus instantaneous current can be found in the diode manufacturer s data sheet. peak secondary current is defined as: ii n n sec peak pri peak p s () () = (1) (2) (3) (4) (5) n n v v p s or sec = 100 0 200 300 400 500 600 700 output current (ma) output voltage (v) 0 1 2 3 4 5 6 7 8 9 10 115 vac 230 vac limits (lnk501) limits (lnk500) auto-restart pi-2956-032403 vir vi r vvv v v rcable o cable rsec sec peak sec sec o rcable dout rsec = = =+ + + ()
AN-35 4 b 4/03 the sum of actual output power p o and the following loss terms: cable power p cable , diode power p diode , bias power p bias (the power required to drive the linkswitch control pin), transformer secondary copper loss p s(cu) , and transformer core loss p core . r cable is the total cable dc resistance, i o is the nominal cc output current, v dout is output diode forward voltage drop, v or is reflected output voltage, i sec(rms) is secondary rms current, r sec is output winding dc resistance, v e is core effective volume and k core is core loss per unit volume. as before, if no better estimates or measurements are available, use 0.15 ? for r sec , 0.7 v for the forward voltage (v dout ) of a schottky diode or 1.1 v for a pn diode, 0.3 ? for r cable and i sec(peak) equal to 4 x i o . both v e and k core can be read from the ferrite core manufacturer s material curves. to find k core , use the core flux swing b m . in discontinuous mode operation, ac flux density b ac is equal to b m : the next transformer design step is to calculate the nominal primary inductance l p . l p tolerance should be within 10% (to meet peak power cc tolerance of 20% for lnk501, 25% for lnk500). the simple linkswitch feedback circuit is designed specifically for discontinuous mode operation. continuous mode designs result in control loop instability and are therefore not recommended. for proper cc operation, the linkswitch transformer must therefore be designed for discontinuous operation under all line/load conditions. at the peak power point, the power processed by the core or p o(eff) is given by: l p is the nominal transformer primary inductance, i p is equal to the linkswitch parameter i lim and f s is the switching frequency. note that i p and f s are enclosed in brackets as the linkswitch data sheet specifies an i 2 f coefficient equal to the i 2 product, normalized to i dct . by normalizing to i dct (the control pin current at 30% duty cycle), the effect of i dct tolerance is included and does not need to be considered separately. output power is therefore dependent primarily on transformer primary inductance tolerance (typically 10% for low cost high volume production methods). as shown above, effective output power p o(eff) is calculated from the total energy stored in the transformer and is therefore figure 3. example schematic for a typical linkswitch charger. (12) plif o eff p p s () = [] 1 2 2 (6) (10) (11) (7) (8) (9) bb ac m = p f s pri pvi pv ma cable cable o diode dout o bias or = = = 2 23 . p kv pi r core core e s cu sec rms sec = = 2 2 () ( ) c1 4.7 f 400 v c2 4.7 f 400 v rf1 10 ? 1 w fusible l1 1 mh r1 20.5 k ? 1% r2 100 ? d5 1n4937 c4 0.1 f 100 v 116 t #34 awg ee13 l p = 2.55 mh 15 t #30 awg tiw 3 4 1 5 t1 6 d6 11dq06 c5 470 f 10 v 85-265 vac u1 linkswitch 5.5 v, 500 ma rtn br1 1 a, 600 v pi-3476-032403 performance summary output power: 2.75 w efficiency: 72% no load consumption: 260 mw, 230 vac 200 mw, 115 vac c3 0.22 f 50 v d s c
AN-35 5 b 4/03 once an estimate for the number of secondary turns n s has been made, the primary turns is found from: at this point the core size should be selected. common core sizes suitable for a linkswitch design include ee13, ef12.6, ee16 and ef16. with the core selected and the number of transformer turns known, the core peak flux density b p (gauss) can be found using the effective cross sectional area of the core a e (cm 2 ), the primary inductance ( h) and the linkswitch peak current limit i lim(max) (a): b p should be in the range of 3000 gauss to 3500 gauss (300 mt to 350 mt). the relative permeability r of the ungapped core must be calculated to estimate the gap length l g . the relative permeability, r is found from core parameters a e (cm 2 ), the effective core path length l e (cm), and ungapped effective inductance a l (nh/t 2 ): gap length l g is the air gap ground into the center leg of the transformer core. grinding tolerances and a l accuracy place a minimum limit of approximately 0.08 mm on l g . if l g is smaller than this then either the core size (a e ) or n p must be increased. l g (mm) is calculated from primary turns n p , core effective pppppp p o eff o cable diode bias s cu core () =+ + + + + () 2 (13) (14) (15) pi-3148-081502 flux density (mt) 100 80 area compensated by ? l term 250 330 primary inductance (%) l p if p nom o eff ps l () = [] () 2 2 ? r le e al a = 04 10 . (16) (17) figure 4. typical reduction in primary inductance with flux density for small e cores with small gap sizes. n v v n p or sec s = the division by two in the expression for p core is required since a flyback transformer only excites the core asymmetrically and the core loss curves are typically specified assuming a symmetrical excitation. k core is then read directly from material core loss curves at the linkswitch switching frequency (typically 42 khz). a figure for b m of approximately 3300 gauss (330 mt) is a good initial estimate. a figure for p core of 0.1 w is a good initial estimate. p o(eff) is calculated from: p o here is defined as the output power seen by the load. note the core loss term is divided in half as only the loss associated with transferring energy to the output during the off time needs to be compensated for in the primary inductance value. nominal primary inductance l p(nom) is calculated from: the typical data sheet value for the i 2 f coefficient should be used to replace i 2 f s , this defining the nominal primary inductance at the nominal output peak power point. as the flux density increases, the inductance falls slightly due to the bh characteristic of the core material as shown in figure 4. this drop in inductance is compensated by increasing the inductance at zero flux density by a factor ? l . this is typically in the range of 1 to 1.05 for common low cost ferrite materials. this effect can be minimized by increasing the gap size, reducing the flux density or using ferrite materials with a higher saturation flux density. transformer inductance tolerance is most affected by the transformer core gap length. inductance must also be stable over temperature and as a function of current. recommended minimum gap length is 0.08 mm (3.2 mils) at a peak flux density of 3300 gauss to 3500 gauss (330 mt to 350 mt). the number of secondary turns for small e cores is typically 2 to 3 turns per volt across the secondary winding (including cable, secondary and diode voltage drops). the actual number is adjusted to meet gap size and flux density limits. p b il na p lim max p pe = 100 ()
AN-35 6 b 4/03 the secondary diode peak voltage was measured as 0.7 v, the secondary winding resistance as 0.15 ? and the cable resistance as 0.23 ? . therefore v sec is defined as: voltage v sec allows the exact v or to be calculated: resistor r fb , a 1%, 0.25 w resistor, converts clamp voltage to linkswitch bias and control current. feedback voltage v fb is calculated from v or and the error due to leakage inductance, v leak . the value for v leak varies depending on the value of leakage inductance, the size of the clamp capacitor and the type of clamp diode selected. for a leakage inductance of 50 h, a value of 5 v is a good initial estimate. once a prototype has been constructed, the value of v fb can be found directly, by measuring the voltage across c clamp at the power supply peak output power point, using a battery powered digital voltmeter. these have sufficient common mode rejection to be unaffected by the switching waveform and provide accurate results. the voltage measured is v fb . by subtracting v or the value for v leak can be determined, useful as an estimate in future designs. for the design in figure 3, v fb was measured as 56.7 v, giving v leak as 5.6 v. an initial value for r fb is calculated from the feedback voltage v fb , the control pin voltage v c(idct) and current i dct at the cc/cv transition point, specified in the linkswitch data sheet. cross sectional area a e (cm 2 ), primary inductance l p ( h), core effective path length l e (cm) and relative permeability r : the gapped effective inductance a lg (nh/t 2 ), required by the transformer manufacturer, is calculated from the primary inductance l p ( h) and the number of primary turns n p : clamp, bias, bypass and feedback an rcd clamp, formed by r fb , c clamp , and d clamp (figure 1), safely limits transformer primary voltage, due to transformer leakage inductance, to below the linkswitch internal mosfet breakdown voltage bv dss each time linkswitch turns off. leading-edge voltage spikes (caused by transformer leakage inductance) are filtered by r lf and c clamp , such that c clamp effectively charges to the transformer reflected voltage. feedback is derived from the reflected voltage, that approximates closely the transformer secondary winding output voltage (v sec in figure 1) multiplied by the transformer turns ratio. due to effects of leakage inductance (causing peak charging), calculated v or may be slightly different from actual voltage measured across c clamp . since linkswitch is in the upper rail, reflected voltage information is now relative to the linkswitch source pin and independent of the input voltage. reflected voltage is directly converted by r fb to linkswitch control pin current for duty cycle control and bias. the control pin capacitor c cp provides bypass filtering, control loop compensation, and the energy storage required during start-up and auto-restart. feedback resistor (r fb ) clamp and feedback circuit design begins by first considering reflected voltage. using the schematic in figure 3 as an example. with primary turns n p = 116 and secondary turns n s = 15 the peak secondary current can be calculated from equation 20, where i pri(peak) is equal to the linkswitch typical current limit i lim(typ) . (20) (22) a l n lg p p = 1000 2 (18) (19) l na l l g pe p e r = ? ? ? ? ? ? ? 04 100 10 2 . (21) (23) v n n v v v or p s sec = = = 116 15 661 51 1 . . vvv fb or leak =+ i n n i a sec peak p s pri peak () () . . = = = 116 15 0 254 196 vvvvv vir v ir va v a v sec o rcable dout rsec o o cable dout sec peak sec =+ ++ =+ + + =+ + + = () () .(. .). (. . ) . () 55 05 023 07 196 015 661 ? ?
AN-35 7 b 4/03 figure 5. effect on output characteristic when r lf or leakage inductance changes. figure 6. increasing r fb to adjust for high leakage increases no load voltage and consumption. clamp resistor (r lf ) the value for r lf , which effectively filters the leakage inductance spike from the reflected voltage waveform, is verified empirically through iteration. r lf has a direct effect on both the average value and slope of both the cv and cc curves as shown in figure 5 and can therefore be used to tune the output characteristic to some extent. in the cv region, increasing r lf increases the average output voltage, while reducing the slope of the cv region (the change in output voltage with the change in output current). in the cc region, increasing r lf makes the average output current lower, while tending to bend the curve inward slightly (fold back). pmarmw rfb fb = () = 2 3 111 2 . v reduced r lf or increased leakage inductance peak power curve reference reduced r lf or increased leakage inductance auto-restart v i i increased r lf or reduced leakage inductance peak power curve reference higher r lf or lower leakage inductance auto-restart pi-2958-081602 v i increased r fb peak power curve reference increased r fb to adjust for l leak auto-restart pi-2959-071902 (25) (24) r vv i vv ma k fb fb c idct dct = ? = ? = () .. . 56 7 5 75 23 22 ? select the nearest standard value. resistor r fb can then be adjusted to center the output voltage. the example in figure 3 uses a 20.5 k ? value for r fb (r1), centering the output voltage v o near 5.5 v at nominal output current i o . note that r fb power dissipation, a significant component of linkswitch standby power, should always be calculated: for applications that do not need to comply with strict standby power requirements, higher values of v or can be used, also increasing the power capability of linkswitch . clamp diode (d clamp ) diode d clamp should be an ultra-fast or fast recovery diode with at least 600 v breakdown voltage. fast types typically offer a slight cost advantage and also reduce emi, so they are preferred. note that normal recovery diodes (1n400x or similar types), which may allow excessive drain voltage ringing, should not be used.
AN-35 8 b 4/03 figure 7. example of battery model load (values for a typical 3 w, 5.5 v battery charger). with stable dielectrics (npo or cog, for example) are higher cost. the value of low cost ceramic capacitors varies significantly with voltage and temperature (z5u dielectric, for example) and should not be used since they may cause output oscillation. control pin capacitor (c cp ) c cp sets the auto-restart period and also the time the output has to reach regulation before entering auto-restart at power supply start-up. if the load is a battery, then a value of 0.22 f is typical. however, if the supply is required to start into a resistive load or constant current load (such as a bench electronic load) at the peak output power point, then this should be increased to 1 f. this ensures enough time during start-up to bring the output into regulation. the type of capacitor is not critical. either a small ceramic or electrolytic may be used with a voltage rating of 10 v or more. output rectifier and filter (d out , c out ) the output diode should be selected with an adequate peak inverse voltage (piv) rating. either pn or schottky diodes can be used. schottky diodes offer higher efficiency at higher cost but provide the most linear cc output characteristic. both fast or ultra fast pn diodes may be used, but ultra fast (t rr ~50 ns) are preferred giving cc linearity close to the performance of a schottky. the output diode voltage rating should be calculated from equation 26. v dc(max) is the maximum primary dc rail voltage (375 v for universal or 230 vac and 187 v for 115 vac only designs). the output voltage v o is multiplied by 1.5 to allow for increased output voltage at no-load. an output diode current rating of 2 x i o is a good initial estimate. the output diode may be placed in either the upper or lower leg of the secondary winding. however, placement in the lower leg may provide lower conducted emi with a suitably constructed transformer. for battery charger applications, the size and cost of the output capacitor c out can be significantly reduced. high ripple current flows through c out for only the short time a fully depleted battery charges. the designer should take into account that c out ripple current rating can be exceeded for short periods of time without reducing lifetime significantly. when the battery is close to fully charged, the linkswitch circuit transitions to cv mode, where capacitor ripple current is much smaller. pi-2975-072402 (26) at no-load, increasing r lf slightly increases the no-load voltage since the primary leakage inductance is filtered more effectively, but the same peak charging due to secondary leakage inductance occurs. although the no-load voltage is slightly higher, there is only a minor effect on no-load consumption. in a design that has high leakage, the value of r fb can be increased to raise the overall output voltage (figure 6). however, this will also increase no-load voltage and therefore no-load input power consumption. to iterate r lf : ? start with typical value of 100 ? and a transformer with nominal inductance. ? verify cc portion of the curve and increase or decrease r lf until cc curve is approximately vertical (current at start of cc and end are approximately the same) ? verify cv portion of the curve. - for minor adjustment, change value of r fb . clamp capacitor (c clamp ) with small values of clamp capacitor c clamp , the output voltage tends to be slightly higher. with larger values for c clamp , output voltage will be slightly lower. further increases in c clamp will not change the output voltage. c clamp is therefore chosen empirically as the smallest value that does not significantly change the output voltage when compared to the next larger value. for most designs, 100 nf is typical and standard device tolerances will have a negligible effect on the output voltage. this capacitor should be rated above the v or , typically 100 v. c clamp must have a stable value over temperature and also over the operating voltage range. metalized plastic film capacitors are the best choice, since the higher voltage ceramic capacitors piv d v n n v out dc max s p o ? ? ? ? ? ? ? + () () . 15 2 x 1n4001 r cable r load r int_res 10,000 f r cable = 0.23 ? r int_res = 0.5 ? r load = 11 ?
AN-35 9 b 4/03 figure 8. uneven core gapping makes cc portion nonlinear and should be avoided. figure 9. effect on output characteristic due to increased output cable resistance. v i increasing cable resistance peak power curve reference increased output cable resistance auto-restart pi-2962-072202 for adapter applications drawing rated load current in steady state, c out should be a low esr type, properly rated for ripple current. designs for battery charging usually do not require an additional output l-c stage ( filter) to reduce switching noise. the battery itself will filter this noise and output ripple. however, if the load is resistive, then this stage may be required to meet ripple and noise specifications. for evaluation of a battery charger during design, a battery load can be simulated using a circuit similar to that shown in figure 7, which models both the battery and output cable. bridge rectifier, energy storage, and emi filter figure 1 shows a typical input stage for a low cost design. d1- d4 rectifies universal ac input voltage. c1 and c2 provide energy storage, smoothing, and emi filtering. rf1 reduces surge current, emi and will also safely open, like a fuse, if another primary component fails in a short circuit. the conducted emissions emi filter has effectively two differential mode stages. rf1 and c1 form the first differential mode stage. the second differential mode filter stage is formed by l1 and c2. rf1 should be a 10 ? low cost wire-wound fusible resistor or be replaced by a fuse. a resistor is preferable to a fuse as it also limits inrush current and protects against input voltage transients and surges (differential or normal mode). lower values increase dissipation (v 2 /r power term) during transients and inrush, while higher values increase steady state dissipation (i 2 r) and lower overall efficiency. metal film types should not be used since they do not have a high enough transient power capability to survive line transient and inrush current and may fail prematurely in service. to meet certain safety agency requirements rf1 should fail open without emitting smoke, fire or incandescent material, that might damage the primary-to-secondary insulation barrier. consult with a safety engineer or local safety agency for specific guidance. diodes d1-d4 should be rated at 400 v or above and be standard recovery types to minimize emi. the combined value of c1 and c2 should be selected to give 3 f per watt (of output power), giving acceptable voltage ripple for universal designs. for high single input voltage ranges (185 vac to 265 vac), this recommendation can be reduced to 1 f/w, however ripple current ratings and differential mode line transient performance should be verified. l1, which is effective for low frequencies, is typically in the range of 680 h to 2.2 mh and should have a current rating of 80 ma rms. hints and tips transformer construction since the primary inductance is crucial in setting the peak output power, the tolerance of this parameter should be well controlled. for a cc tolerance at the peak power point of 20%/ 25% (lnk501/lnk500, respectively) the primary inductance tolerance should be 10% or better. tolerance of ungapped core permeability limits minimum gap size for center leg gapping. for an ee13 core size, the practical minimum center leg gap size, for an overall primary inductance tolerance of 10%, is ~0.08 mm. this varies with core supplier, so this should be verified before committing to a design. pi-2961-072202
AN-35 10 b 4/03 reducing no-load voltage with a pre-load at very light loads (< ~5 ma), the output voltage rises due to secondary peak charging. this can be significantly reduced by the addition of a small pre-load resistor. figure 10 shows the effect of a 1 ma and 2 ma pre-load on a 9 v output design, reducing the no-load voltage by 1.3 v. this level of pre-load has minimal effect on no-load consumption (~10 mw to 20 mw). minimizing no-load consumption the major factors for no-load or standby consumption are p bias and the capacitive switching loss p c(loss) (equations 9 and 28). if no-load consumption is too high, then the transformer may be redesigned with a lower v or . total parasitic capacitance of device and transformer, typically 25 pf to 30 pf, causes a switching loss that increases with input voltage and has a significant effect on standby or no-load output power consumption. v max is typically 340 v for universal or 230 vac applications and f s is 30 khz at light or no load. parasitic capacitance loss p c(loss) is typically 40 mw to 100 mw. this loss is not included in the l p calculation as this power is not processed through the core. to minimize transformer capacitance, double coated magnet wire should be used for the primary winding. the technique of vacuum impregnation should not be used since the varnish acts as a dielectric, increasing winding capacitance. dip varnishing does not cause this problem. an rc snubber placed across the output diode also increases no-load consumption. if necessary, minimize the value of the other gapping techniques allow tighter tolerances, but may not be universally supported, so again, this should be verified with the preferred magnetics vendor. film gapping, where thin material spaces all three legs of the core, allows better mechanical tolerance and improves overall primary inductance tolerance to 7% with a 0.05 mm gap. since a gap now appears on the outer legs of the core, flux spraying may result, causing pick up in the input filter components and resulting in poorer than expected conducted emi. this can be prevented, if necessary, by adding a single shorted turn of copper foil around the outside of the transformer core also known as a belly band. core gaps should be uniform. uneven core gapping (see figure 8), especially with small gap sizes, may cause variation in the primary inductance with flux density (partial saturation) and make the constant current region nonlinear. to verify uniform gapping, it is recommended that the primary switching current waveshape be examined while feeding the supply from a dc source. the slope is defined as di/dt = v/l and should remain constant throughout the mosfet on time. any change in slope of the current ramp is an indication of uneven gapping. verifying discontinuous mode operation to verify a design will remain discontinuous conduction mode under worst case condition use equation 27: where i o(max) is the output current (a) at maximum cc tolerance (typically i o(nom) + 20%), f s(max) is the maximum linkswitch switching frequency (hz), l p(max) is the primary inductance (h) at maximum tolerance, d is duty cycle at minimum input voltage (typically 0.3 at 85 vac or 0.13 at 195 vac) and v dc(min) the minimum dc voltage at lowest input line voltage (typically 100 vdc for 85 vac and 230 vdc for 195 vac). effect of output cable factors such as leakage inductance, the value for r lf , r fb and c clamp have been covered. however, there are other parameters that should be considered when designing with linkswitch . if the gauge of wire selected for the output cable is reduced, then the voltage drop across the cable resistance will increase. as seen at the load, this appears as poorer cv operation and lower efficiency, but with the cv/cc transition at the same output current (see figure 9). ensure that the voltage drop or resistance of the output cable is acceptable. figure 10. a small pre-load can significantly reduce no-load voltage. pi-3227-082202 output current (ma) 15 9 12 8 412 0 output voltage (v) no pre-load 1 ma pre-load 2 ma pre-load 2 1 ? < ifl ddv n n o max s max p max dc min p s () () () () () (27) (28) p cv f c loss tot max s () = 2 2
AN-35 11 b 4/03 capacitor used. if an ultra-fast diode has been selected, try a fast diode as this may allow the snubber to be removed. correct oscilloscope connection to prevent the additional capacitance of an oscilloscope probe from triggering the linkswitch current limit, do not connect the scope ground to the source pin. the scope should be connected as shown in figure 11 to measure source to drain voltage. since the scope is referenced to the dc rail, an isolation transformer must be used. improving cv tolerance with optocoupler the schematic in figure 12 shows an example of adding a secondary reference and optocoupler to improve cv tolerance across the entire load range. the voltage drop (sense voltage) across vr1, u1 and r3 sets the nominal output voltage. the feedback resistor r fb is split into two to form a divider which limits the voltage across the optocoupler phototransistor. the optocoupler therefore effectively adjusts the resistor divider ratio to control the dc voltage across r2 and the current into the control pin. for an output tolerance 5%, vr1 should be replaced by a reference ic (tl431). a full description of the operation with an optocoupler can be found in the linkswitch data sheet. single point failure testing the linkswitch circuit requires few considerations for single point failure testing. breaking the feedback loop by opening either r lf , d clamp or r fb results in linkswitch entering auto- restart. under this condition, the secondary output voltage will rise but the output power is limited to ~8% of normal. this prevents the output capacitor from failing catastrophically. if figure 11. correct method of connecting an oscilloscope to measure switching waveform. figure 12. power supply outline schematic with optocoupler feedback. linkswitch v out rtn s d c c1 c3 c2 u1 r4 r3 vr1 r1 r fb 2 r1 = r2 = d1 r2 pi-3222-082202 u1 pi-3164-032403 isolation transformer
AN-35 12 b 4/03 and biases or deterministic variations (apparent in a single unit when tested). this distinction is made since random variations are added using the root-sum-squares method, whereas biases add directly. a further column ( ? i/ ? v), applicable to the i 2 f and l p terms, contains the value including the effect of the change in output current with output voltage. this is necessary because the cv slope is nonzero. therefore, for example, if the peak power increases, the voltage at the new peak power point tends to be lower, further increasing the output current. the figure of 19.7% in table 1 is the overall variation of the cc region. it is important to note that the figure of 2% for constant current linearity (the straightness of the constant current characteristic) is only valid for designs close to 3 w output power, with a primary inductance of ~3 mh. this is due to the internal compensation for drain current di/dt variations over line voltage. this compensation was arranged to correctly compensate, over a line voltage range of 85 vac to 265 vac, with a primary inductance of 3 mh. in lower power designs, where the primary inductance is lower, an error results which increases the non- linearity in the cc curve. output diode of choice also effects cc linearity. the value in table 1 is based on a schottky diode. the slower forward recovery time of a pn diode can cause the cc characteristic to bend outwards with falling output voltage. constant voltage operation at peak power point during cv operation, the output characteristic is controlled by adjusting the duty cycle, based on the voltage v fb across capacitor c clamp (figure 1). a number of parameters define the actual output voltage, and therefore, the tolerance of the output voltage at the peak power point. the key parameters to consider are: ? current variation through r fb due to line voltage variation ? control pin voltage - v c(idct) desired, a 0.5 w zener can be added across the output to clamp this voltage rise. the zener voltage should be set above the normal maximum output voltage at no-load. short circuiting or opening c cp safely prevents linkswitch operation. however, on opening of c clamp , linkswitch does not enter auto-restart. the output voltage may rise unacceptably high under this condition and cause the failure of the output capacitor. as the supply delivers full power, output clamping requires a zener power rating equal to or above the nominal output power. adding a second capacitor in parallel to c clamp prevents this problem. when c clamp is open circuited the second capacitor acts as c clamp . this second capacitor can be a small value ceramic (0.01 f) capacitor since during normal operation c clamp dominates the parallel combination. appendix a linkswitch tolerance analysis output characteristic tolerances both the device tolerance and external circuit govern the overall tolerance of the linkswitch power supply output characteristic. for a typical design, the peak power point tolerances are 10% for voltage and 20% (lnk501) / 25% (lnk500) for current limit. this is the estimated overall variation due to linkswitch , transformer tolerance and line variation in high volume manufacturing. this appendix provides expressions to allow the calculation of expected circuit variation when in high volume manufacturing for a design employing a lnk501 as shown in figure 3. the same analysis can be extended to the lnk500. the only significant difference is a wider i 2 f tolerance ( 12% compared to 6% for lnk501) and associated increase in ? i/ ? v to 3%. constant current limit the peak power point prior to entering constant current operation is defined by the maximum power transferred by the transformer. since linkswitch is designed to operate in discontinuous mode, the power transferred is given by the expression p = 1/2 l i 2 f, where l is the primary inductance, i is the primary peak current and f is the switching frequency. to simplify analysis, the data sheet parameter table specifies an i 2 f coefficient. this is the product of current limit squared and switching frequency, normalized to the feedback parameter i dct . this provides a single term that specifies the variation of the peak power point in the power supply due to linkswitch . additional variations are summarized in table 1, as both random (unit-to-unit) or statistically independent variations table 1. sources of cc tolerance. primary inductance i 2 f input line cc linearity t j (25-65 c) totals 3 . 2% 1.5% 10% 6% 3% 12.5% 7.5% 3% 2.5% 1.5% variable biases random ? i / ? v 4.7% 2% 2% 15% random + ? i / ? v biases + random 19.7%
AN-35 13 b 4/03 any change in the current through r fb , due to the tolerance of the control pin current at 30% duty cycle, i dct , will also cause a change in the output voltage. the change in the voltage across r fb (k ? ) due to the tolerance of i dct (ma) is given by: expressed as a percentage of the voltage across v fb , the variation is: the overall variation can then be estimated using the expression: using the design shown in figure 3 as an example: the tolerance of r1 (r fb ) is 1%. ? output diode forward voltage - v dout ? current variation through r fb due to control pin voltage tolerance at 30% duty cycle (i dct ) ? feedback resistor tolerance - ? % rfb each of the key parameters above is examined in turn. the most significant variation in the output voltage is the change with input line. the voltage across r fb is defined at i dct , corresponding to a 30% duty cycle at low line voltage. at higher line voltage, the control pin current increases and the voltage across r fb increases. the change in voltage across r fb , ? v fb(line) , depends on the change in duty cycle ? dc, the corresponding change in control pin current ? i c (ma) and the value r fb (k ? ). the change in control pin current for a given change in duty cycle can be found from a curve in the linkswitch data sheet. for a universal input voltage design, ? dc from low line to high line is typically 0.2 (0.09 for a single input design) giving a change in control pin current of typically 0.15 ma. the value of ? v rfb(line) should be expressed as a percentage of v fb to give the variation at the power supply output. the expression for line variation (at the peak power point) is therefore: the control pin voltage v c(idct) is specified at a current equal to i dct , giving a duty cycle of 30% for a typical design at the peak power point, at 85 vac input. the tolerance of this parameter includes temperature variation and can be read from the data sheet directly. since the output voltage is actually controlled using v fb , the variation of v c(idct) must be expressed as a percentage of v fb . the expression for this is given by: any variation in the output diode forward drop with temperature will cause a change in the output voltage. expressing as a percentage of v o gives the expression: typical values for the change in forward voltage for a temperature change of +50 c are +0.1 v for a silicon pn diode and +0.025 v for schottky diode. for device-to-device variations, please consult diode manufacturer. (a4) (a8) (a9) (a5) (a6) (a7) (a3) (a1) ?? vir rfb line c fb () = (a2) (a12) (a10) (a11) ?? vmak rfb line () .. == 015 205 3.1 v (a13) (a14) ? v ii r rfb idct dct max dct min fb () () () = ? 2 ? % . . %.% vdout v v = = 0 025 255 100 0 23 ? ? %% () line rfb line fb v v = 2 100 ? %% () ()() ()() vc idct c idct max c idct typ fb vv v = ? 100 ? ? %% () idct rfb idct fb v v = 100 ? % . . %.% () vc idct vv v = ? = 6575 54 2 100 0 46 ? % . . %.% line v v = = 31 2542 100 2 9 ? % . . %.% idct v v = = 123 54 2 100 2 27 ? %.%.%(.. ) .% .% .% .% cv = + + = = 29 023 046 227 1 29 023 252 565 222 ?? v ma ma k rfb idct () .. . = ? = 236 224 2 20 5 1.23 v ? ? %% vdout dout o v v = 2 100 ??? ? ?? %%% % %% () cv line vdout vc idct idct rfb = + + 2 22
AN-35 14 b 4/03 the overall tolerance is the sum of the deterministic variation due to the change in line voltage and the change in the output diode forward voltage with temperature, together with the root- sum-square addition of the statistically independent circuit and device variables. in equation a14 the ? % line term ( 2.9%) is the expected change in output voltage for a change of 90 vac at 175 vac, the mid point of the specified input voltage range of 85 vac to 265 vac. equivalently, stating with the reference as 85 vac, the output voltage would increase +5.8% (twice 2.9%) when the input increases to 265 vac. the analysis above is for a specific example, factors such as diode choice, temperature range and output voltage can result in a larger tolerance. however, for most cases the designer can be confident the overall tolerance will be < 10%. note that all of the above tolerances other than r fb and v c(idct) are compensated or accounted for in the previous analysis of cc tolerance. the contributions of r fb and v c(idct) , since they are unit-to-unit tolerances, have a very small influence (<0.1% on the total sum of unit-to-unit tolerances). constant voltage operation below peak power point as the output load reduces from the peak power point, the output voltage will tend to rise due to tracking errors compared to the load terminals. sources of these include the output cable drop, output diode forward voltage and leakage inductance, which is the dominant cause. as the load reduces, the primary operating peak current reduces, together with the leakage inductance energy, which reduces the peak charging of c clamp . with a primary leakage inductance figure of 50 h, the output voltage typically rises 40% from full to no-load.
AN-35 15 b 4/03
AN-35 16 b 4/03 singapore power integrations, singapore 51 goldhill plaza #16-05 republic of singapore 308900 phone: +65-6358-2160 fax: +65-6358-2015 e-mail: singaporesales@powerint.com world headquarters americas power integrations, inc. 5245 hellyer avenue san jose, ca 95138 usa main: +1 408-414-9200 customer service: phone: +1 408-414-9665 fax: +1 408-414-9765 e-mail: usasales@powerint.com taiwan power integrations international holdings, inc. 17f-3, no. 510 chung hsiao e. rdl, sec. 5, taipei, taiwan 110, r.o.c. phone: +886-2-2727-1221 fax: +886-2-2727-1223 e-mail: taiwansales@powerint.com china power integrations international holdings, inc. rm# 1705, block a, bao hua bldg. 1016 hua qiang bei lu shenzhen guangdong, 518031 china phone: +86-755-8367-5143 fax: +86-755-8377-9610 e-mail: chinasales@powerint.com europe & africa power integrations (europe) ltd. centennial court easthampstead road bracknell berkshire, rg12 1yq united kingdom phone: +44-1344-462-300 fax: +44-1344-311-732 e-mail: eurosales@powerint.com korea power integrations international holdings, inc. 8th floor, dongsung building, 17-8 yoido-dong, youngdeungpo-gu, seoul, 150-874, korea phone: +82-2-782-2840 fax: +82-2-782-4427 e-mail: koreasales@powerint.com japan power integrations, k.k. keihin-tatemono 1st bldg. 12-20 shin-yokohama 2-chome kohoku-ku, yokohama-shi, kanagawa 222-0033, japan phone: +81-45-471-1021 fax: +81-45-471-3717 e-mail: japansales@powerint.com india (technical support) innovatech #1, 8th main road vasanthnagar bangalore, india 560052 phone: +91-80-226-6023 fax: +91-80-228-9727 e-mail: indiasales@powerint.com applications hotline applications fax world wide +1-408-414-9660 world wide +1-408-414-9760 for the latest updates, visit our web site: www.powerint.com patent information power integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. power integrations does not assume any liability arising from the use of any device or circuit described herein, nor does it convey any license under its patent r ights or the rights of others. the products and applications illustrated herein (including circuits external to the products and transformer construction) may be covered by one or more u.s. and foreign patents or potentially by pending u.s. and foreign patent applications assigned to power integrations. a complete l ist of power integrations patents may be found at www.powerint.com. life support policy power integrations' products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of power integrations, inc. as used herein: 1. life support devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, a nd whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a signi ficant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expecte d to cause the failure of the life support device or system, or to affect its safety or effectiveness. the pi logo, topswitch , tinyswitch , linkswitch and ecosmart are registered trademarks of power integrations, inc. pi expert and dpa-switch are trademarks of power integrations, inc. ?copyright 2003, power integrations, inc. revision a b notes 1) added support for lnk500 date 8/02 4/03

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