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1 HD66732 (graphics liquid crystal display controller/driver supporting jis level-1 and level-2 kanji rom) ade-207-314(z) rev 1.2 aug, 1999 description the HD66732 is a dot-matrix liquid crystal display (lcd) controller and driver lsi that displays 11-by-12 dot japanese characters consisting of kanji and hiragana according to the japanese industrial standard (jis) level-1 and level-2 kanji set. the HD66732 incorporates the following five functions on a single chip: (1) display control function for the dot matrix lcd, (2) a display ram to store character codes, (3) rom fonts to support level-1 and level-2 kanji, (4) an lcd driver, and (5) a booster to drive the lcd. a 4-line 10-character kanji display can be easily achieved by receiving character codes (2 bytes/character) from the microcomputer. the software processing loads on the microcomputer for kanji-font display development can be greatly reduced, and an external kanji character generator or key scan circuit is not needed. the character font includes font roms of 6,353 kanji from the jis level-1 and level-2 kanji set, 285 jis non- kanji characters, and 256 half-size alphanumeric characters and symbols. full-size fonts such as japanese kanji and half-size fonts such as alphanumeric characters can be displayed together. in addition, the HD66732 supports a 120-by-52 dot graphics display function that can display not only characters such as kanji but also graphics such as drawings or maps. the HD66732 has various functions to reduce the power consumption of an lcd system, such as low- voltage operation at 2.4 v, a low-power lcd drive operating amplifier, and a booster to switch the boosting rate. combining these hardware functions with software functions such as standby and sleep modes allows precise power control. the HD66732 is suitable for any battery-driven product requiring long-term driving capabilities such as cellular phones, pagers, or portable devices. features dot-matrix liquid crystal display controller/driver supporting the display of kanji from the jis level-1 and level-2 kanji set kanji display and high-speed font development processing enabled by data transfer of two bytes/character 4-line 10-character kanji and 120-by-52-dot graphics display mark display using 200 monochrome segments (marks) or 40 grayscale segments control up to a 4 x 8 (32 key) matrix key scan (at a serial interface)
HD66732 2 large character generator rom for full-size display: corresponds to 8,128 full-size fonts ? kanji according to jis level-1 kanji (11 x 12 dots): 2,965-character font ? kanji according to jis level-2 kanji (11 x 12 dots): 3,388-character font ? jis non-kanji (11 x 12 dots): 285-character font character generator rom for half-size display: corresponds to 256 half-size fonts ? alphanumeric characters (6 x 12 dots): 128 fonts x 2 banks (256 fonts) 120-by-52-dot bit-map graphics display combined display of 11 x 12 dots for full-size fonts consisting of kanji and kana, 6 x 12 dots for half- size fonts of alphanumeric characters and symbols low-power operation support: ? vcc = 2.4 to 5.5 v (low voltage) ? single, double, triple, or quadruple booster for liquid crystal drive voltage ? operational amplifier for low-power lcd drive supply and bleeder-resistors incorporated ? strong power-save functions such as the standby mode and sleep mode supported ? wake-up function using key scan interrupt ? programmable lcd-drive duty ratios and bias values various display control functions: ? combined display (super-imposed display) of kanji characters and bit map graphics ? vertical smooth scroll (dot unit) ? black-white reversed display of full screen ? display-line-unit black-white reversed/underline/blinking display ? black-white reversed/blinking/black-white reversed blinking character display display data ram: 80 bytes (stores 40-character code in full size) character generator ram: 780 bytes (stores 120-by-52-dot bit map areas) (30 full-size user fonts can be displayed) segment ram: 60 bytes (200 segments can be displayed) three-line clock synchronous serial bus, 4-/8-bit bus interface no wait cycle for instruction execution and ram access 120-segment x 54-common lcd driver three general output ports built-in external r-c oscillator lcd drive voltage: 4.5 v to 13.0 v external dimensions: tape carrier package (tcp) and slim chip with au-bumps
HD66732 3 table 1 programmable display sizes and duty ratios duty ratio optimum drive bias number of full-size kanji display characters graphics display area segment display scanned keys general ports 1/2 1/2 unavailable unavailable 200 32 (4 x 8) 3 1/15 1/5 1 line x 10 characters 120 x 13 dots (grayscale 1/28 1/6 2 lines x 10 characters 120 x 26 dots segments: 1/41 1/7 3 lines x 10 characters 120 x 39 dots 40) 1/54 1/8 4 lines x 10 characters 120 x 52 dots type name type name external dimensions display lines (graphics display) built-in full-size font built-in half-size font HD66732a04tb0l bending tcp 4-line x 10-character (120 x 52 dots) jis level-1 and level-2 kanji set + non-kanji characters alphanumeric characters HD66732a04bp au-bumped chip (slim chip) 4-line x 10-character (120 x 52 dots) jis level-1 and level-2 kanji set + non-kanji characters alphanumeric characters example of liquid crystal display figure 1 combined display of 4-line x 10-character kanji and graphics
HD66732 4 lcd specification comparison for kanji display external kanji rom type items hd66724 hd66725 hd66726 kanji display area 72 x 24 dots 96 x 24 dots 96 x 40 dots kanji character display half-size alphanumeric character display 12 characters x 3 lines 16 characters x 3 lines 16 characters x 5 lines graphics display sizes 72 x 26 dots 96 x 26 dots 96 x 42 dots multiplexing icons 144 192 192 key scan control 8 x 4 8 x 4 8 x 4 general output port 3 3 3 operating power voltages 1.8 v to 5.5 v 1.8 v to 5.5 v 1.8 v to 5.5 v liquid crystal drive voltages 3 v to 6 v 3 v to 6 v 4.5 v to 11 v serial bus clock-synchronized serial clock-synchronized serial clock-synchronized serial parallel bus 4 bits, 8 bits 4 bits, 8 bits 4 bits, 8 bits expansion driver control impossible impossible impossible liquid crystal drive duty ratios 1/2, 10, 18, 26 1/2, 10, 18, 26 1/2, 10, 18, 26, 34, 42 liquid crystal drive biases 1/4 to 1/6.5 1/4 to 1/6.5 1/2 to 1/8 liquid crystal drive waveforms b b b liquid crystal voltage booster single, double or triple single, double, or triple single, double, triple, or quadruple bleeder-resistor for liquid crystal drive incorporated (external) incorporated (external) incorporated (external) liquid crystal drive operational amplifier incorporated incorporated incorporated contrast adjuster incorporated incorporated incorporated horizontal smooth scroll 3-dot unit 3-dot unit impossible vertical smooth scroll raster-row unit raster-row unit raster-row unit double-height display yes yes yes ddram 80 x 8 80 x 8 80 x 8 cgrom 21 k 21 k 21 k incorporated font alphanumeric character + kana alphanumeric character + kana alphanumeric character + kana cgram 384 x 8 384 x 8 480 x 8 segram 72 x 8 96 x 8 96 x 8 number of cgrom fonts 432 432 432 number of cgram fonts 64 64 64 font sizes 6 x 8 6 x 8 6 x 8 r-c oscillation resistor/ oscillation frequency external resistor, incorporated (32 khz) external resistor, incorporated (32 khz) external resistor (50 khz) reset function external external external low power control partial display off display off oscillation off liquid crystal power off key wake-up interrupt partial display off display off oscillation off liquid crystal power off key wake-up interrupt partial display off display off oscillation off liquid crystal power off key wake-up interrupt seg/com direction switching seg, com seg, com seg, com qfp package tcp package tcp tcp tcp bare chip (without bumps) bumped chip yes yes yes number of pins 146 170 185 chip sizes 10.34 x 2.51 10.97 x 2.51 13.13 x 2.51 pad (bump) intervals 80 m m 80 m m 100 m m
HD66732 5 lcd specification comparison for kanji display (cont) internal kanji rom type items hd66730 hd66731 HD66732 kanji display area 71 x 25 dots 119 x 51 dots 120 x 52 dots kanji character display 6 characters x 2 lines 10 characters x 4 lines 10 characters x 4 lines half-size alphanumeric character display 12 characters x 2 lines 20 characters x 4 lines 20 characters x 4 lines graphics display sizes (48 x 26 dots) (48 x 26 dots) 120 x 52 dots multiplexing icons 71 120 200 key scan control 8 x 4 general output port 3 operating power voltages 2.4 v to 5.5 v 2.4 v to 5.5 v 2.4 v to 5.5 v liquid crystal drive voltages 3 v to 15 v 3 v to 15 v 4.5 v to 13 v serial bus clock-synchronized serial clock-synchronized serial clock-synchronized serial parallel bus 8 bits 8 bits 4 bits, 8 bits expansion driver control possible impossible impossible liquid crystal drive duty ratios 1/14, 27, 40, 53 1/14, 27, 40, 53 1/2, 15, 28, 41, 54 liquid crystal drive biases 1/4 to 1/8.3 1/4 to 1/8.3 1/2 to 1/8 liquid crystal drive waveforms b b b + c liquid crystal voltage booster double or triple double or triple single, double, triple, or quadruple bleeder-resistor for liquid crystal drive external external external liquid crystal drive operational amplifier incorporated contrast adjuster incorporated horizontal smooth scroll display unit display unit impossible vertical smooth scroll raster-row unit raster-row unit raster-row unit double-height display ddram 80 x 8 80 x 8 80 x 8 cgrom 507 k + 9 k 507 k + 9 k 1,048 k + 18 k incorporated font jis level-1 kanji set, hungle jis level-1 kanji set, hungle jis level-1 and level-2 kanji set cgram 208 x 8 208 x 8 780 x 8 segram 16 x 8 16 x 8 60 x 8 number of cgrom fonts 3840 + 128 (half size) 3840 + 128 (half size) 8128 + 256 (half size) number of cgram fonts 8 8 30 font sizes 11 x 12 11 x 12 11 x 12 r-c oscillation resistor/ oscillation frequency external resistor (150 khz) external resistor (150 khz) external resistor (45 to 76 khz) reset function external external external low power control booster off internal division function booster off internal division function partial display off display off oscillation off liquid crystal power off key wake-up interrupt seg/com direction switching seg, com qfp package qfp-1420 tcp package tcp tcp bare chip (without bumps) yes bumped chip yes yes number of pins 128 206 221 chip sizes 7.48 x 6.46 7.48 x 6.46 12.68 x 4.31 pad (bump) intervals 180 m m 80 m m 100 m m
HD66732 6 HD66732 block diagram system interface ?clock synchro- nized serial ?4-bit bus ?8-bit bus data register (dr) address counter (ac) timing generator display data ram (ddram) 80 bytes character generator ram (cgram) 780 bytes full-size character generator rom (fcgrom) 1,048 kbits parallel/serial converter 120-bit latch circuit 120-bit segment shift register 54-bit bidirectional common shift register common driver segment driver lcd drive voltage selector cpg instruction decoder rs rw/rd*/sda e/wr*/scl vcc v lcd com1/52 com52/1 seg1/120 seg120/1 osc1 osc2 8 8 6 10 8 7 7 8 8 vci single to quadruple booster c1+ 8 7 segment ram (sgram) 60 bytes im2-1 reset* c1- +- +- +- +- vlout +- gnd coms1/2, coms2/1 vr rrr 0 r r test v1out v2out v3out v4out v5out opoff im0/id key scan timing controller key scan registers (scan0 ?can3) db0/kin0 db7/kin7 kst0 kst3 8 port0 port2 general output port c2+ c2- cs* c3+ c3- contrast adjuster drive bias controller index register control register half-size character generator rom (hcgrom) 18 kbits cursor/ blink control circuit
HD66732 7 HD66732 pad arrangement ?chip size: 12.68 mm x 4.31 mm ?pad coordinates: pad center ?coordinate origin: chip center ?au bump size: 70 m x 70 m ?au bump pitch: 100 m (min.) (top view) HD66732 seg40/81 seg39/82 seg38/83 seg37/84 seg36/85 seg35/86 seg34/87 seg33/88 seg32/89 seg31/90 seg30/91 seg29/92 seg28/93 seg27/94 seg26/95 seg50/71 seg49/72 seg48/73 seg47/74 seg46/75 seg45/76 seg44/77 seg43/78 seg42/79 seg60/61 seg59/62 seg58/63 seg57/64 seg56/65 seg55/66 seg54/67 seg53/68 seg52/69 seg51/70 seg66/55 seg65/56 seg64/57 seg63/58 seg62/59 seg61/60 seg67/54 seg41/80 seg25/96 seg68/53 seg69/52 seg70/51 seg71/50 seg72/49 seg73/48 seg74/47 seg75/46 seg76/45 seg77/44 seg78/43 seg79/42 seg80/41 seg81/40 seg82/39 seg83/38 seg84/37 osc2 osc1 c1+ y x seg85/36 seg86/35 seg87/34 seg88/33 seg89/32 seg90/31 seg91/30 seg92/29 seg93/28 seg94/27 seg95/26 seg96/25 c2- c2+ vci gnd db0/kin0 db1/kin1 db2/kin2 db3/kin3 db4/kin4 kst3 irq* rw/rd*/sda cs* reset* port0 c1- c1- vlout v lcd v lcd c2- c1+ c2+ vci vcc dummy14 rs dummy1 vcc gnd gnd e/wr*/scl db5/kin5 db6/kin6 db7/kin7 kst0 kst1 kst2 port1 port2 gnddum im2 im1 im0/id vccdum opoff test seg97/24 seg98/23 seg99/22 seg100/21 seg101/20 seg102/19 seg103/18 seg104/17 seg105/16 seg106/15 seg107/14 seg108/13 seg109/12 seg110/11 seg111/10 seg112/9 seg113/8 seg114/7 seg115/6 seg116/5 seg117/4 seg118/3 seg119/2 seg120/1 coms1/s2 com1/52 com2/51 com3/50 com4/49 com5/48 com6/47 com28/25 com29/24 com30/23 com31/22 com32/21 com33/20 com34/19 com27/26 com35/18 com36/17 com37/16 com38/15 com39/14 com40/13 com41/12 com42/11 com43/10 c3- c3- c3+ dummy30 dummy13 dummy12 dummy11 dummy15 dummy16 gnd gnd vcc vcc vci vci c3+ c3+ c3- c2+ c2- c1+ c1+ c1- c1- vlout vlout v lcd v1out v2out v3out v4out v5out com44/9 com45/8 com46/7 dummy6 dummy5 dummy4 dummy3 dummy2 com7/46 com8/45 com9/44 com10/43 com11/42 com12/41 com13/40 com15/38 com16/37 com17/36 com18/35 com19/34 com20/33 com21/32 com14/39 com22/31 com23/30 com24/29 com25/28 com26/27 com47/6 com48/5 com49/4 com50/3 com51/2 com52/1 coms2/s1 dummy25 dummy26 dummy27 dummy28 dummy29 seg24/97 seg23/98 seg22/99 seg21/100 seg20/101 seg19/102 seg18/103 seg17/104 seg16/105 seg15/106 seg14/107 seg13/108 seg12/109 seg11/110 seg10/111 seg9/112 seg8/113 seg7/114 seg6/115 seg5/116 seg4/117 seg3/118 seg2/119 seg1/120 vtest1 vtest2 vtest3 dummy9 dummy8 dummy7 dummy10 dummy19 dummy18 dummy17 dummy20 dummy21 gnd vcc gnddum2 dummy22 dummy23 dummy24
HD66732 8 cog routing example ?clock-synchronized serial bus ?unused key scan ?unused port output ?quadruple booster ?internal operational amplifier (top view) HD66732 osc2 osc1 y x db0/kin0 db1/kin1 db2/kin2 db3/kin3 db4/kin4 kst3 irq* cs* reset* port0 c1- vlout vcc db5/kin5 db6/kin6 db7/kin7 kst0 kst1 kst2 port1 port2 gnddum im2 im1 im0/id vccdum opoff test c3+ vci c3- c2+ c2- c1+ v lcd v1out v2out v3out v4out v5out vtest1 vtest2 vtest3 gnddum2 rs rw/rd*/sda e/wr*/scl gnd
HD66732 9 HD66732 pad coordinates pin coordinate pin coordinate pin coordinate no. pad name x y no. pad name x y no. pad name x y dummy1 ?165 1929 7 test ?027 ?989 61 c1+ 3917 ?929 dummy2 ?165 1829 8 port2 ?843 ?989 62 c1 4047 ?929 dummy3 ?165 1729 9 port1 ?659 ?989 63 c1 4147 ?929 dummy4 ?165 1629 10 port0 ?475 ?989 64 c1 4247 ?929 dummy5 ?165 1529 11 irq * ?291 ?989 65 c1 4347 ?929 dummy6 ?165 1428 12 kst3 ?107 ?989 66 vlout 4478 ?929 dummy7 ?165 1328 13 kst2 ?923 ?989 67 vlout 4578 ?929 dummy8 ?165 1228 14 kst1 ?739 ?989 68 vlout 4678 ?929 dummy9 ?165 1128 15 kst0 ?555 ?989 69 vlcd 4808 ?929 228 com46/7 ?114 972 16 db7/kin7 ?371 ?989 70 vlcd 4908 ?929 229 com45/8 ?114 872 17 db6/kin6 ?187 ?989 71 vlcd 5008 ?929 230 com44/9 ?114 772 18 db5/kin5 ?003 ?989 72 v1out 5188 ?940 231 com43/10 ?114 671 19 db4/kin4 ?819 ?989 73 v2out 5318 ?940 232 com42/11 ?114 571 20 db3/kin3 ?635 ?989 74 v3out 5448 ?940 233 com41/12 ?114 471 21 db2/kin2 ?451 ?989 75 v4out 5578 ?940 234 com40/13 ?114 371 22 db1/kin1 ?267 ?989 76 v5out 5709 ?940 235 com39/14 ?114 271 23 db0/kin0 ?083 ?989 77 vtest1 5839 ?940 236 com38/15 ?114 171 24 reset * ?99 ?989 78 vtest2 5969 ?940 237 com37/16 ?114 71 25 cs * ?15 ?989 79 vtest3 6114 ?940 238 com36/17 ?114 ?9 26 rs ?31 ?989 80 gnddum2 6114 ?765 239 com35/18 ?114 ?29 27 e/wr * /scl ?68 ?989 81 com7/46 6114 ?630 240 com34/19 ?114 ?29 28 rw/rd * /sda ?38 ?989 82 com8/45 6114 ?530 241 com33/20 ?114 ?29 29 gnd ?3 ?989 83 com9/44 6114 ?430 242 com32/21 ?114 ?29 30 gnd 77 ?989 84 com10/43 6114 ?330 243 com31/22 ?114 ?29 31 gnd 208 ?989 85 com11/42 6114 ?230 244 com30/23 ?114 ?30 32 gnd 338 ?989 86 com12/41 6114 ?130 245 com29/24 ?114 ?30 33 gnd 468 ?989 87 com13/40 6114 ?030 246 com28/25 ?114 ?30 34 gnd 598 ?989 88 com14/39 6114 ?30 247 com27/26 ?114 ?30 35 osc2 784 ?989 89 com15/38 6114 ?30 248 com6/47 ?114 ?030 36 osc1 968 ?989 90 com16/37 6114 ?30 249 com5/48 ?114 ?130 37 v cc 1148 ?932 91 com17/36 6114 ?30 250 com4/49 ?114 ?230 38 v cc 1278 ?932 92 com18/35 6114 ?29 251 com3/50 ?114 ?330 39 v cc 1408 ?932 93 com19/34 6114 ?29 252 com2/51 ?114 ?430 40 v cc 1538 ?932 94 com20/33 6114 ?29 253 com1/52 ?114 ?530 41 v cc 1668 ?932 95 com21/32 6114 ?29 254 coms1/s2 ?114 ?630 42 vci 1965 ?929 96 com22/31 6114 ?29 dummy10 ?114 ?810 43 vci 1865 ?929 97 com23/30 6114 ?9 dummy11 ?114 ?989 44 vci 2065 ?929 98 com24/29 6114 71 dummy12 ?914 ?989 45 vci 2165 ?929 99 com25/28 6114 171 dummy13 ?814 ?989 46 c3+ 2296 ?929 100 com26/27 6114 271 dummy14 ?714 ?989 47 c3+ 2396 ?929 101 com47/6 6114 371 dummy15 ?613 ?989 48 c3+ 2496 ?929 102 com48/5 6114 471 dummy16 ?513 ?989 49 c3 2626 ?929 103 com49/4 6114 571 dummy17 ?413 ?989 50 c3 2726 ?929 104 com50/3 6114 671 dummy18 ?313 ?989 51 c3 2826 ?929 105 com51/2 6114 772 dummy19 ?213 ?989 52 c2+ 2956 ?929 106 com52/1 6114 872 dummy20 ?113 ?989 53 c2+ 3056 ?929 107 coms2/s1 6114 972 dummy21 ?013 ?989 54 c2+ 3156 ?929 dummy22 6165 1128 1 gnddum1 ?863 ?989 55 c2 3256 ?929 dummy23 6165 1228 2 im2 ?762 ?989 56 c2 3387 ?929 dummy24 6165 1328 3 im1 ?578 ?989 57 c2 3487 ?929 dummy25 6165 1428 4 im0/id ?403 ?989 58 c1+ 3617 ?929 dummy26 6165 1529 5v cc dum ?303 ?989 59 c1+ 3717 ?929 dummy27 6165 1629 6 opoff ?202 ?989 60 c1+ 3817 ?929 dummy28 6165 1729
HD66732 10 pin coordinate pin coordinate pin coordinate no. pad name x y no. pad name x y no. pad name x y dummy29 6165 1829 147 seg40/81 2052 1929 188 seg81/40 ?052 1929 dummy30 6165 1929 148 seg41/80 1952 1929 189 seg82/39 ?152 1929 108 seg1/120 5955 1929 149 seg42/79 1851 1929 190 seg83/38 ?252 1929 109 seg2/119 5855 1929 150 seg43/78 1751 1929 191 seg84/37 ?352 1929 110 seg3/118 5755 1929 151 seg44/77 1651 1929 192 seg85/36 ?452 1929 111 seg4/117 5655 1929 152 seg45/76 1551 1929 193 seg86/35 ?552 1929 112 seg5/116 5554 1929 153 seg46/75 1451 1929 194 seg87/34 ?652 1929 113 seg6/115 5454 1929 154 seg47/74 1351 1929 195 seg88/33 ?752 1929 114 seg7/114 5354 1929 155 seg48/73 1251 1929 196 seg89/32 ?852 1929 115 seg8/113 5254 1929 156 seg49/72 1151 1929 197 seg90/31 ?952 1929 116 seg9/112 5154 1929 157 seg50/71 1051 1929 198 seg91/30 ?052 1929 117 seg10/111 5054 1929 158 seg51/70 951 1929 199 seg92/29 ?153 1929 118 seg11/110 4954 1929 159 seg52/69 851 1929 200 seg93/28 ?253 1929 119 seg12/109 4854 1929 160 seg53/68 751 1929 201 seg94/27 ?353 1929 120 seg13/108 4754 1929 161 seg54/67 651 1929 202 seg95/26 ?453 1929 121 seg14/107 4654 1929 162 seg55/66 550 1929 203 seg96/25 ?553 1929 122 seg15/106 4554 1929 163 seg56/65 450 1929 204 seg97/24 ?653 1929 123 seg16/105 4454 1929 164 seg57/64 350 1929 205 seg98/23 ?753 1929 124 seg17/104 4353 1929 165 seg58/63 250 1929 206 seg99/22 ?853 1929 125 seg18/103 4253 1929 166 seg59/62 150 1929 207 seg100/21 ?953 1929 126 seg19/102 4153 1929 167 seg60/61 50 1929 208 seg101/20 ?053 1929 127 seg20/101 4053 1929 168 seg61/60 ?0 1929 209 seg102/19 ?153 1929 128 seg21/100 3953 1929 169 seg62/59 ?50 1929 210 seg103/18 ?253 1929 129 seg22/99 3853 1929 170 seg63/58 ?50 1929 211 seg104/17 ?353 1929 130 seg23/98 3753 1929 171 seg64/57 ?50 1929 212 seg105/16 ?454 1929 131 seg24/97 3653 1929 172 seg65/56 ?50 1929 213 seg106/15 ?554 1929 132 seg25/96 3553 1929 173 seg66/55 ?50 1929 214 seg107/14 ?654 1929 133 seg26/95 3453 1929 174 seg67/54 ?51 1929 215 seg108/13 ?754 1929 134 seg27/94 3353 1929 175 seg68/53 ?51 1929 216 seg109/12 ?854 1929 135 seg28/93 3253 1929 176 seg69/52 ?51 1929 217 seg110/11 ?954 1929 136 seg29/92 3153 1929 177 seg70/51 ?51 1929 218 seg111/10 ?054 1929 137 seg30/91 3052 1929 178 seg71/50 ?051 1929 219 seg112/9 ?154 1929 138 seg31/90 2952 1929 179 seg72/49 ?151 1929 220 seg113/8 ?254 1929 139 seg32/89 2852 1929 180 seg73/48 ?251 1929 221 seg114/7 ?354 1929 140 seg33/88 2752 1929 181 seg74/47 ?351 1929 222 seg115/6 ?454 1929 141 seg34/87 2652 1929 182 seg75/46 ?451 1929 223 seg116/5 ?554 1929 142 seg35/86 2552 1929 193 seg76/45 ?551 1929 224 seg117/4 ?655 1929 143 seg36/85 2452 1929 184 seg77/44 ?651 1929 225 seg118/3 ?755 1929 144 seg37/84 2352 1929 185 seg78/43 ?751 1929 226 seg119/2 ?855 1929 145 seg38/83 2252 1929 186 seg79/42 ?851 1929 227 seg120/1 ?955 1929 146 seg39/82 2152 1929 187 seg80/41 ?952 1929
HD66732 11 tcp dimensions (HD66732xxxtb0) 0.50 mm coms1/s2 com1/52 com6/47 seg120/1 seg1/120 coms2/s1 com7/46 0.65p x (47 ?1) = 29.90 mm 0.17p x (120 ?1) = 20.23 mm 0.17-mm pitch lcd driver i/o, power supply hitachi hitachi HD66732 HD66732 com27/26 com46/7 im2 im1 im0/id opoff test port2 kst3 kst2 kst1 kst0 db7/kin7 db6/kin6 db5/kin5 db4/kin4 db3/kin3 db2/kin2 db1/kin1 db0/kin0 reset* cs* rs e/wr*/scl rw/rd*/sda gnd osc2 osc1 vcc vci c2+ c2- c1+ c1- vlout vlcd v1out v2out v3out v4out v5out port1 port0 irq* vtest1 vtset2 vtest3 vtest3 0.65-mm pitch dummy dummy c3+ c3- com52/1 com47/6 com26/27 bending slit 4.0 mm 0.20p x (27 ?1) = 5.20 mm 0.50 mm 0.20p x (27 ?1) = 5.20 mm 0.50 mm 0.50 mm 32.63 mm
HD66732 12 pin functions table 2 pin functional description signals number of pins i/o connected to functions im2, im1 2 i v cc or gnd selects the mpu interface mode: im2 im1 mpu interface mode "gnd" "gnd" clock-synchronized serial interface "gnd" "vcc" 68-system parallel bus interface "vcc" "gnd" setting inhibited "vcc" "vcc" 80-system parallel bus interface im0/id 1 i v cc or gnd inputs the id of the device id code for a serial bus interface. selects the transfer bus length for a parallel bus interface. gnd: 8-bit bus, vcc: 4-bit bus cs* 1 i mpu selects the HD66732: low: HD66732 is selected and can be accessed high: HD66732 is not selected and cannot be accessed must be fixed at gnd level when not in use. rs 1 i mpu selects the register for a parallel bus interface. low: instruction high: ram access selects the key scan interrupt method in the standby period for a serial interface. monitors a total of eight keys connected to kst0 at the gnd level and monitors all keys at the vcc level to generate an interrupt. must be fixed at the gnd or vcc level. e/wr*/scl 1 i mpu inputs the serial transfer clock for a serial interface. fetches data at the rising edge of a clock. for a 68-system parallel bus interface, serves as an enable signal to activate data read/write operation. for an 80-system parallel bus interface, serves as a write strobe signal and writes data at the low level. rw/rd*/ sda 1 i or i/o mpu serves as the bidirectional serial transfer data for a serial interface. sends/receives data. for a 68-system parallel bus interface, serves as a signal to select data read/write operation. for an 80-system parallel bus interface, serves as a write strobe signal and reads data at the low level. irq* 1 o mpu generates the key scan interrupt signal. kst0 kst3 4 o key matrix generates strobe signals for latching scanned data from the key matrix at specific time intervals. available for a serial interface only. db0/kin0 db7/kin7 8 i or i/o key matrix or mpu samples key state from key matrix synchronously with strobe signals for a serial interface. serves as a bidirectional data bus for a parallel bus interface. for a 4-bit bus, data transfer uses kin7/db7- kin4/db4; leave kin3/db3-kin0/db0 disconnected.
HD66732 13 table 2 pin functional description (cont) signals number of pins i/o connected to functions port0 port2 3 o general output general output ports. these ports cannot drive current such as for leds or backlighting control. boost the current using an external transistor. coms1/2, coms2/1 2 o lcd common output signals for segment-icon display. com1/52 com52/1 52 o lcd common output signals for character/graphics display: com1 to com13 for the first line, com14 to com26 for the second line, com27 to com39 for the third line, and com40 to com52 for the fourth line. all the unused pins output unselected waveforms. in the sleep mode (slp = 1) or standby mode (stb = 1), all pins output gnd level. the cms bit can change the shift direction of the common signal. for example, if cms = 0, com1/52 is com1. if cms = 1, com1/52 is com52. seg1/120 seg120/1 120 o lcd segment output signals for segment-icon display and character/graphics display. in the sleep mode (slp = 1) or standby mode (stb = 1), all pins output gnd level. the sgs bit can change the shift direction of the segment signal. for example, if sgs = 0, seg1/120 is seg1. if sgs = 1, seg1/120 is seg120. v1out v5out 10 i or o open or external bleeder-resistor used for output from the internal operational amplifiers when they are used (opoff = gnd); attach a capacitor to stabilize the output. when the amplifiers are not used (opoff = v cc ), v1 to v5 voltages can be supplied to these pins externally. v lcd 3 power supply power supply for lcd drive. v lcd ?gnd = 13 v max. v cc , gnd 7 power supply v cc : +2.4 v to +5.5 v; gnd (logic): 0 v osc1, osc2 2 i or o oscillation- resistor or clock for r-c oscillation using an external resistor, connect an external resistor. for external clock supply, input clock pulses to osc1. vci 3 i power supply inputs a reference voltage and supplies power to the booster; generates the liquid crystal display drive voltage from the operating voltage. must be left disconnected when the booster is not used. vlout 3 o v lcd pin/booster capacitance potential difference between vci and gnd is single- to quadruple-boosted and then output. magnitude of boost is selected by instruction. c1+, c1 8 booster capacitance external capacitance should be connected here when using the double, triple, or quadruple booster. c2+, c2 8 booster capacitance external capacitance should be connected here when using the triple or quadruple booster. c3+, c3 8 booster capacitance external capacitance should be connected here when using the quadruple booster.
HD66732 14 table 2 pin functional description (cont) signals number of pins i/o connected to functions reset* 1 i mpu or external r-c circuit reset pin. initializes the lsi when low. must be reset after power-on. opoff 1 i v cc or gnd turns the internal operational amplifier off when opoff = v cc , and turns it on when opoff = gnd. if the amplifier is turned off (opoff = v cc ), v1 to v5 must be supplied to the v1out to v5out pins. vccdum 1 o input pins outputs the internal v cc level; shorting this pin sets the adjacent input pin to the v cc level. gnddum 1 o input pins outputs the internal gnd level; shorting this pin sets the adjacent input pin to the gnd level. test 1 i gnd test pin. must be fixed at gnd level. vtest1 1 i vcc or gnd adjust the driving ability of the internal lcd operational amplifier. normal drive mode in the gnd side, and high-power drive mode in the vcc side. use the high-power drive mode when the display quality is insufficient although current consumption increases. vtest2 1 test pin. must be open. vtest3 1 i vcc or gnd adjust the driving ability of the internal lcd operational amplifier. normal drive mode or high-power drive mode in the gnd side, and low-power drive mode in the vcc side.
HD66732 15 block function description system interface the HD66732 has five types of system interfaces, and a clock-synchronized serial interface, a 68-system 4- bit/8-bit bus, and a 80-system 4-bit/8-bit bus. the interface mode is selected by the im2-0 pins. the key scan of the HD66732 is not available for the 4-bit/8-bit bus interface. instead, use the clock-synchronized serial interface. the HD66732 has five 8-bit registers: an index register (ir), a status register (sr), control registers, a ram address register, and a ram data register. the ir specifies the index address of the register to be accessed. the sr reads the key scan data in the serial interface mode, and the internal states in the bus interface mode. control registers (cnrs) set instructions such as clear display or display control. the ram address register and ram data register store the addresses or data of the display data ram (ddram), character generator ram (cgram), or segment ram (segram). data written into the ram data register from the mpu is automatically written into the ddram, cgram, or segram by internal operation. data is read and temporarily latched in the ram data register when reading from the ram, and the first read data is invalid and the second data is normal. after reading, data in the ddram, cgram, or segram at the next address is sent to the ram data register for the next reading from the mpu. execution time for instructions, excluding clear display, is 0 clock cycles and instructions can be written in succession. table 3 register selection by rs and r/w bits r/w bits rs bits operations 0 0 writes to the index register (ir) 1 0 reads the status register (sr) 0 1 writes to the control register, ram address register, and ram data register 1 1 reads the ram data register
HD66732 16 key scan registers (scan0 to scan3) the key matrix scanner senses and holds the key states at each rising edge of the key strobe signals that are output by the HD66732. the key strobe signals are output as time-multiplexed signals from kst0 to kst3. after passing through the key matrix, these strobe signals are used to sample the key status on eight inputs from kin0 to kin7, enabling up to 32 keys to be scanned. the states of inputs kin0 to kin7 are sampled by key strobe signal kst0 and latched into register scan0. similarly, the data sampled by strobe signals kst1 to kst3 is latched into registers scan1 to scan3, respectively. general output ports (port0 to port 2) the HD66732 has three general output ports. these ports control drive current such as that for leds or backlighting by using the current boosted by an external transistor. address counter (ac) the address counter (ac) assigns addresses to the ddram, cgram, or segram. when an address is written into the ram address register, the address information is sent to the ac. selection of the ddram, cgram, and segram is also determined concurrently by the ram select bit (rm1/0). after writing data into ddram, cgram, or segram, the ac is automatically incremented by 1 (or decremented by 1). after reading the data, the ac is automatically updated or not updated by the rdm bit. the cursor display position is determined by the address counter value. display data ram (ddram) display data ram (ddram) stores display data represented in 8-bit character codes in the character display mode. its capacity is 80 x 8 bits, or 80 characters, which is equivalent to an area of 10 characters x 4 lines. any number of display lines (lcd drive duty ratio) from 1 to 4 can be selected by software. here, assignment of ddram addresses is the same for all display modes. the line to be displayed at the top of the display (display-start line) can also be selected by register settings. the graphics display mode does not use data in the ddram. full-size character generator rom (fcgrom) full-size character generator rom (fcgrom) generates 11 x 12-dot character patterns from 13-bit character codes. it is equipped with 8,128 full-size font patterns such as the jis level-1 and level-2 kanji set or non-kanji set. for the relationships between jis codes and character codes to be set in the ddram, see the combined display of full-size and half-size characters section.
HD66732 17 half-size character generator rom (hcgrom) half-size character generator rom (hcgrom) generates 6 x 12-dot character patterns from 7-bit character codes. it is equipped with two banks of 128 half-size font patterns, and 256 half-size fonts in total. for details, see the combined display of full-size and half-size characters section and the display attribute designation section. character generator ram (cgram) character generator ram (cgram) allows the user to redefine the character patterns in the character display mode. up to 40 character patterns of 12 x 13-dot characters can be simultaneously displayed. dram-specified character code can be selected to display one of these user font patterns. the cgram serves as a ram to store 120 x 52-dot bit pattern data in the graphics display mode. here, display patterns are directly written into cgram. character codes set in the ddram are not used. for details, see the character display functions and graphics display functions section. segment ram (segram) the segment ram (segram) is used to enable control of segments such as icons and marks through the user program. segments and characters are driven by a multiplexing drive method. the segram has a capacity of 120 x 4 bits, and can control a display of up to 200 icon segments. since 40 segments can be controlled by grayscale. while coms1 and coms2 outputs are being selected, 120 segments are driven. the 40 grayscale-controlled segments output the same display data in both the coms1 drive and coms2 drive modes. bits in the segram corresponding to segments to be displayed are set directly by the mpu, regardless of the contents of the ddram and cgram. timing generator the timing generator generates timing signals for the operation of internal circuits such as ddram, cgrom, cgram, and segram. the ram read timing for display and internal operation timing by mpu access are generated separately to avoid interference with one another. this prevents flickering in areas other than the display area when writing data to ddram, for example. cursor/blink controller the cursor/blink (or black-white reversed) control is used to create a cursor or a flashing area on the display in a position corresponding to the location stored in the address counter (ac).
HD66732 18 cursor position display position ddram address note: the cursor/blink or black-white reversed control is also active when the address counter indicates the cgram or segram. however, it has no effect on the display. 12345678 11 910 12 00 01 02 03 04 05 06 07 0a 08 09 0b figure 2 cursor position and ddram address oscillation circuit (osc) the HD66732 can provide r-c oscillation simply through the addition of an external oscillation-resistor between the osc1 and osc2 pins. the appropriate oscillation frequency for operating voltage, display size, and frame frequency can be obtained by adjusting the external-resistor value. clock pulses can also be supplied externally. since r-c oscillation stops during the standby mode, current consumption can be reduced. for details, see the oscillation circuit section. liquid crystal display driver circuit the liquid crystal display driver circuit consists of 54 common signal drivers (com1 to com52, coms1, and coms2) and 120 segment signal drivers (seg1 to seg120). when the number of lines are selected by a program, the required common signal drivers automatically output drive waveforms, while the other common signal drivers continue to output unselected waveforms. character pattern data is sent serially through a 120-bit shift register and latched when all needed data has arrived. the latched data then enables the segment signal drivers to generate drive waveform outputs. the shift direction of 120-bit data can be changed by the sgs bit. the shift direction for the common driver can also be changed by the cms bit by selecting an appropriate direction for the device mounting configuration. when multiplexing drive is not used, or during the standby or sleep mode, all the above common and segment signal drivers output the gnd level, halting the display. booster (dc-dc converter) the booster doubles, triples, or quadruples a voltage input to the vci pin. with this, both the internal logic units and lcd drivers can be controlled with a single power supply. boost output level from single to quadruple boost can be selected by software. for details, see the power supply for liquid crystal display drive section.
HD66732 19 v-pin voltage follower a voltage follower for each voltage level (v1 to v5) reduces current consumption by the lcd drive power supply circuit. no external resistors are required because of the internal bleeder-resistor, which generates different levels of lcd drive voltage. this internal bleeder-resistor can be software-specified from 1/2 bias to 1/8 bias, according to the liquid crystal display drive duty value. the voltage followers can be turned off while multiplexing drive is not being used. for details, see the power supply for liquid crystal display drive section. contrast adjuster the contrast adjuster can be used to adjust lcd contrast in 32 steps by varying the lcd drive voltage by software. this can be used to select an appropriate lcd brightness or to compensate for temperature.
HD66732 20 ddram address map table 4 ddram addresses and display positions display line display character (half size) "00" 123456789101112 1st 2nd 3rd 4th "40" "60" "01" "41" "61" "02" "42" "62" "03" "43" "63" "04" "44" "64" "05" "45" "65" "06" "46" "66" "07" "47" "67" "08" "48" "68" "09" "49" "69" "0a" "4a" "6a" "0b" "4b" "6b" 13 "0c" "4c" "6c" 14 "0d" "4d" "6d" 15 "0e" "4e" "6e" 16 "0f" "4f" "6f" 17 18 19 20 "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "2a" "2b" "2c" "2d" "2e" "2f" "10" "50" "70" "30" "11" "51" "71" "31" "12" "52" "72" "32" "13" "53" "73" "33" note: when sgs = 0, seg1/120 to seg6/115 appear at the first character at the extreme left of the screen. when sgs = 1, seg120/1 to seg115/6 appear at the first character at the extreme left of the screen. table 5 display-line modes, display-start line, and ddram addresses display-start lines display- line mode duty ratio common pins 1st line (sn = 00) 2nd line (sn = 01) 3rd line (sn = 10) 4th line (sn = 11) 1-line (nl = 001) 1/15 com1 com13 00h?3h 20h?3h 40h?3h 60h?3h 2-line (nl = 010) 1/28 com1 com13 00h?3h 20h?3h 40h?3h 60h?3h com14 com26 20h?3h 40h?3h 60h?3h 00h?3h 3-line (nl = 011) 1/41 com1 com13 00h?3h 20h?3h 40h?3h 60h?3h com14 com26 20h?3h 40h?3h 60h?3h 00h?3h com27 com39 40h?3h 60h?3h 00h?3h 20h?3h 4-line (nl = 100) 1/54 com1 com13 00h?3h 20h?3h 40h?3h 60h?3h com14 com26 20h?3h 40h?3h 60h?3h 00h?3h com27 com39 40h?3h 60h?3h 00h?3h 20h?3h com40 com52 60h?3h 00h?3h 20h?3h 40h?3h
HD66732 21 cgram address map table 6 relationship between character code in character display mode (gr = spr = 0) and cgram address 000?0b 100?0b 00c?17 10c?17 018?23 118?23 024?2f 124?2f 030?3b 130?3b 03c?47 13c?47 048?53 148?53 054?5f 154?5f 060?6b 160?6b 06c?77 16c?77 "0000" "0001" "0002" "0003" "0004" "0005" "0006" "0007" "0008" "0009" character code 200?0b 20c?17 218?23 224?2f 230?3b 23c?47 248?53 254?5f 260?6b 26c?77 300?0b 30c?17 318?23 324?2f 330?3b 33c?47 348?53 354?5f 360?6b 36c?77 400?0b 40c?17 418?23 424?2f 430?3b 43c?47 448?53 454?5f 460?6b 46c?77 cgram address db0 db1 db2 db3 db4 db5 db6 db7 db0 db1 db2 db3 db4 100?0b 10c?17 118?23 124?2f 130?3b 13c?47 148?53 154?5f 160?6b 16c?77 "0010" "0011" "0012" "0013" "0014" "0015" "0016" "0017" "0018" "0019" character code cgram address db5 db6 db7 db0 db1 db2 db3 db4 db5 db6 db7 db0 db1 300?0b 30c?17 318?23 324?2f 330?3b 33c?47 348?53 354?5f 360?6b 36c?77 character code cgram address db2 db3 db4 db5 db6 db7 db0 db1 db2 db3 db4 db5 db6 "1000" "1001" "1002" "1003" "1004" "1005" "1006" "1007" "1008" "1009" 400?0b 40c?17 418?23 424?2f 430?3b 43c?47 448?53 454?5f 460?6b 46c?77 character code cgram address db7 db0 db1 db2 db3 db4 db5 db6 db7 db0 db1 db2 db3 "1010" "1011" "1012" "1013" "1014" "1015" "1016" "1017" "1018" "1019" 500?0b 50c?17 518?23 524?2f 530?3b 53c?47 548?53 554?5f 560?6b 56c?77 600?0b 60c?17 618?23 624?2f 630?3b 63c?47 648?53 654?5f 660?6b 66c?77 1. in the character display mode (gr = spr = 0), rm1/0 = 10 is set and cgram is used. 2. in the character display mode (gr = spr = 0), the cgram font pattern is displayed using character codes set to the ddram as per the above table. in the graphics display mode (gr = 1 and spr = 0) or super-imposed mode (spr = 1), the cgram data is displayed irrespective of the ddram set data (character code). 3. the least significant bit (lsb) of the write data is displayed on the first line. 4. the 13th raster-row is the cursor position and its display is formed by a logical or with the cursor. 5. a set bit in cgram data 1 corresponds to display selection (lit) and 0 to non-selection (unlit). notes:
HD66732 22 table 7 relationship between display position and cgram address in graphics display mode (gr = 1, spr = 0) and super-imposed display mode (spr = 1) db0 000 db1 db2 db3 db4 db5 db6 db7 001 002 003 004 005 006 007 008 009 00a 00b 00c00d00e 00f 010 076 077 075 074 073 com1 com2 com3 com4 com5 com6 com7 com8 seg1/120 seg2/119 seg3/118 seg4/117 seg5/116 seg6/115 seg7/114 seg8/113 seg9/112 seg10/111 seg11/110 seg12/109 seg13/108 seg14/107 seg15/106 seg16/105 seg17/104 seg116/5 seg117/4 seg118/3 seg119/2 seg120/1 1 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 00 0 0 0 0 0 0 0 0 00 00 00 00 0 000 0 0 0 0 0 0 0 0 0 0 0 0 0 000 00 00 00 00 0 00 0 00 0 000 segment driver common segment (hex) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 10 0 000000 00 0 00 0 000 00 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sgs=0 sgs=1 077 076 075 074 073 072 071 070 06f 06e06d06c06b 06a 069 068 067 001 000 002 003 004 100 101 102 103 104 105 106 107 108 109 10a 10b 10c10d10e 10f 110 176 177 175 174 173 (hex) sgs=0 sgs=1 177 176 175 174 173 172 171 170 16f 16e 16d16c16b 16a 169 168 167 101 100 102 103 104 com9 com16 db0 db7 200 201 202 203 204 205 206 207 208 209 20a 20b 20c20d20e 20f 210 276 277 275 274 273 (hex) sgs=0 sgs=1 277 276 275 274 273 272 271 270 26f 26e 26d26c26b 26a 269 268 267 201 200 202 203 204 com17? com24 db0 db7 300 301 302 303 304 305 306 307 308 309 30a 30b 30c30d30e 30f 310 376 377 375 374 373 (hex) sgs=0 sgs=1 377 376 375 374 373 372 371 370 36f 36e 36d36c36b 36a 369 368 367 301 300 302 303 304 com25 com32 db0 db7 400 401 402 403 404 405 406 407 408 409 40a 40b 40c40d40e 40f 410 476 477 475 474 473 (hex) sgs=0 sgs=1 477 476 475 474 473 472 471 470 46f 46e 46d46c46b 46a 469 468 467 401 400 402 403 404 com33 com40 db0 db7 500 501 502 503 504 505 506 507 508 509 50a 50b 50c50d50e 50f 510 576 577 575 574 573 (hex) sgs=0 sgs=1 577 576 575 574 573 572 571 570 56f 56e 56d56c56b 56a 569 568 567 501 500 502 503 504 com41 com48 db0 db7 600 601 602 603 604 605 606 607 608 609 60a 60b 60c60d60e 60f 610 676 677 675 674 673 (hex) sgs=0 sgs=1 677 676 675 674 673 672 671 670 66f 66e 66d66c66b 66a 669 668 667 601 600 602 603 604 com49 db0 db1 db2 db3 com50 com51 com52 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 address address address address address address address notes: 1. when the rm1/0 bit is set to "10", the cgram can be selected. 2. in the graphics display mode (gr = 1 and spr = 0) and super-imposed display mode (spr = 1), the cgram data is displayed irrespective of the ddram set data. 3. writing to the upper four bits (db4?b7) in cgram addresses 600h?77h is invalid. 4. a set bit in cgram 1 corresponds to display selection (lit) and 0 to non-selection (unlit).
HD66732 23 segram address map table 8 relationship between segram address and screen display position db0 000 db1 db2 db7 001 002 003 004 005 006 007 008 009 00a 00b 00c00d00e 00f 010 076 077 075 074 073 coms1 seg1/120 seg2/119 seg3/118 seg4/117 seg5/116 seg6/115 seg7/114 seg8/113 seg9/112 seg10/111 seg11/110 seg12/109 seg13/108 seg14/107 seg15/106 seg16/105 seg17/104 seg116/5 seg117/4 seg118/3 seg119/2 seg120/1 segment driver (hex) common segment db3 db4 db5 db6 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 077 076 075 074 073 072 071 070 06f06e 06d06c 06b06a 069 068 001 000 002 003 004 067 sgs=0 sgs=1 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * (invalid area) coms2 address notes: 1. when the rm1/0 bit is set to "11", the segram can be selected. 2. writing to the lower four bits (db0?b3) in the segram is invalid. 3. the segment output that can be controlled by grayscale is enabled for only the 40 segments (table 9). these grayscale-controlled segments are driven by the same grayscale data at coms1 and coms2 selection. 4. other outputs than the grayscale-controlled segment outputs can control segment on/off and blinking. the coms1 and coms2 outputs are independently controlled. table 9 relationship between segment driver output pin and segment display function when sgs = 0 when sgs = 1 remarks seg1/120, seg4/117, seg7/114, seg10/111, seg13/108, seg16/105, seg19/102, seg22/99, seg25/96, seg28/93, seg31/90, seg34/87, seg37/84, seg40/81, seg43/78, seg46/75, seg49/72, seg52/69, seg55/66, seg58/63, seg61/60, seg64/57, seg67/54, seg70/51, seg73/48, seg76/45, seg79/42, seg82/39, seg85/36, seg88/33, seg91/30, seg94/27, seg97/24, seg100/21, seg103/18, seg106/15, seg109/12, seg112/9, seg115/6, seg118/3 seg120/1, seg117/4, seg114/7, seg111/10, seg108/13, seg105/16, seg102/19, seg99/22, seg96/25, seg93/28, seg90/31, seg87/34, seg84/37, seg81/40, seg78/43, seg75/46, seg72/49, seg69/52, seg66/55, seg63/58, seg60/61, seg57/64, seg54/67, seg51/70, seg48/73, seg45/76, seg42/79, seg39/82, seg36/85, seg33/88, seg30/91, seg27/94, seg24/97, seg21/100, seg18/103, seg15/106, seg12/109, seg9/112, seg6/115, seg3/118 the coms1 and coms2 outputs are controlled by the same grayscale. total: 40 segments output pins other than above output pins other than above the coms1 and coms2 outputs are independently controlled. total: 80 x 2 = 160 segments
HD66732 24 table 10 relationship between segram data and grayscale-controlled segment display segram data db7 db6 db5 db4 effective applied voltage for coms1 and coms2 output 00000 (always unlit) 00011 (always lit) 0010 0.34 (grayscale display) 0011 0.38 (grayscale display) 0100 0.41 (grayscale display) 0101 0.44 (grayscale display) 0110 0.47 (grayscale display) 0111 0.50 (grayscale display) 1000 (blink display)* 1001 0.53 (grayscale display) 1010 0.56 (grayscale display) 1011 0.59 (grayscale display) 1100 0.63 (grayscale display) 1101 0.66 (grayscale display) 1110 0.69 (grayscale display) 1111 0.72 (grayscale display) notes: 1. for details, see the reflective color mark/blink mark display section. 2. blinking is provided by repeatedly turning on the segment for 32 frames and turning it off for the next 32 frames. table 11 relationship between segram data and blinking segment display (1) segram data db5 db4 lcd display control for coms1 segment 0 0 always unlit 0 1 always lit 1 0 blinking display (32-frame unit) 1 1 double-speed blinking display (16-frame unit)
HD66732 25 table 12 relationship between segram data and blinking segment display (2) segram data db7 db6 lcd display control for coms2 segment 0 0 always unlit 0 1 always lit 1 0 blinking display (32-frame unit) 1 1 double-speed blinking display (16-frame unit)

HD66732 34 table 15 a00 standard half-size font pattern (rom bank 0 (rom = 0) lower 0123456789abcdef rom upper 000123456789 01 02 space 03 04 05 06 07 table 16 a00 standard half-size font pattern (rom bank 1 (rom = 1) lower 0123456789abcdef rom upper 000123456 789 01 02 space 03 04 abcdefgh i jklmno 05pqrstuvwxyz 06#abcde f gh i j k ^_ lmno 07pqrstuvwxyz
HD66732 35 HD66732 cgrom character pattern write 1. when using two 1-m eproms (for full size) + one 32-k eprom (for half size) 1.1 full-size character (level-1 kanji set, non-kanji) (fcgrom-1) 11 x 12 dots, up to 4064 types (not including 32 types of cgram (character code: 0000 to 001f)) eprom: hn27c101g/ag x one divide the character pattern into six left-half dots (a16 = 0) and five right-half dots (a16 = 1) eprom addresses a16 to a 0 designate the "left/right distinction bit + full-size character code (c11 to c0) + line position" (not using c12 of a full-size character code) write "0" into i/0s 7 and 6 of the left-half character pattern (a16 = 0) write "0" into i/0s 7, 6 and 5 of the right-half character pattern (a16 = 1) when a3, a2, a1, or a0 = $c to $f (1100 to 1111), write "0" into i/os 7 to 0 write "0" into $0 to $1ff and $10000 to $101ff (corresponding to the cgram character codes 0000 to 001f) (the data of $0 to $1ff, and $10000 to $101ff are ignored) table 17 fcgrom-1 write (1) i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 54321043210 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 0000 01000010100 0001 00101111111 0010 00000010100 0011 10001111111 0100 01001001001 0101 00001111111 0110 00000001000 0111 00101111111 1000 00100001000 1001 01001111111 1010 01000010100 1011 10001100011 1100 00000000000 1101 00000000000 1110 00000000000 1111 00000000000 character code (c11 to c0) line position character pattern note: for character codes (c12 to c0), 0000 to 001f are used as cgram codes, and eprom addresses $0 to $1ff and the data of $10000 to $101ff are ignored. fcgrom-1 a16 = 0 (left) a16 = 1 (right) eprom address data
HD66732 36 1.2 full-size character (level-2 kanji set) (fcgrom-2) [the same as a full-size character (level-1 kanji set, non-kanji) (fcgrom-1)] 11 x 12 dots, up to 4064 types (not including 32 types of cgram (character code: 1000 to 101f)) eprom: hn27c101g/ag x one divide the character pattern into six left-half dots (a16 = 0) and five right-half dots (a16 = 1) eprom addresses a16 to a 0 designate the "left/right distinction bit + full-size character code (c11 to c0) + line position" (not using c12 of a full-size character code) write "0" into i/0s 7 and 6 of the left-half character pattern (a16 = 0) write "0" into i/0s 7, 6 and 5 of the right-half character pattern (a16 = 1) when a3, a2, a1, or a0 = $c to $f (1100 to 1111), write "0" into i/os 7 to 0 write "0" into $0 to $1ff and $10000 to $101ff (corresponding to the cgram character codes 1000 to 101f) (the data of $0 to $1ff, and $10000 to $101ff are ignored) table 18 fcgrom-2 write (1) i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 54321043210 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 0000 00000100100 0001 00000100010 0010 00000010000 0011 11111111110 0100 00000010000 0101 00000001000 0110 01111001000 0111 00000001000 1000 00000000100 1001 00011100100 1010 11100000101 1011 00000000011 1100 00000000000 1101 00000000000 1110 00000000000 1111 00000000000 character code (c11 to c0) line position character pattern note: for character codes (c12 to c0), 1000 to 101f are used as cgram codes, and eprom addresses $0 to $1ff and the data of $10000 to $101ff are ignored. fcgrom-1 a16 = 0 (left) a16 = 1 (right) eprom address data
HD66732 37 1.3 half-size character (hcgrom) 6 x 12 dots, up to 256 types (128 types x 2 banks) eprom: an eprom with 512 bytes or more capacity, such as the hn27c256ag eprom addresses a11 to a0 designate the "half-size cgrom bank bit (bk) + half-size character code (c6 to c0) + line position" write "0" into the rightmost bit as a character space (i/o 0 = 0) write "0" into i/os 7 and 6 when a3, a2, a1, or a0 = $c to $f (1100 to 1111), write "0" into i/os 7 to 0 table 19 hcgrom write hcgrom a16 = 0 eprom address data i/o i/o i/o i/o i/o i/o a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 543210 bk c6 c5 c4 c3 c2 c1 c0 0000 011110 j 0001 000100 0010 000100 0011 000100 0100 000100 0101 000100 0110 000100 0111 000100 1000 000100 1001 100100 1010 100100 1011 011000 1100 000000 1101 000000 1110 000000 1111 000000 half-size cgrom bank bit character code (c6 to c0) line position character pattern "0" space * relationship between HD66732 full-size character codes and jis codes table 20 full-size character codes and jis codes ?full-size character codes 0 a1 a2 c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 b7 b6 b5 0 a7a6b3b2b1 0 0 a5a4a3a2a1 0 1 0 0 b7b4b3b2b1a7a6a5a4a3a2a1 0 1 1 0 b7b4b3b2b1a7a6a5a4a3a2a1 1 0 0 1 b6b4b3b2b1a7a6a5a4a3a2a1 1 0 1 1 b6b4b3b2b1a7a6a5a4a3a2a1 1 1 0 1 a7a6b3b2b1 0 0 a5a4a3a2a1 1 1 1 u60000000u5u4u3u2u1 user font (cgram) ?jis codes b7 b6 b5 b4 b3 b2 b1 a7 a6 a5 a4 a3 a2 a1 jis first byte jis second byte ?character codes for cgram (40 characters) ?0000 to 0009 ?0010 to 0019 ?1000 to 1009 ?1010 to 1019 (codes for 24 remaining characters are reserved.)
HD66732 38 2. when using one 4-m eprom 2.1 full-size character (level-1 kanji set, non-kanji) (fcgrom-1) 11 x 12 dots, up to 4064 types (not including 32 types of cgram (character code: 0000 to 001f)) eprom: hn27c4001g x one (address: $0 to $1ffff) divide character pattern into six left-half dots (a16 = 0) and five right-half dots (a16 = 1) eprom addresses a18 to a 0 designate the "0 + full-size character code (c12) + left/right distinction bit + full-size character code (c11 to c0) + line position" (c12 of the full-size character code is used as an eprom address a17) write "0" into i/0s 7 and 6 of the left-half character pattern (a16 = 0) write "0" into i/0s 7, 6 and 5 of the right-half character pattern (a16 = 1) when a3, a2, a1, or a0 = $c to $f (1100 to 1111), write "0" into i/os 7 to 0 write "0" into $0 to $1ff, and $10000 to $101ff (corresponding to the cgram character codes 0000 to 001f) (the data of $0 to $1ff, and $10000 to $101ff are ignored) table 21 fcgrom-1 write (2) fcgrom-1 (*) a16 = 0 (left) (*) a16 = 1 (right) eprom address data i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 54321043210 0 c12 (*) c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 0000 01000010100 0001 00101111111 0010 00000010100 0011 10001111111 0100 01001001001 0101 00001111111 0110 00000001000 0111 00101111111 1000 00100001000 1001 01001111111 1010 01000010100 1011 10001100011 1100 00000000000 1101 00000000000 1110 00000000000 1111 00000000000 character code (c11 to c0) line position character pattern note: for character codes (c12 to c0), 0000 to 001f are used as cgram codes, and eprom addresses $0 to $1ff and the data of $10000 to $101ff are ignored.
HD66732 39 2.2 full-size character (level-2 kanji set) (fcgrom-2) 11 x 12 dots, up to 4064 types (not including 32 types of cgram (character code: 1000 to 101f)) eprom: hn27c4001g x one (address: $20000 to $3ffff) divide character pattern into six left-half dots (a16 = 0) and five right-half dots (a16 = 1) eprom addresses a18 to a 0 designate the "0 + full-size character code (c12) + left/right distinction bit + full-size character code (c11 to c0) + line position" (c12 of the full-size character code is used as eprom address a17) write "0" into i/0s 7 and 6 of the left-half character pattern (a16 = 0) write "0" into i/0s 7, 6 and 5 of the right-half character pattern (a16 = 1) when a3, a2, a1, or a0 = $c to $f (1100 to 1111), write "0" into i/os 7 to 0 write "0" into $0 to $1ff, and $10000 to $101ff (corresponding to the cgram character codes 1000 to 101f) (the data of $0 to $1ff, and $10000 to $101ff are ignored) table 22 fcgrom-2 write (2) i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 54321043210 0 c12 (*) c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 0000 00000100100 0001 00000100010 0010 00000010000 0011 11111111110 0100 00000010000 0101 00000001000 0110 01111001000 0111 00000001000 1000 00000000100 1001 00011100100 1010 11100000101 1011 00000000011 1100 00000000000 1101 00000000000 1110 00000000000 1111 00000000000 character code (c12) character code (c11 to c0) line position character pattern note: for character codes (c12 to c0), 1000 to 101f are used as cgram codes, and eprom addresses $20000 to $201ff and the data of $30000 to $301ff are ignored. fcgrom-2 (*) a16 = 0 (left) (*) a16 = 1 (right) eprom address data
HD66732 40 2.3 half-size character (hcgrom) 6 x 12 dots, up to 256 types (128 types x 2 banks) eprom: hn27c4001g x one (address: $40000 to $40fff) eprom addresses a18 to a0 designate the "$40 + half-size cgrom bank bit (bk) + half-size character code (c6 to c0) + line position" write "0" into the rightmost bit as a character space (i/o 0 = 0) write "0" into i/os 7 and 6 when a3, a2, a1, or a0 = $c to $f (1100 to 1111), write "0" into i/os 7 to 0 table 23 hcgrom write (2) hcgrom a16 = 0 eprom address data i/o i/o i/o i/o i/o i/o a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 543210 1000000 bk c6 c5 c4 c3 c2 c1 c0 0000 011110 j 0001 000100 0010 000100 0011 000100 0100 000100 0101 000100 0110 000100 0111 000100 1000 000100 1001 100100 1010 100100 1011 011000 1100 000000 1101 000000 1110 000000 1111 000000 half-size cgrom bank bit character code (c6 to c0) line position character pattern "0" space table 24 4-m eprom address 4-m eprom address a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 hex. level 1 (left) 0000000000000000000 0 kanji ?????? set + 0001111111111111111 ffff non- (right) 0010000000000000000 10000 kanji ?????? 0011111111111111111 1ffff (left) 0100000000000000000 20000 level 2 ?????? kanji 0101111111111111111 2ffff set (right) 0110000000000000000 30000 ?????? 0111111111111111111 3ffff bk = 0 1000000000000000000 40000 half- (bank 0) ?????? size 1000000011111111111 407ff font bk = 1 1000000000000000000 40800 (bank 1) ?????? 1000000011111111111 40fff
HD66732 41 instruction registers outline the HD66732 consists of the following five types of register: index register (ir): selects control registers, ram addresses, or data registers status register (sr): reads the internal state or key scan data control registers (r0?c): set the display control or key scan control ram address registers (rd and re): select rams and set ram addresses ram data register (rf): receives the write and read data for the ram normally, instructions that transfer display data are used the most. however, auto-incrementation by 1 (or auto-decrementation by 1) of internal HD66732 ram addresses after each data write can reduce the mpu program load. because instructions other than the clear-display instruction are executed in 0 cycles, instructions can be written in succession. while the clear-display instruction is being executed for internal operation, or during reset, no instruction other than the sr read instruction can be executed.
HD66732 42 instruction descriptions index register (ir) the index register designates control registers (r0 to rc), ram address registers (rd and re), and ram data register (rf). the register index value must be set between addresses 0000 to 1110. r/w rs db7 db0 10 db6 db5 db4 db3 db2 db1 0 0 0 0 id3 id2 id1 id0 ir: figure 3 index register instruction status register (sr) the status register reads the busy flag (bf), lcd-driven display lines (nf1/0), and display raster-rows (lf3 to lf0). in a serial interface, the sr reads the key scan data in key scan registers scan0 to scan3. after the start byte has been transferred, the sr starts reading from scan0, then scan1, scan2, and scan3. after scan3 has been read, scan0 is read again. for details, see the key scan control section. r/w rs db7 db0 10 db6 db5 db4 db3 db2 db1 lf3 lf2 lf1 lf0 0 nf0 nf1 bf 10 sd3 sd2 sd1 sd0 sd4 sd5 sd6 sd7 (bus interface) (serial interface) sr: sr: figure 4 status register instruction table 25 display line position nf1 nf0 display line position 0 0 displaying the 1st line 0 1 displaying the 2nd line 1 0 displaying the 3rd line 1 1 displaying the 4th line
HD66732 43 table 26 display raster-row position lf3 lf2 lf1 lf0 display raster-row position 0000 displaying the 1st raster-row 0001 displaying the 2nd raster-row 0010 displaying the 3ed raster-row 0011 displaying the 4th raster-row 0100 displaying the 5th raster-row 0101 displaying the 6th raster-row 1011 displaying the 12th raster-row 1100 displaying the 13th raster-row clear display (r0) the clear display instruction writes half-size space code a0h (half-size hcrom for character code a0h must be a blank pattern) into all ddram addresses. it then sets ddram address 0 into the address counter (ac). it also sets i/d to 1 (increment mode) in the entry mode set instruction. since the execution time of this instruction needs 85 clock cycles, do not transfer the next instruction during this time. r/w rs db7 db0 01 db6 db5 db4 db3 db2 db1 00000001 r0: figure 5 clear display instruction start oscillation (r1) the start oscillation instruction restarts the oscillator from the halt state in the standby mode. after issuing this instruction, wait at least 10 ms for oscillation to stabilize before issuing the next instruction. (see the standby mode section.) r/w rs db7 db0 01 db6 db5 db4 db3 db2 db1 00000001 r1: figure 6 start oscillation instruction
HD66732 44 driver output control (r2) nl2-0: specify the display lines. display lines change the liquid crystal display drive duty ratio. ddram address mapping does not depend on the number of display lines. cen: switches the com1 output start position. when cen = 1, it shifts com1 by one line (13 raster- rows) and outputs com1 from the center of the screen (the second line). for details, see the partial- display-on function section. cms: selects the output shift direction of a common driver. when cms = "0", com1/52 shifts to com1, and com52/1 to com52. when cms = "1", com1/52 shifts to com52, and com52/1 to com1. output position of a common driver shifts depending on the cen bit setting. for details, see the display on/off control section. sgs: selects the output shift direction of a segment driver. when sgs = "0", seg1/120 shifts to seg1, and seg120/1 to seg120. when sgs = "1", seg1/120 shifts seg120, and seg120/1 to seg1. r/w rs db7 db0 01 db6 db5 db4 db3 db2 db1 0 nl2 nl1 nl0 0 cen cms sgs r2: figure 7 driver output control instruction table 27 nl bits and display lines nl2 nl1 nl0 display lines liquid crystal display drive duty ratio common driver used 0 0 0 segment display 1/2 duty coms1, coms2 0 0 1 one character line + segment display 1/15 duty com1?3, coms1, coms2 0 1 0 two character lines + segment display 1/28 duty com1?6, coms1, coms2 0 1 1 three character lines + segment display 1/41 duty com1?9, coms1, coms2 1 0 0 four character lines + segment display 1/54 duty com1?2, coms1, coms2
HD66732 45 lcd driving wave (r3) b/c: specifies the lcd alternating method. when b/c = "0", a b-pattern waveform is generated and alternates in every frame. when b/c = "1", a c-pattern waveform is generated and alternates (n-raster-row reversed ac drive) in each raster-row specified by nw4?w0. for details, see the n-raster-row reversed ac drive section. eor: when the c-pattern waveform is set and eor = "1", the odd/even frame-select signals and the n- raster-row reversed signals are eored for alternating drive. eor is used when the lcd is not alternated by combining the set values of the lcd drive duty ratio and n raster-row. nw4?: specify the number of raster-rows n that will alternate at the c-pattern waveform setting. nw4 nw0 alternate in every n + 1 raster-row, and the first to the 32nd raster-row can be selected. r/w rs db7 db0 db6 db5 db4 db3 db2 db1 r3: 01 b/c eor nw3 nw2 nw1 nw0 0 nw4 figure 8 lcd driving wave instruction lcd driving control (r4) bs2?: set the lcd drive bias values in the range of 1/2 to 1/8 bias. the lcd drive bias value can be selected according to the lcd drive duty and lcd drive voltage. for details, see the lcd drive bias selector section. ct4?t0: control the lcd drive voltage (potential difference between v1 and gnd) to adjust contrast. a 32-step adjustment is possible. for details, see the contrast adjuster section. r/w rs db7 db0 db6 db5 db4 db3 db2 db1 r4: 01 bs2 bs1 bs0 ct4 ct3 ct2 ct1 ct0 figure 9 lcd driving control instruction
HD66732 46 v lcd v1 v2 v3 v4 v5 vr r r r 0 r r - + - + - + - + - + gnd HD66732 gnd figure 10 contrast adjuster table 28 bs bits and lcd drive bias value bs2 bs1 bs0 liquid crystal display drive bias value 0 0 0 1/8 bias drive 0 0 1 1/7 bias drive 0 1 0 1/6 bias drive 0 1 1 1/5.5 bias drive 1 0 0 1/5 bias drive 1 0 1 1/4.5 bias drive 1 1 0 1/4 bias drive 1 1 1 1/2 bias drive
HD66732 47 table 29 ct bits and variable resistor value of contrast adjuster ct set value variable ct set value variable ct4 ct3 ct2 ct1 ct0 resistor (vr) ct4 ct3 ct2 ct1 ct0 resistor (vr) 0 0 0 0 0 3.2 x r 1 0 0 0 0 1.6 x r 0 0 0 0 1 3.1 x r 1 0 0 0 1 1.5 x r 0 0 0 1 0 3.0 x r 1 0 0 1 0 1.4 x r 0 0 0 1 1 2.9 x r 1 0 0 1 1 1.3 x r 0 0 1 0 0 2.8 x r 1 0 1 0 0 1.2 x r 0 0 1 0 1 2.7 x r 1 0 1 0 1 1.1 x r 0 0 1 1 0 2.6 x r 1 0 1 1 0 1.0 x r 0 0 1 1 1 2.5 x r 1 0 1 1 1 0.9 x r 0 1 0 0 0 2.4 x r 1 1 0 0 0 0.8 x r 0 1 0 0 1 2.3 x r 1 1 0 0 1 0.7 x r 0 1 0 1 0 2.2 x r 1 1 0 1 0 0.6 x r 0 1 0 1 1 2.1 x r 1 1 0 1 1 0.5 x r 0 1 1 0 0 2.0 x r 1 1 1 0 0 0.4 x r 0 1 1 0 1 1.9 x r 1 1 1 0 1 0.3 x r 0 1 1 1 0 1.8 x r 1 1 1 1 0 0.2 x r 0 1 1 1 1 1.7 x r 1 1 1 1 1 0.1 x r power control (r5) amp: when amp = 1, each voltage follower for v1 to v5 pins and the booster are turned on. when amp = 0, current consumption can be reduced while the display is not being used. bt1-0: switch the output of v5out between single, double, triple, and quadruple boost. the lcd drive voltage level can be selected according to its drive duty ratio and bias. a lower amplification of the booster consumes less current. when bt1/0 = "00", a single boost is output. when bt1/0 = "01", a double boost is output. when bt1/0 = "10", a triple boost is output. when bt1/0 = "11", a quadruple boost is output. slp: when slp = 1, the HD66732 enters the sleep mode, where the internal operations are halted except for the key scan function and the r-c oscillator, thus reducing current consumption. for details, see the sleep mode section. only the following instructions can be executed during the sleep mode. a. key scan data read b. key scan control (ire, kf1/0 bit) c. power control (amp, slp, and stb bits) d. port control (pt2-0 bits) during the sleep mode, the other ram data and instructions cannot be updated although they are retained.
HD66732 48 stb: when stb = 1, the HD66732 enters the standby mode, where display operation and key scan completely stops, halting all the internal operations including the internal r-c oscillator. further, no external clock pulses are supplied. this setting can be used as the system wake-up, because an interrupt is generated when a specific key is pressed. for details, see the standby mode section. only the following instructions can be executed during the standby mode. a. standby mode cancel (stb = 0) b. voltage follower circuit on/off (amp = 1/0) c. start oscillation d. key scan interrupt generation enabled/disabled (ire = 1/0) e. port control (pt2-0 bits) during the standby mode, the other ram data and instructions may be lost. to prevent this, they must be set again after the standby mode is canceled. r/w rs db7 db0 01 db6 db5 db4 db3 db2 db1 amp 0 bt1 bt0 0 0 slp stb r5: figure 11 power control instruction key scan control (r6) pt2-0: control the output level of a port output pin (port2-port0). when pt0 = 0, the port0 pin outputs the gnd level, and when pt0 = 1, it outputs the vcc level. similarly, pt1 and pt2 bits control port1 and port2 output levels respectively. ksb: when ksb = "1", the mode enters key standby and the key scan is stopped. in this case, key scan interrupts can be generated as well as in the standby mode. when ksb = "0", the keys are scanned normally. ire: when ire = 1, it permits interrupts when a key is pressed. this causes interrupts to occur in the standby period when the oscillator clock is halted, as well as key scan interrupts during normal operation, allowing system wake-up. kf1-0: set the key scan cycle. the following table shows the key scan pulse width and key scan cycle used when the oscillation frequency (fosc) is 60 khz, which depend on the oscillation frequency. for details, see the key scan control section. r/w rs db7 db0 01 db6 db5 db4 db3 db2 db1 0 pt2 pt1 pt0 ksb kf1 kf0 ire r6: figure 12 key scan control instruction
HD66732 49 table 30 kf bits and key scan cycle kf1 kf0 key scan pulse width key scan cycle 0 0 0.25 ms 1.1 ms (64 clock cycles) 0 1 0.5 ms 2.1 ms (128 clock cycles) 1 0 1.1 ms 4.3 ms (256 clock cycles) 1 1 2.1 ms 8.5 ms (512 clock cycles) note: the data is a value obtained when the oscillation frequency (fosc) is 60 khz. the value depends on the oscillation frequency. entry mode (r7) rev: when rev = "1", the rev displays all character and graphics display sections except for the segment display section with black-white reversal. for details, see the reversed display function section. spr: when spr = "1", the spr displays combined character and graphics display screens (the super- imposed display mode). in this case, user fonts using the cgram in the character display mode cannot be displayed. for details, see the super-imposed display function section. gr: activates the character mode when gr = ?? displays the font pattern on the cgrom or cgram according to the character code written in the ddram. activates the graphics mode when gr = 1. displays a given pattern according to the bit map data written in the cgram. in this case, data in the ddram is not used for display. segment pattern display set to the segram is enabled both in the character mode and graphics mode. for details, see the character display functions and graphics display functions section. rdm: when rdm = "0", the rdm increments or decrements the address counter value according to the i/d bit setting after reading the data from the ddram/cgram/segram. when rdm = "1", the address counter is not updated after the data has been read from the ram. the address counter is used when the ram data is read, modified, and written. since the first read data is invalid, the read must be done twice. after writing to the ram, the address counter value must be incremented or decremented. i/d: increments (i/d = 1) or decrements (i/d = 0) the ddram address by 1 when a character code is written into or read from ddram. the cursor or blinking moves to the right when incremented by 1 and to the left when decremented by 1. the same applies to the writing and reading of cgram and segram. r/w rs db7 db0 01 db6 db5 db4 db3 db2 db1 0 0 0 rev spr rdm i/d gr r7: figure 13 entry mode set instruction
HD66732 50 address: n set dummy read (invalid data) read (data of address n) modify write (data of address n) address counter (ac) = n address counter (ac) = n address counter (ac) = n + 1 i/d = "1", rdm = "1" address counter (ac) = n figure 14 read, modify, and write sequences in bus interface mode cursor control (r8) ch: executes the cursor home instruction and sets ddram address 0 into the address counter (ac). the ddram contents do not change. the cursor or blinking goes to the top left of the display. lc: when lc = 1, a cursor attribute is assigned to the line that contains the address counter (ac) value. cursor mode can be selected with the b/w, c, and b bits. for details, see the line-cursor display section. b/w : when b/w = 1 and lc = 1, the character at the cursor position is cyclically (every 32 frames) blink- displayed with black-white reversal. when b/w = 1 and lc = 1, all characters including the cursor on the display line appear with black-white reversal. the characters do not blink. for details, see the line-cursor display section. c: the cursor is displayed on the 13th raster-row when c = 1. the 13-dot cursor is ored with the character pattern and displayed on the 13th raster-row. b: the character indicated by the cursor blinks when b = 1. the blinking is displayed as switching between all black dots and displayed characters every 32 frames. the cursor and blinking can be set to display simultaneously. when lc =1, setting b = 1 alternately displays all white dots and character pattern in a line unit. r/w rs db7 db0 01 db6 db5 db4 db3 db2 db1 0 0 0 ch lc b/w c b r8: figure 15 cursor control instruction
HD66732 51 alterna- ting display i) 13th raster-row cursor display example ii) blinking display example iii) black-white reversed display example normal display example cursor alterna- ting display figure 16 cursor control examples display control (r9) dc: character/graphics display is on when dc = 1 and off when dc = 0. when off, the display data remains in the ddram and cgram, and can be displayed instantly by setting d = 1. ds: icon mark segments are on when ds = 1 and off when ds = 0. when off, the display data remains in the segram, and can be displayed again instantly by setting ds = 1. when dc = ds = 0 and all displays are off, all lcd driver outputs are set to the gnd level and the display is off. because of this, the HD66732 can control charging current for the lcd with ac driving. nc1?: sets the number of display characters per line. r/w rs db7 db0 01 db6 db5 db4 db3 db2 db1 0 0 dc ds 0 0 nc1 nc0 r9: figure 17 display control instruction table 31 nc bits and display characters nc1 nc0 number of display characters segment driver used 0 0 6 seg1?eg72 0 1 8 seg1?eg96 1 0 10 seg1?eg120 1 1 inhibited
HD66732 52 scroll control (ra) sn1-0: specify the display start line output from com1. the data is displayed sequentially from the first line to the fourth line then repeated from the first line. sl3?: select the top raster-row to be displayed (display-start raster-row) in the display-start lines specified by sn1 to sn0. any raster-row from the first to fourth can be selected. this function is used to achieve raster-row-unit vertical smooth scrolling together with sn1 to sn0. for details, see the vertical smooth scroll section. r/w rs db7 db0 01 db6 db5 db4 db3 db2 db1 0 0 sl1 sl0 sn1 sn0 sl2 sl3 ra: figure 18 scroll control instruction table 32 sn bits and display-start lines sn1 sn0 display-start line 0 0 1st line 0 1 2nd line 1 0 3rd line 1 1 4th line table 33 sl bits and display-start raster-row sl3 sl2 sl1 sl0 display-start raster-row 0 0 0 0 1st raster-row 0 0 0 1 2nd raster-row 0 0 1 0 3rd raster-row 0 0 1 1 4th raster-row 0 1 0 0 5th raster-row 1 1 0 0 13th raster-row
HD66732 53 half-size rom (hcgrom) select (rb) rl4?: switch the memory bank of the half-size hcgrom for the specified display line. bank 0 and bank 2 of the hcgrom each incorporate 128 fonts, and display 256 fonts in total. the rl1?l4 bits select hcgrom bank 0/1 for the display-line unit. when rl1 = "0", the first line selects bank 0. when rl1 = "1", the first line selects bank 1. the rl2, rl3, and rl4 bits select the second- to fourth-line memory banks, respectively. r/w rs db7 db0 db6 db5 db4 db3 db2 db1 01 0 rl3 rl2 rl1 rl4 000 rb: figure 19 hcgrom select instruction half-size rom (hcgrom) display attribute (rc) a11/10: designate the display attributes of all half-size hcgrom fonts displayed in the first line. a21/20: designate the display attributes of all half-size hcgrom fonts displayed in the second line. a31/30: designate the display attributes of all half-size hcgrom fonts displayed in the third line. a41/40: designate the display attributes of all half-size hcgrom fonts displayed in the fourth line. for details, see the display attribute designation section. the full-size fonts are specified with the two-bit attribute codes in each character code. r/w rs db7 db0 db6 db5 db4 db3 db2 db1 01 a20 a11 a10 a21 a30 a31 a40 a41 rc: figure 20 hcgrom display attribute instruction table 34 attributes and half-size display state a41 a40 a31 a30 a21 a20 a11 a10 half-size display state 00000000 normal display 01010101 black-white reversed display 10101010 blinking display 11111111 black-white reversed blinking display
HD66732 54 ram address (rd/re) rm1-0: select ddram, cgram, and segram. the selected ram is accessed with this setting. ad10-0: initially set ram addresses to the address counter (ac). once the ram data is written, the ac is automatically updated according to the i/d bit. this allows consecutive writing without resetting addresses. once the ram data is read, the ac is automatically updated when rdm = "0", but is not updated when rdm = "1". when the read, modify, and write are executed for every one-byte data, set rdm = "1". ram address setting is not allowed in the sleep mode or standby mode. r/w rs db7 db0 01 db6 db5 db4 db3 db2 db1 0 ad9 ad8 01 ad2 ad1 ad0 ad10 ad3 ad4 rm0 ad5 rm1 ad6 ad7 0 0 rd: re: figure 21 ram address instruction table 35 rm bits and ram selection rm1 rm0 ram selection 0 0 ddram 0 1 inhibited 1 0 cgram 1 1 segram table 36 ad bits and ddram setting rm1/0 ad1?d0 ddram setting 00 "000"h?013"h character code on the 1st line 00 "020"h?033"h character code on the 2nd line 00 "040"h?053"h character code on the 3rd line 00 "060"h?073"h character code on the 4th line
HD66732 55 table 37 ad bits and cgram setting (gr = 0) rm1/0 ad9?d0 cgram (1) setting in the character mode (gr = 0) 10 "000"h?077"h upper font pattern of cgram characters (1) to (10) 10 "100"h?177"h lower font pattern of cgram characters (1) to (10) 10 "200"h?277"h upper font pattern of cgram characters (11) to (20) 10 "300"h?377"h lower font pattern of cgram characters (11) to (20) 10 "400"h?477"h upper font pattern of cgram characters (21) to (30) 10 "500"h?577"h lower font pattern of cgram characters (21) to (30) table 38 ad bits and cgram setting (gr = 1) rm1/0 ad10?d0 cgram setting in the graphics mode (gr = 1) 10 "000"h?077"h bit map data for com1 to com8 10 "100"h?177"h bit map data for com9 to com16 10 "200"h?277"h bit map data for com17 to com24 10 "300"h?377"h bit map data for com25 to com32 10 "400"h?477"h bit map data for com33 to com40 10 "500"h?577"h bit map data for com41 to com48 10 "600"h?677"h bit map data for com49 to com52 table 39 ad bits and segram setting rm1/0 ad10?d0 segram setting 11 "000"h?077"h segram display data ram data (rf) wd7-0 : write 8-bit data to the ddram and cgram, and lower 2-bit data to the segram. the ddram/cgram/segram is selected by the previous specification of the rm 1/0 bit. after a write, the address is automatically incremented or decremented by 1 according to the i/d bit setting in the entry mode set instruction. during the sleep and standby modes, the ddram, cgram, or segram cannot be accessed. rd7-0 : read 8-bit data from the ddram, cgram or segram. the ddram, cgram, or segram is selected by the previous specification of the rm 1/0 bit. in the parallel bus interface mode, the first-byte data read will be invalid immediately after the ram address set, and the consecutive second-byte data will be read normally. in the serial interface mode, two bytes will be invalid immediately after the start byte, and the consecutive third-byte data will be read normally. for details, see the serial data transfer section.
HD66732 56 after a ram read, the address is automatically incremented or decremented by 1 according to the entry mode set instruction. when rdm = "1", the address is not updated. r/w rs db7 db0 01 db6 db5 db4 db3 db2 db1 wd7 wd6 wd5 wd4 wd3 wd2 wd1 wd0 11 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 rf: rf: figure 22 ram data instruction address: n set dummy read (invalid data) read (data of address n) first byte second byte i) parallel bus interface mode address: n set dummy read (invalid data) read (data of address n) first byte third byte ii) serial interface mode start byte start byte dummy read (invalid data) second byte address: n 1 (rdm = "0") address: n (rdm = "1") address: n 1 (rdm = "0") address: n (rdm = "1") figure 23 ram read sequence
HD66732 57 table 40 instruction register list index register code execu- tion no. (hex) name r/w rs db7 db6 db5 db4 db3 db2 db1 db0 description cycle ir index 0 0 id3 id2 id1 id0 sets the register number of the instruction register to be accessed. id = 0000: r0 1111: rf 0 sr status 1 0 bf nf1 nf0 lf3 lf2 lf1 lf0 reads the busy flag (bf), display line position (nf1/0), and display raster- row position (nl3 nl0) in the bus interface mode. 0 1 0 ksd reads the key scan data (ksd) in the serial interface mode. 0 r0 0 clear display 0100 000 001 clears display and sets address 0 into the address counter. 85* r1 1 start oscillation 0100 000 001 starts oscillation during the standby mode. r2 2 driver output control 0 1 0 nl2 nl1 nl0 0 cen cms sgs sets the number of display lines (nl2 0), centering (cen), common driver shift direction (cms), and segment driver shift direction (sgs). 0 r3 3 lcd drive waveform 0 1 b/c eor 0 nw4 nw3 nw2 nw1 nw0 selects the lcd drive waveform (b/c), specifies the eor output (eor), and the number of n raster-rows (nw4 0). 0 r4 4 lcd drive control 0 1 bs2 bs1 bs0 ct4 ct3 ct2 ct1 ct0 sets the lcd drive bias (bs2?) and contrast adjustment (ct4?). 0 r5 5 power control 0 1 amp 0 bt1 bt0 0 0 slp stb turns on the lcd power supply (amp), and sets the boosting output ratio (bt1/0), sleep mode (slp), and standby mode (stb). 0
HD66732 58 table 40 instruction register list (cont) index register code execu- tion no. (hex) name r/w rs db7 db6 db5 db4 db3 db2 db1 db0 description cycle r6 6 key scan control 0 1 0 pt2 pt1 pt0 ksb ire kf1 kf0 sets the port output control (pt2?), key standby mode (ksb), key scan interrupt (ire), and key scan cycle (kf1/0). 0 r7 7 entry mode 0100 0revsprgrrdmi/d sets the black- white reversal (rev), super- imposed display (spr), graphics mode (gr), read/modify/write (rdm), and address counter update direction after ram access (i/d). 0 r8 8 cursor control 0100 0chlcb/wcb sets cursor home (ch), raster-row cursor (lc), black- white reversed cursor (b/w), 13th raster-row cursor (c), and blinking cursor (b). 0 r9 9 display control 0100 dcds0 0nc1nc0 sets display on (dc), segment display on (ds), and the number of display characters (nc1/0). 0 ra a scroll control 0100 sn1sn0sl3sl2sl1sl0 sets the display start line (sn1/0) and start raster-row (sl3?). 0 rb b half-size rom select 0100 00rl4rl3rl2rl1 sets the half-size cgrom bank switch (rl1?) every display line. 0 rc c half-size display attribute 0 1 a41 a40 a31 a30 a21 a20 a11 a10 sets the half-size display attributes every display line. 0 rd d ram address set (upper) 0 1 rm1 rm0 0 0 0 ad10? (upper) initially sets the ram select (rm1/0) and upper three bits of the ram address (ad10?). 0
HD66732 59 table 40 instruction register list (cont) index register code execu- tion no. (hex) name r/w rs db7 db6 db5 db4 db3 db2 db1 db0 description cycle re e ram address set (lower) 0 1 ad7? (lower) initially sets the lower eight bits of the ram address (ad7?). 0 rf f ram data 0 1 write data writes or reads the data to or from the 0 1 1 read data ddram, cgram, or segram. note: the execution time depends on the supplied clock frequency or the internal oscillation frequency.
HD66732 60 bit definition: bf = 1: internal processing nf1/0: display read line positions lf3?: display read raster-row positions nl2?: display line setting (000: segment only, 001: one line, 010: two lines, 011: three lines, 100: four lines) cen = 1: display position shift to the center of the screen cms = 0: com1/52 => com1 sgs = 0: seg1/120 => seg1 b/c = 0: b-pattern waveform drive b/c = 1: c-pattern waveform drive eor = 1: eor alternating drive at c-pattern waveform nw4?: reversed number of n raster-rows at c-pattern waveform drive (alternating with the set value + one raster-row) bs2?: lcd drive bias select ct4?: contrast adjustment amp = 1: operating amplifier/booster on bt1/0: boost output ratio (00: single, 01: double, 10: triple, 11: quadruple) slp = 1: sleep mode stb = 1: standby mode pt2?: port output control (pt2 = 1: port2 = vcc, pt1 = 1: port1 = vcc, pt0 = 1: port0 = vcc) ksb = 1: key standby mode (key scan stop) ire = 1: key scan interrupt generation enabled kf1/0: key scan cycle set rev = 1: black-white reversed display, but excluding the segment display spr = 1: super-imposed display of the character and graphics gr = 0: character display mode gr = 1: graphics display mode rdm = 0: automatically update the address counter after reading rdm = 1: do not automatically update the address counter after reading i/d = 1: address counter increment i/d = 0: address counter decrement ch = 1: cursor home lc = 1: raster-row cursor b/w = 1: black-white reversed cursor c = 1: 13th raster-row cursor b = 1: blinking cursor dc = 1: character/graphics display on ds = 1: segment display on nc1/0: number of display characters (00: six, 01: eight, 10: 10) sn1/0: display-start line specifications (00: 1st line, 01: 2nd line, 10: 3rd line, 11: 4th line) sl3?: scroll-start raster-row specifications (0000: 1st raster-row, 0100: 5th raster-row, 1000: 9th raster-row, 1100: 13th raster row) rl1?: half-size cgrom memory bank selection (rl1: 1st line, rl2: 2nd line, rl3: 3rd line, rl4: 4th line) a11/10: 1st-line half-size display attribute (00: normal, 01: black-white reversal, 10: blinking, 11: black- white reversed blinking)
HD66732 61 a21/20: 2nd-line half-size display attribute a31/30: 3rd-line half-size display attribute a41/40: 4th-line half-size display attribute rm1/0: ram selection (00/01: ddram, 10: cgram, 11: segram) ad10?: ram address
HD66732 62 reset function the HD66732 is internally initialized by reset input. during initialization, the system executes a clear display instruction after reset is canceled. the system executes the other instructions during the reset period. because the busy flag (bf) indicates a busy state (bf = 1) during the reset period and the clear display instruction is executed following reset cancellation, no instruction or ram data access from the mpu is accepted. the reset input must be held for at least 1 ms. any initializing instruction must wait for 200 clock cycles after the reset is canceled so that execution of the clear display instruction can be completed. instruction set initialization: 1. clear display executed (writes half-size space code a0h to ddram) 2. start oscillation executed 3. driver output control (nl2? = 100: 1/54 duty drive, cen = 0, sgs = 0, cms = 0, cen = 0) 4. lcd waveform control (b/c = 0: b-pattern waveform, eor = 0, nw4? = 0000) 5. lcd drive control (bs2? = 000: 1/8 bias drive, ct4? = 00000: weak contrast) 6. power control (amp = 0: lcd power off, bt1/0 = 00: single boost, slp = 0: sleep mode off, stb = 0: standby mode off) 7. key scan control (ksb = 0: key scan, ire = 0: key scan interrupt (irq) generation disabled, kf1/0 = 00: key scan set to 64 cycles) 8. port control (pt2/1/0 = 000: port2/1/0 output = gnd level) 9. entry mode set (rev = 0, spr = 0, gr = 0: character display mode, rdm = 0, i/d = 1: increment by 1) 10. cursor control (ch = 0: cursor home, lc = 0, b/w = 0, c = 0, b = 0) 11. display control (dc/ds = 00: display off, nc1/0 = 00: six-character display) l2. scroll control (sn1/0 = 00, sl3/2/1/0 = 0000: first raster-row displayed at the top of the first line) 13. half-size rom control (rl4/3/2/1 = 0000: bank 0 selection) 14. half-size display attribute (a41/40 = 00, a31/30 = 00, a21/20 = 00, a11/10 = 00: normal half-size display) 15. ram address (rm1/0 = 00: ddram selection, ad10? = 000h) ram data initialization: 1. ddram all addresses are initialized to a0h by the clear-display instruction after the reset is canceled. 2. cgram/segram this is not automatically initialized by the reset input but must be initialized by software while the display is off (d = 0).
HD66732 63 output pin initialization: 1. lcd driver output pins (seg/com): outputs gnd level 2. booster output pins (vlout): outputs v cc level 3. oscillator output pin (osc2): outputs oscillation signal 4. key strobe pins (kst0 to kst3): output strobe signals at specified time intervals 5. key scan interrupt pin (irq*): outputs v cc level 6. general output ports (port0?ort2): output gnd level
HD66732 64 serial data transfer setting the im1 and im2 pins (interface mode pins) to the gnd level allows standard clock-synchronized serial data transfer, using the chip select line (cs*), serial data line (sda), and serial transfer clock line (scl). for a serial interface, the im0/id pin function uses an id pin. the HD66732 initiates serial data transfer by transferring the start byte at the falling edge of cs* input. it ends serial data transfer at the rising edge of cs* input. the HD66732 is selected when the 6-bit chip address in the start byte transferred from the transmitting device matches the 6-bit device identification code assigned to the HD66732. the HD66732, when selected, receives the subsequent data string. the least significant bit of the identification code can be determined by the id pin. the five upper bits must be 01110. two different chip addresses must be assigned to a single HD66732 because the seventh bit of the start byte is used as a register select bit (rs): that is, when rs = 0, an instruction can be issued or key scan data can be read, and when rs = 1, data can be written to or read from ram. read or write is selected according to the eighth bit of the start byte (r/w bit) as shown in table 41. after receiving the start byte, the HD66732 receives or transmits the subsequent data byte-by-byte. the data is transferred with the msb first. to transfer data consecutively, note that only the clear-display instruction requires 85 clock cycles. wait after issuing the clear-display instruction. two bytes of ram read data after the start byte are invalid. the HD66732 starts to read correct ram data from the third byte. table 41 start byte format transfer bit s 1 2 3 4 5 6 7 8 start byte format transfer start device id code rs r/w 011 10id note: id bit is selected by the im0/id pin. table 42 rs and r/w bit function rs r/w function 0 0 sets index address 0 1 reads status register 1 0 writes control register, ram address, or ram data 1 1 reads ram data
HD66732 65 a) basic data-transfer timing through clock-synchronized serial bus interface start byte instruction, ram data, key-scanned data scl (input) cs* (input) transfer start transfer end start byte rs = 1, r/w = 0 scl (input) b) consecutive ram data-transfer timing 1 2 3 4 5 6 7 8 9 101112 131415 16 17 1819 ram write data 1 ram write data 2 20 21 22 23 24 25 26 27 28 29 30 31 32 ram write data 3 start end cs* (input) sda (input/ output) sda (input/ output) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 db7 db6 db5 db4 r/w device id code id rs db3 db2 db1 db0 msb rs "1" r/w "1" "0" "1" "0" lsb start byte rs = 1, r/w = 1 scl (input) c) ram data read-transfer timing 1 2 3 4 5 6 7 8 9 101112 131415 16 17 1819 dummy read 1 dummy read 2 20 21 22 23 24 25 26 27 28 29 30 31 32 ram data read 1 start end cs* (input) sda (input/ output) note: the ram address setting registers (rc and rd) select the write ram or set the write-start ram address. note: two bytes of the ram read data after the start byte are invalid. the HD66732 starts to read the correct ram data from the third byte. figure 24 clock-synchronized serial interface timing sequence
HD66732 66 key scan control the key matrix scanner senses and holds the key states at each rising edge of key strobe signals (kst) that are output by the HD66732. the key strobe signals are output as time-multiplexed signals from kst0 to kst3. after passing through the key matrix, these strobe signals are used to sample the key state of eight inputs kin0 to kin7, enabling up to 32 keys to be scanned. the states of inputs kin0 to kin7 are sampled by key strobe signal kst0 and latched into the scan0 register. similarly, the data sampled by strobe signals kst1 to kst3 is latched into the scan1 to scan3 registers, respectively. key pressing is stored as 1 in these registers. the generation cycle and pulse width of the key strobe signals depend on the operating frequency (oscillation frequency) of the HD66732 and the key scan cycle determined by the kf0 and kf1 bits. for example, when the operating frequency is 60 khz and kf0 and kf1 are both 10, the generation cycle is 4.3 ms and the pulse width is 1.1 ms. when the operating frequency (oscillation frequency) is changed, the above generation cycle and the pulse width are changed in inverse proportion. in order to compensate for the mechanical features of the keys, such as chattering and noise and for the key-strobe generation cycle and the pulse width of the HD66732, software should read the scanned data two to three times in succession to obtain valid data. multiple keypress combinations should also be processed in the software. up to three keys can be pressed simultaneously. note, however, that if the third key is pressed on the intersection between the rows and columns of the first two keys pressed, incorrect data will be sampled. for three-key input, the third key must be on a separate column or row. additionally, the HD66732 supports the key standby mode in which only the key scan circuit enters the standby state. when 1 is set to the key standby mode setting bit (ksb), only key scanning is stopped. in this case, as well as in the normal standby mode, the key scan interrupt function can be used. for example, this function is used when only key scanning is stopped to improve the sensitivity of the wave received by a radio system during calling. the input pins kin0 to kin7 are pulled up to v cc with internal mos transistors (see the electrical characteristics section). external resistors may also be required to further pull the voltages up when the internal pull-ups are insufficient for the desired noise margins or for a large key matrix. scan0 scan1 scan2 scan3 d 03 d 02 d 01 d 00 kin3 kin2 kin1 kin0 (kst0 - ) (kst1 - ) (kst2 - ) (kst3 - ) d 13 d 12 d 11 d 10 d 23 d 22 d 21 d 20 d 33 d 32 d 31 d 30 d 04 kin4 d 14 d 24 d 34 d 05 kin5 d 15 d 25 d 35 d 06 kin6 d 16 d 26 d 36 d 07 kin7 d 17 d 27 d 37 ksd7 ksd6 ksd5 ksd4 ksd3 ksd2 ksd1 ksd0 figure 25 key scan register configuration
HD66732 67 table 43 key scan cycles for each operating frequency kf1 kf0 key scan pulse width key scan cycle 0 0 0.26 ms 1.1 ms (64 clock cycles) 0 1 0.5 ms 2.1 ms (128 clock cycles) 1 0 1.1 ms 4.3 ms (256 clock cycles) 1 1 2.1 ms 8.5 ms (512 clock cycles) note: the data is a value obtained when the oscillation frequency (fosc) is 60 khz. the value depends on the oscillation frequency. 4.3 ms 1.1 ms kst0 key scan cycle kst1 kst2 kst3 figure 26 key strobe output timing (kf1/0 = 10, fcp/fosc = 60 khz) key matrix HD66732 HD66732 key state fetch key strobe detail kin5 kin4 kin3 kin2 kin1 kin0 kst0 kst1 kst2 kst3 d 30 d 31 d 32 d 33 d 34 d 35 d 20 d 21 d 22 d 23 d 24 d 25 d 10 d 11 d 12 d 13 d 14 d 15 d 00 d 01 d 02 d 03 d 04 d 05 kin6 d 36 d 26 d 16 d 06 kin7 d 37 d 27 d 17 d 07 figure 27 key scan configuration
HD66732 68 the key-scanned data can be read by an mpu via a serial interface. first, a start byte should be transferred. after the HD66732 has received the start byte, the mpu reads scan data ksd7 to ksd0 from the scan0 register starting from the msb. similarly, the mpu reads data from scan1, scan2 and scan3 in that order. after reading scan3, the mpu starts at scan0 again. the HD66732 may be read out while it is latching scan data and is thus unstable. consequently, it should also be reconfirmed with software if required. b) consecutive scan data read timing a) scan data read timing through clock-synchronized serial bus interface wait start byte scl (input) sda (input/ output) scan0 data scan1 data scan2 data scan3 data wait wait scan0 data wait 1 2 3 4 5 6 7 8 9 10111213141516 start byte device id code scl (input) sda (input/ output) cs* (input) scan0 data transmission r/w rs transfer start transfer end id 0 1 1 1 0 ksd7 ksd6 ksd5 ksd4 ksd3 ksd2 ksd1 ksd0 0 1 figure 28 scan data serial transfer timing
HD66732 69 key scan interrupt (wake-up function) if the interrupt enable bit (ire) is set to 1, the HD66732 sends an interrupt signal to the mpu on detecting that a key has been pressed in the key scan circuit by setting the irq* output pin to a low level. an interrupt signal can be generated by pressing any key in a 32-key matrix. the interrupt level continues to be output during the key scan cycle while the key is being pressed. normal key scanning is performed and interrupts can occur in the HD66732 sleep mode (slp = 1). accordingly, power consumption can be minimized in the sleep mode, by triggering the mpu to read key states via the interrupt which is generated only when the HD66732 detects a key input. for details, see the sleep mode section. on the other hand, normal key scanning stops in the standby mode (stb = 1) or in the key standby mode (ksb = 1). during this period, the kst0 output is kept low, so the HD66732 can always monitor eight key inputs (kin0-kin7) connected to kst0 when rs = gnd. therefore, if any of the eight keys is pressed, an interrupt occurs. when rs = vcc, all outputs kst0 to kst3 are kept low, so the HD66732 can always monitor 32 key inputs. if any of the 32 keys is pressed, an interrupt occurs. accordingly, power consumption or noise generation can be further minimized in the standby mode, where the whole system is inactive, by triggering the mpu via the interrupt which is generated only when the HD66732 detects a key input from the above keys. for details, see the standby mode section. the irq* output pin is pulled up to the v cc with an internal mos resistor of approximately 50 k w . additional external resistors may be required to obtain stronger pull-ups. interrupts may occur if noise occurs in kin0-kin7 input during key scanning. interrupts must be inhibited if not needed by setting the interrupt enable bit (ire) to 0. irq* interrupt generated HD66732 irq* vcc mpu figure 29 interrupt generator
HD66732 70 enable interrupts (ire = 1) standby mode wait 10 ms or longer (mpu) clear standby mode (stb = 0) mask interrupts (ire = 0) turn off lcd power (amp = 0) set standby mode (stb = 1) key input (key -> HD66732) generate interrupt (HD66732 -> mpu) start r-c oscillation (HD66732) read key-scanned data enable interrupts (ire = 1) mask interrupts (ire = 0) turn off lcd power (amp = 0) set sleep mode (slp = 1) key input (key -> HD66732) generate interrupt (HD66732 -> mpu) read key-scanned data sleep mode figure 30 key scan interrupt processing flow in sleep and standby modes
HD66732 71 parallel data transfer 8-bit interface setting the im2/1/0 (interface mode) to the gnd/vcc/gnd level allows e-clock-synchronized 8-bit parallel data transfer. setting the im2/1/0 (interface mode) to the vcc/vcc/gnd level allows 80-system 8- bit parallel data transfer. when the number of buses or the mounting area is limited, use a 4-bit bus interface or serial data transfer. using a parallel bus interface disables the key scan function. to prevent this, use a clock-synchronized serial interface. c0 c1 c2 a0?7 e/wr* rs r/w / rd* (cs*) db0?b7 h8/325 HD66732 8 *interface via i/o port figure 31 interface to 8-bit microcomputer 4-bit interface setting the im2/1/0 (interface mode) to the gnd/vcc/vcc level allows e-clock-synchronized 4-bit parallel data transfer using pins db7/kin7-db4/kin4. setting the im2/1/0 (interface mode) to the vcc/vcc/vcc level allows 80-system 4-bit parallel data transfer. 8-bit instructions and ram data are divided into four upper/lower bits and the transfer starts from the upper four bits. using a parallel bus interface disables the key scan function. to prevent this, use a clock-synchronized serial interface. note: transfer synchronization function for a 4-bit bus interface the HD66732 supports the transfer synchronization function which resets the upper/lower counter to count upper/lower 4-bit data transfer in the 4-bit bus interface. noise causing transfer mismatch between the four upper and lower bits can be corrected by a reset triggered by consecutively writing a 0000 instruction four times. the next transfer starts from the upper four bits. executing synchronization function periodically can recover any runaway in the display system.
HD66732 72 "0000" "0000" "0000" "0000" rs r/w e db7 ?b4 upper lower (4-bit transfer synchronization) (1) (2) (3) (4) upper/ lower figure 32 4-bit transfer synchronization
HD66732 73 oscillation circuit the HD66732 can either be supplied with operating pulses externally (external clock mode), oscillate using an internal r-c oscillator with an external oscillator-resistor. external oscillator-resistors (rf) can adjust the oscillating frequency. when the power-supply voltage is minimized, the frequency is lowered. see the electrical characteristics notes section for the relationships between the rf resistance value and oscillating frequency. 1) external clock mode 2) external resistor oscillation mode osc1 osc1 osc2 clock rf HD66732 HD66732 figure 33 oscillation circuits table 44 relationship between drive duty ratio and frame frequency number of display characters 6-character display (nc = 00) 8-character display (nc = 01) 10-character display (nc = 10) recommended r-c oscillating frequency frame frequency 45 khz 60 khz 76 khz segment display (nl = 001) 70 hz 70 hz 70 hz 1-line display (nl = 001) 73 hz 71 hz 70 hz 2-line display (nl = 010) 73 hz 71 hz 71 hz 3-line display (nl = 011) 69 hz 73 hz 71 hz 4-line display (nl = 100) 70 hz 70 hz 70 hz
HD66732 74 1 2 3 4 53 54 1 2 3 53 54 v1 v2 v5 gnd coms1 v2 v5 gnd com1 1 frame 1 frame v1 v2 v5 gnd com52 v1 v2 v5 gnd coms2 v1 figure 34 lcd drive output waveform (4-line display with 1/54 multiplexing duty ratio)
HD66732 75 n-raster-row reversed ac drive the HD66732 supports not only the lcd reversed ac drive in a one-frame unit (b-pattern waveform) but also the n-raster-row reversed ac drive which alternates in an n-raster-row unit from one to 32 raster-rows (c-pattern waveform). when a problem affecting display quality occurs, such as crosstalk at high-duty driving of more than three lines (1/42 duty), the n-raster-row reversed ac drive (c-pattern waveform) can improve the quality. determine the number of raster-rows n for alternating after confirmation of the display quality with the actual lcd panel. however, if the number of ac raster-rows is reduced, the lcd alternating frequency becomes high. because of this, the charge or discharge current is increased in the lcd cells. 1 2 3 4 5 6 7 8 9 10 11 12 13 53 54 1 2 3 4 5 6 7 8 9 10 11 12 13 53 54 1 2 3 b-pattern waveform drive ?1/54 duty 1 frame 1 frame c-pattern waveform drive ?1/54 duty ?10-raster-row reversal ?without eors c-pattern waveform drive ?1/54 duty ?9-raster-row reversal ?with eors figure 35 example of an ac signal under n-raster-row reversed ac drive
HD66732 76 liquid crystal display voltage generator when external power supply and internal operational amplifiers are used to supply lcd drive voltage directly from the external power supply without using the internal booster, circuits should be connected as shown in figure 36. here, contrast can be adjusted by software through the ct bits of the contrast adjustment register. the HD66732 incorporates a voltage-follower operational amplifier for each v1 to v5 to reduce current flowing through the internal bleeder-resistors, which generate different levels of liquid-crystal drive voltages. thus, the potential difference between v lcd and v1 must be 0.1 v or higher, and ones between v4 and gnd between v2 and gnd must be 1.4 v or higher. note that the opoff pin must be grounded when using the operational amplifiers. place a capacitor of about 0.1 m f to 0.5 m f between each internal operational amplifier v1out to v5out output and gnd and stabilize the output level of the operational amplifier.
HD66732 77 c1+ v lcd v lcd vr r 0 r r r - + - + - + - + - + gnd booster opoff = gnd r HD66732 v1out + v2out v3out v4out v5out + + + + lcd driver seg1 to seg120 com1 to com52 coms1 to coms2 v1 v3 v4 v2 v5 gnd vci c1- c2+ c2- vlout 0.1 f to 0.5 f gnd figure 36 external power supply circuit for lcd drive voltage generation when an internal booster and internal operational amplifiers are used to supply lcd drive voltage using the internal booster, circuits should be connected as shown in figure 37. here, contrast can be adjusted through the ct bits of the contrast control instruction. temperature can be compensated either through the ct bits or by controlling the reference voltage for the booster (vci pin) using a thermistor. note that vci is both a reference voltage and power supply for the booster. the reference voltage must therefore be adjusted using an emitter-follower or a similar element so that sufficient current can be supplied. in this case, vci must be equal to or smaller than the v cc level. the HD66732 incorporates a voltage-follower operational amplifier for each of v1 to v5 to reduce current flowing through the internal bleeder-resistors, which generate different liquid-crystal drive voltages. thus, the potential difference between v lcd and v1 must be 0.1 v or higher, and ones between v4 and gnd and between v2 and gnd must be 1.4 v or higher. note that the opoff pin must be grounded when using the operational amplifiers. place a capacitor of about 0.1 m f to 0.5 m f between each internal operational amplifier v1out to v5out output and gnd and stabilize the output level of the operational amplifier.
HD66732 78 v lcd vr r 0 r r r - + - + - + - + - + gnd c1+ c1- vci + 0.47 f to 1 f 0.47 f to 1 f vlout gnd + c2+ c2- + 0.47 f to 1 f booster opoff = gnd r HD66732 v1out + v2out v3out v4out v5out + + + + lcd driver seg1 to seg120 com1 to com52 coms1 to coms2 v1 v3 v4 v2 v5 gnd 0.1 f to 0.5 f gnd vci c3+ c3- + 0.47 f to 1 f notes: 1. the reference voltage input (vci) must be adjusted so that the output voltage after boosting will not exceed the absolute maximum rating for the liquid-crystal power supply voltage (13 v). particularly, vci must be 3.3 v or less for quadruple boosting. 2. vci is both a reference voltage and power supply for the booster; connect it to vcc directly or combine it with a transistor so that sufficient current can be obtained. 3. vci must be smaller than vcc. 4. polarized capacitors must be connected correctly. 5. circuits for temperature compensation should be based on the sample circuit in figure 38. figure 37 internal booster for lcd drive voltage generation
HD66732 79 vcc thermistor gnd tr vcc vci HD66732 figure 38 temperature compensation circuit instruction bits (bt1/0) can optionally select the boosting multiplying factor of the internal booster. according to the display status, power consumption can be reduced by changing the lcd drive duty and the lcd drive bias, and by controlling the boosting multiplying factor for the minimum requirements. for details, see the partial-display-on function section. due to the maximum boosting multiplying factor, the following external capacitor needs to be connected. for example, when the maximum boosting is tripled, the capacitors between c3+ and c3?for quadruple boosting are not needed, so these pins must be open. table 45 vlout output status bt1 bt0 vlout output status 0 0 single output (the potential difference between vci and gnd is output to the vlout.) 0 1 double boosting output 1 0 triple boosting output 1 1 quadruple boosting output
HD66732 80 c1+ c1- vci + 0.47 f to 1f 0.47 f to 1f vlout gnd + c2+ c2- + 0.47 f to 1f booster vci c3+ c3- + 0.47 f to 1f i) maximum quadruple boosting c1+ c1- vci + 0.47 f to 1f 0.47 f to 1f vlout gnd + c2+ c2- + 0.47 f to 1f booster vci c3+ c3- ii) maximum triple boosting c1+ c1- vci + 0.47 f to 1f 0.47 f to 1f vlout gnd + c2+ c2- booster vci c3+ c3- iii) maximum double boosting figure 39 booster output multiplying factor switching
HD66732 81 contrast adjuster software can adjust contrast for an lcd by varying the liquid-crystal drive voltage (potential difference between v lcd and v1) through the ct bits of the contrast adjustment register (electron volume function). the value of a variable resistor (vr) can be adjusted within a range from 0.1 x r through 3.2 x r, where r is a reference resistance obtained by dividing the total resistance between v lcd and v1. the HD66732 incorporates a voltage-follower operational amplifier for each of v1 to v5 to reduce current flowing through the internal bleeder resistors, which generate different liquid-crystal drive voltages. thus, ct4-0 bits must be adjusted so that the potential difference between v lcd and v1 is 0.1 v or higher, and ones between v4 and gnd and between v2 and gnd are 1.4 v or higher when liquid-crystal drives. vlcd vr r r r0 r r gnd HD66732 ct v1 v2 v3 v4 v5 gnd - + - + - + - + - + figure 40 contrast adjuster
HD66732 82 table 46 contrast adjustment bits (ct) and variable resistor values 0 ct3 0 ct2 0 ct1 0 ct0 3.2 x r ct set value variable resistor value (vr) 00 0 1 3.1 x r 00 1 0 3.0 x r 00 1 1 2.9 x r 01 0 0 2.8 x r 01 0 1 2.7 x r 01 1 0 2.6 x r 01 1 1 2.5 x r 0 ct4 0 0 0 0 0 0 0 100 1 2.3 x r 0 101 0 2.2 x r 0 potential difference between v1 and gnd display color (small) (large) (light) (deep) 101 2.1 x r 0 11 0 0 2.0 x r 0 1 101 1.9 x r 0 1 11 0 1.8 x r 0 11 1 1 1.7 x r 0 0000 1.6 x r 1 0001 1.5 x r 1 0 01 0 1.4 x r 1 0 01 1 1.3 x r 1 01 0 0 1.2 x r 1 01 0 1 1.1 x r 1 01 1 0 1.0 x r 1 0 11 1 0.9 x r 1 1 000 0.8 x r 1 100 1 0.7 x r 1 101 0 0.6 x r 1 101 1 0.5 x r 1 11 0 0 0.4 x r 1 11 0 1 0.3 x r 1 1 11 0 0.2 x r 1 1 11 1 0.1 x r 1 100 0 2.4 x r 0 1
HD66732 83 table 47 contrast adjustment per bias drive voltage 6 x r + vr 6 x r x (v lcd - gnd) 0.652 x (v lcd -gnd) v dr 0.984 x (v lcd -gnd) 3 1.4 [v] 3 0.1 [v] 6 x r + vr vr x (v lcd -gnd) 6 x r + vr 2 x r x (v lcd -gnd) 5 x r + vr 5 x r x (v lcd - gnd) 0.610 x (v lcd -gnd ) v dr 0.980 x (v lcd -gnd) 3 1.4 [v] 3 0.1 [v] 5 x r + vr vr x (v lcd -gnd ) 5 x r + vr 2 x r x (v lcd -gnd ) 4 x r + vr 4 x r x (v lcd - gnd) 0.556 x (v lcd -gnd) v dr 0.976 x (v lcd -gnd) 3 1.4 [v] 3 0.1 [v] 4 x r + vr vr x (v lcd -gnd) 4 x r + vr 2 x r x (v lcd -gnd) 2 x r + vr 2 x r x (v lcd - gnd) 0.385 x (v lcd -gnd) v dr 0.952 x (v lcd -gnd) 3 1.4 [v] 3 0.1 [v] 2 x r + vr vr x (v lcd -gnd) 2 x r + vr 2 x r x (v lcd -gnd) 4.5 x r + vr 4.5 x r x (v lcd - gnd) 0.556 x (v lcd -gnd) v dr 0.978 x (v lcd -gnd) 3 1.4 [v] 3 0.1 [v] 4.5 x r + vr vr x (v lcd -gnd) 4.5 x r + vr 2 x r x (v lcd -gnd) 5.5 x r + vr 5.5 x r x (v lcd - gnd) 0.632 x (v lcd -gnd) v dr 0.982 x (v lcd -gnd) 3 1.4 [v] 3 0.1 [v] 5.5 x r + vr vr x (v lcd -gnd) 5.5 x r + vr 2 x r x (v lcd -gnd) 7 x r + vr 7 x r x (v lcd - gnd) 0.686 x (v lcd -gnd) v dr 0.986 x (v lcd -gnd) 3 1.4 [v] 3 0.1 [v] vr x (v lcd -gnd) 7 x r + vr 2 x r x (v lcd -gnd) 7 x r + vr bias lcd drive voltage: v dr contrast adjustment range 1/7 bias drive 1/6 bias drive 1/5.5 bias drive 1/5 bias drive 1/4.5 bias drive 1/4 bias drive 1/2 bias drive - lcd drive voltage adjustment range - limit of potential difference between v4 and gnd - limit if potential difference between vlcd and v1 : : : 8 x r + vr 8 x r x (v lcd - gnd) 0.714 x (v lcd -gnd) v dr 0.988 x (v lcd -gnd) 3 1.4 [v] 3 0.1 [v] vr x (v lcd -gnd) 8 x r + vr 2 x r x (v lcd -gnd) 8 x r + vr 1/8 bias drive - lcd drive voltage adjustment range - limit of potential difference between v4 and gnd - limit if potential difference between vlcd and v1 : : : - lcd drive voltage adjustment range - limit of potential difference between v4 and gnd - limit if potential difference between vlcd and v1 : : : - lcd drive voltage adjustment range - limit of potential difference between v4 and gnd - limit if potential difference between vlcd and v1 : : : - lcd drive voltage adjustment range - limit of potential difference between v4 and gnd - limit if potential difference between vlcd and v1 : : : - lcd drive voltage adjustment range - limit of potential difference between v4 and gnd - limit if potential difference between vlcd and v1 : : : - lcd drive voltage adjustment range - limit of potential difference between v4 and gnd - limit if potential difference between vlcd and v1 : : : - lcd drive voltage adjustment range - limit of potential difference between v2 and gnd - limit if potential difference between vlcd and v1 : : :
HD66732 84 lcd drive bias selector an optimum liquid crystal display bias value can be selected using bs2-0 bits, according to the liquid crystal drive duty ratio setting (nl2-0 bits). liquid crystal display drive duty ratio and bias value can be displayed while switching software applications to match the lcd panel display status. the optimum bias value calculated using the following expression is an ideal value where the optimum contrast is obtained. driving by using a lower value than the optimum bias value provides lower contrast and lower liquid crystal display voltage (potential difference between v1 and gnd). when the liquid crystal display voltage is insufficient even if a quadruple booster is used or output voltage is lowered because the battery life has been reached, the display can be made easier to see by lowering the liquid crystal bias. the liquid crystal display can be adjusted by using the contrast adjustment register (ct4-0 bits) and selecting the booster output level (bt1/0 bits). optimum bias value for 1/n duty ratio drive voltage = 1 n + 1 table 48 optimum drive bias values lcd drive duty ratio (nl2-0 set value) 1/54 duty ratio (nl2-0 = 100) 1/41 duty ratio (nl2-0 = 011) 1/28 duty ratio (nl2-0 = 010) 1/15 duty ratio (nl2-0 = 001) 1/2 duty ratio (nl2-0 = 000) optimum drive bias value (bs2-0 set value) 1/8 bias (bs2-0 = 000) 1/7 bias (bs2-0 = 001) 1/6 bias (bs2-0 = 010) 1/4.5 bias (bs2-0 = 101) 1/2 bias (bs2-0 = 111)
HD66732 85 vr v1 v2 v3 v4 v5 r r 3r r r v1 v2 v3,v4 v5 gnd r r r r v1,v4 v2,v5 v3,gnd r r i) 1/ 7 bias (bs2? = 001) vi) 1/ 4 bias (bs2? = 110) viii) 1/ 2 bias (bs2? = 111) gnd vr vr gnd vlcd vlcd vlcd note: r = reference resistor vr v1 v2 v3 v4 v5 r r 2r r r ii) 1/ 6 bias (bs2? = 010) vlcd vr v1 v2 v3 v4 v5 r r 1.5r r r iii) 1/ 5.5 bias (bs2? = 011) vlcd vr v1 v2 v3 v4 v5 r r r r r iv) 1/ 5 bias (bs2? = 100) vlcd gnd gnd gnd gnd gnd gnd gnd gnd vr gnd v1 v2 v3 v4 v5 r r 0.5r r r v) 1/4.5 bias (bs2? = 101) vlcd gnd vr v1 v2 v3 v4 v5 r r 4r r r i) 1/ 8 bias (bs2? = 000) vlcd gnd gnd figure 41 liquid crystal display drive bias circuit
HD66732 86 lcd panel interface the HD66732 has a function for changing the common driver/segment driver output shift direction using the cms bit and sgs bit to meet the chip mounting positions of the HD66732. this is to facilitate the interface wiring to the lcd panel with cog or tcp installed. seg120/1 seg1/120 seg1/120 seg120/1 com14/39 seg1/120 seg120/1 com1/52 com39/14 seg120/1 seg1/120 com7/46 com27/26 com46/7 com52/1 com27/26 com6/47 com26/27 6 13 20 com7/46 com26/27 com1/52 com39/14 com27/26 com6/47 20 6 13 com47/6 com26/27 6 13 20 20 com46/7 com27/26 6 13 com14/39 com52/1 com47/6 com26/27 front of chip ?cms = 0 ?sgs = 1 back of chip ?cms = 0 ?sgs = 0 front of chip ?cms = 1 ?sgs = 0 back of chip ?cms = 1 ?sgs = 1 figure 42 3-line display pattern wiring
HD66732 87 seg120/1 seg1/120 com1/52 com46/7 seg120/1 seg1/120 com7/46 com27/26 com6/47 com26/27 6 20 20 com7/46 com26/27 com1/52 com46/7 com27/26 com6/47 6 20 6 20 6 com47/6 com47/6 com52/1 com51/1 front of chip ?cms = 0 ?sgs = 1 back of chip ?cms = 0 ?sgs = 0 figure 43 4-line display pattern wiring
HD66732 88 combined display of full-size and half-size characters the HD66732 creates a display from the left edge of the display area combining 12-dot full-size (font size: 11 x 12 dots) and 6-dot half-size characters (font size: 5 x 12 dots). there will be a one-dot space between these fonts. the most significant bit in the data (8 bits) in the ddram is allocated to the designation bit indicating a full-size or half-size character. when this msb is 0, the full-size character is selected, and when 1, the half-size character is selected. when the full-size character is selected, two bytes of ddram are linked and used as a 16-bit code. in this case, the lower byte is written into the smaller ddram address. 13 bits of this 16-bit code are used as character codes. since up to 8,192 character codes can be specified, symbols can be used as well as the jis level-1 and level-2 kanji sets. in addition, two of the remaining bits can be allocated to a display- attribute code and can designate a black-white reversed display for individual characters. for details, refer to the display attribute designation section. table 50 shows the relationship between the 16-bit designated jis code and the HD66732 13-bit character code. the 8-bit data designating half-size characters are used as an 8-bit code. specifically, 7 bits of the 8- bit half-size characters become the character codes, so that a total of 128 characters can be displayed (alphanumeric characters and symbols can be displayed as half-size characters). these 128 cgroms (hcgroms) for half-size fonts have two memory banks and incorporate a total of 256 half-size fonts. these memory banks are switched in a display-line unit by bits rl1?l4 in the half-size rom select register (ra). a half-size font display attribute is designated by the half-size display attribute register (rb) in a display-line unit. note that the same display attribute in a character unit such as the full-size font cannot be specified. user fonts can be displayed using the cgram. special symbols not included in the internal cgrom can be displayed as needed. since the display font size of the cgram is 12 x 13 dots, cgram fonts can be displayed to the right, left, top, or bottom, in order to be used to display double-size characters. in the super-imposed display mode, which displays the combined character display mode and graphics display mode, this cgram becomes the bit map memory for the graphics display and cannot be used as the user font for characters. c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 lower character code character code: c 12 ? 0 (13 bits) display attribute code: a 1 /a 0 (2 bits) msb lsb 0 c 11 c 10 c 9 c 8 upper character code a 1 a 0 attribute code upper byte lower byte c 12 figure 44 full-size code format
HD66732 89 table 49 attribute code and display contents a1 a0 display contents 0 0 normal display 0 1 black-white reversed display 1 0 blinking display 1 1 black-white reversed blinking display table 50 jis code and HD66732 character code upper byte lower byte jis code HD66732 character code b7 b6 b5 c 11 c 10 c 9 c 8 c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 non-kanji level-1 kanji 010 011 100 a7 a6 b3 b2 0 0 a5 a4 a3 a2 a1 b1 b7 b4 b3 b2 a5 a4 a3 a2 a1 b1 b7 b4 b3 b2 a5 a4 a3 a2 a1 b1 a7 a6 a7 a6 user font 0 0 0 0 0 0 u2 u1 c 12 0 0 0 u6 level-2 kanji 101 b6 b4 b3 b2 a5 a4 a3 a2 a1 b1 a7 a6 1 110 b6 b4 b3 b2 a5 a4 a3 a2 a1 b1 a7 a6 1 111 a7 a6 b3 b2 a5 a4 a3 a2 a1 b1 0 0 1 u3 u4 u5 0 ?jis level-1 byte code: b7?1 (7 bits) ?jis level-2 byte code: a7?1 (7 bits) ?cgram code for user fonts: u6?1 (6 bits) 1 character code c 6 c 5 c 4 c 3 c 2 c 1 c 0 character code: c 6 ? 0 (7 bits) msb lsb figure 45 half-size code format an example of how to display full-size and half-size characters together is explained here. the full-size character display conforms to the jis code (16 bits). according to the relationship between the 13-bit jis code, the code is converted from 16 bits to 13 bits, and the data of two bytes/character is written to the ddram. write the lower byte to the smaller ddram address (table 51). when displaying a half-size character, refer to the HD66732 half-size font list (table 52) and write the one byte/character data to the ddram. figure 46 shows how to set data to the ddram when performing a 3-line 6-character display and figure 47 shows the resulting lcd display example.
HD66732 90 table 51 example of full-size character code conversion displayed character jis code (first/second byte) character code (c 11 ? 0 ) 45/6c (hex) aec (hex) 35/7e (hex) 2fe (hex) 45/54 (hex) ad4 (hex) 3e/2e (hex) 72e (hex) 4a/3f (hex) d3f (hex) 3b/54 (hex) 5d4 (hex) 4b/5c (hex) ddc (hex) 44/2e (hex) a2c (hex) 24/4e (hex) a0e (hex) table 52 example of half-size character code display character character code (c 6 ? 0 ) display character character code (c 6 ? 0 ) 1 31 (hex) 0 30 (hex) 2 32 (hex) 4 34 (hex) 0 30 (hex) 2 32 (hex) , 2c (hex) 3 33 (hex) m 4d (hex) 5 35 (hex) c 43 (hex) 1 31 (hex)
HD66732 91 0 000 1010 1110 1100 0 000 0010 1111 1110 0 000 1010 1101 0100 0 000 0111 0010 1110 0 000 1101 0011 1111 0 000 0101 1101 0100 0 000 1101 1101 1100 0 000 1010 0010 1110 1 011 0001 0 000 1010 0000 1110 1 011 0010 1 011 0000 1 010 1100 1 100 1101 1 100 0011 "00" (hex) "01" (hex) "02" (hex) "03" (hex) "04" (hex) "05" (hex) "06" (hex) "07" (hex) "08" (hex) "09" (hex) "0a" (hex) "0b" (hex) 1st-line data "20" (hex) "21" (hex) "22" (hex) "23" (hex) "24" (hex) "25" (hex) "26" (hex) "27" (hex) "28" (hex) "29" (hex) "2a" (hex) "2b" (hex) address address 2nd-line data 0 : full-size designation 1 : half-size designation "40" (hex) "41" (hex) "42" (hex) "43" (hex) "44" (hex) "45" (hex) "46" (hex) "47" (hex) "48" (hex) "49" (hex) "4a" (hex) "4b" (hex) address 3rd-line data 1 011 0000 1 011 0100 1 011 0010 1 011 0011 1 010 1101 1 011 0010 1 011 0101 1 010 1101 1 011 0001 1 011 0001 1 011 0001 1 011 0001 note: figure 46 example of character code setting to ddram (3-line mode, 1/41 duty)
HD66732 92 figure 47 example of liquid crystal display (3-line 6-character display)
HD66732 93 display attribute designation the HD66732 allocates 12 bits of the full-size 16-bit code character to an abbreviated character code and 2 bits to a display-attribute code. a black-white reversed display, blinking display, and black-white reversed blinking display can be designated for each full-size character. display attribute control is performed for a 12 x 13 dot matrix unit that includes a 11 x 12 dot full-size character and a column of dots to the right and a row of dots at the bottom. the blinking cycle for the blinking display and black-white reversed blinking display is 64 frames. the blinking display is provided by changing the display pattern every 32 frames. the display attribute can be designated by the half-size display attribute register (rc) in each display-line unit although the display attribute cannot be designated by the 8-bit half-size character code. the half-size fonts in the same display line have the same display attributes. upper character code lower character code attribute code c 10 c 9 c 8 c 11 c 12 a 0 a 1 0 c 2 c 1 c 0 c 3 c 4 c 5 c 6 c 7 figure 48 full-size code format table 53 full-size display attribute designation a 1 a 0 display state 0 0 normal display 0 1 black-white reversed display 1 0 blinking display 1 1 black-white blinking display half-size code format character code a 20 a 11 a 10 a 21 a 30 a 31 a 40 a 41 c 2 c 1 c 0 c 3 c 4 c 5 c 6 1 half-size display attribute register (rb) attribute code figure 49 half-size code format and rb
HD66732 94 table 54 half-size display attribute designation a 11 a 10 display state 0 0 normal display of all half-size characters in the 1st line 0 1 black-white reversed display of all half-size characters in the 1st line 1 0 blinking display of all half-size characters in the 1st line 1 1 black-white blinking display of all half-size characters in the 1st line a 21 a 20 display state 0 0 normal display of all half-size characters in the 2nd line 0 1 black-white reversed display of all half-size characters in the 2nd line 1 0 blinking display of all half-size characters in the 2nd line 1 1 black-white blinking display of all half-size characters in the 2nd line a 31 a 30 display state 0 0 normal display of all half-size characters in the 3rd line 0 1 black-white reversed display of all half-size characters in the 3rd line 1 0 blinking display of all half-size characters in the 3rd line 1 1 black-white blinking display of all half-size characters in the 3rd line a 41 a 40 display state 0 0 normal display of all half-size characters in the 4th line 0 1 black-white reversed display of all half-size characters in the 4th line 1 0 blinking display of all half-size characters in the 4th line 1 1 black-white blinking display of all half-size characters in the 4th line
HD66732 95 setting codes in the ddram and display examples figure 50 example of full-size character display at display attribute designation kanji alphanumeric i) black-white reversed display of full-size " " ?a 1 = 0 ?a 0 = 1 ii) black-white reversed display of half-size characters in the 3rd line ?a 31 = 0 ?a 30 = 1 iii) black-white reversed display of full-size " " ?a 1 = 0 ?a 0 = 1 figure 51 example of black-white reversed character display
HD66732 96 character display functions and graphics display functions the HD66732 has a character display mode (gr = 0) where the cgram or cgrom is used to display font patterns, a graphics display mode (gr = 1) where the bit pattern data is set to the cgram to display given patterns, and a super-imposed display mode (spr = 1) which displays both display modes combined. in the character display mode, kanji characters can easily be provided by sending two-byte-per-character character codes to the ddram. for example, when an lcd panel which displays 4-line 10-character kanji is rewritten, the lcd display can be easily provided simply by transferring 80-byte character codes. this reduces the microcomputer software processing needed to develop kanji fonts. in addition, since the 30 user fonts can be registered by using the cgram, kanji characters other than jis level-1 or level-2, symbols, or marks which are not included in the cgrom can be displayed. in the graphics display mode, all bit pattern data to be displayed need to be sent. however, up to a 120 x 52-dot display is possible using the cgram. the gr bit can switch these modes not only when characters such as kanji are displayed but also when graphics such as maps or games are used. kanji figure 52 example of kanji display in the character display mode (gr = 0)
HD66732 97 game figure 53 example of graphics display in the graphics display mode (gr = 1)
HD66732 98 super-imposed display function the HD66732 has a super-imposed display mode (spr = 1) which displays two modes combined: the character display mode where the full-size and half-size cgrom is used to display font patterns, and the graphics display mode where the bit pattern data is set to the cgram to display given patterns. the super-imposed mode can be supplied with an easy character display mode and various graphics display modes, enabling a flexible high-quality display. for example, this mode is available to insert graphics such as maps or to create facial images in an address book which otherwise only uses characters. when characters are displayed in this mode, user fonts cannot be displayed by using the cgram. the cgram is used as the ram for the graphics display.
HD66732 99 figure 54 example of super-imposed display
HD66732 100 vertical smooth scroll the HD66732 can scroll vertically in units of one dot. vertical smooth scrolling is enabled for the character display, graphics display, and super-imposed display modes. in vertical scrolling, the display start position is controlled in one-raster-row units by incrementing or decrementing the display start line (sn1/0) and display-start raster-row (sl3/2/1/0). however, segment icons (marks) displayed by using the segram are not scrolled. if the response speed of the liquid crystal is slow and cannot keep up with one-raster-row scrolling, scroll multiple raster-row units together. moreover, if vertical smooth scrolling is performed with a four-line display (1/54 duty), the display raster-row that has scrolled out of the display will appear again from the bottom (or the top) (this function is called lap-around). in this case, confirm the display line position (nf1/0) and display raster-row position (lf3?) flags in the status register, and update the display data in the ddram or cgram while lcd driving is not performed.
HD66732 101 figure 55 example of vertical smooth scroll display
HD66732 102 vertical smooth scroll at 3-line display (nl2? = 011) db7 db6 db5 db4 db3 db2 db1 db0 r/w rs 0 000 00 0 1 index register set (ra designation) 10 1 0100 00 normal display (begins display from the 1st raster-row of the 1st line) 2 0 0 cpu wait 0100 00 scrolls four raster-rows up (begins display from the 5th raster-row of the 1st line) 3 0 0 cpu wait 0100 00 4 0 0 cpu wait 00 0 1 1 0 0100 00 5 1 0 cpu wait 00 update the display data in the 1st-line ddram or cgram 0 000 00 0 6 10 1 0100 00 7 1 0 cpu wait 01 0100 00 8 1 0 cpu wait 10 0100 00 9 0 100 update the display data in the 2nd-line ddram or cgram scrolls eight raster-rows up (begins display from the 9th raster-row of the 1st line) scrolls 13 raster-rows up (begins display from the 1st raster-row of the 2nd line) index register set (ra designation) scrolls 21 raster-rows up (begins display from the 9th raster-row of the 2nd line) scrolls 26 raster-rows up (begins display from the 1st raster-row of the 3rd line) scrolls 17 raster-rows up (begins display from the 5th raster-row of the 2nd line) notes: 1. the ddram or cgram has only four-line ram capacity. after the 13th raster-row in the fourth line is displayed, the first raster-row in the first line is lap-around displayed again. 2. in four-line display (nl2? = 100), all areas of the ddram and cgram are used and displayed. therefore, update the contents of the ddram or cgram after checking the flags of the display line position (nf1/0) and display raster-row position (lf3?) in the status register while the lcd driving is not performed. lcd driving is performed by time sharing from the first raster-row in the first line. for example, when the display data in the first line is updated, start driving when the lcd driving line enters the second line by the status register, and complete by the beginning of the 13th raster-row driving in the fourth line. figure 56 vertical scroll control
HD66732 103 reversed display function the HD66732 can display character/graphics display sections by black-white reversal except for the segment/icon display sections. black-white reversal can be easily displayed without rewriting the data in the ram when rev is set to 1. the segment and icon sections are not black-white reversed and do not depend on the rev bit setting. figure 57 example of reversed display
HD66732 104 blink mark display the HD66732 has a grayscale display and blink display based on 200 individual segments (marks). forty of these are for grayscale display and the remainder are for blink display. these 40 segments can also control the grayscale display, providing simple grayscale on specific pictograms or marks. the above display uses a curtailed frame grayscale system, and flicker may result in quick-response liquid crystal materials. table 57 shows the relationship between set data in the segram and the effective applied voltage during the frame curtailing operation. these grayscale control segments are driven with the same grayscale data when coms1 and coms2 are selected. the remaining 160 segments are responsible for normal blinking and double-speed blinking. normal blinking (black and white) is achieved by repeatedly turning on each segment for 32 frames and turning it off for the next 32 frames. double-speed blinking (black and white) is achieved by repeatedly turning each segment on and off every 16 frames. these blinking control segments are driven by the independent blinking data when coms1 and coms2 are selected. table 55 relationship between segment driver output pin and segment display function when sgs = 0 when sgs = 1 remarks seg1/120, seg4/117, seg7/114, seg10/111, seg13/108, seg16/105, seg19/102, seg22/99, seg25/96, seg28/93, seg31/90, seg34/87, seg37/84, seg40/81, seg43/78, seg46/75, seg49/72, seg52/69, seg55/66, seg58/63, seg61/60, seg64/57, seg67/54, seg70/51, seg73/48, seg76/45, seg79/42, seg82/39, seg85/36, seg88/33, seg91/30, seg94/27, seg97/24, seg100/21, seg103/18, seg106/15, seg109/12, seg112/9, seg115/6, seg118/3 seg120/1, seg117/4, seg114/7, seg111/10, seg108/13, seg105/16, seg102/19, seg99/22, seg96/25, seg93/28, seg90/31, seg87/34, seg84/37, seg81/40, seg78/43, seg75/46, seg72/49, seg69/52, seg66/55, seg63/58, seg60/61, seg57/64, seg54/67, seg51/70, seg48/73, seg45/76, seg42/79, seg39/82, seg36/85, seg33/88, seg30/91, seg27/94, seg24/97, seg21/100, seg18/103, seg15/106, seg12/109, seg9/112, seg6/115, seg3/118 the coms1 and coms2 outputs are controlled by the same grayscale. total: 40 segments output pins other than above output pins other than above the coms1 and coms2 outputs are independently controlled. total: 80 x 2 = 160 segments
HD66732 105 table 56 relationship between segram data and blinking segment segram data setting lcd display control for segram data setting lcd display control for db5 db4 coms1 segment db7 db6 coms2 segment 0 0 always unlit 0 0 always unlit 0 1 always lit 0 1 always lit 1 0 normal blinking (32-frame unit) 1 0 normal blinking (32-frame unit) 1 1 double-speed blinking (16-frame unit) 1 1 double-speed blinking (16-frame unit) alternates every 32 frames alternates every 16 frames i) normal blinking display ii) double-speed blinking display figure 58 blinking segment display
HD66732 106 table 57 relationship between segram data and grayscale segment display segram data setting db7 db6 db5 db4 effective applied voltage for coms1 and coms2 outputs 00000 (always unlit) 00011 (always lit) 0010 0.34 (grayscale display) 0011 0.38 (grayscale display) 0100 0.41 (grayscale display) 0101 0.44 (grayscale display) 0110 0.47 (grayscale display) 0111 0.50 (grayscale display) 1000 (blink display) * 1001 0.53 (grayscale display) 1010 0.56 (grayscale display) 1011 0.59 (grayscale display) 1100 0.63 (grayscale display) 1101 0.66 (grayscale display) 1110 0.69 (grayscale display) 1111 0.72 (grayscale display) note: turn on the segment for 32 frames and turn it off for the next 32 frames.
HD66732 107 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 segram set data (on) (blinking) (off) grayscale control range effective applied voltage ratio figure 59 relationship between segram set data and effective applied voltage
HD66732 108 line-cursor display the HD66732 can assign a cursor attribute to an entire line corresponding to the address counter value by setting the lc bit to 1. one of three line-cursor modes can be selected: a black-white reversed cursor (b/w = 1), an underline cursor (c = 1), and a blink cursor (b = 1). the cycle for a blink cursor is 32 frames. these line-cursors are suitable for highlighting an index and/or marker, or for indicating an item in a menu with a cursor or an underline. however, the black-white reversed display described above does not perform black-white blinking. table 58 address counter value and line cursor address counter value (ac) selected line for line cursor 00h to 13h entire 1st line (10 characters) 20h to 33h entire 2nd line (10 characters) 40h to 53h entire 3rd line (10 characters) 60h to 73h entire 4th line (10 characters)
HD66732 109 black-white reserved display (lc = 1, r/w = 1) figure 60 black-white reversed cursor underline cursor (lc = 1, c = 1) figure 61 underline cursor
HD66732 110 blinking display (lc = 1, b = 1) figure 62 blinking display
HD66732 111 partial-display-on function the HD66732 can program the liquid crystal display drive duty ratio setting (nl2-0 bits), liquid crystal display drive bias value selection (bs2-0 bits), boost output level selection (bt1/0 bit) and contrast adjustment (ct4-0 bits). for example, in the four-line display mode (1/54 duty ratio), the HD66732 can drive only two lines in the center of the screen by combining these register functions and the centering display (cen bit) function with the 1/28 duty ratio. this is called partial-display-on. lowering the liquid crystal display drive duty ratio as required saves the liquid crystal display drive voltage, thus reducing internal current consumption. this is suitable for calendar or time display, which needs to be continuous in the system standby state with minimal current consumption. here, the non-displayed lines are constantly driven by the unselected level voltage, thus turning off the lcd for the lines. in general, lowering the liquid crystal display drive duty ratio decreases the optimum liquid crystal display drive voltage and liquid crystal display drive bias value. table 59 partial-display-on function (4-line display) item normal 4-line display partial-on display character/graphics display 4th line displayed only one line in the center of the screen only two lines in the center of the screen lcd drive duty ratio 1/54 (nl2/1/0 = 100) 1/15 (nl2/1/0 = 001) 1/28 (nl2/1/0 = 010) lcd drive bias value (optimum) 1/8 (bs2-0 = 000) 1/5 (bs2-0 = 100) 1/6 (bs2-0 = 010) lcd drive voltage adjustable using bt1/0 and ct4-0 adjustable using bt1/0 and ct4-0 adjustable using bt1/0 and ct4-0 frame frequency (fosc = 76 khz) 70 hz 71 hz 70 hz
HD66732 112 figure 63 partial-on display (date and time indicated)
HD66732 113 sleep mode setting the sleep mode bit (slp) to 1 puts the HD66732 in the sleep mode, where the device stops all internal display operations except for key scan operations, thus reducing current consumption. specifically, lcd drive is completely halted. here, all the seg (seg1 to seg120) and com (com1 to com52, coms1/2) pins output the gnd level, resulting in no display. if the amp bit is set to 0 in the sleep mode, the lcd drive power supply can be turned off, reducing the total current consumption of the lcd module. the key scan circuit operates normally in the sleep mode, thus allowing normal key scan and key scan interrupt generation. for details, see the key scan control section and key scan interrupt (wake-up function) section. table 60 comparison of sleep mode and standby mode function sleep mode (slp = 1) standby mode (stb = 1) key standby mode (ksb = 1) character display turned off turned off normally turned on segment display turned off turned off normally turned on r-c oscillation circuit operates normally halted operates normally key scan circuit can operate normally halted but irq* can be generated
HD66732 114 standby mode setting the standby mode bit (stb) to 1 puts the HD66732 in the standby mode, where the device stops completely, halting all internal operations including the r-c oscillation circuit, thus further reducing current consumption compared to that in the sleep mode. specifically, character and segment displays, which are controlled by the multiplexing drive method, are completely halted. here, all the seg (seg1 to seg120) and com (com1 to com52, coms1/2) pins output the gnd level, resulting in no display. if the amp bit is set to 0 in the standby mode, the lcd drive power supply can be turned off. during the standby mode, no instructions can be accepted other than those for the start-oscillation instruction and the key scan interrupt generation enable instruction. to cancel the standby mode, issue the start-oscillation instruction to stabilize r-c oscillation before setting the stb bit to 0. although key scan is halted in the standby mode, the HD66732 can detect key inputs, thus generating key scan interrupt (irq*). this means, the system can be activated from a completely inactive state. for details, see the key scan interrupt (wake-up function) section. set standby mode: stb = 1 standby mode (key scan interrupt enabled) issue the start-oscillation instruction wait at least 10 ms cancel standby mode: stb = 0 turn on the lcd drive power supply: amp = 1 turn off the lcd power supply: amp = 0 figure 64 procedure for setting and canceling standby mode
HD66732 115 key standby mode when the key standby mode (ksb bit = "1") is set, only key-scan operations are selectively stopped. in this case, however, the display operation, including the internal cr oscillation circuit operation, continues as usual. since noise generation can be suppressed by stopping unnecessary key-scan operations, the receiving sensitivity for such a wireless system can be improved. in this case, although key-scan operations are stopped during standby mode, a key scan interrupt (irq*) can be generated by detecting the key being depressed, as can be done during the standby mode described above. for details, refer to the key scan interrupt (wake-up function) section.
HD66732 116 absolute maximum ratings * item symbol unit value notes* power supply voltage (1) v cc v ?.3 to +7.0 1 power supply voltage (2) v lcd ?gnd v ?.3 to +15.0 1, 2 input voltage vt v ?.3 to v cc + 0.3 1 operating temperature topr c ?0 to +85 3 storage temperature tstg c ?5 to +110 4 note: if the lsi is used above these absolute maximum ratings, it may become permanently damaged. using the lsi within the following electrical characteristics limits is strongly recommended for normal operation. if these electrical characteristic conditions are also exceeded, the lsi will malfunction and cause poor reliability.
HD66732 117 dc characteristics (v cc = 2.4 to 5.5 v, ta = ?0 to +85 c* 3 ) item symbol min typ max unit test condition notes input high voltage v ih 0.7 v cc ? cc v 5, 6 input low voltage v il ?.3 0.15 v cc vv cc = 2.4 to 2.7 v 5, 6 input low voltage v il ?.3 0.15 v cc vv cc = 2.7 to 5.5 v 5, 6 output high voltage (1) (sda, db0-7 pins) v oh1 0.75 v cc vi oh = ?.1 ma 5, 7 output low voltage (1) (sda, db0-7 pins) v ol1 0.2 v cc vv cc = 2.4 to 2.7 v, i ol = 0.1 ma 5 output low voltage (1) (sda, db0-7 pins) v ol1 0.15 v cc vv cc = 2.7 to 5.5 v, i ol = 0.1 ma 5 output high voltage (2) (kst0-7, irq* pins) v oh2 0.7 v cc vi oh = 0.5 m a, v cc = 3 v 5 output low voltage (2) (kst0-7, irq* pins) v ol2 0.2 v cc vi ol = 0.1 ma 5 output high voltage (3) (port0-2 pins) v oh3 0.75 v cc v-i oh = 0.1ma 5 output low voltage (3) (port0-2 pins) v ol3 0.2 v cc vi ol = 0.1ma 5 driver on resistance (com pins) r com 3 20 k w id = 0.05 ma, v lcd = 6 v 8 driver on resistance (seg pins) r seg 3 30 k w id = 0.05 ma, v lcd = 6 v 8 i/o leakage current i li ? 1 m a vin = 0 to v cc 9 pull-up mos current (kin0-7, db0-7, sda pins) -i p 11040 m av cc = 3 v, vin = 0 v 5 current consumption during normal operation (v cc ?nd) i op ?055 m a r-c oscillation, v cc = 3 v, f osc = 60 khz (1/41 duty) 10, 11 current consumption during sleep mode (v cc ?nd) i sl ?3 m a r-c oscillation, v cc = 3 v, f osc = 60 khz (1/41 duty) 10, 11 current consumption during standby mode (v cc ?nd) i st 0.1 5 m a no r-c oscillation, v cc = 3 v, ta = 25 c 10, 11 lcd drive power supply current (v lcd ?nd) i ee ?530 m av lcd ?gnd = 8 v, f osc = 60 khz, 1/7 bias, vtest3 = ? cc 11 lcd drive voltage (v lcd ?gnd) v lcd 4.5 13.0 v 12 note: for the numbered notes, refer to the electrical characteristics notes section following these tables.
HD66732 118 booster characteristics item symbol min typ max unit test condition notes double-boost output voltage (vlout pin) v up2 5.5 5.9 6.0 v v cc = vci = 3.0 v, i o = 0.03 ma, c = 1 m f, f osc = 60 khz, ta = 25 c 15 triple-boost output voltage (vlout pin) v up3 8.5 8.9 9.0 v v cc = vci = 3.0 v, i o = 0.03 ma, c = 1 m f, f osc = 60 khz, ta = 25 c 15 quadruple- boost output voltage (vlout pin) v up4 11.5 11.8 12.0 v v cc = vci = 3.0 v, i o = 0.03 ma, c = 1 m f, f osc = 60 khz, ta = 25 c 15 booster output voltage range v up v cc 13.0 v vci v cc 15, 16 note: for the numbered notes, refer to the electrical characteristics notes section following these tables. ac characteristics (v cc = 2.4 to 5.5 v, ta = ?0 to +85 c* 3 ) clock characteristics (v cc = 2.4 to 5.5 v) item symbol min typ max unit test condition notes external clock frequency fcp 40 60 100 khz 13 external clock duty ratio duty 45 50 55 % 13 external clock rise time trcp 0.2 m s13 external clock fall time tfcp 0.2 m s13 internal rf oscillation frequency t osc 45 60 75 khz rf = 300 k w , v cc = 3 v 14 note: for the numbered notes, refer to the electrical characteristics notes section following these tables.
HD66732 119 68-system bus interface timing characteristics (vcc = 2.4 to 2.7 v) item symbol min typ max unit test condition enable cycle time write t cyce 800 ns figure 71 read 1200 enable high-level pulse width write pw eh 150 ns figure 71 read 450 enable low-level pulse width write pw el 300 ns figure 71 read 450 enable rise/fall time t er , t ef 25 ns figure 71 setup time (rs, r/w to e, cs*) t ase 50 ns figure 71 address hold time t ahe 20 ns figure 71 write data setup time t dswe 60 ns figure 71 write data hold time t he 20 ns figure 71 read data delay time t ddre 400 ns figure 71 read data hold time t dhre 5 ns figure 71 (vcc = 2.7 to 5.5 v) item symbol min typ max unit test condition enable cycle time write t cyce 500 ns figure 71 read 700 enable high-level pulse width write pw eh 80 ns figure 71 read 300 enable low-level pulse width write pw el 250 ns figure 71 read 320 enable rise/fall time t er , t ef 25 ns figure 71 setup time (rs, r/w to e, cs*) t ase 50 ns figure 71 address hold time t ahe 20 ns figure 71 write data setup time t dswe 60 ns figure 71 write data hold time t he 20 ns figure 71 read data delay time t ddre 250 ns figure 71 read data hold time t dhre 5 ns figure 71
HD66732 120 80-system bus interface timing characteristics (vcc = 2.4 to 2.7 v) item symbol min typ max unit test condition bus cycle time write t cycw 800 ns figure 72 read t cycr 1200 ns figure 72 write low-level pulse width pw lw 150 ns figure 72 read low-level pulse width pw lr 450 ns figure 72 write high-level pulse width pw hw 300 ns figure 72 read high-level pulse width pw hr 450 ns figure 72 write/read rise/fall time t wrr , wrf 25 ns figure 72 setup time (rs to cs*, wr*, rd*) t as 50 ns figure 72 address hold time t ah 20 ns figure 72 write data setup time t dsw 60 ns figure 72 write data hold time t h 20 ns figure 72 read data delay time t ddr 400 ns figure 72 read data hold time t dhr 5 ns figure 72 (vcc = 2.7 to 5.5 v) item symbol min typ max unit test condition bus cycle time write t cycw 500 ns figure 72 read t cycr 700 ns figure 72 write low-level pulse width pw lw 80 ns figure 72 read low-level pulse width pw lr 300 ns figure 72 write high-level pulse width pw hw 250 ns figure 72 read high-level pulse width pw hr 300 ns figure 72 write/read rise/fall time t wrr, wrf 25 ns figure 72 setup time (rs to cs*, wr*, rd*) t as 50 ns figure 72 address hold time t ah 20 ns figure 72 write data setup time t dsw 60 ns figure 72 write data hold time t h 20 ns figure 72 read data delay time t ddr 250 ns figure 72 read data hold time t dhr 5 ns figure 72
HD66732 121 clock-synchronized serial interface timing characteristics (2.4 v) (v cc = 2.4 to 2.7 v) item symbol min typ max unit test condition serial clock cycle time write t scyc 0.5 20 m s figure 73 read t scyc 120 m s figure 73 serial clock high-level width write t sch 230 ns figure 73 read t sch 480 ns figure 73 serial clock low-level width write t scl 230 ns figure 73 read t scl 480 ns figure 73 serial clock rise/fall time t scf , t scr 20 ns figure 73 chip select setup time t csu 60 ns figure 73 chip select hold time t ch 200 ns figure 73 serial input data setup time t sisu 100 ns figure 73 serial input data hold time t sih 100 ns figure 73 serial output data delay time t sod 400 ns figure 73 serial output data hold time t soh 5 ns figure 73 (v cc = 2.7 to 5.5 v) item symbol min typ max unit test condition serial clock cycle time write t scyc 0.2 20 m s figure 73 read t scyc 0.5 20 m s figure 73 serial clock high-level width write t sch 80 ns figure 73 read t sch 230 ns figure 73 serial clock low-level width write t scl 80 ns figure 73 read t scl 230 ns figure 73 serial clock rise/fall time t scf , t scr 20 ns figure 73 chip select setup time t csu 60 ns figure 73 chip select hold time t ch 200 ns figure 73 serial input data setup time t sisu 40 ns figure 73 serial input data hold time t sih 40 ns figure 73 serial output data delay time t sod 200 ns figure 73 serial output data hold time t soh 5 ns figure 73
HD66732 122 reset timing characteristics (v cc = 2.4 to 5.5 v) item symbol min typ max unit test condition reset low-level width t res 1 ms figure 74
HD66732 123 electrical characteristics notes 1. all voltage values are referred to gnd = 0 v. if the lsi is used above the absolute maximum ratings, it may become permanently damaged. using the lsi within the given electrical characteristic is strongly recommended to ensure normal operation. if these electrical characteristics are exceeded, the lsi may malfunction or exhibit poor reliability. 2. vlcd > gnd must be maintained. 3. for bare die products, specified up to 85?c. 4. for bare die products, specified by the common die shipment specification. 5. the following three circuits are i/o pin configurations (figure 65). pins: reset*, cs*, e/wr*/scl, rs, osc1, opoff, im2/1, im0/id, test pins: kst3 to kst0, irq* port2 to port0, osc2 pmos nmos vcc gnd pin: rw/rd*/sda pmos nmos vcc gnd (tri-state output circuit) (input circuit) (pull-up mos) pmos pmos nmos pmos nmos gnd vcc output enable output data vcc vcc im1 im2 figure 65 i/o pin configuration
HD66732 124 im0 pin: db7/kin7 to db4/kin4 (tri-state output circuit) (input circuit) (pull-up mos) pmos pmos nmos pmos nmos gnd vcc output enable output data vcc vcc im1 pin: db3/kin3 to db0/kin0 (tri-state output circuit) (input circuit) (pull-up mos) pmos pmos nmos pmos nmos gnd vcc output enable output data vcc vcc im1 figure 65 i/o pin configuration (cont) 6. the test pin must be grounded and the im2/1, im0/id, and opoff pins must be grounded or connected to vcc. 7. corresponds to the high output for clock-synchronized serial interface. 8. applies to the resistor value (rcom) between power supply pins v1out, v2out, v5out, gnd and common signal pins (com1 to com52, coms1 and coms2), and resistor value (rseg) between power supply pins v1out, v3out, v4out, gnd and segment signal pins (seg1 to seg120), when current id is flown through all driver output pins. 9. this excludes the current flowing through pull-up moss and output drive moss. 10. this excludes the current flowing through the input/output units. the input level must be fixed high or low because through current increases if the cmos input is left floating. 11. the following shows the relationship between the operation frequency (fosc) and current consumption (icc) (figure 66).
HD66732 125 cr oscillation frequency: fosc (khz) 60 40 20 0 iop ( a) vcc = 3 v 0 display on (typ.) sleep (typ.) typ. 30 20 10 0 i lcd ( a) vcc = 3 v, fosc = 60 khz 6.0 lcd drive voltage: vlcd (v) 8.0 10.0 12.0 standby (typ.) 20 100 80 60 40 referential data figure 66 relationship between the operation frequency and current consumption 12. each com and seg output voltage is within 0.15 v of the lcd voltage (vcc, v1, v2, v3, v4, v5) when there is no load. 13. applies to the external clock input (figure 67). oscillator osc1 open osc2 t rcp t fcp th tl 0.7vcc 0.5vcc 0.3vcc duty = th+tl th 100% figure 67 external clock supply
HD66732 126 14. applies to the internal oscillator operations using oscillation resistor rf (figure 68). osc1 osc2 rf since the oscillation frequency varies depending on the osc1 and osc2 pin capacitance, the wiring length to these pins should be minimized. referential data external resistance (rf) cr oscillation frequency : fosc vcc = 2.2 v 117 khz 73 khz 67 khz 56 khz 45 khz 37 khz vcc = 3.0 v 130 khz 85 khz 73 khz 60 khz 48 khz 40 khz vcc = 4.0 v 138 khz 93 khz 78 khz 62 khz 50 khz 42 khz vcc = 5.0 v 143 khz 98 khz 81 khz 63 khz 51 khz 43 khz 120 k 180 k 240 k 300 k 390 k 470 k figure 68 internal oscillation 15. booster characteristics test circuits are shown in figure 69. (triple boosting) (double boosting) gnd vcc 1 f vci c1+ c1- vlout + vlcd c2+ c2- 1 f + gnd vcc 1 f vci c1+ c1- vlout + vlcd c2+ c2- 1 f + 1 f + (quadruple boosting) gnd vcc 1 f vci c1+ c1- vlout + vlcd c2+ c2- 1 f + 1 f + c3+ c3- c3+ c3- c3+ c3- 1 f + figure 69 booster
HD66732 127 vup2 = v lout ?gnd; vup3 = v lout ?gnd; vup4 = v lout ?gnd 5.0 4.0 3.0 2.0 4 5 6 7 8 9 10 11 (i) relation between the obtained voltage and input voltage vci (v) vup2/ vup3/ vup4 (v) vci = vcc, fcp = 60 khz, ta = 25?c (ii) relation between the obtained voltage and temperature referential data 12 13 14 15 double boosting triple boosting quadruple boosting (iii) relation between the obtained voltage and capacitance (iv) relation between the obtained voltage and current vci = vcc = 3.0 v, fosc = 60 khz, io = 30 a triple boosting ta (?c) vup3 (v) 100 60 20 0 ?0 ?0 7.5 8.0 8.5 9.0 9.5 typ. vci = vcc = 3.0 v, fosc = 60 khz, io = 30 a vci = vcc = 3.0 v, fosc = 60 khz, io = 30 a 1.5 1.0 0.5 9.0 9.5 10.0 11.5 12.0 typ. c ( f) vup4(v) triple boosting quadruple boosting c ( f) vup3(v) 1.5 1.0 0.5 7.0 7.5 8.0 8.5 9.0 typ. vci = vcc = 3.0 v, fosc = 60 khz, ta = 25 c io ( a) vup2/vup3/vup4 (v) 100 50 0.0 single boosting triple boosting quadruple boosting 4.0 5.0 6.0 7.0 8.0 9.0 11.0 12.0 3.0 2.0 1.0 10.0 30 double boosting figure 69 booster (cont)
HD66732 128 16. vcc 3 vci must be maintained.
HD66732 129 load circuits ac characteristics test load circuits data bus: db7 to db0, sda test point 50 pf figure 70 load circuit
HD66732 130 timing characteristics 68-system bus operation rs note: pw eh is defined as the overlapped period of cs* low-level and e high-level. r/w cs* e db0 to db7 db0 to db7 v ih v il t ase t ahe pw eh * t ef t er t dswe t he write data t cyce t ddre t dhre v oh1 v ol1 v oh1 v ol1 read data v ih v il v il v il v ih v ih v il v il v ih v il v ih v il pw el v il figure 71 68-system bus timing
HD66732 131 80-system bus operation rs cs* wr* rd* db0 to db7 db0 note: pw lw is defined as the overlapped period of cs* low-level and wr* low-level. pw lr is defined as the overlapped period of cs* low-level and rd* low-level. to db7 v ih v il t as t ah pw lr, pw ld t wrf t wrr t dsw t hwr write data t cycw, t cycr t ddr t dhrd v oh1 v ol1 v oh1 v ol1 read data v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih pw hr, pw hd figure 72 80-system bus timing
HD66732 132 clock-synchronized serial operation cs* scl sda t csu t sch v il t sisu tscr v ih v il v ih v il v ih v il t ch v ih v il v ih v il t cwl tscf t sih v il t scyc input data v ih start: s end: p input data sda t sod v oh1 v oh1 v oh1 v ol1 output data output data t soh v il figure 73 clock-synchronized serial interface timing reset operation reset* v il v il t res figure 74 reset timing
HD66732 133 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/indx.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 179 east tasman drive, san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to:

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