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ics for communications analog front end for telephone systems sam-afe psb 4851 version 2.1 data sheet 09.99 ds 1
for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representatives worldwide: see our webpage at http://www.infineon.com psb 4851 revision history: current version: 09.99 previous version: none page (in previous version) page (in new version) subjects (major changes since last revision) edition 09.99 published by infineon technologies ag tr, balanstra?e 73, 81541 mnchen ? infineon technologies ag 1999. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreement we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the infineon technologies ag, may only be used in life-support devices or systems 2 with the express written approval of the infineon technologies ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. if they fail, it is reasonable to assume that the health of the user may be en- dangered. abm ? , aop ? , arcofi ? , arcofi ? -ba, arcofi ? -sp, digitape ? , epic ? -1, epic ? -s, elic ? , falc ? 54, falc ? 56, falc ? -e1, falc ? -lh, idec ? , iom ? , iom ? -1, iom ? -2, ipat ? -2, isac ? -p, isac ? -s, isac ? -s te, isac ? -p te, itac ? , iwe ? , musac ? -a, octat ? -p, quat ? -s, sicat ? , sicofi ? , sicofi ? -2, sicofi ? -4, sicofi ? -4c, slicofi ? are registered trademarks of infineon technologies ag. ace ? , asm ? , asp ? , potswire ? , quadfalc ? , scout ? are trademarks of infineon technologies ag.
psb 4851 data sheet iii 09.99 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 1.3 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.4 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 1.5 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 1.6 system integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 1.6.1 analog featurephone with digital answering machine . . . . . . . . . . . . . .10 1.6.2 dect basestation with full duplex featurephone . . . . . . . . . . . . . . . . .11 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.1 signal paths and functional units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.2 line powered operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2.3 attenuation plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 2.4 analog front end interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 2.5 serial control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 2.6 test loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 2.6.1 analog loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 2.6.2 digital loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 4.2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 4.3 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
psb 4851 data sheet 4 09.99 1 overview the psb 4851 integrates all amplifiers to directly connect the transducers to the chip. it features two completely independent channels. an integrated analog multiplexer allows the connection of three signal sources (handset microphone, speakerphone microphone, analog line) to the two channels. furthermore the psb 4851 supports a sophisticated power management and a loop mode in the analog domain. these features can be used to implement a line powered mode for emergency operation of the phone. the chip is programmed by a simple four wire serial control interface.
p-tqfp-144 data sheet 5 09.99 analog front end for telephone systems sam-afe psb 4851 version 2.1 cmos type package psb 4851 p-tqfp-144 1.1 features ? direct connection to handset ? direct connection to microphone ? direct connection to loudspeaker (50 w ) ? low power emergency operation ? serial control interface for programming ? 3.3v or 5v operation (full operating mode) ? 3v-5v voltage range (emercency mode) ? 2.4 v reference voltage ? two differential inputs ? support for controlled loudhearing ? compliant to g.712
psb 4851 data sheet 6 09.99 1.2 pin configuration (top view) figure 1-1 pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v ddd v dda v ddp v ssd v ssa v ssp afedu afedd afeclk afefs sclk sdx sdr cs rst axi min1 mip1 min2 mip2 axo hop hon lsp lsn v refbg v ref n.c.
psb 4851 data sheet 7 09.99 1.3 pin definitions and functions table 1-1 pin definitions and functions pin no. p-dso-28-1 symbol dir. reset function 5 v ddd -- power supply (3.0v - 3.6v or 4.75v - 5.25v) power supply for digital parts. must be at the same level as v dda and v ddp . 6 v dda -- power supply (3.0v - 3.6v or 4.75v - 5.25v) power supply for analog parts. must be at the same level as v ddd and v ddp . 15 v ddp -- power supply (3.0v - 3.6v or 4.75v - 5.25v) power supply for amplifiers. must be at the same level as v dda and v ddd . 22 v ssd -- power supply (0 v) ground for digital parts. 7 v ssa -- power supply (0 v) ground for analog parts. 17 v ssp -- power supply (0 v) ground for amplifiers. 1afeduol data upstream: data output to psb 4860. 2afeddi- data downstream: data input from psb 4860. 3afeclki- data clock: 6.912 mhz clock. 4afefsi- frame synchronization: 8khz frame synchronization from psb 4860. 28 sclk i - serial clock: clock for serial control interface (sci). 27 sdx od h serial data transmit: data output for serial control interface (sci). 26 sdr i - serial data receive: data input for serial control interface (sci). 25 cs i- chip select: select signal for serial control interface (sci).
psb 4851 data sheet 8 09.99 23 rst i - reset: active high reset signal. 10 axi i - auxiliary input: single ended analog input (e.g. line in) 13 14 min1 mip1 i i - microphone input 1: this input provides a highly symmetrical differential input for commonly used telephone microphones. 11 12 min2 mip2 i i - microphone input 2: this input provides a highly symmetrical differential input for commonly used telephone microphones. 21 axo o 0 v auxiliary output: single ended analog output (e.g line out). 19 20 hop hon o o 0v 0v handset earpiece output: differential outputs which can drive common handset earpiece transducers (200 w ) directly. 16 18 lsp lsn o0v 0v loudspeaker output: differential outputs which can drive a 50 w loudspeaker at 5v or a 25 w loudspeaker at 3.3v directly. a piezo transducer can be used for ringing instead of the loudspeaker. 8v refbg o0v reference bandgap voltage connection to external 22 nf capacitor for low pass filtering. 9 v ref o0v reference voltage (2.4 v): output for biasing external circuitry, e.g. electret microphone. connection to external 100 nf capacitor. table 1-1 pin definitions and functions pin no. p-dso-28-1 symbol dir. reset function
psb 4851 data sheet 9 09.99 1.4 logic symbol figure 1-2 logic symbol of psb 4851 sdx sdr sclk cs sci mip 1 min 1 afeclk afefs afedd afedu psb 4860 mip 2 min 2 axi lsp lsn hop hon axo v ddd v dda v ddp v ssd rst v ssa v ssp v ref ref bg psb 4851 analog analog inputs outputs
psb 4851 data sheet 10 09.99 1.5 functional block diagram figure 1-3 block diagram of psb 4851 1.6 system integration the psb 4851 is the standard analog interface for several digital telecommunication ics such as: ? psb 4860 (digital answering machine) ? psb 2170 (acoustic echo canceller) the psb 4851 is especially suited for applications that need two independent analog channels where one codec interfaces to a loudspeaker/microphone combination while the other codec serves the line. 1.6.1 analog featurephone with digital answering machine figure 1-4 shows an example of an analog telephone system. the telephone can operate during power failure by line powering. in this case only the handset is active. all other parts of the chipset are shut down leaving enough power for the external microcontroller to perform basic tasks like keyboard monitoring. sdx sdr sclk cs mip 1 min 1 afeclk afefs afedd afedu mip 2 min 2 axi lsp lsn hop hon axo rst mux control interface data interface mux a/d a/d d/a d/a vref v ref
psb 4851 data sheet 11 09.99 for answering machine operation the voice data is stored in aram or flash memory devices and voice prompts can be played back from an optional voice prompt eprom. if flash memory is used the functionality of the voice eprom can be realized by the flash memory devices. figure 1-4 analog full duplex speakerphone with digital answering machine 1.6.2 dect basestation with full duplex featurephone figure 1-5 shows a dect basestation with acoustic echo cancellation based on the psb 2170. the full duplex featurephone can be switched to the basestation or a mobile handset dynamically. for programming the serial control interface (sci) is used while voice data is transferred via the strobed serial data interface (ssdi). voice prompt aram flash memory eprom microcontroller 077-3445 line tip/ ring psb 4851 psb 4860 afe sci
psb 4851 data sheet 12 09.99 figure 1-5 dect basestation with full duplex speakerphone psb 2170 psb 4851 microcontroller 077-3445 antenna burstmode controller dect hf line tip/ ring afe sci iom ? -2/ssdi
psb 4851 data sheet 13 09.99 2 functional description the psb 4851 provides two bidirectional channels from the analog domain to the digital domain, an internal loopback and a sophisticated power management for line-powered operation. the first section describes the signal paths and functional units of the psb 4851 while the second section discusses the support of the line powered operation. 2.1 signal paths and functional units the psb 4851 supports three analog inputs, three analog outputs and two digital channels (table 2-1). these signals can be routed in either pass-through or loopback mode (fig. 2-1). in loopback mode different loops are available for test purposes and line powered operation. in loopback mode the digital part of the psb 4851 can be completely shut down if it is not needed. the loop on the analog side remains fully functional. figure 2-1 basic configurations of psb 4851 table 2-1 analog inputs pins comment axi line input from tip/ring interface mip1, min1 mic. 1, e.g. speakerphone microphone mip2, min2 mic. 2, e.g. handset microphone analog outputs axo line output to tip/ring interface hop, hon handset earpiece lsp, lsn speakerphone loudspeaker digital channels afedd, afedu, afefs, afeclk channel 1and 2 of afe interface (to/ from psb 2170, psb 4860) c 1 c 2 line hs/ psb 4851 c 1 c 2 line hs psb 4851 pass-through loopback mic/spkr
psb 4851 data sheet 14 09.99 a detailed functional diagram of the psb 4851 is shown in figure 2-2. figure 2-2 detailed block diagram of psb 4851 two differential inputs for microphones and one single ended input for the tip/ring interface are fed to two analog input amplifiers (mic2, mic1). these amplifiers can be programmed for a gain of up to 42 db in steps of 6 db. for both the loudspeaker and the handset transducer differential amplifiers (als, ahs) are provided. these amplifiers can be programmed within a range of 33 (24) db in steps of 3 db or muted. a third programmable amplifier (axc) is provided for the tip/ring interface. the high passes (hp) have a cut-off frequency of 150 hz. these filters can be disabled individually for the receive and transmit direction. v ref axi mip1 mip2 min1 min2 hop lsp lsn hon axo als 50 w 200 w ahs axc mic1 mic2 pofi 2 pofi 1 prefi 1 prefi 2 d/a d/a deci 1 a/d 1 a/d 2 int 2 deci 2 int 1 afedu afedd inter- face vref 10 k w hp hp hp hp
psb 4851 data sheet 15 09.99 2.2 line powered operation the psb 4851 supports line powered operation by a flexible power management. the controller can power down all elements that are not needed for the current task. in particular, the following three states are useful in line powered operation: 1. idle all elements are powered down. the power consumption is minimal. this state is automatically entered by reset. 2. ringing mic1 is in bypass mode, prefi1 is powered up and als is connected to prefi1. therefore a signal fed into axi is amplified by als and output at lsp/lsn. in order to maximize the loudness of the ringing signal one of the output drivers of als (either lsp or lsn) can be forced to gnd thus providing a single ended output. figure 2-3 shows the signal routing and the remaining active elements in this mode (single ended mode). figure 2-3 emergency ringing mode v ref axi lsp lsn als 50 w prefi 1 vref
psb 4851 data sheet 16 09.99 3. speech mic1, prefi1, mic2, prefi2, ahs and axc are powered up. ahs is connected to prefi1 and axc is connected to prefi2. therefore the signal fed into mip2/min2 is amplified by mic2 and axc and output at axo. the signal fed into axi is amplified by mic1 and ahs and output at hop/hon. figure 2-4 shows the signal routing and the active elements. figure 2-4 emergency speech mode note: an external circuitry should be provided to detect power failure and inform the controller. the controller in turn should reduce the gain of the als amplifier if necessary to avoid excessive power consumption. note: the serial control interface must remain operational even when some of the connected devices are without power supply. some devices have clamping diodes at their inputs and might block the bus. v ref axi mip2 min2 hop hon axo 200 w ahs axc mic1 mic2 prefi 1 prefi 2 vref 10 k w
psb 4851 data sheet 17 09.99 2.3 attenuation plan figure 2-5 shows the attenuation plan for 3.3v and 5v operation. at the digital side the reference signal level is 3.14dbmo (maximum digital signal value). the stated gain settings at the amplifiers are the maximum gains for the guaranteed transmission characteristics. values above the signal lines refer to 3.3v operation, values below the signal lines refer to 5v operation. figure 2-5 attenuation plan 3.14 dbmo a/d 1/2 mic 1/2 36db 2.33db 0.81dbm (0.85 v rms = 1.2 v p ) 6.81dbm (1.70 v rms = 2.4 v p ) -35.2dbm (13.5 mv rms ) -29.2dbm (26.9 mv rms ) als ahs axc 3.14 dbmo d/a 1/2 -2.33db -3.67db 3.67db 0.81dbm (0.85 v rms = 1.2 v p ) 6.81dbm (1.70 v rms = 2.4 v p ) 2.5db 2.5db -6db 3.31dbm (1.13 v rms ) 3.31dbm (1.13 v rms ) 9.31dbm (2.26 v rms ) 9.31dbm (2.26 v rms ) -5.19dbm (0.42 v rms ) 0.81dbm (0.85 v rms )
psb 4851 data sheet 18 09.99 2.4 analog front end interface the psb 4851 uses a four wire interface similar to the iom ? -2 interface to exchange information in the digital domain. the main difference is that all timeslots and the channel assignments are fixed as shown in figure 2-6. . figure 2-6 afe interface - frame structure channel c 1 channel c 3 channel c 2 afefs afedd 125 m s als afedu unused 000ov 16 bit 16 bit 8 bit
psb 4851 data sheet 19 09.99 voice data is transferred in 16 bit linear coding in two bidirectional channels c 1 and c 2 . for controlled loudhearing an auxiliary channel c 3 is used to transfer the current setting of the loudspeaker amplifier als to the psb 4860. the remaining bits are fixed to zero. in the other direction c 3 transfers an override value for als from the psb 4860 to the psb 4851. an additional override bit ov determines if the currently transmitted value should override the aoar:lsc setting. the aoar:lsc setting is not affected by c 3 :als override. table 2-2 shows the source control of the gain for the als amplifier. therefore the psb 4860 can control the gain of the loudspeaker amplifier (als) independently from the gain of the handset amplifier (ahs) as shown in figure 2-7. figure 2-7 afe interface - signal routing table 2-2 source control of the gain for the als amplifier aopr:ovre c 3 :ov gain of als amplifier 0 - aoar:lsc 1 0 aoar:lsc 11c 3 :als axi mip1/min1 mip2/min2 hop/hon lsp/lsn axo als ahs axc mic1 mic2 d/a a/d a/d 10k w d/a channel 1 (afedd) channel 2 (afedu) channel 1 (afedu) channel 2 (afedd) channel 3 (afedd/afedu)
psb 4851 data sheet 20 09.99 figure 2-8 shows the synchronization of a frame by afefs. the first clock of a new frame (t 1 ) is indicated by afefs switching from low to high before the falling edge of t 1 . afefs may remain high during subsequent cycles up to t 32 . figure 2-8 afe interface - frame start the data is shifted out with the rising edge of afeclk and sampled at the fa lling edge of afeclk (figure 2-9). figure 2-9 afe interface - data transfer if aopr:ovre is not set, the channel c 3 is not used by the psb 4851. all values (c 1 , c 2 , c 3 :als) are transferred msb first. the data clock (afeclk) rate is fixed at 6.912 mhz. table 2-3 shows the clock cycles used for the three channels. table 2-3 clock cycles clock cycles afedd (driven by psb 4860) afedu (driven by psb 4851) t 1 -t 16 c 1 data c 1 data t 17 -t 32 c 2 data c 2 data t 33 -t 40 c 3 data c 3 data t 41 -t 864 0tristate afeclk afefs t 1 t 2 afeclk t 1 t 2 afedd afedu bit 7 bit 6 bit 5 bit 7 bit 6 bit 5
psb 4851 data sheet 21 09.99 2.5 serial control interface the serial control interface (sci) uses four lines. data is transferred by the lines sdr and sdx at the rate given by sclk. the falling edge of cs indicates the beginning of an access. data is sampled by the psb 4851 at the rising edge of sclk and shifted out at the falling edge of sclk. each access must be terminated by a rising edge of cs . data is transferred in bytes (8 bits). data from the controller is latched into a register at the rising edge of cs . figure 2-10 shows a write access to the psb 4851 and figure 2- 11 shows a read access to the psb 4851. figure 2-10 sci interface - write access figure 2-11 sci interface - read access cs sclk sdr 00000r 2 r 1 r 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r2,r1,r0: psb 4851 register cs sclk sdr 00010r 2 r 1 r 0 sdx d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r2,r1,r0: psb 4851 register
psb 4851 data sheet 22 09.99 2.6 test loops the psb 4851 supports several internal loops for performance testing. there are two kinds of loops: analog loops and digital loops. 2.6.1 analog loops analog loops connect the analog inputs to the analog outputs within the psb 4851. emergency mode is the most basic loop involving a minimal amount of components within the chip. these loops can be programmed by the bit field altf of register tfcr. the next figures show the programmable loops besides emergency mode. figure 2-12 analog loop via converter v ref axi mip1 mip2 min1 min2 hop lsp lsn hon axo als 50 w 200 w ahs axc mic1 mic2 pofi 2 pofi 1 prefi 1 prefi 2 d/a d/a a/d 1 a/d 2 vref 10k w
psb 4851 data sheet 23 09.99 figure 2-13 analog loop via 64 khz the loop via 64 khz incorporates only a part of the interpolation and decimation filters. figure 2-14 analog loop via interface v ref axi mip1 mip2 min1 min2 hop lsp lsn hon axo als 50 w 200 w ahs axc mic1 mic2 pofi 2 pofi 1 prefi 1 prefi 2 d/a d/a a/d 1 a/d 2 int 2 int 1 vref 10k w dec 1 dec 2 v ref axi mip1 mip2 min1 min2 hop lsp lsn hon axo als 50 w 200 w ahs axc mic1 mic2 pofi 2 pofi 1 prefi 1 prefi 2 d/a d/a a/d 1 a/d 2 int 2 int 1 vref 10k w dec 1 dec 2 hp hp hp hp
psb 4851 data sheet 24 09.99 2.6.2 digital loops the digital loops can be programmed by bit field dltf of register tfcr. these loops feed the input from the analog front end interface directly back to the analog front end interface. as no analog parts of the psb 4851 are involved these loops are only useful for functional tests. the loops are as follows: ? digital loop via pcm register received data is fed back without modification. ? digital loop via 64 khz received data is passed through the interpolation filters (int 1 , int 2 ), fed back into the decimation filters (dec 1 , dec 2 ) and then sent back.
psb 4851 data sheet 25 09.99 3 register description a summary of the registers of the psb 4851 is presented in table 3-1. all registers except tmr are set to 0 after reset. table 3-1 summary of the registers name reg 7 0 aiar 1 mic2 mic1 aipr 2 0 adc2 adc1 evref 0 0 iss aoar 3 hoc lsc aocr 4 sem axc dhop dhon dlsp dlsn aopr 5 oss dac2 dac1 pss 0 ovre tfcr 6 dhpr dhpx altf dltf 0 tmr 7 -- 1) 1) undefined 000000
psb 4851 data sheet 26 09.99 reg 1: aiar - afe input amplification register mic1 mic1 amplifier control mic2 mic2 amplifier control 7 0 mic2 mic1 3210description 0 0 0 0 mic1and prefi1 are in power down mode 0 0 0 1 0 db amplification 0 0 1 0 6 db amplification 0 0 1 1 12 db amplification 0 1 0 0 18 db amplification 0 1 0 1 24 db amplification 0 1 1 0 30 db amplification 0 1 1 1 36 db amplification 1 0 0 0 42 db amplification 1 1 1 1 mic1 is in bypass mode, prefi1 is powered up 7654description 0 0 0 0 mic2 and prefi2 are in power-down mode 0 0 0 1 0 db amplification 0 0 1 0 6 db amplification 0 0 1 1 12 db amplification 0 1 0 0 18 db amplification 0 1 0 1 24 db amplification 0 1 1 0 30 db amplification 0 1 1 1 36 db amplification 1 0 0 0 42 db amplification 1 1 1 1 mic2 is in bypass mode, prefi2 is powered up
psb 4851 data sheet 27 09.99 reg 2: aipr - afe input path register iss input source selection evref enable vref 0: vref module is enabled when any other module needs the reference voltage 1: vref module always enabled adc1 a/d control 1 0: a/d 1 is in power down mode 1: a/d 1 active adc2 a/d control 2 0: a/d 2 is in power down mode 1: a/d 2 active note: if adc1 and adc2 are set to 0 then dec 1 , dec 2 , int 1 , int 2 and the timing generation are also forced into power down mode. 7 0 0 adc2 adc1 evref 0 0 iss 1 0 description 0 0 reserved 0 1 axi connected to a/d1, mip1/min1 connected to a/d2 1 0 mip1/min1 connected to a/d1, mip2/min2 connected to a/d2 1 1 axi connected to a/d1, mip2/min2 connected to a/d2
psb 4851 data sheet 28 09.99 reg 3: aoar - afe output amplification register lsc loudspeaker amplifier control hoc handset amplifier control 7 0 hoc lsc 3 210description 0 0 0 0 als is in power-down mode 0 0 0 1 11.5 db amplification 0 0 1 0 8.5 db amplification 0 0 1 1 5.5 db amplification 0 1 0 0 2.5 db amplification 0 1 0 1 -0.5 db amplification 0 1 1 0 -3.5 db amplification 0 1 1 1 -6.5 db amplification 1 0 0 0 -9.5 db amplification 1 0 0 1 -12.5 db amplification 1 0 1 0 -15.5 db amplification 1 0 1 1 -18.5 db amplification 1 1 0 0 -21.5 db amplification 1 1 1 1 reserved 7654description 0 0 0 0 ahs is in power-down mode 0 0 0 1 2.5 db amplification 0 0 1 0 -0.5 db amplification 0 0 1 1 -3.5 db amplification 0 1 0 0 -6.5 db amplification 0 1 0 1 -9.5 db amplification 0 1 1 0 -12.5 db amplification 0 1 1 1 -15.5 db amplification
psb 4851 data sheet 29 09.99 1 0 0 0 -18.5 db amplification 1 0 0 1 -21.5 db amplification 1111reserved 7654description
psb 4851 data sheet 30 09.99 reg 4: aocr - afe output configuration register dlsn disable loudspeaker amplifier output n 0: lsn output of als amplifier controlled by lsc setting 1: lsn controlled by sem setting dlsp disable loudspeaker amplifier output p 0: lsp output of als amplifier controlled by lsc setting 1: lsp controlled by sem setting dhon disable handset amplifier output n 0: hon output of ahs amplifier controlled by hoc setting 1: hon output of ahs amplifier disabled (power down) dhop disable handset amplifier output p 0: hop output of ahs amplifier controlled by hoc setting 1: hop output of ahs amplifier disabled (power down) axc auxiliary output control sem single ended mode 0: lsn (lsp) fixed to gnd 1: lsn (lsp) tristated 7 0 sem axc dhop dhon dlsp dlsn 6 5 4 description 0 0 0 axo is in power-down mode 0 0 1 -6 db amplification 0 1 0 -9 db amplification 0 1 1 -12 db amplification 1 0 0 -15 db amplification 1 0 1 -18 db amplification 1 1 0 -21 db amplification 1 1 1 -24 db amplification
psb 4851 data sheet 31 09.99 reg 5: aopr - afe output path register ovre override enable 0: gain for als is always defined by lsc 1: gain for als can be overridden by interchip communication dac1 d/a control 1 0: pofi 1 and d/a 1 are in power down mode 1: pofi 1 and d/a 1 are active pss power supply selection 0: 3.3v power supply 1: 5v power supply dac2 d/a control 2 0: pofi 2 and d/a 2 are in power down mode 1: pofi 2 and d/a 2 are active oss output source selection 7 0 oss dac2 dac1 pss 0 ovre 7 6 5 description 0 0 0 als and ahs are connected to prefi 1, axc is connected to prefi 2 , pofi 1 and pofi 2 must be set to power down 0 0 1 als is connected to prefi 1 , ahs and axc are connected to prefi 2 , pofi 1 and pofi 2 must be set to power down 01 -reserved 10 -reserved 1 1 0 als and ahs are connected to pofi 2 , axc is connected to pofi 1 1 1 1 als is connected to pofi 2 , ahs and axc are connected to pofi 1
psb 4851 data sheet 32 09.99 reg 6: tfcr - test function configuration register dhpr disable high-pass (receive direction) 0: high pass activated (receive) 1: high pass disabled (receive) dhpx disable high-pass (transmit direction) 0: high pass activated (transmit) 1: high pass disabled (transmit) altf analog loop test function dltf digital loop test function 7 0 dhpr dhpx altf dltf 0 5 4 3 description 0 0 0 normal mode 0 0 1 analog loop via front end 0 1 0 analog loop via converter 0 1 1 analog loop via 64khz 1 0 0 analog loop via interface 2 1 description 00normal mode 0 1 digital loop via pcm register 1 0 digital loop via 64khz 1 1 reserved
psb 4851 data sheet 33 09.99 reg 7: tmr - test mode register this register is reserved for factory tests. do not write this register. 7 0 - 1) 1) undefined - 000000
psb 4851 data sheet 34 09.99 4 electrical characteristics 4.1 absolute maximum ratings esd-integrity (according mil-std 883d, method 3015.7): 1000 v exception: the pins #16, #18, #19 and #20 are not protected against voltage stress >630v note: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum ratings conditions for extended periods may affect device reliability. parameter symbol limit values unit ambient temperature under bias t a 1) 1) reduced performance e.g. noise and gain tracking C 40 to 85 c storage temperature t stg C 65 to125 c voltage on any pin with respect to ground v s C 0.3 to v dd + 0.3 v maximum voltage on any pin v max 7 v
psb 4851 data sheet 35 09.99 4.2 dc characteristics the performance is guaranteed for 3.0v-3.6v or 4.75v-5.25v only. in emergency mode the supply voltage range is 3.0v-5.25v for v ddd /v dda /v ddp . v ddd / v dda /v ddp = 3.0v-3.6v or 4.75v-5.25v; v ssd / v ssa / v ssp = 0 v; t a = 0 to 70 c parameter symbol limit values unit test condition min. typ. max. input leakage current i il C 1.0 1.0 m a0v v in v dd h-input level v ih 2.0 v dd + 0.3 v l-input level v il C 0.3 0.8 v h-output level v oh v dd C 0.45 v i o = 2 ma l-output level v ol 0.45 v i o = C 2 ma input capacitance c i 10 pf output capacitance c o 15 pf v dd standby supply current i dds1 i dds2 200 50 1.8 m a m a ma v dd =5 v, power down (after reset), no clock on afeclk, v dd =3.3 v, power down (after reset), no clock on afeclk, v vref = on v dd supply current operating 1) 1) operating power dissipation is measured with all analog outputs open. all analog inputs are set to v ref . i ddo1 i ddo2 i ddo3 3.8 5.1 20.0 ma ma ma emergency ringing via als (single ended mode) emergency speech mode (ahs in differential mode) full operation (loudhearing)
psb 4851 data sheet 36 09.99 4.3 ac characteristics digital inputs are driven to 2.4 v for a logical 1 and to 0.45 v for a logical 0. timing reference points are 2v and 0.8 v. the ac-testing waveforms are shown below. figure 38 input/output waveforms for ac-tests the performance is guaranteed for 3.0v-3.6v aor 4.75v-5.25v only. in emergency mode the supply voltage range is 3.0v-5.25v for v ddd /v dda /v ddp . analog front end input characteristics 1) parameter symbol limit values unit test condition min. typ. max. axi-input impedance z axi 12.5 20.5 k w 300 C 3400 hz axi-input voltage swing v axi 19 mvpk 42 db, v dd =5 v axi-input voltage swing v axi 1.67 vpk 0 db, v dd =5 v axi-input voltage swing v axi 9.53 mvpk 42 db, v dd =3.3 v axi-input voltage swing v axi 0.75 vpk 0 db, v dd =3.3 v axi-gain g axi 42 db 9.55 mv @ 1 khz axi-input impedance in bypass-mode z axi 160 270 k w 300 C 3400 hz axi-gain in bypass-mode g axi 0db1v @ 1 khz mip/min1,2-input voltage swing v mip/min 19 mvpk 42 db, v dd =5 v mip/min1,2-input voltage swing v mip/min 9.53 mvpk 42 db, v dd =3.3 v mip/min1,2-gain g mip/min 42 db 9.55 mv @ 1 khz 1) the maximum voltage swing at the internal paths corresponds to the maximum pcm-code ( 127).
psb 4851 data sheet 37 09.99 rst input t rstl 1 m s analog front end output characteristics aho-output impedance z aho 2 w 300 C 3400 hz aho-output voltage swing 1) v aho 3.2 vpk v dd = 5v, load measured from hop to hon aho-output voltage swing 1) v aho 1.6 vpk v dd = 3.3v, load measured from hop to hon als-output impedance z als 2 w 300 C 3400 hz als-output voltage swing 1) v als 3.2 vpk v dd = 5v, load measured from lsp to lsn als-output voltage swing 1) v als 1.6 vpk v dd = 3.3v, load measured from lsp to lsn axo-output impedance z axo 15 21 w 300 C 3400 hz axo-output voltage swing 1) v axo 1.2 vpk v dd = 5v, load measured from axo to gnd axo-output high voltage 1) v axoh 3.6 vpk v dd = 5v, input load C 0.12 ma reference: gnd axo-output low voltage 1) v axol 1.2 vpk v dd = 5v, input load + 0.12 ma reference: gnd axo-output voltage swing 1) v axo 0.7 vpk v dd = 3.3v, load measured from axo to gnd parameter symbol limit values unit test condition min. typ. max.
psb 4851 data sheet 38 09.99 v ref output impedance z vref 35 w load measured from v ref to v ssa v ref output voltage v vref 2.3 2.4 2.5 v input load C 2 ma v refbg output voltage v vrefbg 1.2 v with ext. capacitor parameter symbol limit values unit test condition min. typ. max.
psb 4851 data sheet 39 09.99 transmission characteristics v ddd / v dda /v ddp = 3.0v-3.6v or 4.75v-5.25v; v ssd / v ssa / v ssp = 0 v; t a = 0 to 70 c parameter limit values unit test condition min. max. attenuation distortion @ 0 dbmo 0 C 0.25 C 0.25 C 0.25 C 0.25 0 0.25 0.45 0.9 db db db db db db < 200 hz 200 C 300 hz 300 C 2400 hz 2400 C 3000 hz 3000 C 3400 hz > 3400 hz out-of-band signals C 35 C 45 C 35 C 40 db db db db receive signal filtering: 4.6 khz >8.0 khz transmit: 4.6 khz >8.0 khz group delay distortion @ 0 dbmo 750 380 130 750 m s m s m s m s 500 C 600 hz 600 C 1000 hz 1000 C 2600 hz 2600 C 2800 hz signal-to-total distortion (sine signal) 50 39 29 24 db db db 0 to C 20dbm0 1) C 30 dbm0 C 40 dbm0 C 45 dbm0 1) for single ended inputs only within gain settings 0 db to 24 db at v dd = 5v and within gain settings 0 db to 18 db at v dd = 3.3v. for differential inputs 0 db to 36 db. gain tracking (sine signal) @ C 10 dbmo C 0.3 C 0.6 C 1.6 0.3 0.6 1.6 db db db 3 to C 40 db C 40 to C 50 db C 50 to C 55 db idle-channel noise (psophometric) C 75 C 66 dbmo dbmo receive transmit channel crosstalk C 75 db reference: 0 dbmo programmable gain C 0.5 C 1.0 0.5 1.0 db db step accuracy overall accuracy
psb 4851 data sheet 40 09.99 figure 4-1 sci interface parameter sci interface symbol limit values unit min max sclk cycle time t 1 500 ns sclk high time t 2 100 ns sclk low time t 3 100 ns cs setup time t 4 0ns cs hold time t 5 10 ns sdr setup time t 6 40 ns sdr hold time t 7 40 ns sdx data out delay t 8 80 ns cs high to sdx tristate t 9 40 ns sclk to sdx active t 10 80 ns cs sclk sdr sdx t 4 t 2 t 3 t 1 t 10 t 9 t 5 t 6 t 7 t 8
psb 4851 data sheet 41 09.99 figure 4-2 afe interface - bit synchronization timing figure 4-3 afe interface - frame synchronization timing afedd afeclk afedu afedu first bit last bit bit n bit n+1 t 4 t 6 t 7 t 8 t 5 t 2 t 1 t 3 afefsc afefs afeclk t 9 t 10 t 9 t 10 t 11
psb 4851 data sheet 42 09.99 parameter afe interface symbol limit values unit min max afeclk period t 1 125 165 ns afeclk high t 2 50 ns afeclk low t 3 50 ns afedd setup t 4 20 ns afedd hold t 5 20 ns afedu high impedance to active t 6 20 ns afedu from active to high impedance t 7 20 ns afedu output delay t 8 20 ns afefs setup t 9 20 ns afefs hold t 10 20 ns afefs high t 11 1 t 1
psb 4851 data sheet 43 09.99 figure 4-4 power and reset timing parameter power and reset timing symbol limit values unit min max v ddd / v dda rise time 5%-95% t 1 20 ms supply voltages stable to rst high t 2 100 ns rst high t 3 100 ns rst t 3 v ddd / v dda t 1 t 2
psb 4851 data sheet 44 09.99 5 package outlines p plastic package, p-dso-28-1 (smd) (dual small outline) sorts of packing package outlines for tubes, trays etc. are contained in our dimensions in mm smd = surface mounted device

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