View LXT901LC_1112938.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

lxt901/907 universal 10base-t and aui transceivers datasheet the lxt901 and lxt907 universal 10base-t and aui transceivers are designed for ieee 802.3 physical layer applications. they provide all the active circuitry to interface most standard 802.3 controllers to either the 10base-t media or attachment unit interface (aui). in addition to standard 10 mbps ethernet, they also support full-duplex operation at 20 mbps. the lxt901 and lxt907 are identical except for the function of one pin. the lxt901 offers selectable termination impedance to allow the use of either shielded or unshielded twisted-pair cable. the lxt907 offers a signal quality error (sqe) disable function. common lxt901 and lxt907 functions include manchester encoding/decoding, receiver squelch and transmit pulse shaping, jabber, link testing and reversed polarity detection/ correction. integrated filters simplify the design work required for fcc-compliant emi performance. applications product features 10base-t hub and switching products computer/workstation 10base-t lan adapters functional features integrated manchester encoder/decoder 10base-t transceiver aui transceiver full-duplex capable (20 mbps) diagnostic features four led drivers aui/rj45 loopback remote signaling of link down and jabber conditions convenience features automatic/manual aui/rj45 selection automatic polarity correction sqe disable function ( lxt907 only ) programmable impedance driver ( lxt901 only ) power down mode and four loopback modes lxt901 available in 64-pin lqfp and 44- pin plcc lxt907 available in 44-pin plcc as of january 15, 2001, this document replaces the level one document order number: 249097-001 lxt901/907 ? universal 10base-t and aui transceivers . january 2001
datasheet information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel?s terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the lxt901/907 may contain design defects or errors known as errata which may cause the product to deviate from published speci fications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800- 548-4725 or by visiting intel?s website at http://www.intel.com. copyright ? intel corporation, 2001 *third-party brands and names are the property of their respective owners.
datasheet 3 universal 10base-t and aui transceivers ? lxt901/907 contents 1.0 pin assignments and signal descriptions ...................................................... 8 2.0 functional description ...........................................................................................12 2.1 controller compatibility modes ...........................................................................13 2.2 transmit function................................................................................................13 2.2.1 jabber control function .........................................................................14 2.2.2 sqe function .........................................................................................14 2.2.2.1 sqe disable function (lxt907 only) ......................................15 2.3 receive function.................................................................................................15 2.3.1 polarity reverse function ......................................................................16 2.3.2 collision detection function...................................................................16 2.4 loopback functions ............................................................................................17 2.4.1 standard tp loopback...........................................................................17 2.4.2 external loopback..................................................................................17 2.4.3 forced tp loopback ..............................................................................17 2.4.4 aui loopback.........................................................................................17 2.5 link integrity test function .................................................................................17 2.5.1 remote signaling ...................................................................................19 3.0 application information .........................................................................................20 3.1 twisted-pair impedance matching ......................................................................20 3.2 crystal information ..............................................................................................20 3.3 magnetics information .........................................................................................21 3.4 typical applications.............................................................................................21 3.4.1 auto port select with external loopback control...................................21 3.4.2 full duplex support................................................................................24 3.4.3 dual network support - 10base-t and token ring ...............................25 3.4.4 manual port select with link test function ...........................................26 3.4.5 three media application.........................................................................28 3.4.6 aui encoder/decoder only..................................................................29 3.4.7 150 ? shielded twisted-pair only (lxt901 only)..................................30 4.0 test specifications ..................................................................................................31 4.1 timing diagrams for mode 1 (md1 = low, md0 = low) figure 17 through figure 22 ................................................................................35 4.2 timing diagrams for mode 2 (md1=low, md0=high) figure 23 through figure 28 ................................................................................37 4.3 timing diagrams for mode 3 (md1 = high, md0 = low) figure 29 through figure 36 ................................................................................39 4.4 timing diagrams for mode 4 (md1 = high, md0 = high) figure 37 through figure 42 ................................................................................42 5.0 mechanical specifications ....................................................................................44
lxt901/907 ? universal 10base-t and aui transceivers 4 datasheet figures 1 lxt901/907 block diagram .................................................................................. 7 2 lxt901/907 pin assignments............................................................................... 8 3 lxt901/907 tpo output waveform .................................................................. 13 4 jabber control function ..................................................................................... 14 5 sqe function ..................................................................................................... 15 6 collision detection function ............................................................................... 16 7 link integrity test function ................................................................................ 18 8 remote signaling link integrity pulse timing .................................................... 19 9 lan adapter board - auto port select with external lpbk control .................. 23 10 full-duplex operation ........................................................................................ 24 11 380c26 interface for dual network support of 10base-t and token ring ...... 25 12 lan adapter board - manual port select with link test function ..................... 26 13 manual port select with seeq 8005 controller .................................................. 27 14 three media application .................................................................................... 28 15 aui encoder/decoder only application ............................................................. 29 16 150 ? shielded twisted-pair only application (lxt901) ................................... 30 17 mode 1 rclk/start-of-frame timing ................................................................ 35 18 mode 1 rclk/end-of-frame timing .................................................................. 35 19 mode 1 transmit timing .................................................................................... 36 20 mode 1 collision detect timing ......................................................................... 36 21 mode 1 col/ci output timing ........................................................................... 36 22 mode 1 loopback timing ................................................................................... 36 23 mode 2 rclk/start-of-frame timing ................................................................ 37 24 mode 2 rclk/end-of-frame timing .................................................................. 37 25 mode 2 transmit timing .................................................................................... 38 26 mode 2 collision detect timing ......................................................................... 38 27 mode 2 col/ci output timing ........................................................................... 38 28 mode 2 loopback timing ................................................................................... 38 29 mode 3 rclk/start-of-frame timing (lxt901 only) ....................................... 39 30 mode 3 rclk/end-of-frame timing (lxt901 only) .......................................... 39 31 mode 3 rclk/start-of-frame timing (lxt907 only) ....................................... 40 32 mode 3 rclk/end-of-frame timing (lxt907 only) .......................................... 40 33 mode 3 transmit timing .................................................................................... 41 34 mode 3 collision detect timing ......................................................................... 41 35 mode 3 col/ci output timing ........................................................................... 41 36 mode 3 loopback timing ................................................................................... 41 37 mode 4 rclk/start-of-frame timing ................................................................ 42 38 mode 4 rclk/end-of-frame timing .................................................................. 42 39 mode 4 transmit timing .................................................................................... 43 40 mode 4 collision detect timing ......................................................................... 43 41 mode 4 col/ci output timing ........................................................................... 43 42 mode 4 loopback timing ................................................................................... 43 43 lxt901/907 package specifications .................................................................. 44
datasheet 5 universal 10base-t and aui transceivers ? lxt901/907 tables 1 lxt901/907 signal descriptions ........................................................................... 9 2 controller compatibility modes ...........................................................................13 3 crystal specifications ..........................................................................................20 4 suitable crystals .................................................................................................20 5 suitable magnetics ..............................................................................................21 6 absolute maximum ratings.................................................................................31 7 recommended operating conditions .................................................................31 8 i/o electrical characteristics ...............................................................................31 9 aui electrical characteristics ..............................................................................32 10 tp electrical characteristics ...............................................................................32 11 switching characteristics ....................................................................................33 12 rclk/start-of-frame timing...............................................................................33 13 rclk/end-of-frame timing................................................................................33 14 transmit timing...................................................................................................34 15 collision, col/ci output and loopback timing..................................................34
lxt901/907 ? universal 10base-t and aui transceivers 6 datasheet revision history revision date description
universal 10base-t and aui transceivers ? lxt901/907 datasheet 7 figure 1. lxt901/907 block diagram mode select logic controller compatibility port select loopback link test squelch / link detect manchester decoder collision logic watchdog timer xtal osc manchester encoder select: pls only or pls / mau do md0 tpopa tpona tponb tpip tpin pulse shaper and filter twisted pair interface collision/ polarity detect correct rc rc di lpbk collision receiver ci md1 tpopb dop don dip din cip cin ledr ledt/pdn ledc/fde nth jab plr + - drop cable interface ecl tx amp rx slicer cmos tx amp *dsqe *(lxt907 only) *stp remote signaling *(lxt901 only) autosel paui lbk li tclk clko clki ten txd cd ledl rxd rclk col rld rjab rcmpt rx slicer
lxt901/907 ? universal 10base-t and aui transceivers 8 datasheet 1.0 pin assignments and signal descriptions figure 2. lxt901/907 pin assignments 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 n/c n/c paui dip din n/c dop don vcca vcc1 cip cin nth md0 md1 n/c n/c n/c tpin tpip n/c dsqe (907) or stp (901) tponb tpona vcc2 gnd2 tpopa tpopb plr rjab n/c n/c 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 n/c rld li n/c jab test tclk txd ten clko clki col autosel n/c n/c n/c n/c rclk cd rxd rcmpt n/c rbias n/c gnda gnd1 lbk ledc/fde ledl ledt/pdn ledr n/c 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 7 8 9 10 11 12 13 14 15 16 17 rld li jab test tclk txd ten clko clki col autosel tpin tpip dsqe (907) or stp (901) tponb tpona vcc2 gnd2 tpopa tpopb plr rjab 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 ledr ledt/pdn ledl ledc/fde lbk gnd1 rbias rcmpt rxd cd rclk md1 md0 nth cin cip vcc1 don dop din dip paui 6 5 4 3 2 1 44 43 42 41 40 lxt901/907pc xx xxxxxx xxxxxxxx part # lot # fpo # rev # LXT901LC xx xxxxxx xxxxxxxx part # lot # fpo # rev #
universal 10base-t and aui transceivers ? lxt901/907 datasheet 9 table 1. lxt901/907 signal descriptions plcc lqfp symbol i/o description 1 34 - 10 56 9 vcc1 vcc2 vcca i i i power inputs. power supply inputs of +5 volts. (lqfp only) 2 3 11 12 cip cin i i aui collision pair. differential input to the aui transceiver ci circuit. the input is collision signaling or sqe. 413nthi normal threshold. selects normal or reduced threshold. when nth is high, the normal tp squelch threshold is in effect. when nth is low, the normal tp squelch threshold is reduced by 4.5 db. 5 6 14 15 md0 md1 i i mode select 0 (md0), mode select 1 (md1). mode select pins determine the controller compatibility mode in accordance with table 2 . 718rldo remote link down. output goes high to signal to the controller that the remote port is in link down condition. 819 li 1 link test enable. controls link integrity test; enabled when li = high, disabled when li = low 921 jabo jabber indicator. output goes high to indicate jabber state. 10 22 test i test. for intel internal use only. it is recommended to tie this pin high externally. 11 23 tclk o transmit clock. a 10 mhz clock output. this clock signal should be directly connected to the transmit clock input of the controller. 12 24 txd i transmit data. input signal containing nrz data to be transmitted on the network. connect txd directly to the transmit data output of the controller. 13 25 ten i transmit enable. enables data transmission and starts the watchdog timer. synchronous to tclk (see test specifications for details). 14 15 26 27 clko clki o i crystal oscillator. a 20 mhz crystal must be connected across these pins, or a 20 mhz clock applied at clki with clko left open. 16 28 col o collision detect. output which drives the collision detect input of the controller. 17 29 autosel i automatic port select. when high, automatic port selection is enabled (the 901/907 defaults to the aui port only if tp link integrity = fail). when low, manual port selection is enabled (the paui pin determines the active port). 18 34 ledr od receive led. open drain driver for the receive indicator led. output is pulled low during receive. 19 35 ledt/ pdn od i transmit led (ledt)/power down (pdn ). open drain driver for the transmit indicator. output is pulled low during transmit. do not allow this pin to float. if unused, tie high. if externally pulled low, the lxt901/907 goes to power down state. 20 36 ledl od i link led. open drain driver for link integrity indicator. output is pulled low during link test pass. if externally tied low, internal circuitry is forced to ? link pass ? state and the 901/ 907 will transmit link test pulses continuously. 1. i/o column coding: i = input, o = output, od = open drain
lxt901/907 ? universal 10base-t and aui transceivers 10 datasheet 21 37 ledc/ fde od i collision led (ledc)/full duplex enable (fde ). open drain driver for the collision indicator pulls low during collision. led ? on ? (i.e., low output) time is extended by approximately 100 ms. if externally tied low, the lxt901/907 enables full duplex operation by disabling the internal tp loopback and collision detection circuits in anticipation of external tp loopback or full duplex operation. if this pin is not used, tie high or directly to v cc . 22 38 lbk i loopback. enables internal loopback mode. refer to functional descriptions for details. 23 33 ? 39 55 40 gnd1 gnd2 gnda ? ? ? ground returns. grounds (lqfp only) 24 42 rbias i bias control. a 12.4 k ? 1% resistor to ground at this pin controls operating circuit bias. 25 44 rcmpt o remote compatibility. output goes high to signal the controller that the remote port is compatible with the lxt901/lxt907 remote signaling features. 26 45 rxd o receive data. connect rxd directly to the receive data input of the controller. 27 46 cd o carrier detect. an output to notify the controller of activity on the network. 28 47 rclk o receive clock. a recovered 10 mhz clock which is synchronous to the received data. connect to the controller receive clock input. 29 51 rjab o remote jabber. output goes high to indicate the remote port is in jabber condition. 30 52 plr o polarity reverse. output goes high to indicate reversed polarity at the tp input. 31 36 32 35 53 58 54 57 tpopb tponb tpopa tpona o o o o twisted-pair transmit pairs a & b. two differential driver pair outputs (a and b) to the twisted-pair cable. the outputs are pre-equalized. each pair must be shorted together and tied to the transformer with a 24.9 ? 1% series resistor to match impedance of 100 ? . refer to figure 16 in the applications section for information on 150 ? configurations. 37 59 stp (lxt901) i stp select (lxt901 only). when stp is low, 150 ? termination for shielded tp is selected. when stp is high, 100 ? termination for unshielded tp is selected. lxt907 is designed for 100 ? utp termination (not selectable). dsqe (lxt907) i disable sqe (lxt907 only). when dsqe is high, the sqe function is disabled. when dsqe is low, the sqe function is enabled. sqe must be disabled for normal operation in hub/switch applications. lxt901operates with sqe enabled (not selectable). 38 39 61 62 tpip tpin i i twisted-pair receive pair. a differential input pair from the tp cable. receive filter is integrated on-chip. no external filters are required. 40 3 paui i port/aui select. in manual port select mode (autosel low), paui selects the active port. when paui is high, the aui port is selected. when paui is low, the tp port is selected. in auto port select mode, paui must be tied to ground. table 1. lxt901/907 signal descriptions (continued) plcc lqfp symbol i/o description 1. i/o column coding: i = input, o = output, od = open drain
universal 10base-t and aui transceivers ? lxt901/907 datasheet 11 41 42 4 5 dip din i i aui receive pair. differential input pair from the aui transceiver di circuit. the input is manchester encoded. 43 44 7 8 dop don o o aui transmit pair. a differential output driver pair for the aui transceiver cable. the output is manchester encoded. ? 1, 2, 6, 16, 17, 20, 30, 31, 32, 33, 41, 43, 48, 49, 50, 60, 63, 64 n/c ? no connect (internally tied to ground). table 1. lxt901/907 signal descriptions (continued) plcc lqfp symbol i/o description 1. i/o column coding: i = input, o = output, od = open drain
lxt901/907 ? universal 10base-t and aui transceivers 12 datasheet 2.0 functional description the lxt901/907 universal 10base-t and aui transceivers perform the physical layer signaling (pls) and media attachment unit (mau) functions as defined by the ieee 802.3 specification. they function as pls-only devices (for use with 10base-2 or 10base-5 coaxial cable networks) or as integrated pls/mau devices (for use with 10base-t twisted-pair networks). in addition to standard 10 mbps operation, they also support full-duplex 20 mbps operation. unless otherwise noted, all the information in this data sheet applies to both the lxt901 and lxt907. the lxt901/907 interfaces a back end controller to either an aui drop cable or a twisted-pair (tp) cable. the controller interface includes transmit and receive clock and nrz data channels, as well as mode control logic and signaling. the aui interface comprises three circuits: data output (do), data input (di) and collision (ci). the twisted-pair interface comprises two circuits: twisted-pair input (tpi) and twisted-pair output (tpo). in addition to the three basic interfaces, the lxt901/907 contains an internal crystal oscillator and four led drivers for visual status reporting. functions are defined from the back end controller side of the interface. the transmit function refers to data transmitted by the back end to the aui cable (pls-only mode) or to the twisted-pair network (integrated pls/mau mode). the receive function refers to data received by the back end from the aui cable (pls-only) or from the twisted-pair network (integrated pls/mau mode). in the integrated pls/mau mode, the lxt901/907 performs all required mau functions defined by the ieee 802.3 10base?t specification such as collision detection, link integrity testing, signal quality error messaging, jabber control and loopback. in the pls-only mode, the lxt901/907 receives incoming signals from the aui di circuit with 18 ns of jitter and drives the aui do circuit.
universal 10base-t and aui transceivers ? lxt901/907 datasheet 13 2.1 controller compatibility modes the lxt901/907 are compatible with most industry standard controllers including devices produced by motorola, amd, intel, fujitsu, national semiconductor, seeq and texas instruments. four different control signal timing and polarity schemes (modes 1 through 4) are required to achieve this compatibility. mode select pins (md0 and md1) determine controller compatibility modes as listed in table 2 . refer to test specifications for a complete set of timing diagrams for each mode. 2.2 transmit function the lxt901/907 receives nrz data from the controller at the txd input as shown in the block diagram on the first page of this data sheet, and passes it through a manchester encoder. the encoded data is then transferred to either the aui cable (the do circuit) or the twisted-pair network (the tpo circuit). the advanced integrated pulse shaping and filtering network produces the output signal on tpon and tpop, shown in figure 3 . the tpo output is pre-distorted and prefiltered to meet the 10base-t jitter template. an internal continuous resistor-capacitor filter is used to remove any high-frequency clocking noise from the pulse shaping circuitry. integrated filters simplify the design work required for fcc compliant emi performance. during idle periods, the lxt901/907 transmits link integrity test pulses on the tpo circuit (if li is enabled and integrated pls/ mau mode is selected). external resistors control the termination impedance for lxt907. external resistors and the stp pin control termination impedance on the lxt901. table 2. controller compatibility modes controller mode setting md1 md0 mode 1 for motorola 68en360, mpc860, advanced micro devices am7990, or compatible controllers l o w l o w mode 2 for intel 82596 or compatible controllers 1 l o w h i g h mode 3 for fujitsu mb86950, mb86960 or compatible controllers (seeq 8005) 2 high low mode 4 for national semiconductor 8390 or compatible controllers (ti tms380c26) high high 1. refer to intel application note 51 when designing with intel controllers. 2. seeq controllers require inverters on clki, lbk, rclk and col. figure 3. lxt901/907 tpo output waveform
lxt901/907 ? universal 10base-t and aui transceivers 14 datasheet 2.2.1 jabber control function figure 4 is a state diagram of the lxt901/907 jabber control function. the on-chip watchdog timer prevents the dte from locking into a continuous transmit mode. when a transmission exceeds the time limit, the watchdog timer disables the transmit and loopback functions, and activates the jab pin. once the lxt901/907 is in the jabber state, the txd circuit must remain idle for a period of 250 to 750ms before it will exit the jabber state. 2.2.2 sqe function in the integrated pls/mau mode, the lxt901/907 supports the signal quality error (sqe) function as shown in figure 5 . after every successful transmission on the 10base-t network when sqe is enabled, the lxt901/907 transmits the sqe signal for 10bt 5bt over the internal ci circuit which is indicated on the col pin of the device. when using the 10base-2 port of the lxt901/907, the sqe function is determined by the external mau attached. figure 4. jabber control function no output nonjabber output start_xmit_max_timer power on do=active jab xmit=disable lpbk=disable ci=sqe unjab wait start_unjab_timer xmit=disable lpbk=disable ci=sqe do=active* xmit_max_timer_done do=idle do=idle unjab_ timer_done do=active* unjab_timer_not_done
universal 10base-t and aui transceivers ? lxt901/907 datasheet 15 2.2.2.1 sqe disable function (lxt907 only) sqe must be disabled for normal operation in hub and switch applications. the lxt907 offers an sqe disable function. the sqe function is disabled when dsqe is set high, and enabled when dsqe is low. 2.3 receive function the lxt901/907 receive function acquires timing and data from the twisted-pair network (the tpi circuit) or from the aui (the di circuit). valid received signals are passed through the on-chip filters and manchester decoder then output as decoded nrz data and receive timing on the rxd and rclk pins, respectively. an internal rc filter and an intelligent squelch function discriminate noise from link test pulses and valid data streams. the receive function is activated only by valid data streams above the squelch level and with proper timing. if the differential signal at the tpi or the di circuit inputs falls below 75% of the threshold level (unsquelched) for 8 bit times (typical), the lxt901/907 receive function enters the idle state. if the polarity of the tpi circuit is reversed, lxt901/907 detects the polarity reverse and reports it via the plr output. the lxt901/907 automatically corrects reversed polarity. figure 5. sqe function output idle output detected power on do=active sqe wait test start_sqe_test__wait_timer sqe test start_sqe_test_timer ci=sqe sqe_test__wait_timer_done ? xmit=enable do=idle sqe_test_timer_done xmit=disable
lxt901/907 ? universal 10base-t and aui transceivers 16 datasheet 2.3.1 polarity reverse function the lxt901/907 polarity reverse function uses both link pulses and end-of-frame data to determine the polarity of the received signal. if link integrity testing is disabled, polarity detection is based only on received data. a reversed polarity condition is detected when eight opposite receive link pulses are detected without receipt of a link pulse of the expected polarity. reversed polarity is also detected if four frames are received with a reversed start-of-idle. whenever a correct polarity frame or a correct link pulse is received, these two counters are reset to zero. if the lxt901/907 enters the link fail state and no valid data or link pulses are received within 96 to 128 ms, the polarity is reset to the default non-flipped condition. polarity correction is always enabled. 2.3.2 collision detection function the collision detection function operates on the twisted pair side of the interface. for standard (half-duplex) 10base-t operation, a collision is defined as the simultaneous presence of valid signals on both the tpi circuit and the tpo circuit. the lxt901/907 reports collisions to the back-end via the col pin. if the tpi circuit becomes active while there is activity on the tpo circuit, the tpi data is passed to the back-end over the rxd circuit, disabling normal loopback. figure 6 is a state diagram of the lxt901/907 collision detection function. refer to test specifications for collision detection and col/ci output timing. (note: for full-duplex operation on tp and aui ports, the collision detection circuitry must be disabled.) figure 6. collision detection function idle power on a collision tpo=do di=tpi ci=sqe output tpo=do di=do input di=tpi do=active ? tpi=idle ? xmit=enable do=active ? tpi=active ? xmit=enable a a do=active ? tpi=active ? xmit=enable do=active ? tpi=idle do=idle+ xmit=disable do=idle tpi=idle tpi=active
universal 10base-t and aui transceivers ? lxt901/907 datasheet 17 2.4 loopback functions 2.4.1 standard tp loopback the lxt901/907 provides the standard loopback function defined by the 10base-t specification for the twisted-pair port. the loopback function operates in conjunction with the transmit function. data transmitted by the back-end is internally looped back within the lxt901/907 from the txd pin through the manchester encoder/decoder to the rxd pin and returned to the back-end. this standard loopback function is disabled when a data collision occurs, clearing the rxd circuit for the tpi data. standard loopback is also disabled during link fail and jabber states. the lxt901/ 907 also provides three additional loopback functions. 2.4.2 external loopback an external loopback mode, useful for system-level testing, is controlled by the ledc pin. when ledc is tied low, the lxt901/907 disables the collision detection and internal loopback circuits, to allow external loopback. external loopback mode can be set on either tp or aui ports. 2.4.3 forced tp loopback ? forced ? tp loopback is controlled by the lbk pin. when the tp port is selected and lbk is high, tp loopback is ? forced ? , overriding collisions on the tp circuit. when lbk is low, normal loopback is in effect. 2.4.4 aui loopback aui loopback is also controlled by the lbk pin. when the aui port is selected and lbk is high, data transmitted by the back-end is internally looped back from the txd pin through the manchester encoder/decoder to the rxd pin. when lbk is low, no aui loopback occurs. 2.5 link integrity test function figure 7 is a state diagram of the lxt901/907 link integrity test function. the link integrity test is used to determine the status of the receive side twisted-pair cable. link integrity testing is enabled when the li pin is tied high. when enabled, the receiver recognizes link integrity pulses which are transmitted in the absence of receive traffic. if no serial data stream or link integrity pulses are detected within 50 - 150 ms, the chip enters a link fail state and disables the transmit and normal loopback functions. the lxt901/907 ignores any link integrity pulse with interval less than 2 - 7 ms. the lxt901/907 will remain in the link fail state until it detects either a serial data packet or two or more link integrity pulses.
lxt901/907 ? universal 10base-t and aui transceivers 18 datasheet figure 7. link integrity test function idle test start_link_loss_timer start_link_test_min_timer power on link test fail reset link_count=0 xmit=disable rcvr=disable lpbk=disable link_loss_timer_done ? tpi=idle ? link_test_rcvd=false tpi=active+ (link_test_rcvd=true ? link_test_min_timer_done) link test fail wait xmit=disable rcvr=disable lpbk=disable link_count=link_count + 1 link test fail start_link_test_min_timer start_link_test_max_timer xmit=disable rcvr=disable lpbk=disable link_test_rcvd=false ? tpi=idle tpi=active tpi=active link_test_rcvd=idle ? tpi=idle link test fail extended xmit=disable rcvr=disable lpbk=disable tpi=active + link_count=lc_max link_test_min_timer_done ? link_test_rcvd=true (tpi=idle ? link_test_max_timer_done) + (link_test_min_timer_not_done ? link_test_rcvd=true) tpi=idle ? do=idle
universal 10base-t and aui transceivers ? lxt901/907 datasheet 19 2.5.1 remote signaling the lxt901/907 transmits standard link pulses which meet the 10base-t specification. however, the lxt901/907 encodes additional status information into the link pulse by varying the link pulse timing. this is referred to as remote signaling. using alternate pulse intervals, the lxt901/907 can signal three local conditions: link down, jabber and remote signaling compatibility. figure 8 shows the interval variations used to signal local status to the other end of the line. the lxt901/907 also recognizes these alternate pulse intervals when received from a remote unit. remote status conditions are reported to the controller over the rld, rjab and rcmpt output pins. figure 8. remote signaling link integrity pulse timing 10 ms 20 ms 10 ms 20 ms 10 ms 10 ms 20 ms 20 ms 10 ms 10 ms 15 ms 20 ms 10 ms 20 ms 10 ms 15 ms 15 ms 20 ms 20 ms 10 ms 15 ms 20 ms 10 ms 15 ms 20 ms 15 ms 10 ms li-rld (note 1) (note 2) (note 3) li-rjab li-rcmpt 907f07.vsd notes: 1. for remote link down (rld) signaling, the interval between li pulses increments from 10ms to 15ms, and then the cycle starts over. 2. for remote jabber (rjab) signaling, the interval between li pulses decrements from 20ms to 15ms to 10ms, and then the cycle starts over. 3. for remote compatibility (rcmpt) signaling, the interval between li pulses continually switches between 10ms and 20ms.
lxt901/907 ? universal 10base-t and aui transceivers 20 datasheet 3.0 application information 3.1 twisted-pair impedance matching resistors must be installed on each input and output pair to match impedance of the network media being used. lxt907 is configured with 100 ? termination for unshielded twisted-pair (utp). in this case, the positive and negative sides of both output pairs are shorted together (tpopa/tpopb and tpona/tponb) and tied to the transformer through a 24.9 ? 1% series resistor. the lxt901 is designed with an stp select pin that allows the device to match both 100 ? and 150 ? media. a dual resistor combination can be configured to accommodate either line termination as shown in figure 16 . when 100 ? termination is selected, both a and b pairs are driven in parallel. when 150 ? termination is selected, the b pair is tri-stated and only the a pair is driven. 3.2 crystal information designers should test and validate crystals to system requirements before committing to a specific component. crystal specifications for lxt901/907 are shown in table 3 . based on limited evaluation, table 4 lists some suitable crystals. table 3. crystal specifications parameter min nom max units frequency ? 25.0 ? mhz frequency 1 stability ?? +/-80 ppm 1. test condition = -40 - 85 o c table 4. suitable crystals manufacturer part number mtron mp-1 mp-2
universal 10base-t and aui transceivers ? lxt901/907 datasheet 21 3.3 magnetics information the lxt901 and lxt907 require a 1:1 ratio for the receive transformer and a 1: 2 ratio for the transmit transformer on the twisted-pair interface. the aui interface requires a 1:1 ratio for both the transmit and receive transformers. designers should test and validate magnetics for system requirements before committing to a specific component. table 5 lists some suitable magnetics. 3.4 typical applications figure 9 through figure 16 show typical lxt901/907 applications. 3.4.1 auto port select with external loopback control figure 9 is a typical lxt901/907 application. the diagram is arranged to group similar pins together; it does not represent the actual lxt901/907 pinout. the controller interface pins (transmit data, clock and enable; receive data and clock; and the collision detect, carrier detect and loopback control pins) are shown at the top left. table 5. suitable magnetics manufacturer part number twisted-pair fil-mag 23z128 23z128sm valor pt4069 st7011 belfuse a553-0716 s553-0716 halo td42-2006q tg42-1406n1 aui fil-mag 23z90 23z90sm valor lt6032 st7032 halo td01-0756k tg01-0756n
lxt901/907 ? universal 10base-t and aui transceivers 22 datasheet programmable option pins are grouped center left. the paui pin is tied low and all other option pins are tied high. this set-up selects the following options: automatic port selection (paui low and autosel high) normal receive threshold (nth high) mode 4, compatible with national ns8390 controllers (md0 high, md1 high) sqe disabled (dsqe high on lxt907 only) 100 ? termination utp cable (stp high on lxt901 only) link testing enabled (li high) status outputs are grouped at lower left. local status outputs drive led indicators and remote status indicators are available as required. power and ground pins are shown at the bottom of the diagram. a single power supply is used for both vcc1 and vcc2 with a decoupling capacitor installed between the power and ground busses. the tp and aui interfaces are shown at upper and lower right, respectively. impedance matching resistors for 100 ? utp are installed in each i/o pair but no external filters are required.
universal 10base-t and aui transceivers ? lxt901/907 datasheet 23 figure 9. lan adapter board - auto port select with external lpbk control lxt901/907 20 mhz 20 pf 20 pf clki txd tpin 50 ? 50 ? tpip 1 : 1 116 14 6 5 4 3 2 1 11 0.1 f 9 rj45 3 6 8 to 10 base-t twisted- pair network 1 2 4 5 7 89 10 12 13 15 16 1 2 3 4 5 6 7 8 15 14 13 12 9 10 11 + 12 v cin cip don dop din dip rbias gnd2 gnd1 ten d - connector to aui drop cable chassis gnd fuse 78 ? 78 ? 78 ? 12.4 k ? 1% tclk rclk rxd cd col lbk paui autosel nth md0 md1 dsqe (907) stp (901) li jab plr txd txe txc rxc rxd crs col lbk green red red red ns8390 back-end controller interface loopback enable programming options line status +5 v ledc/fde ledr ledt/pdn ledl vcc1 vcc2 2 clko 330 330 330 330 test tpona tponb tpopa tpopb 24.9 ? 1% 24.9 ? 1% bias resistor rbias should be located close to the pin and isolated from other signals. optional: centertap capacitor may improve emc depending on board layout and system design. 2 1 1 1 : 2 1 : 1 rjab rld rcmpt remote status 1 : 1
lxt901/907 ? universal 10base-t and aui transceivers 24 datasheet 3.4.2 full duplex support figure 10 shows the lxt907 with a texas instruments 380c24 commprocessor. the 380c24 is compatible with mode 4 (md0 and md1 both high). when used with the 380c24 or other full duplex-capable controller, the lxt907 supports full-duplex ethernet, effectively doubling the available bandwidth of the network. in this application the sqe function is enabled (dsqe tied low), and the aui port is not used. figure 10. full-duplex operation lxt907 clki txd tpin 50 ? 50 ? tpip 1 : 1 116 14 6 5 4 3 2 1 11 0.1 f 9 rj45 3 6 8 cin cip don dop din dip rbias gnd2 gnd1 ten 2 12.4 k ? tclk rclk rxd cd col lbk ledc/fde txd txen txc rxc rxd csn coll lpbk 1 % +5 v vcc1 vcc2 clko tms380c24 1 : 2 to 10 base-t twisted- pair network 20 mhz 20 pf 20 pf *test0 1n914 10 k ? 4 bias resistor rbias should be located close to the pin and isolated from other signals. 1 2 3 4 half/full duplex selection controlled by tms380c24 pin s test0 and outsel0. autosel nth md0 md1 li jab plr green red red programming options line status ledr ledt/pdn ledl 330 330 outsel0 paui 330 1 4.7 k ? test dsqe (907) *open collector driver tpona tponb tpopa tpopb 24.9 ? 1% 24.9 ? 1% the tms380c26 may be substituted for dual network support of 10base-t and token ring. optional: centertap capacitor may improve emc depending on board layout and system design. 3 rjab rld rcmpt remote status
universal 10base-t and aui transceivers ? lxt901/907 datasheet 25 3.4.3 dual network support - 10base-t and token ring figure 11 shows the lxt901/907 with a texas instruments 380c26 commprocessor. the 380c26 is compatible with mode 4 (md0 and md1 both high). when used with the 380c26, both the lxt901/907 and a tms38054 token ring transceiver can be tied to a single rj45 allowing dual network support from a single connector. the lxt901/907 aui port is not used. the lxt901 stp is high and the lxt907 dsqe is low. figure 11. 380c26 interface for dual network support of 10base-t and token ring lxt901/907 20 mhz 20 pf 20 pf clki txd tpin 50 ? 50 ? tpip 1 : 1 116 14 6 5 4 3 2 1 11 0.1 f 9 2 tpona tponb tpopb tpopa rj45 3 6 8 from ti tms38054 token ring transceiver cin cip don dop din dip rbias gnd2 gnd1 ten 1 12.4 k ? 1% tclk rclk rxd cd col lbk paui autosel nth md0 md1 li jab plr txd txe txc rxc rxd crs col lbk green red red red programming options line status +5 v ledc/fde ledr ledt/pdn ledl vcc1 vcc2 3 clko 330 330 330 330 380c26 to ti tms38054 token ring transceiver 1 : 2 to 10 base-t twisted- pair network bias resistor rbias should be located close to the p and isolated from other signals. 1 2 3 additional magnetics and switching logic (not shown ) are required to implement the dual network solution. 24.9 ? 1% 24.9 ? 1% test optional: centertap capacitor may improve emc depending on board layout and system design. dsqe (lxt907) stp (lxt901) rjab rld rcmpt remote status
lxt901/907 ? universal 10base-t and aui transceivers 26 datasheet 3.4.4 manual port select with link test function with md0 low and md1 tied high, the lxt901/907 logic and framing are set to mode 3 (compatible with fujitsu mb86950 and mb86960, and seeq 8005 controllers). figure 12 shows the setup for fujitsu controllers. figure 12 on page 26 shows the four inverters required to interface with the seeq 8005 controller. as in figure 9 on page 23 , both these mode 3 applications show the li pin tied high, enabling link testing; and the stp (lxt901 only) and nth pins are both tied high, selecting the standard receiver threshold and 100 ? termination for unshielded tp cable. however, in these applications autosel is tied low, allowing external port selection through the paui pin. the remote status outputs are inverted to drive led indicators. figure 12. lan adapter board - manual port select with link test function lxt901/907 20 mhz 20 pf 20 pf clki txd tpin 50 ? 50 ? tpip 1 : 1 116 14 6 5 4 3 2 1 11 0.1 f 9 2 tpona tponb tpopb tpopa rj45 3 6 8 to 10 base-t twisted- pair network 1 2 4 5 7 89 10 12 13 15 16 1 2 3 4 5 6 7 8 15 14 13 12 9 10 11 + 12 v cin cip don dop din dip rbias gnd2 gnd1 ten d - connector to aui drop cable chassis gnd fuse 1 78 ? 78 ? 78 ? 12.4 k ? tclk rclk rxd cd col lbk autosel nth md0 md1 dsqe (907) stp (901) li jab plr txd ten tckn rckn rxd xcd lbc red red red mb86950 or mb86960 back-end/ controller interface remote & line status 1 % +5 v ledc/fde ledr ledt/pdn ledl vcc1 vcc2 clko 330 330 330 green 330 bias resistor rbias should be located close to the pin and isolated from other signals. 2 1 test 24.9 ? 1% 24.9 ? 1% xcol optional: centertap capacitor may improve emc depending on board layout and system design. 1 : 1 1 : 2 rjab rld rcmpt paui port selection programming options 330 330 amber 330 amber amber 1 : 1
universal 10base-t and aui transceivers ? lxt901/907 datasheet 27 figure 13. manual port select with seeq 8005 controller lxt901/907 clki lbk tpin 50 ? 50 ? tpip 1 : 1 116 14 6 5 4 3 2 1 11 0.1 f 9 1 tpona tponb tpopb tpopa rj45 3 6 8 to 10 base-t twisted- pair network 1 2 4 5 7 89 10 12 13 15 16 1 2 3 4 5 6 7 8 15 14 13 12 9 10 11 + 12 v cin cip don dop din dip rbias gnd2 gnd1 cd d - connector to aui drop cable chassis gnd fuse 78 ? 78 ? 78 w 12.4 k ? rxd rclk col ten tclk txd paui autosel nth md0 md1 dsqe (907) stp (901) jab plr red red red remote & line status 1 % +5 v ledc/fde ledr ledt/pdn ledl vcc1 vcc2 330 330 330 1 : 2 green 330 port selection clko 8005 clki lpbk csn rxd rxc coll txen txc txd external 20 mhz source left open bias resistor rbias should be located close to the pin and isolated from other signals. test 24.9 ? 1% 24.9 ? 1% optional: centertap capacitor may improve emc depending on board layout and system design. 2 2 1 1 : 1 1 : 1 li rjab rld rcmpt 330 330 amber 330 amber amber
lxt901/907 ? universal 10base-t and aui transceivers 28 datasheet 3.4.5 three media application figure 14 shows the lxt907 in mode 2 (compatible with intel 82596 controllers) with additional media options for the aui port. two transformers are used to couple the aui port to either a d- connector or a bnc connector. (a dp8392 coax transceiver with pm6044 power supply are required to drive the thin coax network through the bnc.) figure 14. three media application clki txd tpin 50 ? tpip 1 : 1 116 14 6 5 4 3 2 1 11 9 tpona tponb tpopb tpopa rj45 3 6 8 to 10base-t twisted- pair network 1 2 3 4 5 6 7 8 15 14 13 12 9 10 11 + 12 v cin cip don dop dip rbias gnd2 gnd1 ten d - connector to aui drop cable (thick coax) chassis gnd fuse 1 78 ? 78 ? 12.4 ? tclk rclk rxd cd col lbk paui autosel nth li md1 md0 jab plr txd rts txc rxc rxd crs cdt lbk 82596 back-end/ controller interface programming options mode select line status 1 % +5 v ledc/fde ledr ledt/pdn ledl vcc1 vcc2 clko 1 : 2 20 mhz system clock clk linktest enable power down 1 2 4 5 7 89 10 12 13 15 16 78 ? 1 2 4 5 7 89 10 12 13 15 16 din cd- cd+ tx- vee tx+ rx- rx+ vee cds txd rxi vee rr- rr+ gnd hbe 1n916 0v bnc to thin coax network 1 k ? 1% -9v v+ n/c v- 5v 5v en gnd gnd 12 13 9 1 +5 v 2 3 23 1 m ? 1/2 w 24 test 1.5 k ? 0.01 f75 f / 1 kv 2 1 bias resistor rbias should be located close to the pin and isolated from other signals. pm6044 dp8392 10 k ? d s q e ( 9 0 7 ) 10 k ? lxt907 f 0.1 f 0.1 50 ? 2 optional: centertap capacitor may improve emc depending on board layout and system design. 2 4 . 9 ? 1 % 2 4 . 9 ? 1 % 1:1 1:1
universal 10base-t and aui transceivers ? lxt901/907 datasheet 29 3.4.6 aui encoder/decoder only in figure 15 , the dte is connected to a coaxial network through the aui. autosel is tied low and paui is tied high, manually selecting the aui port. the twisted-pair port is not used. with md1 and md0 both low, the logic and framing are set to mode 1 (compatible with amd am7990 controllers). the li pin is tied low, disabling the link test function. the dsqe pin is also low, enabling the sqe function on the lxt907. the lbk input controls loopback. a 20 mhz system clock is supplied at clk1 with clk0 left open. figure 15. aui encoder/decoder only application lxt907 txd rbias gnd2 gnd1 ten tclk rclk rxd cd col lbk autosel nth md0 md1 dsqe (907) li jab plr tx tena tclk rclk rx rena clsn lbk red red red am7990 back-end/ controller interface loopback control programming options line status green +5 v ledc/fde ledr ledt/pdn ledl vcc1 vcc2 clki 330 330 330 330 1 2 4 5 7 89 1 10 12 13 15 16 1 2 3 4 5 6 7 8 15 14 13 12 9 10 11 + 12 v cin cip don dop din dip d - connector to aui drop cable chassis gnd fuse 78 ? 78 ? 78 ? 12.4 ? 1% clko paui bias resistor rbias should be located close to the pin and isolated from the other signals. 20 mhz left open system clock test 1 rjab rld rcmpt remote status 1:1 1:1
lxt901/907 ? universal 10base-t and aui transceivers 30 datasheet 3.4.7 150 ? shielded twisted-pair only (lxt901 only) figure 16 shows the lxt901 in a typical twisted-pair only application. the dte is connected to a 10base-t network through the twisted-pair rj45 connector. (the aui port is not used). with md0 tied high and md1 low, the lxt901 logic and framing are set to mode 2 (compatible with intel 82596 controllers). a 20 mhz system clock input at clk1 is used in place of the crystal oscillator. (clk0 is left open). the l1 pin externally controls the link test function. the utp/stp and nth pins are both tied low, selecting the reduced receiver threshold and 150 ? termination for shielded tp cable. the switch at ledt/pdn manually controls the power down mode. figure 16. 150 ? shielded twisted-pair only application (lxt901) lxt901 tpin 75 ? 75 ? tpip 1 : 1 116 14 6 5 4 3 2 1 11 0.1 f 9 tpona tponb tpopb tpopa rj45 3 6 8 to 10 base-t twisted- pair network rbias gnd2 gnd1 paui autosel nth md0 md1 jab plr ledc/fde ledr ledt/pdn ledl vcc1 vcc2 1 : 2 test 75 ? 1% 37.5 ? 1% 12.4 k ? 1% 20 mhz system clock 82596 back-end/ controller interface clk0 rclk 75 ? 1% 37.5 ? 1% +5 v bias resistor rbias should be located close to the pin and isolated from other signals. 2 1 10k line status 10k programming options stp clk txd rts txc rxc rxd crs cdt lbk clk1 txd ten tclk rclk rxd cd col lbk left open 2 optional: centertap capacitor may improve emc depending on board layout and system design. 1 li link test enable rjab rld rcmpt remote status
universal 10base-t and aui transceivers ? lxt901/907 datasheet 31 4.0 test specifications note: table 6 through table 15 and figure 17 through figure 42 represent the performance specifications of the lxt901/907. these specifications are guaranteed by test except where noted ? by design. ? minimum and maximum values listed in table 8 through table 15 apply over the recommended operating conditions specified in table 7 . table 6. absolute maximum ratings parameter symbol min max units supply voltage v cc -0.3 6 v ambient operating temperature t a 070 o c storage temperature t stg -65 +150 o c caution: exceeding these values may cause permanent damage. functional operation under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 7. recommended operating conditions parameter symbol min typ max units recommended supply voltage 1 v cc 4.75 5.0 5.25 v recommended operating temperature t op 0 ? 70 o c 1. voltages with respect to ground unless otherwise specified. power supply should be filtered to suppress high frequency transients, consistent with good pcb design. table 8. i/o electrical characteristics parameter sym min typ 1 max units test conditions input low voltage 2 v il ?? 0.8 v input high voltage 2 v ih 2.0 ?? v output low voltage v ol ?? 0.4 v i ol = 1.6 ma v ol ?? 10 %v cc i ol < 10 a output low voltage (open drain led driver) v oll ?? 0.7 %v cc i oll = 10 ma output high voltage v oh 2.4 ?? vi oh = 40 a v oh 90 ?? %v cc i oh < 10 a output rise time tclk & rclk cmos ?? 312nsc load = 20 pf ttl ?? 28ns output fall time tclk & rclk cmos ?? 312nsc load = 20 pf ttl ?? 28ns clki rise time (externally driven) ??? 10 ns clki duty cycle (externally driven) ?? 50/50 40/60 % 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. limited functional tests are performed at these input levels. the majority of functional tests are performed at levels of 0v and 3v.
lxt901/907 ? universal 10base-t and aui transceivers 32 datasheet supply current normal mode i cc ? 65 85 ma idle mode i cc ? 90 110 ma transmitting on tp i cc ? 70 90 ma transmitting on aui power down mode i cc ? 0.75 2 ma table 9. aui electrical characteristics parameter symbol min typ 1 max units test conditions input low current i il ?? -700 a input high current i ih ?? 500 a differential output voltage v od 550 ? 1200 mv differential squelch threshold v ds 150 250 350 mv 5 mhz square wave input 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. table 10. tp electrical characteristics parameter symbol min typ 1 max units test conditions transmit output impedance z out ? 5 ? ? transmit timing jitter addition ?? 3.3 10 ns 0 line length for internal mau transmit timing jitter added by the mau and pls sections ?? 3.3 5.5 ns after line model specified by ieee 802.3 for 10base-t internal mau receive input impedance z in ? 20 ? k ? between tpip/tpin, cip/ cin & dip/din differential squelch threshold normal threshold; nth = high v ds 300 400 585 mv 5 mhz square wave input reduced threshold; nth = low v ds 180 250 345 mv 5 mhz square wave input 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. table 8. i/o electrical characteristics (continued) parameter sym min typ 1 max units test conditions 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. limited functional tests are performed at these input levels. the majority of functional tests are performed at levels of 0v and 3v.
universal 10base-t and aui transceivers ? lxt901/907 datasheet 33 table 11. switching characteristics parameter symbol minimum typical 1 maximum units jabber timing maximum transmit time ? 20 ? 150 ms unjab time ? 250 ? 750 ms link integrity timing time link loss receive ? 50 ? 150 ms link min receive ? 2 ? 7ms link max receive ? 50 ? 150 ms link transmit period ? 810 24ms 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. table 12. rclk/start-of-frame timing parameter symbol minimum typical 1 maximum units decoder acquisition time aui t data ? 900 1100 ns tp t data ? 1200 1500 ns cd turn-on delay aui t cd ? 25 200 ns tp t cd ? 425 550 ns receive data setup from rclk mode 1 t rds 60 70 ? ns modes 2, 3 and 4 t rds 30 45 ? ns receive data hold from rclk mode 1 t rdh 10 20 ? ns modes 2, 3 and 4 t rdh 30 45 ? ns rclk shut off delay from cd assert (lxt907 only; mode 3) tsws ? 90 ? ns 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. table 13. rclk/end-of-frame timing parameter type sym mode 1 mode 2 mode 3 mode 4 units rclk after cd off min t rc 51275bt rcv data throughput delay max t rd 400 375 375 375 ns cd turn off delay 2 max t cdoff 500 475 475 475 ns receive block out after ten off typ 1 t ifg 550 ?? bt rclk switching delay after cd off (lxt907 only; mode 3) typ 1 t swe ?? 120(80) ? ns 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. cd turn-off delay measured from middle of last bit: timing specification is unaffected by the value of the last bit.
lxt901/907 ? universal 10base-t and aui transceivers 34 datasheet table 14. transmit timing parameter symbol minimum typical 1 maximum units ten setup from tclk t ehch 22 ?? ns txd setup from tclk t dsch 22 ?? ns ten hold after tclk t chel 5 ?? ns txd hold after tclk t chdu 5 ?? ns transmit start-up delay - aui t stud ? 220 450 ns transmit start-up delay - tp t stud ? 430 450 ns transmit through-put delay - aui t tpd ?? 300 ns transmit through-put delay - tp t tpd ? 300 350 ns 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. table 15. collision, col/ci output and loopback timing parameter symbol minimum typical 1 maximum units col turn-on delay t cold ? 40 500 ns col turn-off delay t coloff ? 420 500 ns col (sqe) delay after ten off t sqed 0.65 1.2 1.6 s col (sqe) pulse duration t sqep 500 1000 1500 ns lbk setup from ten t kheh 10 25 ? ns lbk hold after ten t khel 10 0 ? ns 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing.
universal 10base-t and aui transceivers ? lxt901/907 datasheet 35 4.1 timing diagrams for mode 1 (md1 = low, md0 = low) figure 17 through figure 22 figure 17. mode 1 rclk/start-of-frame timing figure 18. mode 1 rclk/end-of-frame timing 1 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 1 1 0 1 0 1 t cd t data tpip/tpin or dip/din cd rclk rxd t rds t rdh 0 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 t rd t cdoff tpip/tpin or dip/din cd rclk rxd t rc
lxt901/907 ? universal 10base-t and aui transceivers 36 datasheet figure 19. mode 1 transmit timing figure 20. mode 1 collision detect timing figure 21. mode 1 col/ci output timing figure 22. mode 1 loopback timing t chel t ehch t chdu ten tclk txd tpo t tpd t dsch t stud t coloff t cold ci col t sqep t sqed ten col t khel t kheh lbk ten
universal 10base-t and aui transceivers ? lxt901/907 datasheet 37 4.2 timing diagrams for mode 2 (md1=low, md0=high) figure 23 through figure 28 figure 23. mode 2 rclk/start-of-frame timing figure 24. mode 2 rclk/end-of-frame timing 1 0 1 0 1 0 1 1 1 0 1 0 1 t cd t rds t rdh cd rclk rxd t data tpip/tpin or dip/din 1 1 0 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 0 note: 1. rxd changes at the rising edge of rclk. the controller is sampled at the falling edge. 1 0 1 0 1 0 1 0 0 t rd tpip/tpin or dip/din cd rclk rxd 1 0 1 0 1 0 1 0 0 t cdoff note: 1. rxd changes at the rising edge of rclk. the controller is sampled at the falling edge.
lxt901/907 ? universal 10base-t and aui transceivers 38 datasheet figure 25. mode 2 transmit timing figure 26. mode 2 collision detect timing figure 27. mode 2 col/ci output timing figure 28. mode 2 loopback timing t chel t ehch t chdu ten tclk txd tpo t dsch t tpd t stud t coloff t cold ci col t sqed ten col t ifg t sqep t khel t kheh lbk ten
universal 10base-t and aui transceivers ? lxt901/907 datasheet 39 4.3 timing diagrams for mode 3 (md1 = high, md0 = low) figure 29 through figure 36 figure 29. mode 3 rclk/start-of-frame timing (lxt901 only) figure 30. mode 3 rclk/end-of-frame timing (lxt901 only) 1 0 1 0 1 0 1 1 1 0 1 0 1 t rds t rdh t data cd rclk rxd tpip/tpin or dip/din 1 1 0 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 t cd note: 1. rxd changes at the rising edge of rclk. the controller is sampled at the falling edge. t rd t cdoff cd rclk rxd 1 0 1 0 1 0 1 0 0 tpip/tpin or dip/din 1 0 1 0 1 0 1 0 0 27 bits note: 1. rxd changes at the rising edge of rclk. the controller is sampled at the falling edge.
lxt901/907 ? universal 10base-t and aui transceivers 40 datasheet figure 31. mode 3 rclk/start-of-frame timing (lxt907 only) figure 32. mode 3 rclk/end-of-frame timing (lxt907 only) 1 0 1 0 1 0 1 1 1 0 1 0 1 t rds t rdh t data cd rclk rxd tpip/tpin or dip/din 1 1 0 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 t cd t sws recovered from input data stream generated from tclk note: 1. rxd changes at the rising edge of rclk. the controller is sampled at the falling edge. t rd t cdoff cd rclk rxd t swe recovered clock generated from tclk 1 0 1 0 1 0 1 0 0 tpip/tpin or dip/din 1 0 1 0 1 0 1 0 0 note: 1. rxd changes at the rising edge of rclk. the controller is sampled at the falling edge.
universal 10base-t and aui transceivers ? lxt901/907 datasheet 41 figure 33. mode 3 transmit timing figure 34. mode 3 collision detect timing figure 35. mode 3 col/ci output timing figure 36. mode 3 loopback timing t chel t ehch t chdu ten tclk txd tpo t stud t dsch t tpd t coloff t cold ci col t sqed ten col t sqep note: 1. rxd changes at the rising edge of rclk. the controller is sampled at the falling edge. t khel t kheh lbk ten
lxt901/907 ? universal 10base-t and aui transceivers 42 datasheet 4.4 timing diagrams for mode 4 (md1 = high, md0 = high) figure 37 through figure 42 figure 37. mode 4 rclk/start-of-frame timing figure 38. mode 4 rclk/end-of-frame timing 1 0 1 0 1 0 1 1 1 0 1 0 1 t cd t data cd rclk rxd tpip/tpin or dip/din t rds t rdh 1 1 0 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 note: 1. rxd changes at the rising edge of rclk. the controller is sampled at the falling edge. 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 t rd tpip/tpin or dip/din cd rclk rxd t cdoff note: 1. rxd changes at the rising edge of rclk. the controller is sampled at the falling edge.
universal 10base-t and aui transceivers ? lxt901/907 datasheet 43 figure 39. mode 4 transmit timing figure 40. mode 4 collision detect timing figure 41. mode 4 col/ci output timing figure 42. mode 4 loopback timing t chel t ehch t chdu ten tclk txd tpo t dsch t stud t tpd t coloff t cold ci col t sqep t sqed ten col t khel t kheh lbk ten
lxt901/907 ? universal 10base-t and aui transceivers 44 datasheet 5.0 mechanical specifications figure 43. lxt901/907 package specifications dim inches millimeters min max min max a 0.165 0.180 4.191 4.572 a 1 0.090 0.120 2.286 3.048 a 2 0.062 0.083 1.575 2.108 b 0.050 ? 1.270 ? c 0.026 0.032 0.660 0.813 d 0.685 0.695 17.399 17.653 d 1 0.650 0.656 16.510 16.662 f 0.013 0.021 0.330 0.533 44-pin plcc part number lxt901pc and lxt907pc commercial temp range (0 o c to 70 o c) 64-pin lqfp part number LXT901LC commercial temp range (0 o c to 70 o c) dim inches millimeters min max min max a ? 0.063 ? 1.60 a1 0.002 0.006 0.05 0.15 a2 0.053 0.057 1.35 1.45 b 0.007 .011 0.17 0.27 d 0.472 bsc 12.00 bsc d1 0.394 bsc 10.00 bsc e 0.472 bsc 12.00 bsc e1 0.394 bsc 10.00 bsc e 0.020 bsc 0.50 bsc l 0.018 0.030 0.45 0.75 l1 0.039 ref 1.00 ref 311 o 13 o 11 o 13 o 0 o 7 o 0 o 7 o a 2 a d f a 1 c b d 1 d c l d d 1 for sides with even number of pins e / 2 for sides with odd number of pins e a 1 a 2 l a b l 1 3 3 e e 1

▲Up To Search▲

Price & Availability of LXT901LC

	To Download LXT901LC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .