publication #: 19195 rev. c amendment/ 0 issue date: august 1995 this document contains information on a product under development at advanced micro devices. the information is intended to help you evaluate this product. amd reserves the right to change or discontinue work on this proposed product without notice. advanced micro devices clock gating recommendations application note microprocessor motherboard design requires that special attention be paid to the design of the clock control circuitry. a designer must provide for timing control of the clock at startup. keeping this requirement in mind, this application note provides three examples of clock delay circuits. amd recommends that the clk input to an am486 ? or am5 x 86? microprocessor be grounded until v cc has reached its normal operating level. once v cc reaches its normal operating level, the cpu is able to receive its specified clock frequency. methods of gating the cpu clock include: n using a chipset that does not clock the cpu until v cc has fully ramped. n using a clock driver with an output enable. n using a clock clamping circuit to gate the cpu clock. for proper operation of am486 and am5 x 86 devices, the system timing must be maintained as illustrated in figure 1. good design practice dictates gating or hold- ing off the cpu clock until the system v cc has reached its normal operating voltage. the timing diagram illus- trates that once v cc reaches its operating voltage point (either 3.3 v or 5 v), and the pwrgood signal is active, reset must be asserted for at least 1 ms to allow the cpus internal pll to lock prior to system operation. chipset with internal delay because many 486 core logic chipsets use pwrgood and clk as inputs to generate reset and cpuclk as outputs, they have the potential to incorporate an internal delay function, holding off the cpu until v cc has reached its normal operating voltage. figure 2 illustrates a chipset capable of providing inter- nal clock gating. figure 2. internal delay function of chipset note: check your chipsets data sheet for specifics on your chipsets internal delay function. figure 1. timing diagram of picopower redwood chipset delay function chipset clk cpuclk reset pwrgood
amd clock gating recommendations 2 clock driver with output enable a clock synthesizer (or other driver) with an output en- able pin for the cpu clock can be used to prevent the cpu from being clocked until v cc has reached its nor- mal operating voltage. the circuit in figure 3 consists of a frequency generator with a dedicated oe , which may be used to hold off or gate the clock until v cc has reached its normal operating level using pwrgood as the output enable. figure 3. clock synthesizer with oe clock clamping circuit a third method of gating the cpu clock is to use a clock clamping circuit to effectively ground the clock input for a predetermined period of time. in addition to delaying the cpu clock, the clock clamp- ing circuit, shown in figure 4, also prevents noise glitch- es on the clock signal from being sensed by the cpu during the power-on sequence when v cc of the micro- processor is making the transition from 0 v to v cc (e.g., 3.3 v or 5 v). microprocessor clock noise glitches usually are caused by one of the following conditions: n bad clock generator start-up circuit design n poor layout of the microprocessor printed circuit trace on the pc motherboard n power supply ringing during transition from 0 v to v cc n a very long voltage slew rate (e.g., 100 ms). in any case, the clock clamping circuit ensures that a clock signal glitch is not sensed by the microprocessor clock input circuit during startup. cpu clock signal integrity is best maintained by passing the clock directly from the core logic. figure 4. clock clamping circuit clock synthesizer oe crystal clk pwrgood to system 1 k w
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