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in 2 in 1 nc nc gnd v+ substrate nc nc s 2 d 1 d 2 s 1 v nc dual-in-line 1 2 3 4 5 6 7 14 13 12 11 10 9 8 top view metal can nc top view d 1 v s 1 in 1 v+ (substrate and case) in 2 gnd s 2 d 2 1 2 3 4 5 6 7 8 9 10 dg200a vishay siliconix document number: 70035 s-00399erev. d, 13-sep-99 www.siliconix.com faxback 408-970-5600 4-1 monolithic dual spst cmos analog switch

15 v input signal range 44-v maximum supply ranges on-resistance: 45 ttl and cmos compatibility wide dynamic range simple interfacing reduced external component count servo control switching programmable gain amplifiers audio switching programmable filters

the dg200a is a dual, single-pole, single-throw analog switch designed to provide general purpose switching of analog signals. this device is ideally suited for designs requiring a wide analog voltage range coupled with low on-resistance. the dg200a is designed on vishay siliconix' improved plus-40 cmos process. an epitaxial layer prevents latchup. each switch conducts equally well in both directions when on, and blocks up to 30 v peak-to-peak when off. in the on condition, this bi-directional switch introduces no offset voltage of its own.

logic switch 0 on 1 off logic a0o 0.8 v logic a1o 24v g logic a1o 2.4 v
dg200a vishay siliconix www.siliconix.com faxback 408-970-5600 4-2 document number: 70035 s-00399erev. d, 13-sep-99
temp range package part number 0 to 70 c 14-pin plastic dip dg200acj 25 to 85 c 14-pin cerdip dg200abk 25 to 85 c 10-pin metal can dg200aba 55 125 c 14 pi c dip dg200aak 55 to 125 c 14-pin cerdip dg200aak/883, jm38510/12301bca, 5962-9562901qca 55 to 125 c 10 - pin metal can dg200aaa 10 - pin metal can dg200aaa/883, jm38510/12301bic 14-pin sidebraze jm38510/12301bcc
v+ to v 44 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd to v 25 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . digital inputs a , v s , v d (v) 2 v to (v+) +2 v or . . . . . . . . . . . . . . . . . . . . . . . . 30 ma, whichever occurs first current (any terminal) continuous 30 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . current s or d (pulsed at 1 ms, 10% duty cycle max) 100 ma . . . . . . . . . . . . . . . . . . . . . . . . storage temperature (ax, bx suffix) 65 to 150 c . . . . . . . . . . . . . . (cj suffix) 65 to 125 c . . . . . . . . . . . . . . . . . . power dissipation (package) b 10-pin metal can c 450 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-pin cerdip d 825 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-pin plastic dip e 470 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . notes: a. signals on s x , d x , or in x exceeding v+ or v will be clamped by internal diodes. limit forward diode current to maximum current ratings. b. all leads welded or soldered to pc board. c. derate 6 mw/ c above 75 c d. derate 11 mw/ c above 75 c e. derate 6.5 mw/ c above 25 c
figure 1. v+ in x v gnd + s d v v+
dg200a vishay siliconix document number: 70035 s-00399erev. d, 13-sep-99 www.siliconix.com faxback 408-970-5600 4-3
test conditions unless otherwise specified a suffix 55 to 125 c b, c suffix parameter symbol v+ = 15 v, v = 15 v v in = 2.4 v, 0.8 v f temp b typ c min d max d min d max d unit analog switch analog signal range e v analog full 15 15 15 15 v drain-source on-resistance r ds(on) v d = 10 v, i s = 1 ma room full 45 70 100 80 100 source off leakage current i s(off) v s = 14 v, v d = 14 v room full 0.01 2 100 2 100 5 100 5 100 a drain off leakage current i d(off) v d = 14 v, v s = 14 v room full 0.01 2 100 2 100 5 100 5 100 na channel on leakage current f i d(on) v s = v d = 14 v room full 0.1 2 200 2 200 5 200 5 200 digital control input current with itvlt hih i inh v in = 2.4 v room full 0.0009 0.5 1 1 10 a p input voltage high i inh v in = 15 v room full 0.005 0.5 1 1 10 a input current with input voltage low i inl v in = 0 v room full 0.0015 0.5 1 1 10 dynamic characteristics turn-on time t on see switching time test circuit room 440 1000 1000 ns turn-off time t off see switching t ime t est circuit room 340 425 425 ns charge injection q c l = 1000 pf, v g = 0 v r g = 0 room 10 pc source-off capacitance c s(off) f = 140 khz v5v v s = 0 v room 9 f drain-off capacitance c d(off) v in = 5 v v d = 0 v room 9 pf channel-on capacitance c d(on) + c s(on) v d = v s = 0 v, v in = 0 v room 25 pf off isolation oirr v in = 5 v , r l = 75 room 75 db crosstalk (channel-to-channel) x talk v in = 5 v , r l = 75 v s = 2 v, f = 1 mhz room 90 db power supplies positive supply current i+ both channels on or off v0vd24v room 0.8 2 2 ma negative supply current i v in = 0 v and 2.4 v room 0.23 1 1 ma notes: a. refer to process option flowchart. b. room = 25 c, full = as determined by the operating temperature suffix. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. the algebraic convention whereby the most negative value is aminimum and the most positive a maximum, is used in this data sheet. e. guaranteed by design, not subject to production test. f. v in = input voltage to perform proper function.
dg200a vishay siliconix www.siliconix.com faxback 408-970-5600 4-4 document number: 70035 s-00399erev. d, 13-sep-99
leakage currents vs. analog voltage r ds(on) vs. v d and power supply voltage r ds(on) () (pa) i , i sd v d drain voltage (v) v analog analog voltage (v) 120 15 d c +6 15 e 015 100 80 60 40 20 015 0 6 12 18 24 i d(off) or i s(off) i d(on) t a = 25 c a: 5 v b: 10 v c: 12 v d: 15 v e: 20 v 12 6 6 12 9 3 3 9 12 9 6 3 3 6 9 12 b a supply currents vs. toggle frequency input switching threshold vs. v+ and v supply voltages v+, v positive and negative supplies (v) toggle frequency (hz) (v) t v i+, i (ma) 6 2.5 0 2.0 1.5 1.0 0.5 0 5 4 3 2 1 0 5 10 15 20 i+ i v+ = 15 v v = 15 v both logic inputs toggled simutaneously 1 k 10 k 100 k 1 m
dg200a vishay siliconix document number: 70035 s-00399erev. d, 13-sep-99 www.siliconix.com faxback 408-970-5600 4-5 figure 2. switching time figure 3. charge injection c l 1000 pf v g 3 v d v+ v r g 15 v gnd in s v o +15 v v o v o in x on on off v o = measured voltage error due to charge injection the charge injection in coulombs is q = c l x v o v o is the steady state output with switch on. feedthrough via gate capacitance may result in spikes at leading and trailing edge of output waveform. 50% 0 v 3 v t off t on v o v s t r <20 ns t f <20 ns logic input switch input switch output 90% c l 35 pf r l 1 k v o = v s r l + r ds(on) r l v s = +5 v v o v v+ in s d 3 v 15 v gnd +15 v figure 4. off isolation s in r l d r g = 50 v s v o 5 v off isolation = 20 log v s v o v+ 15 v gnd v c c +15 v in 1 0v v o +15 v 15 v gnd r l v+ v nc x talk = 20 log c v s c v o 0v 50 v s s 1 in 2 s 2 r g = 50 d 1 d 2 c = rf bypass figure 5. channel-to-channel crosstalk

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