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" for more information + ! " migration from am29lv640du to mirrorbit am29lv640mu application note publication number 25628 revision a amendment 0 issue date january 2, 2002
publication# 25628 rev: a amendment/ 0 issue date: january 2, 2002 migration from am29lv640du to mirrorbit tm am29lv640mu application note introduction note: this application note assumes that users are fa- miliar with flash technology and hw/sw system de- sign. amd?s mirrorbit tm technology offers customers a low- cost flash memory solution. mirrorbit technology en- ables a flash memory product to hold twice as much data as standard flash, without compromising device endurance, performance, or reliability. amd's mirrorbit am29lv640mu device is pin-compat- ible with amd?s am29lv640du product. the products are very similar, enabling easy migration. along with improvements added to the am29lv640mu, there are a few minor changes between the two products. this application note will focus on these changes and new performance-enhancing features. migrate to mirrorbit am29lv640mu products are offered in the same 0.8mm pitch fbga package and with the same pin out as amd?s am29lv640du product. as an extension to the previous product offering, the am29lv640du is also available in the 1.0 mm pitch fortified bga pack- age to support migration to the 64 mbit mirrorbit de- vice, the am29lv640mu. existing systems using am29lv640du can migrate to mirrorbit am29lv640mu without board redesign. for more in- formation on alternate mirrorbit packages, refer to the ?mirrorbit packages? application note, publication num- ber 25694. figure 1. fine-pitch bga package (63-ball) connection diagram c2 d2 e2 f2 g2 h2 j2 k2 c3 d3 e3 f3 g3 h3 j3 k3 c4 d4 e4 f4 g4 h4 j4 k4 c5 d5 e5 f5 g5 h5 j5 k5 c6 d6 e6 f6 g6 h6 j6 k6 c7 d7 a7 b7 a8 b8 a1 b1 a2 e7 f7 g7 h7 j7 k7 l7 l8 m7 m8 l1 l2 m1 m2 nc* nc* nc* nc* nc* nc* nc* nc* nc* nc* nc* nc nc nc nc dq15 v ss v io a16 a15 a14 a12 a13 dq13 dq6 dq14 dq7 a11 a10 a8 a9 v cc dq4 dq12 dq5 a19 a21 reset# we# dq11 dq3 dq10 dq2 a20 a18 acc ry/by# dq9 dq1 dq8 dq0 a5 a6 a17 a7 oe# v ss ce# a0 a1 a2 a4 a3 * balls are shorted together via the substrate but not connected to the die.
2 migration from am29lv640du to mirrorbit tm am29lv640mu figure 2. fortified bga (1.0 mm pitch) connection diagram device id change on amd mirrorbit devices device identification (id) in amd flash devices is available either via a software command sequence or through a high voltage hardware method. device id is a unique set of readable data values, which distinguishes between different vendors and device type. the main difference between am29lv640du and mirrorbit am29lv640mu is the am29lv640du uses a single-byte device code whereas am29lv640mu uses a three-byte device code. tables 1 and 2 show the difference between single- byte device code and three-byte device code using the high-voltage hardware method. table 1. device id for am29lv640du, high voltage method note: v id = 8.5 ? 12.5 v. b3 c3 d3 e3 f3 g3 h3 b4 c4 d4 e4 f4 g4 h4 b5 c5 d5 e5 f5 g5 h5 b6 c6 d6 e6 f6 g6 h6 b7 c7 d7 e7 f7 g7 h7 b8 c8 d8 e8 f8 g8 h8 rfu rfu rfu v ss v io rfu rfu v ss dq15 nc a16 a15 a14 a12 dq6 dq13 dq14 dq7 a11 a10 a8 dq4 v cc dq12 dq5 a19 a21 reset# dq3 dq11 dq10 dq2 a20 a18 acc dq1 dq9 dq8 dq0 a5 a6 a17 a3 a4 a5 a6 a7 a8 rfu a13 a9 we# ry/by# a7 b2 c2 d2 e2 f2 g2 h2 v ss oe# ce# a0 a1 a2 a4 a2 a3 b1 c1 d1 e1 f1 g1 h1 rfu rfu v io rfu rfu rfu rfu a1 rfu description ce# oe# we# a21? a15 a14? a10 a9 a8? a7 a6 a5?a2 a1 a0 dq15? dq0 manufacturer id: amd ll h x xv id x l x l l 0001h device id: am29lv640d ll h x xv id x l x l h 22d7h
migration from am29lv640du to mirrorbit tm am29lv640mu 3 table 2. device id for am29lv640mu, high voltage method note: v id = 8.5 ? 12.5 v. the device id read command sequence is extended from four to six cycles for mirrorbit devices. in the de- vice code only the lower byte of the data bus is mean- ingful. all three bytes of the device code must be read to determine the device type. the first byte of the code (7e) only indicates that there are two more device id bytes to be read. for more detailed information on three-byte device code refer to migration from single- byte to three-byte device ids? application note, publi- cation number 25538. tables 3 and 4 illustrate different bus cycles between am29lv640du and am29lv640mu. table 3. device id command sequence for am29lv640du table 4. device id command sequence for am29lv640mu difference in power consumption mirrorbit am29lv640mu devices have higher power consumption during active read. active read current is higher due to the new page mode access feature. erase/program current is higher because the device will program up to 8 bits at a time instead of the tradi- tional 4 bits. these new features mean that reading, programming, and erase occur in less time. the active power is higher but over a shorter period of time. table 5 compares power consumption between am29lv640du and am29lv640mu. description ce# oe# we# a21? a10 a9 a8 a7 a6 a5? a4 a3 a2 a1 a0 dq15? dq0 manufacturer id: amd llh x v id xxlxxxll0001h device id read 1 llh x v id x x l x l l l h 227eh device id read 2 llh x v id x l l l h h h l 2213h device id read 3 llh x v id x l l l h h h h 2201h command sequence bus cycles first second third fourth addr data addr data addr data addr data manufacturer id 555 aa 2aa 55 555 90 x00 0001 device id 555 aa 2aa 55 555 90 x01 22d7 command sequence bus cycles first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data manufacturer id 555 aa 2aa 55 555 90 x00 0001 device id 555 aa 2aa 55 555 90 x01 227e x0e 2213 x0f 2201
4 migration from am29lv640du to mirrorbit tm am29lv640mu table 5. power consumption new page read buffer and write buffer features page read buffer and page write buffer are two new performance-enhancing features in mirrorbit devices. the page read buffer feature increases read perfor- mance significantly. this mode provides faster read access speed for random locations within a page. the page size of the device is 4 words. pages are located on 4 word boundaries. the first access within a page requires the full random access time for the device, 90 to 120ns depending on the speed grade. subsequent accesses that remain within the same page address range, while chip select (ce#) remains asserted, have a reduced page access time of 25 to 40 ns. the page read buffer is automatically used by standard read ac- cesses. no special commands or signals are needed. the system only needs to keep ce# active throughout page mode accesses and be aware of the reduced ac- cess time for accesses remaining within a page. the system can reduce the number of wait states for within page accesses and take advantage of the increased read performance. the addition of a page write buffer doubles the pro- gramming throughput compared to current am29lv640du devices. the page write buffer is a set of registers used to hold several words that are to be programmed as a group. the page write buffer al- lows the system to write to a maximum of 16 words in one programming operation. the write buffer pro- gramming command sequence is initiated by first writ- ing two unlock cycles. below is the flowchart for write buffer programming. see ?mirrorbit tm flash memory write buffer programming and page mode read? ap- plication note, publication 25539 , for more detailed in- formation. specification lv640mu lv640du current consumption initial read 30 ma 9 ma intra-page read 10 ma n/a program 50 ma 26 ma erase 50 ma 26 ma standby 1 a 0.4 a accelerated program acc pin 10 ma 5 ma v cc pin 30 ma 15 ma power consumption random read 90 mw 27 mw intra-page read 30 mw n/a program 150 mw 78 mw erase 150 mw 78 mw 64 kbyte sector erase 3 w 1.2 w accelerated program (acc pin) 210 mw 87 mw energy consumption (based on operational timing below) 4-word read page 10.35 nj n/a random 32.4 nj 9.72 nj 16-word program buffer 14.16 j n/a random 307.2 j 13.73 j 64 kbyte sector erase 60 mj 124.8 mj 16-word accelerated program (acc pin) 23.52 j 9.744 j operation timing initial read 90 ns 90 ns intra-page read 25 ns n/a 1-word program 5.9 s 11 s sector erase 0.4 s 1.6 s 1-word accelerated program 7 s 7 s
migration from am29lv640du to mirrorbit tm am29lv640mu 5 figure 3. write buffer programming flowchart write ?write to buffer? command and sector address write number of locations to program minus 1(wc) and sector address write program buffer to flash confirm, sector address write first address/data write to a different sector address fail or abort pass read dq7 - dq0 with address = last loaded address read dq7 - dq0 with address = last loaded address write next address/data pair wc = wc - 1 wc = 0 ? part of ?write to buffer? command sequence ye s ye s ye s ye s ye s ye s no no no no no no abort write to buffer operation? dq7 = data? dq7 = data? dq5 = 1? dq1 = 1? write to buffer aborted. must write ?write-to-buffer abort reset? command sequence to return to read mode.
6 migration from am29lv640du to mirrorbit tm am29lv640mu conclusion mirrorbit technology is a major landmark in flash mem- ory. mirrorbit devices provide a flash memory solution at a lower cost, without compromising device perfor- mance, endurance, or reliability. am29lv640mu de- vices in 0.8 mm fbga are pin-compatible with amd?s current am29lv640du product family of devices in the same package ranging from 8 mb to 64 mb. therefore it is easy to migrate from am29lv640mu to am29lv640du. the addition of the page read buffer and page write buffer increases read performance and reduces the programming time bottleneck that is inher- ent to very high density flash memory devices. mirrorbit products are a superior and cost-competitive solution for designers requiring higher non-volatile memory densities. trademarks copyright ? 2002 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are registered trademarks of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies .

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