View GS8150F32_1171115.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev: 1.01 11/2000 1/23 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8150 f 18/ 32/ 36 t - 7/8/8.5/10/11 1m x 18, 512k x 32, 512k x 36 16mb sync burst srams 7 ns?11 ns 3.3 v v dd 2.5 v or 3.3 v i/o 100-pin tqfp commercial temp industrial temp features ? flow through mode operation; pin 14 = no connect ? 3.3 v +10%/?5% core power supply ? 2.5 v or 3.3 v i/o supply ? lbo pin for linear or interleaved burst mode ? internal input resistors on mode pins allow floating mode pins ? byte write ( bw ) and/or global write ( gw ) operation ? internal self-timed write cycle ? automatic power-down for portable applications ? jedec-standard 100-lead tqfp package functional description applications the gs 8150 f 18 /32 /36 t is a 18,874,368-bit (16,777,216-bit for x32 version) high performance synchronous sram with a 2-bit burst address counter. although of a type originally developed for level 2 cache applications supporting high performance cpus, the device now finds application in synchronous sram applications, ranging from dsp main store to networking chip set support. controls addresses, data i/os, chip enable s ( e1 , e2, e3 ), address burst control inputs ( adsp , adsc , adv ), and write control inputs ( bx , bw , gw ) are synchronous and are controlled by a positive-edge-triggered clock input (ck). output enable ( g ) and power down control (zz) are asynchronous inputs. burst cycles can be initiated with either adsp or adsc inputs. in burst mode, subsequent burst addresses are generated internally and are controlled by adv . the burst address counter may be configured to count in either linear or interleave order with the linear burst order ( lbo ) input. the burst function need not be used. new addresses can be loaded on every cycle with no degradation of chip performance. designing for compatibility the jedec standard for burst rams calls for a ft mode pin option on pin 14. board sites for flow through burst rams should be designed with v ss connected to the ft pin location to ensure the broadest access to multiple vendor sources. boards designed with ft pin pads tied low may be stuffed with gsi?s pipeline/flow through-configurable burst rams or any vendor?s flow through or configurable burst sram. boards designed with the ft pin location tied high or floating must employ a non-configurable flow through burst ram, like this ram, to achieve flow through functionality. byte write and global write byte write operation is performed by using byte write enable ( bw ) input combined with one or more individual byte write signals ( bx ). in addition, global write ( gw ) is available for writing all bytes at one time, regardless of the byte write control inputs. sleep mode low power (sleep mode) is attained through the assertion (high) of the zz signal, or by stopping the clock (ck). memory data is retained during sleep mode. core and interface voltages the gs 8150 f 18 /32 /36 t operates on a 3.3 v power supply. all input are 3.3 v- and 2.5 v-compatible. separate output power ( v ddq ) pins are used to decouple output noise from the internal circuits and are 3.3 v- and 2.5 v-compatible. -7 - 7.5 - 8 - 8.5 - 10 - 11 unit flow through 2-1-1-1 t kq tcycle curr (x18) curr (x32) curr (x36) 7.0 8.5 205 240 240 7.5 10 185 210 210 8 10 185 210 210 8.5 10 185 210 210 10 10 185 210 210 11 15 140 160 160 ns ns ma ma ma
rev: 1.01 11/2000 2/23 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8150 f 18/ 32/ 36 t - 7/8/8.5/10/11 gs 8150 f 18 100-pin tqfp pinout 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ddq v ss dq b1 dq b2 v ss v ddq dq b3 dq b4 v dd nc v ss dq b5 dq b6 v ddq v ss dq b7 dq b8 dq b9 v ss v ddq v ddq v ss v ss dq a8 dq a7 v ss v ddq dq a6 dq a5 v ss nc v dd zz dq a4 dq a3 v ddq v ss dq a2 dq a1 v ss v ddq l b o a 5 a 4 a 3 a 2 a 1 a 0 n c n c v s s v d d a 1 8 a 1 7 a 1 0 a 1 1 a 1 2 a 1 3 a 1 4 a 1 6 a 6 a 7 e 1 e 2 n c n c b b b a e 3 c k g w b w v d d v s s g a d s c a d s p a d v a 8 a 9 a 1 5 1m x 18 top view dq a9 a 19 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 nc
rev: 1.01 11/2000 3/23 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8150 f 18/ 32/ 36 t - 7/8/8.5/10/11 gs 8150 f 32 100-pin tqfp pinout 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ddq v ss dq c4 dq c3 v ss v ddq dq c2 dq c1 v dd nc v ss dq d1 dq d2 v ddq v ss dq d3 dq d4 dq d5 v ss v ddq v ddq v ss dq b4 dq b3 v ss v ddq dq b2 dq b1 v ss nc v dd zz dq a1 dq a2 v ddq v ss dq a3 dq a4 v ss v ddq l b o a 5 a 4 a 3 a 2 a 1 a 0 n c n c v s s v d d a 1 8 a 1 7 a 1 0 a 1 1 a 1 2 a 1 3 a 1 4 a 1 6 a 6 a 7 e 1 e 2 b d b c b b b a e 3 c k g w b w v d d v s s g a d s c a d s p a d v a 8 a 9 a 1 5 512k x 32 top view dq b5 nc dq b7 dq b8 dq b6 dq a6 dq a5 dq a8 dq a7 nc dq c7 dq c8 dq c6 dq d6 dq d8 dq d7 nc dq c5 nc 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 nc
rev: 1.01 11/2000 4/23 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8150 f 18/ 32/ 36 t - 7/8/8.5/10/11 gs 8150 f 36 100-pin tqfp pinout 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ddq v ss dq c4 dq c3 v ss v ddq dq c2 dq c1 v dd nc v ss dq d1 dq d2 v ddq v ss dq d3 dq d4 dq d5 v ss v ddq v ddq v ss dq b4 dq b3 v ss v ddq dq b2 dq b1 v ss nc v dd zz dq a1 dq a2 v ddq v ss dq a3 dq a4 v ss v ddq l b o a 5 a 4 a 3 a 2 a 1 a 0 n c n c v s s v d d a 1 8 a 1 7 a 1 0 a 1 1 a 1 2 a 1 3 a 1 4 a 1 6 a 6 a 7 e 1 e 2 b d b c b b b a e 3 c k g w b w v d d v s s g a d s c a d s p a d v a 8 a 9 a 1 5 512k x 36 top view dq b5 dq b9 dq b7 dq b8 dq b6 dq a6 dq a5 dq a8 dq a7 dq a9 dq c7 dq c8 dq c6 dq d6 dq d8 dq d7 dq d9 dq c5 dq c9 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 nc
rev: 1.01 11/2000 5/23 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8150 f 18/ 32/ 36 t - 7/8/8.5/10/11 tqfp pin description pin location symbol typ e description 37, 36 a 0 , a 1 i address field lsbs and address counter preset inputs 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50, 43, 42, a 2 ? a 18 i address inputs 80 a 19 i address inputs (x18 versions) 63, 62, 59, 58, 57, 53, 52 68, 69, 72, 73, 74, 75, 78, 79 13, 12, 9, 8, 7, 6, 3, 2 18, 19, 22, 23, 24, 25, 28, 29 dq a1 ? dq a8 dq b1 ? dq b8 dq c1 ? dq c8 dq d1 ? dq d8 i/o data input and output pins ( x32, x36 version) 51, 80, 1, 30 dq a9 , dq b9 , dq c9 , dq d9 i/o data input and output pins (x36 version) 58, 59, 62, 63, 68, 69, 72, 73, 74 8, 9, 12, 13, 18, 19, 22, 23, 24 dq a1 ? dq a9 dq b1 ? dq b9 i/o data input and output pins (x18 version) 51, 52, 53, 56, 57 75, 78, 79, 1, 2, 3, 6, 7, 25, 28, 29, 30 nc ? no connect (x18 version) 87 bw i byte write?writes all enabled bytes; active low 93, 94 b a , b b i byte write enable for dq a , dq b data i/os; active low 95, 96 b c , b d i byte write enable for dq c , dq d data i/os; active low ( x32, x36 version) 95, 96 nc ? no connect (x18 version) 89 ck i clock input signal; active high 88 gw i global write enable?writes all bytes; active low 98 , 92 e 1 , e 3 i chip enable; active low 97 e 2 i chip enable; active high 86 g i output enable; active low 83 adv i burst address counter advance enable; active low 84, 85 adsp , adsc i address strobe (processor, cache controller); active low 64 zz i sleep mode control; active high 31 lbo i linear burst order mode; active low 15, 41, 65, 91 v dd i core power supply 5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90 v ss i i/o and core ground 4, 11, 20, 27, 54, 61, 70, 77 v ddq i output driver power supply 14, 16, 38, 39, 66 nc ? no connect
rev: 1.01 11/2000 6/23 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8150 f 18/ 32/ 36 t - 7/8/8.5/10/11 gs 8150 f 18/32/36 block diagram a1 a0 a0 a1 d0 d1 q1 q0 counter load d q d q register register d q register d q register d q register d q register d q register d q register d q r e g i s t e r d q r e g i s t e r a0?an lbo adv ck adsc adsp gw bw e 1 g zz power down control memory array 36 36 4 a q d e 2 e 3 dqx0?dqx9 note: only x36 version shown for simplicity. 1 b a b b b c b d 0
rev: 1.01 11/2000 7/23 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8150 f 18/ 32/ 36 t - 7/8/8.5/10/11 note: there is a pull-down device on the zz pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the above tables. burst counter sequences bpr 1999.05.18 byte write truth table notes: 1. all byte outputs are active in read cycles regardless of the state of byte write enable inputs. 2. byte write enable inputs b a , b b , b c , and/or b d may be used in any combination with bw to write single or multiple bytes. 3. all byte i/os remain high-z during all write operations regardless of the state of byte write enable inputs. 4. bytes ? c ? and ? d ? are only available on the x32 and x36 version s . mode pin functions mode name pin name state function burst order control lbo l linear burst h interleaved burst power down control zz l or nc active h standby, i dd = i sb function gw bw b a b b b c b d notes read h h x x x x 1 read h l h h h h 1 write byte a h l l h h h 2, 3 write byte b h l h l h h 2, 3 write byte c h l h h l h 2, 3, 4 write byte d h l h h h l 2, 3, 4 write all bytes h l l l l l 2, 3, 4 write all bytes l x x x x x linear burst sequence note: the burst counter wraps to initial state on the 5th clock. i nterleaved burst sequence note: the burst counter wraps to initial state on the 5th clock. a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11 00 01 10 a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 00 11 10 3rd address 10 11 00 01 4th address 11 10 01 00
rev: 1.01 11/2000 8/23 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8150 f 18/ 32/ 36 t - 7/8/8.5/10/11 synchronous truth table operation address used state diagram key 5 e 1 e 2 adsp adsc adv w 3 dq 4 deselect cycle, power down none x h x x l x x high-z deselect cycle, power down none x l f l x x x high-z deselect cycle, power down none x l f h l x x high-z read cycle, begin burst external r l t l x x x q read cycle, begin burst external r l t h l x f q write cycle, begin burst external w l t h l x t d read cycle, continue burst next cr x x h h l f q read cycle, continue burst next cr h x x h l f q write cycle, continue burst next cw x x h h l t d write cycle, continue burst next cw h x x h l t d read cycle, suspend burst current x x h h h f q read cycle, suspend burst current h x x h h f q write cycle, suspend burst current x x h h h t d write cycle, suspend burst current h x x h h t d notes: 1. x = don?t care, h = high, l = low 2. e = t (true) if e 2 = 1; e = f (false) if e 2 = 0 3. w = t (true) and f (false) is defined in the byte write truth table preceding 4. g is an asynchronous input. g can be driven high at any time to disable active output drivers. g low can only enable active drivers (shown as ?q? in the truth table above). 5. all input combinations shown above are tested and supported. input combinations shown in gray boxes need not be used to accompli sh basic synchronous or synchronous burst operations and may be avoided for simplicity. 6. tying adsp high and adsc low allows simple non-burst synchronous operations. see bold items above. 7. tying adsp high and adv low while using adsc to load new addresses allows simple burst operations. see italic items above.
rev: 1.01 11/2000 9/23 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8150 f 18/ 32/ 36 t - 7/8/8.5/10/11 first write first read burst write burst read deselect r w cr cw x x w r r w r x x x s i m p l e s y n c h r o n o u s o p e r a t i o n s i m p l e b u r s t s y n c h r o n o u s o p e r a t i o n cr r cw cr cr simplified state diagram notes: 1. the diagram shows only supported (tested) synchronous state transitions. the diagram presumes g is tied low. 2. the upper portion of the diagram assumes active use of only the enable ( e1 , e2, and e3 ) and write ( b a , b b , b c , b d , bw , and gw ) control inputs and that adsp is tied high and adsc is tied low. 3. the upper and lower portions of the diagram together assume active use of only the enable, write, and adsc control inputs and assumes adsp is tied high and adv is tied low.
rev: 1.01 11/2000 10/23 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8150 f 18/ 32/ 36 t - 7/8/8.5/10/11 first write first read burst write burst read deselect r w cr cw x x w r r w r x x x cr r cw cr cr w cw w cw simplified state diagram with g notes: 1. the diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of g . 2. use of ?dummy reads? (read cycles with g high) may be used to make the transition from read cycles to write cycles without passing through a deselect cycle. dummy read cycles increment the address counter just like normal read cycles. 3. transitions shown in grey tone assume g has been pulsed high long enough to turn the ram?s drivers off and for incoming data to meet data input set up time.
rev: 1.01 11/2000 11/23 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8150 f 18/ 32/ 36 t - 7/8/8.5/10/11 note: permanent damage to the device may occur if the absolute maximum ratings are exceeded. operation should be restricted to recomme nded operating conditions. exposure to conditions exceeding the absolute maximum ratings, for an extended period of time, may affect reliability of this component. notes: 1. unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 v v ddq 2.375 v (i.e., 2.5 v i/o) and 3.6 v v ddq 3.135 v (i.e., 3.3 v i/o), and quoted at whichever condition is worst case. 2. this device features input buffers compatible with both 3.3 v and 2.5 v i/o drivers. 3. most speed grades and configurations of this device are of f ered in both commercial and industrial temperature ranges. the part number of industrial temperature range versions end the character ?i?. unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 4. input under/overshoot voltage must be ?2 v > vi < v dd +2 v with a pulse width not to exceed 20% tkc. absolute maximum ratings (all voltages reference to v ss ) symbol description value unit v dd voltage on v dd pins ?0.5 to 4.6 v v ddq voltage in v ddq pins ?0.5 to v dd v v ck voltage on clock input pin ?0.5 to 6 v v i/o voltage on i/o pins ?0.5 to v ddq +0.5 ( 4.6 v max.) v v in voltage on other input pins ?0.5 to v dd +0.5 ( 4.6 v max.) v i in input current on any pin +/?20 ma i out output current on any i/o pin +/?20 ma p d package power dissipation 1.5 w t stg storage temperature ?55 to 125 o c t bias temperature under bias ?55 to 125 o c recommended operating conditions parameter symbol min. typ. max. unit notes supply voltage v dd 3.135 3.3 3.6 v i/o supply voltage v ddq 2.375 2.5 v dd v 1 input high voltage v ih 1.7 ? v dd +0.3 v 2 input low voltage v il ?0.3 ? 0.8 v 2 ambient temperature (commercial range versions) t a 0 25 70 c 3 ambient temperature (industrial range versions) t a ?40 25 85 c 3
rev: 1.01 11/2000 12/23 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8150 f 18/ 32/ 36 t - 7/8/8.5/10/11 note: these parameters are sample tested. notes: 1. junction temperature is a function of sram power dissipation, package thermal resistance, mounting board temperature, ambient. t emper- ature air flow, board density, and pcb thermal resistance. 2. scmi g-38-87 3. average thermal resistance between die and top surface, mil spec-883, method 1012.1 capacitance (t a = 25 o c , f = 1 mh z , v dd = 3.3 v) parameter symbol test conditions typ. max. unit input capacitance c in v in = 0 v 4 5 pf input/output capacitance c i/o v out = 0 v 6 (x36) 12 (x18) 7 (x36) 12 (x18) pf package thermal characteristics rating layer board symbol max unit notes junction to ambient (at 200 lfm) single r q ja 40 c/w 1,2 junction to ambient (at 200 lfm) four r q ja 24 c/w 1,2 junction to case (top) ? r q jc 9 c/w 3 20% tkc v ss ? 2.0 v 50% v ss v ih undershoot measurement and timing overshoot measurement and timing 20% tkc v dd + 2.0 v 50% v dd v il
rev: 1.01 11/2000 13/23 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8150 f 18/ 32/ 36 t - 7/8/8.5/10/11 notes: 1. include scope and jig capacitance. 2. test conditions as specified with output loading as shown in fig. 1 unless otherwise noted. 3. output load 2 for t lz , t hz , t olz and t ohz 4. device is deselected as defined by the truth table. ac test conditions parameter conditions input high level 2.3 v input low level 0.2 v input slew rate 1 v/ns input reference level 1.25 v output reference level 1.25 v output load fig. 1& 2 dc electrical characteristics parameter symbol test conditions min max input leakage current (except mode pins) i il v in = 0 to v dd ?1 ua 1 ua zz input current i in zz v dd 3 v in 3 v ih 0 v v in v ih ?1 ua ?1 ua 1 ua 300 ua mode pin input current i in m v dd 3 v in 3 v il 0 v v in v il ?300 ua ?1 ua 1 ua 1 ua output leakage current i ol output disable, v out = 0 to v dd ?1 ua 1 ua output high voltage v oh i oh = ? 4 ma, v ddq = 2.375 v 1.7 v ? output high voltage v oh i oh = ? 4 ma, v ddq = 3.135 v 2.4 v ? output low voltage v ol i ol = 4 ma ? 0.4 v dq vt = 1.25 v 50 w 30pf * dq 2.5 v output load 1 output load 2 225 w 225 w 5pf * * distributed test jig capacitance
rev: 1.01 11/2000 14/23 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8150 f 18/ 32/ 36 t - 7/8/8.5/10/11 o p e r a t i n g c u r r e n t s p a r a m e t e r t e s t c o n d i t i o n s m o d e s y m b o l - 7 - 7 . 5 - 8 - 8 . 5 - 1 0 - 1 1 u n i t 0 t o 7 0 c ? 4 0 t o 8 5 c 0 t o 7 0 c ? 4 0 t o 8 5 c 0 t o 7 0 c ? 4 0 t o 8 5 c 0 t o 7 0 c ? 4 0 t o 8 5 c 0 t o 7 0 c ? 4 0 t o 8 5 c 0 t o 7 0 c ? 4 0 t o 8 5 c o p e r a t i n g c u r r e n t d e v i c e s e l e c t e d ; a l l o t h e r i n p u t s 3 v i h o r v i l o u t p u t o p e n ( x 3 6 ) f l o w t h r o u g h i d d i d d q 1 9 9 3 9 2 0 9 4 9 1 7 7 3 3 1 8 7 4 3 1 7 7 3 3 1 8 7 4 3 1 7 7 3 3 1 8 7 4 3 1 7 7 3 3 1 8 7 4 3 1 3 4 2 2 1 4 4 3 2 m a ( x 1 8 ) f l o w t h r o u g h i d d i d d q 1 8 6 1 9 1 9 6 2 9 1 6 6 1 7 1 7 6 2 7 1 6 6 1 7 1 7 6 2 7 1 6 6 1 7 1 7 6 2 7 1 6 6 1 7 1 7 6 2 7 1 2 7 1 1 1 3 7 2 1 m a s t a n d b y c u r r e n t z z 3 v d d ? 0 . 2 v ? f l o w t h r o u g h i s b 1 0 2 0 1 0 2 0 1 0 2 0 1 0 2 0 1 0 2 0 1 0 2 0 m a d e s e l e c t c u r r e n t d e v i c e d e s e l e c t e d ; a l l o t h e r i n p u t s 3 v i h o r v i l ? f l o w t h r o u g h i d d 6 0 6 5 5 0 5 5 5 0 5 5 5 0 5 5 5 0 5 5 4 5 5 0 m a
rev: 1.01 11/2000 15/23 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8150 f 18/ 32/ 36 t - 7/8/8.5/10/11 ac electrical characteristics notes: 1. these parameters are sampled and are not 100% tested. 2. zz is an asynchronous signal. however, in order to be recognized on any given clock cycle, zz must meet the specified setup and hold times as specified above. parameter symbol - 7 ns - 7.5 ns - 8 ns - 8.5 ns - 10 ns - 11 ns unit min max min max min max min max min max min max flow through clock cycle time tkc 8.5 ? 10.0 ? 10.0 ? 10.0 ? 10.0 ? 15.0 ? ns clock to output valid tkq ? 7 ? 7.5 ? 8.0 ? 8.5 ? 10.0 ? 11.0 ns clock to output invalid tkqx 3.0 ? 3.0 ? 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns clock to output in low-z tlz 1 3.0 ? 3.0 ? 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns clock high time tkh 1.3 ? 1.3 ? 1.3 ? 1.3 ? 1.5 ? 1.7 ? ns clock low time tkl 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.7 ? 2 ? ns clock to output in high-z thz 1 1.5 2.5 1.5 3.0 1.5 3.2 1.5 3.5 1.5 3.8 1.5 4.0 ns g to output valid toe ? 2.5 ? 3.2 ? 3.2 ? 3.5 ? 3.8 ? 4.0 ns g to output in low-z tolz 1 0 ? 0 ? 0 ? 0 ? 0 ? 0 ? ns g to output in high-z tohz 1 ? 2.5 ? 3.0 ? 3.2 ? 3.5 ? 3.8 ? 4.0 ns setup time ts 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns hold time th 0.5 ? 0.5 ? 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns zz setup time tzzs 2 5 ? 5 ? 5 ? 5 ? 5 ? 5 ? ns zz hold time tzzh 2 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? ns zz recovery tzzr 100 ? 100 ? 100 ? 100 ? 100 ? 100 ? ns
rev: 1.01 11/2000 16/23 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8150 f 18/ 32/ 36 t - 7/8/8.5/10/11 ck adsp adsc adv gw bw g wr2 wr3 wr1 wr1 wr2 wr3 tkc single write burst write d2 a d2 b d2 c d2 d d3 a d1 a t kl t kh ts th ts th ts th ts th ts th ts th ts th ts th write specified byte for 2 a and all bytes for 2 b , 2 c & 2 d adv must be inactive for adsp write adsc initiated write adsp is blocked by e inactive a 0 ?an b a ? b d dq a ?dq d write deselected hi-z wr1 wr2 wr3 write cycle timing e 1 e 3 ts th ts th ts th e 2 and e 3 only sampled with adsp or adsc e 1 masks adsp e 2 deselected with e 2
rev: 1.01 11/2000 17/23 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8150 f 18/ 32/ 36 t - 7/8/8.5/10/11 q1 a q3 a q2 d q2c q2 b q2 a tkq tlz toe tohz tolz tkqx thz tkqx ck adsp adsc bw g gw adv burst read rd2 rd3 tkl ts th th ts th ts th adsc initiated read suspend burst single read adsp is blocked by e inactive a 0 ?an b a ? b b tkh tkc ts th ts ts th dq a ?dq d rd1 hi-z suspend burst flow through read cycle timing e 2 ts th th th e 1 masks adsp e 2 and e 3 only sampled with adsp or adsc deselected with e 2 e 3 e 1 ts ts
rev: 1.01 11/2000 18/23 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8150 f 18/ 32/ 36 t - 7/8/8.5/10/11 flow through read-write cycle timing ck adsp adsc adv gw bw g rd1 rd2 q1 a q2 a q2 b q2c q2 d single read burst read toe tohz ts th th ts th ts th ts th ts th tkh adsc initiated read dq a ?dq d b a ? b d a 0 ?a n tkl tkc ts single write adsp is blocked by e inactive tkq hi-z q2 a burst wrap around to it?s initial state e 1 e 3 e 2 ts ts th ts e 1 masks adsp e 2 and e 3 only sampled with adsp and adsc deselected with e 3 th th wr1 ts wr1 ts th d1 a ts th
rev: 1.01 11/2000 19/23 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8150 f 18/ 32/ 36 t - 7/8/8.5/10/11 ck adsp adsc th tkh tkl tkc ts zz tzzr tzzh tzzs ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ snooze sleep mode timing diagram
rev: 1.01 11/2000 20/23 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8150 f 18/ 32/ 36 t - 7/8/8.5/10/11 tqfp package drawing d 1 d e1 e p i n 1 b e c l l1 a2 a1 y q notes: 1. all dimensions are in millimeters (mm). 2. package width and length do not include mold protrusion. symbol description min. nom. max a1 standoff 0.05 0.10 0.15 a2 body thickness 1.35 1.40 1.45 b lead width 0.20 0.30 0.40 c lead thickness 0.09 ? 0.20 d terminal dimension 21.9 22.0 22.1 d1 package body 19.9 20.0 20.1 e terminal dimension 15.9 16.0 16.1 e1 package body 13.9 14.0 14.1 e lead pitch ? 0.65 ? l foot length 0.45 0.60 0.75 l1 lead length ? 1.00 ? y coplanarity ? ? 0.10 q lead angle 0 ? 7
rev: 1.01 11/2000 21/23 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8150 f 18/ 32/ 36 t - 7/8/8.5/10/11 ordering information for gsi synchronous burst rams org part number 1 type package speed 2 (mhz/ns) t a 3 status 1m x 18 gs8150f18t-7 flow through tqfp 7 c 1m x 18 gs8150f18t-7.5 flow through tqfp 7.5 c 1m x 18 gs8150f18t-8 flow through tqfp 8 c 1m x 18 gs8150f18t-8.5 flow through tqfp 8.5 c 1m x 18 gs8150f18t-10 flow through tqfp 10 c 1m x 18 gs8150f18t-11 flow through tqfp 11 c 512k x 32 gs8150f36t-7 flow through tqfp 7 c 512k x 32 gs8150f36t-7.5 flow through tqfp 7.5 c 512k x 32 gs8150f36t-8 flow through tqfp 8 c 512k x 32 gs8150f36t-8.5 flow through tqfp 8.5 c 512k x 32 gs8150f36t-10 flow through tqfp 10 c 512k x 32 gs8150f36t-11 flow through tqfp 11 c 512k x 36 gs8150f36t-7 flow through tqfp 7 c 512k x 36 gs8150f36t-7.5 flow through tqfp 7.5 c 512k x 36 gs8150f36t-8 flow through tqfp 8 c 512k x 36 gs8150f36t-8.5 flow through tqfp 8.5 c 512k x 36 gs8150f36t-10 flow through tqfp 10 c 512k x 36 gs8150f36t-11 flow through tqfp 11 c 1m x 18 gs8150f18t-7i flow through tqfp 7 i not available 1m x 18 gs8150f18t-7.5i flow through tqfp 7.5 i not available 1m x 18 gs8150f18t-8i flow through tqfp 8 i 1m x 18 gs8150f18t-8.5i flow through tqfp 8.5 i 1m x 18 gs8150f18t-10i flow through tqfp 10 i 1m x 18 gs8150f18t-11i flow through tqfp 11 i 512k x 32 gs8150f36t-7i flow through tqfp 7 i not available 512k x 32 gs8150f36t-7.5i flow through tqfp 7.5 i not available 512k x 32 gs8150f36t-8i flow through tqfp 8 i 512k x 32 gs8150f36t-8.5i flow through tqfp 8.5 i 512k x 32 gs8150f36t-10i flow through tqfp 10 i 512k x 32 gs8150f36t-11i flow through tqfp 11 i notes: 1. customers requiring delivery in tape and reel should add the character ?t? to the end of the part number. example: gs 8150f18 - 8 t . 2. the speed column indicates the cycle frequency (mhz) of the device in pipeline mode and the latency (ns) in flow through mode. each device is pipeline/flow through mode-selectable by the user. 3. t a = c = commercial temperature range. t a = i = industrial temperature range. 4. gsi offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. see the gsi technology web site ( www.gsitechnology.com ) for a complete listing of current offerings.
rev: 1.01 11/2000 22/23 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8150 f 18/ 32/ 36 t - 7/8/8.5/10/11 512k x 36 gs8150f36t-7i flow through tqfp 7 i not available 512k x 36 gs8150f36t-7.5i flow through tqfp 7.5 i not available 512k x 36 gs8150f36t-8i flow through tqfp 8 i 512k x 36 gs8150f36t-8.5i flow through tqfp 8.5 i 512k x 36 gs8150f36t-10i flow through tqfp 10 i 512k x 36 gs8150f36t-11i flow through tqfp 11 i org part number 1 type package speed 2 (mhz/ns) t a 3 status notes: 1. customers requiring delivery in tape and reel should add the character ?t? to the end of the part number. example: gs 8150f18 - 8 t . 2. the speed column indicates the cycle frequency (mhz) of the device in pipeline mode and the latency (ns) in flow through mode. each device is pipeline/flow through mode-selectable by the user. 3. t a = c = commercial temperature range. t a = i = industrial temperature range. 4. gsi offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. see the gsi technology web site ( www.gsitechnology.com ) for a complete listing of current offerings.
rev: 1.01 11/2000 23/23 ? 2000, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. preliminary gs 8150 f 18/ 32/ 36 t - 7/8/8.5/10/11 0.18u 16m sync sram data sheet revision history ds/daterev. code: old; new types of changes format or content page;revisions;reason 8150f18_r1 ? creation of new datasheet 8150f18_r1; 8150f18_r1_01 content ? updated features list on page 1 ? completely reworked table on page 1 ? updated mode pin functions table on page 7

▲Up To Search▲

Price & Availability of GS8150F32

	To Download GS8150F32 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .