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1/16 september 2002 M48Z08 m48z18 5v, 64 kbit (8kb x 8) zeropower ? sram features summary n integrated, ultra low power sram and power-fail control circuit n unlimited write cycles n read cycle time equals write cycle time n automatic power-fail chip deselect and write protection n write protect voltages (v pfd = power-fail deselect voltage): C M48Z08: v cc = 4.75 to 5.5v 4.5v v pfd 4.75v C m48z18: v cc = 4.5 to 5.5v 4.2v v pfd 4.5v n self-contained battery in the caphat? dip package n pin and function compatible with jedec standard 8k x 8 srams figure 1. 28-pin caphat, dip package pcdip28 (pc) battery/crystal caphat 28 1
M48Z08, m48z18 2/16 table of contents summary description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 logic diagram (figure 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 signal names (table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 dip connections (figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 block diagram (figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 absolute maximum ratings (table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 operating and ac measurement conditions (table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ac testing load circuit (figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 capacitance (table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 dc characteristics (table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 operating modes (table 6.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 read mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 read mode ac waveforms (figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 read mode ac characteristics (table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 write enable controlled, write mode ac waveform (figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . 8 chip enable controlled, write mode ac waveforms (figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . 8 write mode ac characteristics (table 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 data retention mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 power down/up mode ac waveforms (figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 power down/up ac characteristics (table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 power down/up trip points dc characteristics (table 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 crystal accuracy across temperature (figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 v cc noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 supply voltage protection (figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3/16 M48Z08, m48z18 summary description the M48Z08/18 zeropower ? ram is a 8k x 8 non-volatile static ram which is pin and functional compatible with the ds1225. the monolithic chip is available in two special packages to provide a highly integrated battery backed-up memory solution. the M48Z08/18 is a non-volatile pin and function equivalent to any jedec standard 8k x 8 sram. it also easily fits into many rom, eprom, and eeprom sockets, providing the non-volatility of proms without any requirement for special write timing or limitations on the number of writes that can be performed. the 28-pin, 600mil dip caphat? houses the M48Z08/18 silicon with a long life lithium button cell in a single package. figure 2. logic diagram table 1. signal names figure 3. dip connections ai01022 13 a0-a12 w dq0-dq7 v cc M48Z08 m48z18 g v ss 8 e a0-a12 address inputs dq0-dq7 data inputs / outputs e chip enable g output enable w write enable v cc supply voltage v ss ground nc not connected internally a1 a0 dq0 a7 a4 a3 a2 a6 a5 nc a10 a8 a9 dq7 w a11 g e dq5 dq1 dq2 dq3 v ss dq4 dq6 a12 nc v cc ai01183 M48Z08 m48z18 8 1 2 3 4 5 6 7 9 10 11 12 13 14 16 15 28 27 26 25 24 23 22 21 20 19 18 17
M48Z08, m48z18 4/16 figure 4. block diagram maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 2. absolute maximum ratings note: 1. for dip package: soldering temperature not to exceed 260c for 10 seconds (total thermal budget not to exceed 150c for longer than 30 seconds). caution: negative undershoots below C0.3v are not allowed on any pin while in the battery back-up mode. ai01394 lithium cell v pfd v cc v ss voltage sense and switching circuitry 8k x 8 sram array a0-a12 dq0-dq7 e w g power symbol parameter value unit t a ambient operating temperature 0 to 70 c t stg storage temperature (v cc off, oscillator off) C40 to 85 c t sld (1) lead solder temperature for 10 seconds 260 c v io input or output voltages C0.3 to 7 v v cc supply voltage C0.3 to 7 v i o output current 20 ma p d power dissipation 1 w
5/16 M48Z08, m48z18 dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 3. operating and ac measurement conditions note: output hi-z is defined as the point where data is no longer driven. figure 5. ac testing load circuit table 4. capacitance note: 1. effective capacitance measured with power supply at 5v; sampled only, not 100% tested. 2. at 25c, f = 1mhz. 3. outputs deselected. parameter M48Z08 m48z18 unit supply voltage (v cc ) 4.75 to 5.5 4.5 to 5.5 v ambient operating temperature (t a ) 0 to 70 0 to 70 c load capacitance (c l ) 100 100 pf input rise and fall times 5 5ns input pulse voltages 0 to 3 0 to 3 v input and output timing ref. voltages 1.5 1.5 v ai01398 5v out c l = 100pf or 30pf c l includes jig capacitance 1.8k w device under test 1k w symbol parameter (1,2) min max unit c in input capacitance 10 pf c io (3) input / output capacitance 10 pf
M48Z08, m48z18 6/16 table 5. dc characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.75 to 5.5v or 4.5 to 5.5v (except where noted). 2. outputs deselected. 3. negative spikes of C1v allowed for up to 10ns once per cycle. operation modes the M48Z08/18 also has its own power-fail detect circuit. the control circuitry constantly monitors the single 5v supply for an out of tolerance condi- tion. when v cc is out of tolerance, the circuit write protects the sram, providing a high degree of data security in the midst of unpredictable system operation brought on by low v cc . as v cc falls be- low approximately 3v, the control circuitry con- nects the battery which maintains data until valid power returns. table 6. operating modes note: x = v ih or v il ; v so = battery back-up switchover voltage. 1. see table 10, page 11 for details. symbol parameter test condition (1) min max unit i li input leakage current 0v v in v cc 1 a i lo (2) output leakage current 0v v out v cc 1 a i cc supply current outputs open 80 ma i cc1 supply current (standby) ttl e = v ih 3ma i cc2 supply current (standby) cmos e = v cc C 0.2v 3ma v il (3) input low voltage C0.3 0.8 v v ih input high voltage 2.2 v cc + 0.3 v v ol output low voltage i ol = 2.1ma 0.4 v v oh output high voltage i oh = C1ma 2.4 v mode v cc e g w dq0-dq7 power deselect 4.75 to 5.5v or 4.5 to 5.5v v ih x x high z standby write v il x v il d in active read v il v il v ih d out active read v il v ih v ih high z active deselect v so to v pfd (min) (1) x x x high z cmos standby deselect v so (1) x x x high z battery back-up mode
7/16 M48Z08, m48z18 read mode the M48Z08/18 is in the read mode whenever w (write enable) is high and e (chip enable) is low. the device architecture allows ripple-through access of data from eight of 65,536 locations in the static storage array. thus, the unique address specified by the 13 address inputs defines which one of the 8,192 bytes of data is to be accessed. valid data will be available at the data i/o pins within address access time (t avqv ) after the last address input signal is stable, providing that the e and g access times are also satisfied. if the e and g access times are not met, valid data will be available after the latter of the chip enable access time (t elqv ) or output enable access time (t glqv ). the state of the eight three-state data i/o signals is controlled by e and g . if the outputs are activat- ed before t avqv , the data lines will be driven to an indeterminate state until t avqv . if the address in- puts are changed while e and g remain active, output data will remain valid for output data hold time (t axqx ) but will go indeterminate until the next address access. figure 6. read mode ac waveforms note: write enable (w ) = high. table 7. read mode ac characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.75 to 5.5v or 4.5 to 5.5v (except where noted). 2. c l = 30pf. symbol parameter (1) M48Z08/m48z18 unit min max t avav read cycle time 100 ns t avqv address valid to output valid 100 ns t elqv chip enable low to output valid 100 ns t glqv output enable low to output valid 50 ns t elqx (2) chip enable low to output transition 10 ns t glqx (2) output enable low to output transition 5 ns t ehqz (2) chip enable high to output hi-z 50 ns t ghqz (2) output enable high to output hi-z 40 ns t axqx address transition to output transition 5 ns ai01385 tavav tavqv taxqx telqv telqx tehqz tglqv tglqx tghqz valid a0-a12 e g dq0-dq7 valid
M48Z08, m48z18 8/16 write mode the M48Z08/18 is in the write mode whenever w and e are active. the start of a write is refer- enced from the latter occurring falling edge of w or e . a write is terminated by the earlier rising edge of w or e . the addresses must be held valid through- out the cycle. e or w must return high for a mini- mum of t ehax from chip enable or t whax from write enable prior to the initiation of another read or write cycle. data-in must be valid t d- vwh prior to the end of write and remain valid for t whdx afterward. g should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on e and g , a low on w will disable the outputs t wlqz after w falls. figure 7. write enable controlled, write mode ac waveform figure 8. chip enable controlled, write mode ac waveforms ai01386 tavav twhax tdvwh data input a0-a12 e w dq0-dq7 valid tavwh tavel twlwh tavwl twlqz twhdx twhqx ai01387b tavav tehax tdveh a0-a12 e w dq0-dq7 valid taveh tavel tavwl teleh tehdx data input
9/16 M48Z08, m48z18 table 8. write mode ac characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.75 to 5.5v or 4.5 to 5.5v (except where noted). 2. c l = 30pf. 3. if e goes low simultaneously with w going low, the outputs remain in the high impedance state. symbol parameter (1) M48Z08/m48z18 unit min max t avav write cycle time 100 ns t av wl address valid to write enable low 0 ns t av el address valid to chip enable 1 low 0 ns t wlwh write enable pulse width 80 ns t eleh chip enable low to chip enable 1 high 80 ns t whax write enable high to address transition 10 ns t ehax chip enable high to address transition 10 ns t dvwh input valid to write enable high 50 ns t dveh input valid to chip enable 1 high 30 ns t whdx write enable high to input transition 5 ns t ehdx chip enable high to input transition 5 ns t wlqz (2,3) write enable low to output hi-z 50 ns t avwh address valid to write enable high 80 ns t ave h address valid to chip enable high 80 ns t whqx (2,3) write enable high to output transition 10 ns
M48Z08, m48z18 10/16 data retention mode with valid v cc applied, the M48Z08/18 operates as a conventional bytewide? static ram. should the supply voltage decay, the ram will au- tomatically power-fail deselect, write protecting it- self when v cc falls within the v pfd (max), v pfd (min) window. all outputs become high imped- ance, and all inputs are treated as don't care. note: a power failure during a write cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the ram's con- tent. at voltages below v pfd (min), the user can be assured the memory will be in a write protected state, provided the v cc fall time is not less than t f . the M48Z08/18 may respond to transient noise spikes on v cc that reach into the deselect window during the time the device is sampling v cc . there- fore, decoupling of the power supply lines is rec- ommended. when v cc drops below v so , the control circuit switches power to the internal battery which pre- serves data. the internal button cell will maintain data in the M48Z08/18 for an accumulated period of at least 11 years when v cc is less than v so . as system power returns and v cc rises above v so , the battery is disconnected, and the power supply is switched to external v cc . write protec- tion continues until v cc reaches v pfd (min) plus t rec (min). e should be kept high as v cc rises past v pfd (min) to prevent inadvertent write cycles prior to system stabilization. normal ram operation can resume t rec after v cc exceeds v pfd (max). for more information on battery storage life refer to the application note an1012. figure 9. power down/up mode ac waveforms note: inputs may or may not be recognized at this time. caution should be taken to keep e high as v cc rises past v pfd (min). some systems may perform inadvertent write cycles after v cc rises above v pfd (min) but before normal system operations begin. even though a power on reset is being applied to the processor, a reset condition may not occur until after the system is running. ai00606 v cc inputs (per control input) outputs don't care high-z tf tfb tr trec tpd trb tdr valid valid note (per control input) recognized recognized v pfd (max) v pfd (min) v so
11/16 M48Z08, m48z18 table 9. power down/up ac characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.75 to 5.5v or 4.5 to 5.5v (except where noted). 2. v pfd (max) to v pfd (min) fall time of less than tf may result in deselection/write protection not occurring until 200s after v cc pass- es v pfd (min). 3. v pfd (min) to v ss fall time of less than t fb may cause corruption of ram data. table 10. power down/up trip points dc characteristics note: 1. all voltages referenced to v ss . 2. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.75 to 5.5v or 4.5 to 5.5v (except where noted). symbol parameter (1) min max unit t pd e or w at v ih before power down 0s t f (2) v pfd (max) to v pfd (min) v cc fall time 300 s t fb (3) v pfd (min) to v ss v cc fall time 10 s t r v pfd (min) to v pfd (max) v cc rise time 0s t rb v ss to v pfd (min) v cc rise time 1s t rec e or w at v ih before power up 2ms symbol parameter (1,2) min typ max unit v pfd power-fail deselect voltage M48Z08 4.5 4.6 4.75 v m48z18 4.2 4.3 4.5 v v so battery back-up switchover voltage 3.0 v t dr expected data retention time 11 years
M48Z08, m48z18 12/16 figure 10. crystal accuracy across temperature v cc noise and negative going transients i cc transients, including those produced by output switching, can produce voltage fluctuations, re- sulting in spikes on the v cc bus. these transients can be reduced if capacitors are used to store en- ergy which stabilizes the v cc bus. the energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. a ceramic by- pass capacitor value of 0.1f (as shown in figure 11) is recommended in order to provide the need- ed filtering. in addition to transients that are caused by normal sram operation, power cycling can generate neg- ative voltage spikes on v cc that drive it to values below v ss by as much as one volt. these negative spikes can cause data corruption in the sram while in battery backup mode. to protect from these voltage spikes, stmicroelectronics recom- mends connecting a schottky diode from v cc to v ss (cathode connected to v cc , anode to v ss ). schottky diode 1n5817 is recommended for through hole and mbrs120t3 is recommended for surface mount. figure 11. supply voltage protection ai02124 -80 -60 -100 -40 -20 0 20 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 d f = -0.038 (t - t 0 ) 2 10% f ppm c 2 t 0 = 25 c ppm c ai02169 v cc 0.1 m f device v cc v ss
13/16 M48Z08, m48z18 part numbering table 11. ordering information scheme note: 1. the M48Z08/18 part is offered with the pcdip28 (e.g., caphat?) package only. for a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the st sales office nearest you. example: m48z 08 C100 pc 1 tr device type m48z supply voltage and write protect voltage 08 (1) = v cc = 4.75 to 5.5v; v pfd = 4.5 to 4.75v 18 = v cc = 4.5 to 5.5v; v pfd = 4.2 to 4.5v speed C100 = 100ns package pc = pcdip28 temperature range 1 = 0 to 70c shipping method blank = tubes tr = tape & reel
M48Z08, m48z18 14/16 package mechanical information figure 12. pcdip28 C 28-pin plastic dip, battery caphat, package outline note: drawing is not to scale. table 12. pcdip28 C 28-pin plastic dip, battery caphat, package mechanical data symb mm inches typ min max typ min max a 8.89 9.65 0.350 0.380 a1 0.38 0.76 0.015 0.030 a2 8.38 8.89 0.330 0.350 b 0.38 0.53 0.015 0.021 b1 1.14 1.78 0.045 0.070 c 0.20 0.31 0.008 0.012 d 39.37 39.88 1.550 1.570 e 17.83 18.34 0.702 0.722 e1 2.29 2.79 0.090 0.110 e3 29.72 36.32 1.170 1.430 ea 15.24 16.00 0.600 0.630 l 3.05 3.81 0.120 0.150 n28 28 pcdip a2 a1 a l b1 b e1 d e n 1 c ea e3
15/16 M48Z08, m48z18 revision history table 13. document revision history date rev. # revision details march 1999 1.0 first issue 07/19/01 2.0 2-socket soh and 2-pin sh packages removed; reformatted; temperature information added to tables (table 4, 5, 7, 8, 9, 10) 12/19/01 2.1 remove all references to clock 12/21/01 2.2 changes to text to reflect addition of M48Z08y option 05/20/02 2.3 modify reflow time and temperature footnotes (table 2) 09/10/02 2.4 remove all references to snaphat and M48Z08y part (figure 2; table 2, 3, 7, 8, 10, 11)
M48Z08, m48z18 16/16 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com

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