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MT4C4256(l) micron semiconductor, inc., reserves the right to change products or specifications without notice. rev. 4/94 ? 1994, micron semiconductor, inc. 1 MT4C4256(l) 256k x 4 dram obsolete features ? 512-cycle refresh in 8ms (MT4C4256) or 64ms (MT4C4256 l) ? industry-standard x4 pinout, timing, functions and packages ? high-performance cmos silicon-gate process ? single +5v 10% power supply ? low power, 0.8mw standby; 175mw active, typical ? all inputs, outputs and clocks are ttl-compatible ? fast page mode access cycle ? refresh modes: / r ? a / s only, / c ? a / s-before- / r ? a / s (cbr), hidden and extended (MT4C4256 l only) ? low cmos standby current, 200 m a maximum (MT4C4256 l) options marking ? timing 60ns access -6 70ns acces -7 80ns access -8 ? packages plastic dip (300 mil) none plastic soj (300 mil) dj plastic zip (350 mil) z ? version 512-cycle refresh in 8 ms none 512-cycle refresh in 64 ms l ? part number example: MT4C4256dj-7 l dram 256k x 4 dram standard or low power, extended refresh pin assignment (top view) general description the MT4C4256(l) is a randomly accessed solid-state memory containing 1,048,576 bits organized in a x4 configu- ration. during read or write cycles, each bit is uniquely addressed through the 18 address bits, which are entered 9 bits (a0 -a8) at a time. / r ? a / s is used to latch the first 9 bits and / c ? a / s the latter 9 bits. read and write cycles are selected with the ? w / e input. a logic high on ? w / e dictates read mode while a logic low on ? w / e dictates write mode. during a write cycle, data-in (d) is latched by the falling edge of ? w / e or / c ? a / s, whichever occurs last. if ? w / e goes low prior to / c ? a / s going low, the output pin(s) remain open (high-z) until the next / c ? a / s cycle. if ? w / e goes low after data reaches the output pin, data-out (q) is activated and retains the selected cell data as long as / c ? a / s remains low (regardless of ? w / e or / r ? a / s). this late ? w / e pulse results in a read write cycle. the four data inputs and four data outputs are routed through four pins using common i/o and pin direction is controlled by ? w / e and ? o / e. fast page mode operations allow faster data opera- tions (read, write or read-modify-write) within a row-address-defined (a0 -a8) page boundary. the fast page mode cycle is always initiated with a row-address strobed-in by / r ? a / s followed by a column-address strobed- 20/26-pin soj (dc-1) dq1 dq2 we ras nc a0 a1 a2 a3 vcc vss dq4 dq3 cas oe a8 a7 a6 a5 a4 1 2 3 4 5 9 10 11 12 13 26 25 24 23 22 18 17 16 15 14 20-pin dip (da-2) 20-pin zip (db-1) dq1 dq2 we ras nc a0 a1 a2 a3 vcc 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 vss dq4 dq3 cas oe a8 a7 a6 a5 a4 oe dq3 vss dq2 ras a0 a2 vcc a5 a7 cas dq4 dq1 we nc a1 a3 a4 a6 a8 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20
MT4C4256(l) micron semiconductor, inc., reserves the right to change products or specifications without notice. rev. 4/94 ? 1994, micron semiconductor, inc. 2 MT4C4256(l) 256k x 4 dram obsolete in by / c ? a / s. / c ? a / s may be toggled-in by holding / r ? a / s low and strobing-in different column-addresses, thus execut- ing faster memory cycles. returning / r ? a / s high terminates the fast page mode cycle. returning / r ? a / s and / c ? a / s high terminates a memory cycle and decreases chip current to a reduced standby level. also, the chip is preconditioned for the next cycle during the / r ? a / s high time. memory cell data is retained in its correct state by maintaining power and executing any / r ? a / s cycle (read, write) or / r ? a / s refresh cycle ( / r ? a / s only, cbr, or hidden) so that all 512 combinations of / r ? a / s addresses (a0 -a8) are executed at least every 8ms for the MT4C4256 and every 64ms for the MT4C4256 l, regardless of sequence. the cbr refresh cycle will invoke the internal refresh counter for automatic / r ? a / s addressing. functional block diagram fast page mode a0 a1 a2 a3 a4 a5 a6 a7 a8 ras 9 9 9 no. 2 clock generator refresh controller no. 1 clock generator vcc vss 9 refresh counter we cas 9 *early write detection circuit column- address buffer(9) row- address buffers (9) 512 oe dq1 dq2 dq3 dq4 4 4 4 4 512 512 512 complement select row decoder row select (1 of 512) column decoder data-out buffer data-in buffer 512 sense amplifiers i/o gating 512 x 512 x 4 memory array *note: 1. if ? w / e goes low prior to / c / a / s going low, ew detection circuit output is a high (early write). 2. if / c / a / s goes low prior to ? w / e going low, ew detection circuit output is a low (late write).
MT4C4256(l) micron semiconductor, inc., reserves the right to change products or specifications without notice. rev. 4/94 ? 1994, micron semiconductor, inc. 3 MT4C4256(l) 256k x 4 dram obsolete truth table addresses data-in/out function ? r ? a / s ? c ? a / s ? w / e ? o / e t r t c dq1-dq4 standby h h > xxxxx high-z read l l h l row col data-out early write l l l x row col data-in read write l l h > ll > h row col data-out, data-in fast-page-mode 1st cycle l h > l h l row col data-out read 2nd cycle l h > l h l n/a col data-out fast-page-mode 1st cycle l h > l l x row col data-in early-write 2nd cycle l h > l l x n/a col data-in fast-page-mode 1st cycle l h > lh > ll > h row col data-out, data-in read-write 2nd cycle l h > lh > ll > h n/a col data-out, data-in / r ? a / s only refresh l h x x row n/a high-z hidden read l > h > l l h l row col data-out refresh write l > h > l l l x row col data-in cbr refresh h > llxxxx high-z extended refresh h > llxxxx high-z (MT4C4256 l only)
MT4C4256(l) micron semiconductor, inc., reserves the right to change products or specifications without notice. rev. 4/94 ? 1994, micron semiconductor, inc. 4 MT4C4256(l) 256k x 4 dram obsolete absolute maximum ratings* voltage on any pin relative to v ss .................... -1v to +7v operating temperature, t a (ambient) .......... 0 c to +70 c storage temperature (plastic) .................... -55 c to +150 c power dissipation ............................................................. 1w short circuit output current ..................................... 50ma *stresses greater than those listed under absolute maxi- mum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indi- cated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. parameter/condition version symbol -6 -7 -8 units notes standby current: (ttl) i cc 1 222ma ( / r ? a / s = / c ? a / s = v ih ) standby current: (cmos) MT4C4256 i cc 2 111ma ( / r ? a / s = / c ? a / s = v cc -0.2v) MT4C4256 l i cc 2 200 200 200 m a operating current: random read/write average power supply current i cc 3 90 80 70 ma 3, 4, ( / r ? a / s, / c ? a / s, single address cycling: t rc = t rc [min]) 29 operating current: fast page mode average power supply current i cc 4 70 60 50 ma 3, 4, ( / r ? a / s = v il , / c ? a / s, address cycling: t pc = t pc [min]) 29 refresh current: / r ? a / s only average power supply current i cc 5 90 80 70 ma 3, 29 ( / r ? a / s cycling, / c ? a / s = v ih : t rc = t rc [min]) refresh current: cbr average power supply current i cc 6 90 80 70 ma 3, 5 ( / r ? a / s, / c ? a / s, address cycling: t rc = t rc [min]) refresh current: extended average power supply current during extended refresh: / c ? a / s = 0.2v or cbr cycling; / r ? a / s = t ras (min) to1 m s; MT4C4256 l i cc 7 200 200 200 m a 3, 5, ?/ w / e, a0-a8 and d in = vcc -0.2v or 0.2v (d in may be 27 left open); t rc = 125 m s (512 rows at 125 m s = 64ms) max dc electrical characteristics and recommended dc operating conditions (notes: 1, 6, 7) (v cc = +5v 10%) parameter/condition symbol min max units notes supply voltage v cc 4.5 5.5 v input high (logic 1) voltage, all inputs v ih 2.4 v cc +1 v input low (logic 0) voltage, all inputs v il -1.0 0.8 v input leakage current any input 0v v in 6.5v i i -2 2 m a (all other pins not under test = 0v) output leakage current: (q is disabled; 0v v out 5.5v) i oz -10 10 m a output levels v oh 2.4 v output high voltage (i out = -5ma) output low voltage (i out = 4.2ma) v ol 0.4 v
MT4C4256(l) micron semiconductor, inc., reserves the right to change products or specifications without notice. rev. 4/94 ? 1994, micron semiconductor, inc. 5 MT4C4256(l) 256k x 4 dram obsolete capacitance parameter symbol min max units notes input capacitance: a0-a8 c i 1 5pf2 input capacitance: / r ? a / s, / c ? a / s, ? w / e, / o / ec i 2 7pf2 input/output capacitance: dq c io 7pf2 electrical characteristics and recommended ac operating conditions (notes: 6, 7, 8, 9, 10, 11, 12, 13, 23) (v cc = +5v 10%) ac characteristics -6 -7 -8 parameter sym min max min max min max units notes random read or write cycle time t rc 110 130 150 ns read write cycle time t rwc 165 185 205 ns fast-page-mode t pc 35 40 45 ns read or write cycle time fast-page-mode t prwc 90 95 100 ns read-write cycle time access time from / r ? a / s t rac 60 70 80 ns 14 access time from / c ? a / s t cac 20 20 20 ns 15 output enable t oe 20 20 20 ns access time from column-address t aa 30 35 40 ns access time from / c ? a / s precharge t cpa 35 40 45 ns / r ? a / s pulse width t ras 60 100,000 70 100,000 80 100,000 ns / r ? a / s pulse width (fast page mode) t rasp 60 100,000 70 100,000 80 100,000 ns / r ? a / s hold time t rsh 20 20 20 ns / r ? a / s precharge time t rp 40 50 60 ns / c ? a / s pulse width t cas 20 100,000 20 100,000 20 100,000 ns / c ? a / s hold time t csh 60 70 80 ns / c ? a / s precharge time t cpn 10 10 10 ns 16 / c ? a / s precharge time (fast page mode) t cp 10 10 10 ns / r ? a / s to / c ? a / s delay time t rcd 20 40 20 50 20 60 ns 17 / c ? a / s to / r ? a / s precharge time t crp 5 5 5 ns row-address setup time t asr 0 0 0 ns row-address hold time t rah 10 10 10 ns / r ? a / s to column- t rad 15 30 15 35 15 40 ns 18 address delay time column-address setup time t asc 0 0 0 ns column-address hold time t cah 15 15 15 ns column-address hold time t ar 45 55 60 ns (referenced to / r ? a / s) column-address to t ral 30 35 40 ns / r ? a / s lead time read command setup time t rcs 0 0 0 ns read command hold time t rch 0 0 0 ns 19 (referenced to / c ? a / s) read command hold time t rrh 0 0 0 ns 19 (referenced to / r ? a / s) / c ? a / s to output in low-z t clz 0 0 0 ns
MT4C4256(l) micron semiconductor, inc., reserves the right to change products or specifications without notice. rev. 4/94 ? 1994, micron semiconductor, inc. 6 MT4C4256(l) 256k x 4 dram obsolete electrical characteristics and recommended ac operating conditions (notes: 6, 7, 8, 9, 10, 11, 12, 13, 23) (vcc = +5v 10%) ac characteristics -6 -7 -8 parameter sym min max min max min max units notes output buffer turn-off delay t off 3 20 3 20 3 20 ns 20, 26, 28 output disable t od 15 20 20 ns 26 ? w / e command setup time t wcs 0 0 0 ns 21 write command hold time t wch 10 15 15 ns write command hold time t wcr 45 55 60 ns (referenced to / r ? a / s) write command pulse width t wp 10 15 15 ns write command to / r ? a / s lead time t rwl 20 20 20 ns write command to / c ? a / s lead time t cwl 20 20 20 ns data-in setup time t ds 0 0 0 ns 22 data-in hold time t dh 15 15 15 ns 22 data-in hold time t dhr 45 55 60 ns (referenced to / r ? a / s) / r ? a / s to ? w / e delay time t rwd 85 100 110 ns 21 column-address t awd 60 65 70 ns 21 to ? w / e delay time / c ? a / s to ? w / e delay time t cwd 40 50 55 ns 21 transition time (rise or fall) t t 3 50 3 50 3 50 ns 9, 10 refresh period (512 cycles) MT4C4256 / MT4C4256 l t ref 8 / 64 8 / 64 8 / 64 ms / r ? a / s to / c ? a / s precharge time t rpc 0 0 0 ns / c ? a / s setup time (cbr refresh) t csr 10 10 10 ns 5 / c ? a / s hold time (cbr refresh) t chr 10 15 15 ns 5 ? o / e hold time from ? w / e during t oeh 15 20 20 ns 25 read-modify-write cycle ? o / e setup prior to / r ? a / s during t ord 0 0 0 ns 24 hidden refresh cycle
MT4C4256(l) micron semiconductor, inc., reserves the right to change products or specifications without notice. rev. 4/94 ? 1994, micron semiconductor, inc. 7 MT4C4256(l) 256k x 4 dram obsolete notes 1. all voltages referenced to v ss . 2. this parameter is sampled. v cc = 5v 10%; f = 1 mhz. 3. i cc is dependent on cycle rates. 4. i cc is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time and the outputs open. 5. enables on-chip refresh and address counters. 6. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is assured. 7. an initial pause of 100 m s is required after power-up followed by any eight / r ? a / s cycles before proper device operation is assured. the eight / r ? a / s cycle wake-ups should be repeated any time the t ref refresh requirement is exceeded. 8. ac characteristics assume t t = 5ns. 9. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih and v il (or between v il and v ih ). 10. in addition to meeting the transition rate specifica- tion, all input signals must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 11. if / c ? a / s = v ih , data output is high-z. 12. if / c ? a / s = v il , data output may contain data from the last valid read cycle. 13. measured with a load equivalent to two ttl gates and 100pf. 14. assumes that t rcd < t rcd (max). if t rcd is greater than the maximum recommended value shown in this table, t rac will increase by the amount that t rcd exceeds the value shown. 15. assumes that t rcd 3 t rcd (max). 16. if / c ? a / s is low at the falling edge of / r ? a / s, q will be maintained from the previous cycle. to initiate a new cycle and clear the data-out buffer, / c ? a / s must be pulsed high for t cpn. 17. operation within the t rcd (max) limit ensures that t rac (max) can be met. t rcd (max) is specified as a reference point only; if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac. 18. operation within the t rad (max) limit ensures that t rac (min) and t cac (min) can be met. t rad (max) is specified as a reference point only; if t rad is greater than the specified t rad (max) limit, then access time is controlled exclusively by t aa. 19. either t rch or t rrh must be satisfied for a read cycle. 20. t off (max) defines the time at which the output achieves the open circuit condition and is not referenced to v oh or v ol . 21. t wcs, t rwd, t awd and t cwd are not restrictive operating parameters. t wcs applies to early write cycles. t rwd, t awd and t cwd apply to read-modify-write cycles. if t wcs 3 t wcs (min), the cycle is an early write cycle, and the data output will remain an open circuit throughout the entire cycle. if t rwd 3 t rwd (min), t awd 3 t awd (min) and t cwd 3 t cwd (min), the cycle is a read-modify-write cycle, and the data output will contain data read from the selected cell. if neither of the above conditions is met, the state of data-out is indeterminate. / o / e held high and ? w / e taken low after / c ? a / s goes low results in a late write ( ? o / e-controlled) cycle. t wcs, t rwd, t cwd and t awd are not applicable in a late write cycle. 22. these parameters are referenced to / c ? a / s leading edge in early write cycles and ? w / e leading edge in late write or read-modify-write cycles. 23. if / o / e is tied permanently low, late write or read-modify-write operations are not possible. 24. a hidden refresh may also be performed after a write cycle. in this case, ? w / e = low and ?/ o / e = high. 25. late write and read-modify-write cycles must have both t od and t oeh met ( ? o / e high during write cycle) in order to ensure that the output buffers will be open during the write cycle. if ? o / e is taken back low while / c ? a / s remains low, the dqs will remain open. 26. the dqs open during read cycles once t od or t off occur. if ? c ? a / s goes high before ? o / e, the dqs will open regardless of the state of ? o / e. if ? c ? a / s stays low while ? o / e is brought high, the dqs will open. if ? o / e is brought back low ( ? c ? a / s still low), the dqs will provide the previously read data. 27. extended refresh current is reduced as t ras is reduced from its maximum specification during the extended refresh cycle. 28. the 3ns minimum is a parameter guaranteed by design. 29. column-address changed once each cycle.
MT4C4256(l) micron semiconductor, inc., reserves the right to change products or specifications without notice. rev. 4/94 ? 1994, micron semiconductor, inc. 8 MT4C4256(l) 256k x 4 dram obsolete read cycle t rrh t clz t cac t rac t aa valid data open t off t rch row t rcs t asc t rah t rad t ar t cah t ral t rcd t cas t rsh t csh t rp t rc t ras t crp t asr row open ras v v ih il cas v v ih il addr v v ih il dq v v ioh iol v v ih il t od t oe oe v v ih il column we early write cycle don? care undefined v v ih il cas valid data row column row t ds t dh t dhr t wp t wch t wcs t wcr t rwl t cwl t cah t asc t rah t asr t rad t ral t ar t cas t rsh t csh t rcd t crp t ras t rc t rp v v ih il addr v v ih il we v v ih il dq v v ioh iol ras oe v v ih il
MT4C4256(l) micron semiconductor, inc., reserves the right to change products or specifications without notice. rev. 4/94 ? 1994, micron semiconductor, inc. 9 MT4C4256(l) 256k x 4 dram obsolete read write cycle (late write and read-modify-write cycles) fast-page-mode read cycle valid d out valid d in row column row v v ih il cas v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras open open t oe t od t cac t rac t aa t clz t ds t dh t awd t wp t rwl t cwl t cwd t rwd t rcs t asc t cah t ar t asr t rad t ral t crp t rcd t cas t rsh t csh t ras t rwc t rp t rah oe t oeh we valid data valid data valid data column column column row row t rcs t cah t asc t ral t cpn t cas t rsh t cp t cas t cp t cas t rcd t crp t pc t csh t rasp t rp t cah t asc t cah t asc t ar t rah t rad t asr t rcs t rch t rch t rcs t rrh t rch t off t cac t cpa t aa t clz t off t cac t cpa t aa t clz t off t cac t rac t aa t clz t oe t od t oe t od t oe t od open open v v ih il cas v v ih il addr v v ih il we v v ih il dq v v ioh iol v v ih il ras oe don?t care undefined
MT4C4256(l) micron semiconductor, inc., reserves the right to change products or specifications without notice. rev. 4/94 ? 1994, micron semiconductor, inc. 10 MT4C4256(l) 256k x 4 dram obsolete fast-page-mode early-write cycle fast-page-mode read-write cycle (late write and read-modify-write cycles) don? care undefined t oe t oe t oe open d out valid d in valid d out valid d in valid d out valid d in valid open t dh t ds t aa t cpa t clz t cac t dh t ds t aa t cpa t clz t cac t dh t ds t aa t clz t cac t rac t wp t cwl t rwl t cwd t awd t wp t cwl t cwd t awd t wp t cwl t cwd t awd t rcs t rwd t asr t rah t asc t rad t ar t cah t asc t cah t asc t cah t ral t cp t cas t rsh t cpn t rp t rasp t cas t cp t cas t rcd t csh t pc t crp row column column column row v v ih il cas v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras oe we t prwc t oeh t od t od t od * t ds t dh t ds t dh t ds t dh t dhr t wcr valid data valid data valid data t rwl t wp t cwl t wch t wcs t wp t cwl t wch t wcs t wp t cwl t wch t wcs t cah t asc t ral t cah t asc t cah t asc t rah t asr t rad t ar column column column row row t cpn t cas t rsh t cp t cas t cp t cas t rcd t crp t pc t csh t rasp t rp v v ih il cas v v ih il addr v v ih il we v v ih il dq v v ioh iol ras oe v v ih il * t pc is for late write only.
MT4C4256(l) micron semiconductor, inc., reserves the right to change products or specifications without notice. rev. 4/94 ? 1994, micron semiconductor, inc. 11 MT4C4256(l) 256k x 4 dram obsolete note: 1. do not drive data prior to tristate: t cpp(min) or t cp(whichever is greater) + t ds(min) + any guardband between data-out and driving the bus with the new data-in. row v v ih il cas v v ih il addr v v ih il ras t rc t ras t rp t crp t asr t rah row open dq v v oh ol t rpc // // / r ?? ?? ? a // // / s only refresh cycle (addr = a0-a8; ? w / e = dont care) fast-page-mode read-early-write cycle (pseudo read-modify-write) row valid data valid data open open t crp t rcd t cas t rsh t rasp t rp t pc t asc t cah t ar t asr t rad t rah t wcs t wp t rwl t rcs t dh t ds t cac t off v v ih il cas v v ih il addr v v ih il ras d v v ih il q v v oh ol we v v ih il t csh column t cpp t cpn t asc t cah t ral t cwl t wch t clz t aa rac don?t care undefined t note 1 oe v v ih il row column t cas
MT4C4256(l) micron semiconductor, inc., reserves the right to change products or specifications without notice. rev. 4/94 ? 1994, micron semiconductor, inc. 12 MT4C4256(l) 256k x 4 dram obsolete don? care undefined t clz t off open valid data open column row (read) (refresh) t cac t rac t aa t cah t asc t rah t asr t rad t ar t ral t crp t rcd t rsh t ras t rp t chr t ras dq v v ioh iol v v ih il addr v v ih il cas v v ih il ras v v ih il t oe t od oe t ord cbr refresh cycle (a0-a8, ? w / e and / o / e = dont care) hidden refresh cycle 24 ( ? w / e = high; / o / e = low) extended refresh cycle (MT4C4256 l only) (a0-a8, ? w / e and / o / e = dont care) t rp v v ih il ras t ras open t chr t csr v v ih il cas v v oh ol dq t rp t ras t rpc t csr t rpc t chr t cpn t rp v v ih il ras t ras open t chr t csr v v ih il cas v v oh ol dq t rp t ras t rpc t csr t rpc t chr t cpn 125?
MT4C4256(l) micron semiconductor, inc., reserves the right to change products or specifications without notice. rev. 4/94 ? 1994, micron semiconductor, inc. 13 MT4C4256(l) 256k x 4 dram obsolete 20-pin plastic dip (300 mil) .062 (1.57) .014 (0.36) .008 (0.20) .016 (0.41) seating plane pin #1 index .330 (8.38) .330 (8.38) .380 (9.65) .155 (3.94) .170 (4.32) .120 (3.05) .140 (3.56) .050 (1.27) .900 (22.86) typ .021 (0.53) .100 (2.54) typ .145 (3.68) .135 (3.43) .310 (7.87) .291 (7.39) .285 (7.24) .973 (24.71) .967 (24.56) pin 1 note: 1. all dimensions in inches (millimeters) max or typical where noted. min 2. package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.
MT4C4256(l) micron semiconductor, inc., reserves the right to change products or specifications without notice. rev. 4/94 ? 1994, micron semiconductor, inc. 14 MT4C4256(l) 256k x 4 dram obsolete 20-pin plastic zip (350 mil) .014 (0.36) .008 (0.20) .107 (2.72) .113 (2.87) .100 (2.54) .140 (3.56) .075 (1.91) .045 (1.14) .432 (10.97) .508 (12.90) .024 (0.61) .016 (0.41) .015 (0.38) .040 (1.07) .050 (1.27) typ .950 (24.13) seating plane pin #1 index .050 (1.27) .332 (8.43) .368 (9.35) .293 (7.44) .287 (7.29) .993 (25.22) .999 (25.37) 45 .106 (2.69) .128 (3.25) note: 1. all dimensions in inches (millimeters) max or typical where noted. min 2. package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.
MT4C4256(l) micron semiconductor, inc., reserves the right to change products or specifications without notice. rev. 4/94 ? 1994, micron semiconductor, inc. 15 MT4C4256(l) 256k x 4 dram obsolete 20/26-pin plastic soj (300 mil) seating plane .040 (1.02) .030 (0.76) .275 (6.99) .260 (6.60) .080 (2.03) .095 (2.41) .142 (3.61) .132 (3.35) .015 (0.38) .020 (0.51) pin #1 index .600 (15.24) typ .050 (1.27) typ .330 (8.38) .340 (8.64) .673 (17.09) .679 (17.25) .305 (7.75) .299 (7.59) r .025 (0.64) min .037 (0.94) max dambar protrusion .026 (0.66) .032 (0.81) note: 1. all dimensions in inches (millimeters) max or typical where noted. min 2. package width and length do not include mold protrusion; allowable mold protrusion is .01" per side. 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.micron.com, customer comment line: 800-932-4992 micron is a registered trademark of micron technology, inc.

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