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preliminary data this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. january 2006 rev1.0 1/23 2 NAND01G-N 1 gbit (x8/x16) 2112 byte page nand flash memory and 512 mbit (x16) lpsdram, 1.8v, multi-chip package features summary multi-chip package ? nand flash memory ? 512 mbit or 1 gbit (x8/x16) large page size nand flash memory ? 512 mbit (x16) sdr or ddr lpsdram temperature range ? -30 up to 85 c supply voltage ? nand flash : v ddf = 1.7v to 1.95v ?lpsdram: v ddd = v ddqd = 1.7v to 1.9v electronic signature ecopack ? packages flash memory nand interface ? x8 or x16 bus width ? multiplexed address/data page size ? x8 device: (2048 + 64 spare) bytes ? x16 device: (1024 + 32 spare) words block size ? x8 device: (128k + 4k spare) bytes ? x16 device: (64k + 2k spare) words page read/program ? random access: 25s (max) ? sequential access: 50ns (min) ? page program time: 300s (typ) copy back program mode ? fast page copy without external buffering fast block erase ? block erase time: 2ms (typ) chip enable ?don?t care? ? for simple interfacing with microcontrollers status register sdr/ddr lpsdram interface: x16 bus width programmable partial array self refresh auto temperature compensated self refresh deep power down mode 1.8v lvcmos interface quad internal banks controlled by ba0 and ba1 wrap sequence: sequential/interleaved automatic and controlled precharge auto refresh and self refresh 8,192 refresh cycles/64ms burst termination by burst stop command and precharge command fbga tfbga107 10.5 x 13 x 1.2mm tfbga149 10 x 13.5 x 1.2mm www.st.com
NAND01G-N 2/23 rev1.0 table 1. product list reference part number nand product lpsdram product (1) package NAND01G-N nand01gr3n6 1gbit 1.8v (x8) sdr 512mbit (x16) 1.8v, 133mhz tfbga107 nand01gr4n5 1gbit 1.8v (x16) ddr 512mbit (x16) 1.8v, 133 mhz tfbga149 1. sdr = single data rate; ddr = double data rate.
NAND01G-N contents rev1.0 3/23 contents 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 nand flash component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 lpsdram component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 flash memory inputs/outputs (i/o0-i/o7) . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 flash memory inputs/outputs (i/o8-i/o15) . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 flash memory address latch enable (al) . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 flash memory command latch enable (cl) . . . . . . . . . . . . . . . . . . . . . . 12 2.5 flash memory chip enable (ef) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.6 flash memory read enable (r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.7 flash memory write enable (wf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.8 flash memory write protect (wp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.9 flash memory ready/busy (rb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.10 flash memory v ddf supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.11 flash memory v ssf ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.12 lpsdram address inputs (a0-a12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.13 lpsdram bank select address inputs (ba0-ba1) . . . . . . . . . . . . . . . . . 14 2.14 lpsdram data inputs/outputs (dq0-dq15) . . . . . . . . . . . . . . . . . . . . . 14 2.15 lpsdram chip select (ed) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.16 lpsdram column address strobe (cas) . . . . . . . . . . . . . . . . . . . . . . . 14 2.17 lpsdram row address strobe (ras) . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.18 lpsdram write enable (wd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.19 lpsdram clock input (k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.20 lpsdram clock input (k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.21 lpsdram clock enable (ke) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.22 lpsdram lower/upper data input/output mask (dqm0, dqm1) . . . . . 15 2.23 lower/upper data read/write strobe input/output (ldqs, udqs) . . . . 15 2.24 lpsdram v ddd supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.25 lpsdram v ddqd supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.26 lpsdram v ssd ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
contents NAND01G-N 4/23 rev1.0 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
NAND01G-N list of tables rev1.0 5/23 list of tables table 1. product list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 table 2. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 4. tfbga107 10.5x13mm - 10x14 active ball array, 0.80mm pitch, mechanical data . . . . . . 19 table 5. tfbga149 10x13.5mm - 12x16 active ball array, 0.80mm pitch, mechanical data . . . . . . 20 table 6. ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 7. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
list of figures NAND01G-N 6/23 rev1.0 list of figures figure 1. logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. tfbga107 connections, x16 bus width (top view through package) . . . . . . . . . . . . . . . . 10 figure 3. tfbga149 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4. functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 5. tfbga107 10.5x13mm - 10x14 active ball array, 0.80mm pitch, package outline . . . . . . 19 figure 6. tfbga149 10x13.5mm - 12x16 active ball array, 0.80mm pitch, package outline . . . . . . 20
NAND01G-N summary description rev1.0 7/23 1 summary description the NAND01G-N is a family that combine two memory devices in a multi-chip package: a 1 gbit nand flash memory and 512 mbit lpsdram with 2kbyte pages. the nand flash memory and lpsdram components have separate power supplies and grounds. they also have separate control, address and input/output signals, which allows simultaneous access to both devices at any moment. they are distinguished by two chip enable inputs: e f for the nand flash memory and e d for the lpsdram. the multi-chip packages are available with a 1.8v supply. see ta b l e 1 for a complete list of the products available. all devices are stacked and are offered in: tfbga107 (10.5 x 13 x 1.2mm) tfbga149 (10 x 13.5 x 1.2mm) they are supplied with all the nand flash memory bits erased (set to ?1?). this datasheet should be read in conjunction with the nand flash and lpsdram datasheets. nand flash component NAND01G-N devices contain a 1 gbit (x8/x16) 2112 byte/1056 word page, nand flash memory. for detailed information on how to use the devices, see the nandxxx-b datasheet which is available from your local stmicroelectronics distributor. lpsdram component NAND01G-N devices contain a 512 mbit (x16) lpsdram. for detailed information on how to use the devices, see: m65ka512ab: sdr 512mb (x16) m65kg512ab: ddr 512mb (x16) all above st datasheets available from st divisional marketing.
summary description NAND01G-N 8/23 rev1.0 figure 1. logic diagram 1. available on nand01gr4n5 only. ai10142d 13 a0-a12 dq0-dq15 v ssqd k ke w d v ddqd e d cas dqm1 dqm0 v ssf v ddf w f i/o8-i/o15, x16 (1) i/o0-i/o7, x8/x16 v ddd NAND01G-N e f v ssd wp al cl rb r ras 2 ba0-ba1 k (1) udqs-ldqs (1)
NAND01G-N summary description rev1.0 9/23 table 2. signal names nand flash memory i/o0-i/o7 data input/outputs for x8 and x16 devices i/o8-i/o15 data inputs/outputs for x16 devices al address latch enable cl command latch enable e f chip enable r read enable rb ready/busy (open-drain output) w f write enable wp write protect v ddf supply voltage v ssf ground lpsdram a0-a12 address inputs a10 determines the precharge mode. ba0-ba1 bank select inputs dq0-dq15 data inputs/outputs udqs-ldqs (1) 1. available on nand01gr4n5 only. data strobe inputs/outputs k clock input k (1) clock input ke clock enable input e d chip select inputs w d write enable input ras row address strobe input cas column address strobe input dqm0 dq mask enable input (controls dq0-dq7) dqm1 dq mask enable input (controls dq8-dq15) v ddd supply voltage v ddqd input/output supply voltage v ssd ground v ssqd input/output ground nc not connected internally du do not use
summary description NAND01G-N 10/23 rev1.0 figure 2. tfbga107 connections, x16 bus width (top view through package) ai10143c v ddd a8 dqm1 nc v ssd ke a12 dqm0 h a9 d r c dq4 a1 b nc a3 a 8 7 6 5 4 3 2 1 v ssd v ddqd g f e v ddqd du wp a0 ba0 dq6 v ssqd cas a11 nc w f ba1 a10 du v ddd v ssd 9 nc a2 e d m l k j du dq15 nc nc dq11 nc i/o6 v ddqd v ssqd nc dq9 nc i/o5 dq13 v ddd nc nc v ssf v ddf a7 i/o4 i/o7 a5 du du v ssqd a4 du p n 10 nc rb dq2 nc nc e f nc i/o3 nc v ddf i/o2 nc cl al dq0 v ssf nc i/o1 nc v ssd i/o0 k nc dq1 dq3 dq5 dq7 v ddd dq10 dq12 dq14 v ssf dq8 du du du du a6 w d nc ras v ddf nc nc
NAND01G-N summary description rev1.0 11/23 figure 3. tfbga149 connections (top view through package) ai11007c dqm1 ke a11 dqm0 h a9 d r c dq4 a1 b a3 a 8 7 6 5 4 3 2 1 g f e du wp a0 ba0 dq6 cas w f ba1 du v ddd 9 nc a7 e d m l k j du dq15 nc dq13 v ssf i/o0 i/o7 du du v ssqd du p n 12 nc rb dq2 nc nc e f i/o2 nc cl al dq0 v ssd i/o1 k dq1 dq3 dq5 dq7 v ddd dq10 v ssd dq8 du du du du wd nc ras v ddf nc nc nc a10 du a8 du nc du nc v ddqd nc du du du du du du du du du du du du du du 10 11 t r nc du v ssd v ddd du nc i/o6 i/o5 a6 a12 nc nc a2 a5 i/o4 nc nc a4 nc v ddf v ssf nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc i/o3 nc dq11 dq14 dq12 dq9 v ddqd v ssd i/o9 i/o8 i/o15 i/o14 i/o13 i/o10 i/o12 i/o11 ldqs udqs k
signals description NAND01G-N 12/23 rev1.0 2 signals description see figure 1 in conjunction with ta b l e 2 , for a brief overview of the signals connected to this device. for extra details on the signals, refer to the nand flash and the lpsdram datasheets. 2.1 flash memory inputs/outputs (i/o0-i/o7) input/outputs 0 to 7 are used by the nand flash memory to input the selected address, output the data during a read operation or input a command or data during a write operation. the inputs are latched on the rising edge of write enable. i/o0-i/o7 are left floating when the nand flash memory is deselected or the outputs are disabled. 2.2 flash memory inputs/outputs (i/o8-i/o15) input/outputs 8 to 15 are only available in x16 nand flash devices. they are used to output the data during a read operation or input data during a write operation. command and address inputs only require i/o0 to i/o7. the inputs are latched on the rising edge of write enable. i/o8-i/o15 are left floating when the device is deselected or the outputs are disabled. 2.3 flash memory address latch enable (al) the address latch enable activates the latching of the address inputs in the command interface of the nand flash memory. when al is high, the inputs are latched on the rising edge of write enable. 2.4 flash memory command latch enable (cl) the command latch enable activates the latching of the command inputs in the command interface of the nand flash memory. when cl is high, the inputs are latched on the rising edge of write enable. 2.5 flash memory chip enable (e f ) the nand flash memory chip enable input activates the memory control logic, input buffers, decoders and sense amplifiers. when chip enable is low, v il , the nand flash memory device is selected. if chip enable goes high, v ih , while the nand flash memory is busy, the device remains selected and does not go into standby mode.
NAND01G-N signals description rev1.0 13/23 2.6 flash memory read enable (r ) the nand flash memory read enable pin, r , controls the sequential data output during read operations. the falling edge of r also increments the internal column address counter by one. 2.7 flash memory write enable (w f ) the nand flash memory write enable input, w , controls writing to the command interface, input address and data latches. both addresses and data are latched on the rising edge of write enable. 2.8 flash memory write protect (wp ) the write protect pin is a nand flash memory input that gives a hardware protection against unwanted program or erase operations. when write protect is low, v il , the nand flash memory device does not accept any program or erase operations. it is recommended to keep the write protect pin low, v il , during power-up and power-down. 2.9 flash memory ready/busy (rb ) the ready/busy output, rb , is an open-drain nand flash memory output that can be used to identify if the p/e/r controller is currently active. when ready/busy is low, v ol , a read, program or erase operation is in progress. when the operation completes ready/busy goes high, v oh . the use of an open-drain output allows the ready/busy pins from several memories to be connected to a single pull-up resistor. a low will then indicate that one, or more, of the memories is busy. 2.10 flash memory v ddf supply voltage v ddf provides the power supply to the internal core of the nand flash memory device. it is the main power supply for all operations (read, program and erase). 2.11 flash memory v ssf ground ground, v ssf, is the reference for the power supply for the nand flash memory. it must be connected to the system ground.
signals description NAND01G-N 14/23 rev1.0 2.12 lpsdram address inputs (a0-a12) the a0-a12 address inputs are used by the lpsdram to select the row or column to be made active. if a row is selected, all thirteen, a0-a12 address inputs are used. if a column is selected, only the nine least significant address inputs, a0-a8, are used. in this latter case, a10 determines whether auto precharge is used. if a10 is high (set to ?1?) during read or write, the read or write operation includes an auto precharge cycle. if a10 is low (set to ?0?) during read or write, the read or write cycle does not include an auto precharge cycle. 2.13 lpsdram bank select address inputs (ba0-ba1) the ba0 and ba1 banks select address inputs are used by the lpsdram to select the bank to be made active. the lpsdram must be enabled, the row address strobe, ras , must be low, v il , the column address strobe, cas , and w must be high, v ih , when selecting the addresses. 2.14 lpsdram data inputs/outputs (dq0-dq15) on the lpsdram, dq0-dq15 output the data stored at the selected address during a read operation, or are used to input the data during a write operation. 2.15 lpsdram chip select (e d ) the chip select input e activates the lpsdram state machine, address buffers and decoders when driven low, v il . when high, v ih the device is not selected. 2.16 lpsdram column address strobe (cas ) the column address strobe, cas , is used in conjunction with address inputs a8-a0 and ba1-ba0, to select the starting column location prior to a read or write. 2.17 lpsdram row address strobe (ras ) the row address strobe, ras , is used in conjunction with address inputs a11-a0 and ba1-ba0, to select the starting address location prior to a read or write. 2.18 lpsdram write enable (w d ) the lpsdram write enable input, w , controls writing to the lpsdram.
NAND01G-N signals description rev1.0 15/23 2.19 lpsdram clock input (k) the clock signal, k, is used to clock the read and write cycles on the lpsdram. during normal operation, the clock enable pin, ke, is high, v ih . the clock signal k can be suspended to switch the device to the self-refresh, power-down or deep power-down mode by driving ke low, v il . 2.20 lpsdram clock input (k ) the clock signal, k , is only available on the ddr lpsdram. it is used in conjunction with the clock signal, k. all lpsdram input signals except dqm0/dqm1, udqs/ldqs and dq0-dq15 are referred to the cross point of k rising edge and k falling edge. 2.21 lpsdram clock enable (ke) the clock enable, ke, pin is used by the lpsdram to control the synchronizing of the signals with clock signal k (and k on ddr lpsdram). if ke is high, v ih , the next clock rising edge is valid. when ke is low, v il , the signals are no longer clocked and data read and write cycles are extended. ke is also involved in switching the device to the self- refresh, power-down and deep power-down modes. 2.22 lpsdram lower/upper data input/output mask (dqm0, dqm1) data mask enable inputs are used to mask the read or write data. 2.23 lower/upper data read/write strobe input/output (ldqs, udqs) ldqs and udqs are only available on the ddr lpsdram. they can be either input or output signals and act as write data strobe and read data strobe respectively. ldqs and udqs are the strobe signals for dq0 to dq7 and dq8 to dq15, respectively. 2.24 lpsdram v ddd supply voltage v ddd provides the power supply to the internal core of the lpsdram. it is the main power supply for all operations (read and write).
signals description NAND01G-N 16/23 rev1.0 2.25 lpsdram v ddqd supply voltage v ddqd provides the power supply to the i/o pins of the lpsdram and enables all outputs to be powered independently of v ddd . v ddqd can be tied to v ddd or can use a separate supply. it is recommended to power-up and power-down v ddd and v ddqd together to avoid certain conditions that would result in data corruption. 2.26 lpsdram v ssd ground ground, v ssd, is the reference for the core power supply for the lpsdram. it must be connected to the system ground.
NAND01G-N functional description rev1.0 17/23 3 functional description the nand flash memory and lpsdram components have separate power supplies and grounds. they also have separate control signals, addresses and data input/outputs, which allows simultaneous access to both devices at any moment. figure 4. functional block diagram 1. available on root part number 2 only. v ssd wp 1 gbit nand flash memory v ddf al w d cas ras lpsdram v ddd dqm0 dqm1 ba0-ba1 ai12401 e d i/o0-i/o7 cl e f r w f i/o8-i/o15 rb v ssf v ddqd a0-a12 k k (1) ke v ssqd dq0-dq15 ldqs-udqs (1)
maximum rating NAND01G-N 18/23 rev1.0 4 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 3. absolute maximum ratings symbol parameter value unit min max t a ambient operating temperature -30 85 c t bias temperature under bias (1) tbd tbd c t stg storage temperature -55 125 c v io nand flash input or output voltage 1.8v -0.6 2.7 v lpsdram input or output voltage 1.8v -1.0 2.6 v v ddf nand flash supply voltage 1.8v -0.6 2.7 v v ddd , v ddqd lpsdram supply voltage 1.8v -1.0 2.6 v lpsdram short circuit output current i os 50 ma lpsdram power dissipation pd 1 w 1. tbd stands for ?to be determined?.
NAND01G-N package mechanical rev1.0 19/23 5 package mechanical figure 5. tfbga107 10.5x13mm - 10x14 active ball array, 0.80mm pitch, package outline a2 a1 a bga-z24 ddd d e e b se fd fe e1 e sd d1 ball "b1" table 4. tfbga107 10.5x13mm - 10x14 active ball array, 0.80mm pitch, mechanical data symbol millimeters inches typ min max typ min max a 1.20 0.047 a1 0.25 0.010 a2 0.80 0.031 b 0.45 0.40 0.50 0.018 0.016 0.020 d 10.50 10.40 10.60 0.413 0.409 0.417 d1 7.20 0.283 ddd 0.10 0.004 e 13.00 12.90 13.10 0.512 0.508 0.516 e1 10.40 0.409 e 0.80??0.031?? fd 1.65 0.065 fe 1.30 0.051 sd 0.40 0.016 se 0.40 0.016
package mechanical NAND01G-N 20/23 rev1.0 figure 6. tfbga149 10x13.5mm - 12x16 active ball array, 0.80mm pitch, package outline 1. drawing not to scale. a2 a1 a bga-z78 ddd d e e b se fd fe e1 e sd d1 ball "a1" table 5. tfbga149 10x13.5mm - 12x16 active ball array, 0.80mm pitch, mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.250 0.0098 a2 0.800 0.0315 b 0.450 0.400 0.500 0.0177 0.0157 0.0197 d 10.000 9.900 10.100 0.3937 0.3898 0.3976 d1 8.800 0.3465 ddd 0.100 0.0039 e 13.500 13.400 13.600 0.5315 0.5276 0.5354 e1 12.000 0.4724 e 0.800 ? ? 0.0315 ? ? fd 0.600 0.0236 fe 0.750 0.0295 sd 0.400 ? ? 0.0157 ? ? se 0.400 ? ? 0.0157 ? ?
NAND01G-N part numbering rev1.0 21/23 6 part numbering devices are shipped from the factory with the flash memory content bits, in valid blocks, erased to ?1?. for further information on any aspect of this device, please contact your nearest st sales office. table 6. ordering information scheme example: nand01g r 3 n 6 a zb 5 e device type nand flash memory nand flash density 01g = 1gb nand flash operating voltage r = 1.7v to 1.95v bus width 3 = x8 4 = x16 family identifier n = 2112 byte page nand flash + lpsdram device options 5 = ddr lpsdram 512mbit (x16), 133 mhz, bga149 6 = sdr lpsdram 512mbit (x 16), 133mhz, bga107 product version a package zb = tfbga zc = lfbga reserved option e = ecopack package, standard packing f = ecopack package, tape & reel packing
revision history NAND01G-N 22/23 rev1.0 7 revision history table 7. document revision history date version revision details 18-oct-2004 0.1 first issue 19-oct-2004 0.2 figure 1: logic diagram modified. table 1: product list modified. 26-oct-2005 0.3 nand512-n device removed from the document.tfbga137 packages removed from document. sdr 256mb (x32) and sdr 512mb (x32) devices removed from document. nand01gr3n3 removed throughout document. ldqm and udqm replaced respectively by dqm0 and dqm1throughout document. dram changed to lpsdram throughout document. lfbga107 added throughout document. nand01gr3n1, nand01gr3n2, nand01gr3n6, nand01gr4n5 added throughout document. 31-jan-2006 1.0 note 1 below table 2: signal names and figure 1: logic diagram added to cover both part numbers. figure 2: tfbga107 connections, x16 bus width (top view through package) and figure 3: tfbga149 connections (top view through package) updated. section 2: signals description and section 3: functional description added. 256mb lpsdram removed. lfbga107 (12 x 13 x 1.4mm) and lfbga149 (10 x 13.5 x 1.4mm) replaced by tfbga107 (10.5x13x1.2mm) and tfbga149 (10x13.5x1.2mm), respectively.
NAND01G-N 23/23 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorize representative of st, st products are not designed, authorized or warranted for use in military, air craft, space, life saving, or life sustaining applications, nor in products or systems, where failure or malfunction may result in personal injury, death, or severe property or environmental damage. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2006 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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