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1 of 31 110501 features open drain pio pins are controlled and their logic level can be determined over 1-wire ? bus for closed-loop control replaces and is fully compatible with ds2407 but no user-programmable power-on settings and no hidden mode pio channel a sink capability of 50ma at 0.4v with soft turn-on; channel b 8ma at 0.4v maximum operating vo ltage of 13v at pio-a, 6.5v at pio-b 1024 bits user-programmable otp eprom user-programmable status memory to control the device multiple ds2406?s can be identified on a common 1-wire bus and be turned on or off independently of other devices on the bus unique, factory-lasered and tested 64-bit registration number (8-bit family code + 48-bit serial number + 8-bit crc tester) assures error-free selection and absolute identity because no two parts are alike on-chip crc16 generator allows detection of data transfer errors built-in multidrop controller ensures compatibility with other 1-wire net products reduces control, address, data, programming and power to a single data pin directly connects to a single port pin of a microprocessor and communicates at up to 16.3 kbits/s supports conditional search with user- selectable condition v cc bondout for optional external supply to the device (tsoc package only) 1-wire communication operates over a wide voltage range of 2.8v to 6.0v from -40c to +85c low cost to-92 or 6-pin tsoc surface mount package pin assignment 6-pin tsoc package top view 1 2 3 6 5 4 side view dallas ds2406 bottom view 1 2 3 to-92 see mech. drawings section 123 pin description to-92 tsoc/csp pin 1 ground ground pin 2 data data pin 3 pio-a pio-a pin 4 --- v cc pin 5 --- nc pin 6 --- pio-b ordering information ds2406 to-92 package ds2406p 6-pin tsoc package ds2406/t&r tape & reel of ds2406 ds2406p/t&r tape & reel of ds2406p ds2406x chip scale pkg., tape & reel ds2406 dual addressable switch plus 1kbit memory www.maxim-ic.com
ds2406 2 of 31 addressable switch description the ds2406 dual addressable switch? plus memory offe rs a simple way to remotely control a pair of open drain transistors and to monitor the logic level at each transistor?s output via the 1-wire bus for closed loop control. each ds2406 has its own 64-bit ro m registration number that is factory lasered into the chip to provide a guaranteed unique identity for absolute traceability. the device?s 1024 bits of eprom can be used as electronic label to store in formation such as switch function, physical location, and installation date. communica tion with the ds2406 follows th e standard dallas semiconductor 1-wire protocol and can be accomplished with min imal hardware such as a single port pin of a microcontroller. multiple ds2406 devices can reside on a common 1-wire ne twork and be operated independently of each other. individual devices will respond to a conditional search command if they qualify for certain user-specified conditions, which in clude the state of the out put transistor, the static logic level or a voltage transition at the transistor?s output. ds2406 block diagram figure 1 64-bit lasered rom program voltage detect memory function control crc16 generator parasite power int vdd data 8-bit scratchpad pio-a pio-b pio control status memory 5 bytes eprom 1 byte sram 1-wire bus data memory 1024-bit eprom (4 pages of 32 bytes each) 1-wire function control v cc
ds2406 3 of 31 overview the block diagram in figure 1 shows the relationships between the major control and memory sections of the ds2406. the device has four major data component s: 64-bit lasered rom, 1024 bits of eprom data memory, status memory, and the pio-control block. the hierarchical structure of the 1-wire protocol is shown in figure 2. the bus master must first pr ovide one of the five rom function commands: read rom, match rom, search rom, sk ip rom, or conditional search rom. the protocol required for these rom functions is described in figure 13. after a rom functions command is successfully executed, the pio-control and memory functions beco me accessible and the master may provide any one of the six memory- and control f unction commands. the protocol for these functions is described in figure 7. all data is read and written least significant bit first. hierarchical structure for 1-wire protocol figure 2 ds2406 command level available commands data fields affected 1-wire bus other devices bus master read rom match rom search rom skip rom conditional search rom 64-bit rom 64-bit rom 64-bit rom n/a conditional search settings at status memory location 7, write memory write status read memory read status ext. read memory channel access status memory 1024-bit eprom pio channels 1024-bit eprom status memory 1024-bit eprom ds2406 specific memory function commands (see figure 7) 1-wire rom function commands (see figure 13) 64-bit rom, device/channel status
ds2406 4 of 31 parasite power the ds2406 can derive its power entirely from the 1-wire bus by storing energy on an internal capacitor during periods of time when the signal line is high. during low times the device continues to operate off of this ?parasite? power source until the 1-wire bus returns high to replenish the parasite (capacitor) supply. in applications where the device may be te mporarily disconnected from the 1-wire bus or where the low-times of the 1-wire bus may be very long the v cc pin may be connected to an external voltage supply to maintain the device status. when writing to the eprom memory, the 1-wire communication occurs at normal voltage levels and then is pulsed momentarily to the programming voltage to cause the selected eprom bits to be programmed. the bus master must be able to provide 12v and 10ma to adequately program the eprom portions of the device. during programming, only eprom-based devices are allowed to be present on the 1-wire bus. 64-bit lasered rom each ds2406 contains a unique rom code that is 64 bits long. the first 8 bits are a 1-wire family code. the next 48 bits are a unique serial number. the last 8 bits are a crc of the first 56 bits. (see figure 3). the 1-wire crc is generated using a polynomial generator consisting of a shift register and xor gates as shown in figure 4. the polynomial is x 8 + x 5 + x 4 + 1. additional information about the dallas 1- wire cyclic redundancy check is available in a pplication note 27 or the book of ds19xx ibutton? standards. the shift register bits are initialized to ze ro. then starting with the least significant bit of the family code, 1 bit at a time is shifted in. after the 8th bit of the family code has been entered, then the serial number is entered. after the 48th bit of the serial number has been entered, the shift register contains the crc value. shifting in the 8 bits of crc should return the shift register to all zeros. the 64-bit rom and the 1-wire function control section allow the ds2406 to operate as a 1-wire device and follow the protocol detailed in the section ?1-wire bus system?. 64-bit lasered rom figure 3 msb lsb 8-bit crc code 48-bit serial number 8-bit family code (12h) msb lsb msb lsb msb lsb 1-wire crc generator figure 4 r x 2 x 1 x 0 x 8 x 7 x 6 x 5 x 4 x 3 8th stage 7th stage 6th stage 5th stage 4th stage 3rd stage 2nd stage 1st stage s input data polynomial = x 8 + x 5 + x 4 + 1
ds2406 5 of 31 memory map the ds2406 has two memory secti ons, called data memory and st atus memory. the data memory consists of 1024 bits of one-time programmable eprom organized as 4 pages of 32 bytes each. the address range of the device?s status memory is 8 byte s. the first seven bytes of status memory (addresses 0 to 6) are implemented as eprom. the eighth byte (address 7) consists of static ram. the complete memory map is shown in figure 5. th e 8-bit scratchpad is an additional register that acts as a buffer when writing the memory. data is first written to the scratchpad and then verified by reading a 16-bit crc from the ds2406 that confirms proper receipt of the data and address. this proce ss ensures data integrity when programming the memory. if the buffer conten ts are correct, the bus master should transmit a programming pulse (eprom) or a dummy byte ffh (ram) to transfer the data from the scratchpad to the addressed memory location. the details for r eading and programming the ds2406 are given in the memory function commands section. ds2406 memory map figure 5 8-bit scratchpad page # address range description 0 0000h to 001fh 32-byte final storage data memory 1 0020h to 003fh 32-byte final storage data memory 2 0040h to 005fh 32-byte final storage data memory 3 0060h to 007fh 32-byte final storage data memory valid device settings (sram) 00 factory test byte redirection bytes bitmap of used pages write-protect bits data memory ds2406 status memory map figure 6 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 (eprom) bm3 bm2 bm1 bm0 wp3 wp2 wp1 wp0 1 (eprom)1 11111redir. 0redir. 0 2 (eprom)1 11111redir. 1redir. 1 3 (eprom)1 11111redir 2redir 2 4 (eprom)1 11111redir 3redir 3 5 (eprom) eprom factory test byte 6 (eprom) don?t care, always reads 00 7 (sram) supply indication (read only) pio-b channel flip-flop pio-a channel flip-flop css4 channel select css3 channel select css2 source select css1 source select css0 polarity 1k-bit eprom 8 bytes status memor y
ds2406 6 of 31 status memory the status memory can be read or written to indicate various conditions to the software interrogating the ds2406. these conditions include special features for the data memory, definition of the settings for the conditional search as well as the channel flip-flops and the external power supply indication. how these functions are assigned to the bits of th e status memory is detailed in figure 6. the first 4 bits of the status memory (address 0, bits 0 to 3) contain the write protect page bits which inhibit programming of the corresponding page in th e 1024-bit data memory area if the appropriate write protection bit is programmed. once a bit has been pr ogrammed in the write protect page section of the status memory, the entire 32-byte page that corresponds to that bit can no longer be altered but may still be read. the remaining 4 bits of status memory loca tion 0 are reserved for use by the ibutton operating software tmex. their purpose is to indicate which memory pages are already in use. originally, all of these bits are unprogrammed, indicating that the devi ce does not contain any data. as soon as data is written to any page of the device under control of tm ex, the bit inside this bitmap corresponding to that page will be programmed to 0, marking this page as used. these bits are application flags only and have no impact on the internal logic of the ds2406. the next four bytes of the status memory (addresses 1 to 4) contain the page address redirection bytes which indicate if one or more of the pages of da ta in the 1024-bits eprom memory section have been invalidated by software and redirected to the page address contained in the a ppropriate redirection byte. the hardware of the ds2406 makes no decisions based on the contents of the pa ge address redirection bytes. since with eprom technology bits can only be changed from a logical 1 to a logical 0 by programming, it is not possible to simply rewrite a pa ge if the data requires changing or updating. but with space permitting, an entire page of data can be redirected to another page within the ds2406. under tmex, a page is redirected by writing the one?s co mplement of the new page address into the page address redirection byte that corresponds to the orig inal (replaced) page. this architecture allows the user?s software to make a ?data patch? to the eprom by indicating that a particular page or pages should be replaced with those indicated in the page address redirection bytes. under tmex, if a page address redirection byte has a ffh value, the data in the main memory that corresponds to that page is valid. if a page address redirection byte has some other hex value than ffh, the data in the page corresponding to that redirecti on byte is invalid. according to the tmex definitions, the valid data will now be found at the one?s complement of the page address indicated by the hex value stored in the associated page addr ess redirection byte. a value of fdh in the redirection byte for page 1, for example, would i ndicate that the updated data is now in pa ge 2. since the data memory consists of four pages only, the 6 most significant bits of the redirection bytes cannot be programmed to zeros. status memory location 5 serves as a test byte a nd is programmed to 00h at the factory. status memory location 6 has no function with the ds2406. it is f actory-programmed to 00h to distinguish the ds2406 from the ds2407, which both share the same family code. a ds2407 with status memory location 6 programmed to 00h will power-up into hidden mode and will only respond if the bus master addresses it by a match rom command followed by the correct de vice rom code. conversely, a device that does respond to a read rom command with family code 12h can only be a ds2406 if its status memory location 6 reads 00h.
ds2406 7 of 31 status memory location 7 serves three purposes: 1) it holds the selection code for the conditional search function, 2) provides the bus master a memory mapped access to the ch annel flip-flops that control the pio output transistors, and 3) allows the bus mast er to determine whether the device is hooked up to a v cc power supply. bit locations 0 to 4 store the cond itional search settings. their codes are explained in the section ?rom function commands? later in this document. the channel flip-flops are accessible through bit locations 5 and 6 as well as through the channel access function. the power-on default for the conditional search settings and the channel flip-flops is all 1?s. setting a channel flip-flop to 0 will make the associated pio-transist or conducting or on; settin g the flip-flop to 1 will switch the transistor off, which is identical to the power-on default. with the v cc pin connected to a suitable power supply the power indicator bit 7 will read 1. the power supply indicator can also be read through the channel access function. memory function commands the ?memory function flow chart? (figure 7) describes the protocols necessary for accessing the various data fields and pio channels within th e ds2406. the memory function control section, 8-bit scratchpad, and the program voltage detect circuit combine to interpret the commands issued by the bus master and create the correct control signals within the device. a three-byte protocol is issued by the bus master. it is comprised of a command byte to dete rmine the type of operati on and two address bytes to determine the specific starting byte location within a data field or to supply and exchange setup and status data when accessing the pio channels. the command byte indicates if the device is to be read or written or if the pio channels are to be accessed. writin g data involves not only issuing the correct command sequence but also providing a 12-volt programming voltage at the appropriate times. to execute a write sequence, a byte of data is first loaded into the scratchpad and then programmed into the selected address. write sequences always occur a byte at a time. to execute a read sequence, the starting address is issued by the bus master and data is read from the part beginning at that initial location and continuing to the end of the selected data field or until a reset sequenc e is issued. all bits transferred to the ds2406 and received back by the bus master are sent least significant bit first. read memory [f0h] the read memory command is used to read data from the 1024-bit eprom data memory field. the bus master follows the command byte with a two-byte address (ta1=(t7:t0), ta2=(t15:t8)) that indicates a starting byte location within the data field. since the data memory contains 128 bytes, t15:t8 and t7 should all be zero. with every subsequent read data time slot the bus master receives data from the ds2406 starting at the initial address a nd continuing until the end of the 1024-bits data field is reached or until a reset pulse is issued. if reading occurs through the end of memory space, the bus master may issue sixteen additional read time slots and th e ds2406 will respond with a 16-bit crc of the command, address bytes and all data bytes read from the initial starting byte through the last byte of memory. this crc is the result of clearing the crc generator and then shifting in the command byte followed by the two address bytes and the data bytes beginning at the first a ddressed memory loca tion and continuing through to the last byte of the eprom data memory. after the crc is received by the bus master, any subsequent read time slots will appear as logical 1s until a reset pulse is issued. any reads ended by a reset pulse prior to reaching the end of memory will not have the 16-bit crc available. typically the software controlling the device should store a 16-bit crc with each page of data to insure rapid, error-free data transfers that eliminate having to read a page multiple times to determine if the received data is correct or not. (see book of ds19xx ibutton standards, chapter 7 for the recommended file structure to be used with the 1-wire environment). if crc values are imbedded within the data it is unnecessary to read the end-of-memory crc. the read memory command can be ended at any point by issuing a reset pulse.
ds2406 8 of 31 extended read memory [a5h] the extended read memory command supports page redirection when reading data from the 1024-bit eprom data field. one major difference betwee n the extended read memory and the basic read memory command is that the bus master receives the redirection byte (see description of status memory) first before investing time in reading data from the addressed memory location. this allows the bus master to quickly decide whether to continue and access the data at the selected starting page or to terminate and restart the reading process at the redirected page address. in addition to page redirecti on, the extended read memory comma nd also supports ?bit-oriented? applications where the user cannot store a 16-bit crc w ith the data itself. with bit-oriented applications the eprom information may change over time with in a page boundary making it impossible to include an accompanying crc that will always be valid. therefore, the extended read memory command concludes each page with the ds2406 generating and supplying a 16-bit crc that is based on and therefore always consistent with the current data st ored in each page of the 1024-bit eprom data field. after having sent the command code of the exte nded read memory command, the bus master sends a two-byte address (ta1=(t7:t0), ta2=(t15:t8)) that indicates a starting byte location within the data field. by sending eight read data time slots, the master receives the redirection byte associated with the page given by the starting address. with the next sixteen read data time slots, the bus master receives a 16-bit crc of the command byte, address bytes and the redirection byte. this crc is computed by the ds2406 and read back by the bus master to check if the command word, starting address and redirection byte were received correctly. if the crc read by the bus master is incorrect, a reset pulse must be issued and the entire sequence must be repeated. if the crc received by the bus master is correct, the bus master i ssues read time slots and receives data from the ds2406 starting at the initial address and continuing until the end of a 32-byte page is reached. at that point the bus master will send sixteen additional read time slots and receive a 16- bit crc that is the result of shifting into the crc gene rator all of the data bytes from the initial starting byte to the last byte of the current page. with the next 24 read data time slots the master will receive the redirection byte of the next page followed by a 16-bit crc of the redirection byte. after this, data is again read from the 1024-bits eprom data field starting at the beginning of the new page. this sequence will continue until the final page and its accompanying crc are read by the bus master. the extended read memory command provides a 16-bit crc at two locations within the transaction flow chart: 1) after the redirection byte and 2) at the end of each memory page. the crc at the end of the memory page is always the result of clearing the crc generator and shifting in the data bytes beginning at the first addressed memory location of the eprom data page until the last byte of this page. with the initial pass through the extended read memory flow chart the 16-bit crc value after the redirection byte is the result of shifting the command byte into the cleared crc generator, followed by the two address bytes and the redi rection byte. subsequent passes through the extended read memory flow chart will generate a 16-bit crc that is the result of clearing the crc generator and then shifting in the redirection byte only. after the 16-bit crc of the last page is read, the bus master will receive logical 1s from the ds2406 until a reset pulse is issued. the extended read memory command sequence can be ended at any point by issuing a reset pulse.
ds2406 9 of 31 writing eprom memory the function flow for writing to the data memory and status memory is almost identical. after the appropriate write command has been issued, the bus master will send a two-byte starting address (ta1=(t7:t0), ta2=(t15:t8)) and a byte of data (d7:d0). a 16-bit crc of the command byte, address bytes, and data byte is computed by the ds2406 and read back by the bus master to confirm that the correct command word, starting address, and data byte were received. if the crc read by the bus master is incorrect, a reset pulse must be issued and the entire sequence must be repeated. if the crc received by the bus master is correct, a programming pulse (12v on the 1-wire bus for 480 s) is issued by the bus master. pr ior to programming, the entire unprogrammed eprom memory field will appear as logical 1s. for each bit in the data byte provided by the bus master that is set to a logical 0, the corresponding bit in the selected byte of the eprom memory is programmed to a logical 0 after the programming pulse has been applied. after the 480 s programming pulse is applied and the data line return s to the idle level (5v), the bus master issues eight read time slots to verify that the appropriate bits have been programmed. the ds2406 responds with the data from the sele cted eprom address sent least signif icant bit first. this byte contains the bit-wise logical and of all data ever written to this address. if th e eprom byte contains 1s in bit positions where the byte issued by the master containe d 0s, a reset pulse should be issued and the current byte address should be programme d again. if the ds2406 eprom byte contains 0s in the same bit positions as the data byte, the programming was succ essful and the ds2406 will automatically increment its address counter to select the next byte in the eprom memory fi eld. the new two-byte address will also be loaded into the 16-bit crc generator as a starting value. the bus master will issue the next byte of data using eight write time slots. as the ds2406 receives this byte of data into the scratchpad, it also shifts the data into the crc generator that has been preloaded with the current address and the result is a 16-bit crc of the new data byte and the new address. after supplying the data byte, the bus master will read this 16-bit crc from the ds2406 with sixteen read time slots to confirm that the address incremented properly and the data byte was received correctly. if the crc is incorrect, a reset pu lse must be issued and the write sequence must be restarted. if the crc is correct, the bus master will issue a programming pulse and the selected byte in memory will be programmed. note that the initial pass through the write flow chart will generate an 16-bit crc value that is the result of shifting the command byte into the crc generator, followed by the two address bytes, and finally the data byte. subsequent passes thro ugh the write flow chart due to the ds2406 automatically incrementing its address counter will generate a 16-bit crc that is the result of loading (not shifting) the new (incremented) address into the crc generator and then shifting in the new data byte. for both of these cases, the decision to continue (to apply a program pulse to the ds2406) is made entirely by the bus master, since the ds2406 will not be able to determine if the 16-bit crc calculated by the bus master agrees with the 16-bit crc calculated by the ds2406. if an incorrect crc is ignored and the bus master applies a program pulse, incorrect programming could occur within the ds2406. also note that the ds2406 will always increment its internal addr ess counter after the rece ipt of the eight read time slots used to confirm the programming of the selected eprom byte. the decision to continue is again made entirely by the bus master. therefore if the ep rom data byte does not ma tch the supplied data byte but the master continues with the write command, incorrect progra mming could occur within the ds2406. the write command sequence can be ended at any point by issuing a reset pulse.
ds2406 10 of 31 memory function flow chart figure 7 spare vertical f0h read memory ? ta1(t7:t0), ta2 (t15:t8) bus master tx address = (t15:t0) ds2406 sets memory a5h extended rd. memory ? r s bus master tx memory function command to figure 7 2nd part yy nn master tx reset ? y increments ds2406 address counter end of data mem. ? master tx reset ? y n n y n command, address, data bus master rx crc16 of y n bus master rx "1"s master tx reset ? ta1(t7:t0), ta2 (t15:t8) bus master tx address = (t15:t0) ds2406 sets memory redirection byte bus master rx address, redir. byte (1st pass) bus master rx crc16 of command, crc16 of redir. byte (subs. passes) crc correct ? master tx reset ? end of page ? preceding page of data bus master rx crc16 of crc correct ? end of data mem. ? from data memory bus master rx data from data memory bus master rx data y n bus master rx "1"s master tx reset ? increments ds2406 address counter increments ds2406 address counter reset pulse bus master tx reset pulse bus master tx presence pulse ds2406 tx n y n y n y n y legend: decision made by bus master decision made by ds2406 y n
ds2406 11 of 31 memory function flow chart (continued) figure 7 spare vertical write memory ? ta1(t7:t0), ta2 (t15:t8) bus master tx address = (t15:t0) ds2406 sets memory y address, data (1st pass); crc16 of bus master rx crc16 of command, address, data (subsequent passes) data byte (d7:d0) bus master tx crc correct ? program pulse bus master tx pad to data eprom ds2406 copies scratch- from data eprom bus master rx byte eprom byte correct ? end of data mem. ? address counter ds2406 increments into crc generator ds2406 loads new address r to figure 7 3rd part 0fh n from figure 7 1st part n write status ? ta1(t7:t0), ta2 (t15:t8) bus master tx address = (t15:t0) ds2406 sets memory s y data byte (d7:d0) bus master tx crc correct ? program pulse bus master tx pad to status eprom ds2406 copies scratch- from status eprom bus master rx byte eprom byte correct ? address < 7 ? address counter ds2406 increments into crc generator ds2406 loads new address 55h address, data (1st pass); crc16 of bus master rx crc16 of command, address, data (subsequent passes) reset pulse bus master tx presence pulse ds2406 tx byte from bus master rx volatile status scratchpad to ds2406 copies volatile status legend: decision made by bus master decision made by ds2406 bus master tx ffh or program pulse y n y n y n y n y n y n
ds2406 12 of 31 memory function flow chart (continued) figure 7 spare vertical aah read status ? ta1(t7:t0), ta2 (t15:t8) bus master tx address = (t15:t0) ds2406 sets status f5h channel access ? s y y nn master tx reset ? y increments ds2406 address counter end of status mem. ? master tx reset ? y n n y n command, address, data bus master rx crc16 of y n bus master rx "1"s master tx reset ? control bytes 1, 2 bus master tx ch.- from status memory bus master rx data presence pulse ds2406 tx y from figure 7 2nd part master tx reset ? y n master tx reset ? r control, data (1st pass) bus master rx crc16 of command, crc16 of data (subsequent passes) crc* enabled ? crc due * ? increments ds2406 crc byte counter n y n y y n master tx reset ? master tx reset ? from pios bus master rx data channel f/f bus master tx data to crc byte counter ds2406 clears y n r/w toggle enabled ? r/w mode ds2406 toggles n bus master rx channel info byte reset pulse bus master tx presence pulse ds2406 tx * see channel control byte 1 and figure 7a mode ? access read write * * y n
ds2406 13 of 31 write memory [0fh] the write memory command is used to program th e 1024-bit eprom data memo ry. the details of the functional flow chart are described in the section ?writing eprom memory?. the data memory address range is 0000h to 007fh. if the bus master sends a st arting address higher than this, the nine most significant address bits are set to zeros by the internal circuitry of the chip. this will result in a mismatch between the crc calculated by the ds2406 and the crc calculated by the bus master, indicating an error condition. write status [55h] the write status command is used to program the st atus memory, which includes the specification of the conditional search settings. the details of the functional flow chart are described in the section ?writing eprom memory?. the status memory address range is 0000h to 0007h. th e general programming algorithm is valid for the eprom section of the status memory (addresses 0 to 4) only. the status memory locations 5 and 6 are already pre-programmed to 00h and therefore cannot be altered. status memory location 7 consists of static ram, which can be re programmed without limita tion and does not require a 12v programming pulse. the supply indication (bit 7) is read-only; attemp ts to write to it are ignored. the function flow for writing to status memory location 7 is basically the same as for the other eprom status memory bytes. however, instead of a programming pulse the bus master may send a ffh byte (equivalent to 8 write-one time slots) to transfer the new value from the scratchpad to the status memory. if the bus master sends a starting address higher than 0007h, the nine most significant address bits are set to zeros by the internal circuitry of the chip. the address bits t3:t6 remain unchanged and will be ignored by the address decoder of the ds2406. only if one or more of the address bits t8:t15 is set, the bus master will be able to discover an error condition based on the crc16 that is calculated by the ds2406. read status [aah] the read status command is used to read data from the status memory field. the functional flow chart of this command is identical to the read memory co mmand. since the status memory is only 8 bytes, the ds2406 will send the 16-bit crc after the last byte of status information has been transmitted. channel access [f5h] the channel access command is used to access the pio channels to sense the logical status of the output node and the output transistor and to change the status of the output transistor. the bus master will follow the command byte with two channel control bytes and will receive back the channel info byte. the channel control bytes allow the master to select a pio-channel to communicate with, to specify communication parameters, and to reset the activity latches. figure 8 shows the details channel control byte 1. the bit assignments of channel control byte 2 are reserved for future development. the bus master should always send ffh for the second channel control byte. channel control byte 1 figure 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 alr im tog ic chs1 chs0 crc1 crc0
ds2406 14 of 31 most easily understood are the bits chs0 and chs1, which select the channe ls to communicate with. one can select one of the two channels or both cha nnels together. the selecti on codes are shown in the table below. chs1 chs0 description 0 0 (not allowed) 0 1 channel a only 1 0 channel b only 1 1 both channels interleaved when reading only a single channel, the logic level at the selected pio is sampled at the beginning of each read time slot (figure 10a) and is immediately si gnaled through the 1-wire line. because the pio logic levels are sensed at the beginning of the time slot, the bus master does not see transitions at the pio that occur during the time slot. when writing to a single channel, the selected pio will show the new status after (but not necessarily immediately after) the 1-wire line has returned to its idle level of typically 5v (see figure 10a). if the bus master transmits a 1 (write one time slot), the output transistor of the selected channel will change its status afte r time td1, which is 15s to 60s after the beginning of the time slot. if the bus master transmits a 0 (write zero time slot), the output transistor will change its status with a delay of td0 after the 1-wire line has returned to its idle level. the value of td0 may vary between 200 and 300 ns (see figure 10a). depending on the load conditions, there may be additional delay until the voltage at the pio reaches a new logical level. when communicating with both channels, the interleave control bit ic controls when data is sampled and when data arrives at the pio pins. there is an asynchronous mode (ic = 0) and a synchronous mode (ic = 1). for the asynchronous mode, both channels ar e accessed in an alternating way. for the synchro- nous mode, both channels are accessed simultaneous ly. for single-channel operation the interleave control bit must be set to 0. when reading in the asynchronous mode each channel is sampled alternately at the start of each read time slot, beginning with channel a. the logic level detected at the pio is immediately transmitted to the master during the same time slot. when read ing in the synchronous mode, both channels will be sampled at the same time. the data bit from channel a will be sent to the master immediately during the same time slot while the data bit from channel b follows with the next time slot which does not sample the pios. both channels will be sampled again with the time slot that follows the transmission of the data bit from pio-b (figure 10b). when writing in the asynchronous mode, each channel will change its status independently of the other. the change of status occurs with the same timing relations as for communication with one channel. however, every second write time slot addresses the same channel. th e first time slot is directed to channel a, the second to channel b, the next to ch annel a and so on. as a consequence, in asynchronous mode both pios can never change their status at the same time. when writing in the synchronous mode, both channels operate together. af ter the new values for both channe ls have arrived at the ds2406 the change of status at both channels occurs with the same timing relations as for communication with one channel. as with the asynchronous mode, every s econd write time slot cont ains data for the same channel. the first time slot addr esses channel a, the second channe l b and so on. depending on the data values, in the synchronous mode both pios can change their status at the same time (figure 10c). in any of these cases, the information of channel a and channel b will appear alternating on the 1-wire line, always starting with channel a. by varying the idle-time between time slots on the 1-wire line one has full control over the time points of sampling and the waveforms generated at the pio-pins when writing to the device.
ds2406 15 of 31 the tog bit of channel control byte 1 specifies if one is always reading or writing (tog = 0) or if one is going to change from reading to writing or vice versa after every data byte that has been sent to or received from the ds2406 (tog = 1). when accessing one ch annel, one byte is equi valent to eight reads from or writes to the selected pio pin. when accessing two channels, one byte is equivalent to four reads or writes from/to each channel. the initial mode (reading or writing) for accessing the pio channels is specified in the im bit. for read- ing, im has to be set to 1, for writing im needs to be 0. if the tog bit is set to 0, the device will always read or write as specified by the im bit. if tog is 1, the device will use the setting of im for the first byte to be transmitted and will alternate between reading and writing after every byte. table 1 illustrates the effect of tog and im for one-channel as well as for two-channel operation. the effect of toggle mode and initial mode table 1 tog im channels effect 0 0 one channel write all bits to the selected channel 0 1 one channel read all bits from the selected channel 1 0 one channel write 8 bits, read 8 bits, write, read, etc. to/from the selected channel 1 1 one channel read 8 bits, write 8 bits, read, write, etc. from/to the selected channel 0 0 two channels repeat: four times ( write a, write b) 0 1 two channels repeat: four times ( read a, read b) 1 0 two channels four times: ( write a, write b), four times: ( read a, read b), write, read, etc. 1 1 two channels four times: ( read a, read b), four times: ( write a, write b), read, write, etc. the alr bit of channel control byte 1 controls whether the activity latch of each channel gets reset. both activity latches are cleared simultaneously if the alr bit is 1. they are not changed if the alr bit is 0. an activity latch is set with a negative or positive edge that occurs at its associated pio channel. channel control byte 1 also controls the internal crc generator to safeguard data transmission between the bus master and the ds2406 for channel access. it does not affect reading from or writing to the memory sections of the ds2406. the crc control bits (bit 0 and bit 1) can be set to create and protect data packets that have the size of 8 bytes or 32 by tes. if desired, the device can safeguard even single bytes by a 16-bit crc. this setting, however, limits th e average pio sampling rate to about one third of its maximum possible value. the codes for the crc control are shown in the table below. crc1 crc0 description 0 0 crc disabled (no crc at all) 0 1 crc after every byte 1 0 crc after 8 bytes 1 1 crc after 32 bytes the crc provides a high level of safeguarding data. a detailed description of crcs is found in application note 27 and the ?book of ds19xx ibutton standards?. if the crc is disabled, the crc- related sections in the flow chart are skipped.
ds2406 16 of 31 after the channel control bytes have been transmitted the bus master receives the channel info byte (figure 9). this byte indicates the status of the channel flip-flops, the pio pins, the activity latches as well as the availability of channel b and external power supply. to be able to read from a pio channel, the output transistor needs to be non-conducting, whic h is equivalent to a 1 for the channel flip-flop. reading 0 for both the channel flip-flop and the sensed le vel indicates that the output transistor of the pio is pulling the node low. for the channel info byte pi o a and b are sampled at the same time, as in the synchronous mode. if channel b is available, bit 6 of the channel info byte reads 1. for 1-channel versions of the ds2406, the pio b sensed level, chan nel flip-flop value, and activity latch value should be ignored. without an external supply, the supply i ndication bit (bit 7) reads 0. as long as the voltage applied to the v cc pin is high enough to operate the device this bit will read 1. channel info byte figure 9 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 supply indication 0 = no supply number of channels 0 = channel a only pio-b activity latch pio-a activity latch pio b sensed level pio a sensed level pio-b channel flip-flop q pio-a channel flip-flop q one-channel read/write figure 10a pio 1-wire read (ic=0, asynchronous mode) write (ic=0, asynchronous mode) pio 1-wire td1 td0 15 s < td1 < 60 s 200 ns < td0 < 300 ns pio sampling two-channel read figure 10b pio-a pio sampling 1-wire 1-wire pio-b ic=1, synchronous mode ic=0, asynchronous mode 13579 8 6 4 2 a1 b1 a3 b3 a5 b5 a7 b7 a9 a1 b2 a3 b4 a5 b6 a7 b8 a9
ds2406 17 of 31 two-channel write figure 10c 1-wire td1 pio-a 15 s < td1 < 60 s 200 ns < td0 < 300 ns pio-b pio-a pio-b ic=1, synchronous mode ic=0, asynchronous mode a1 b1 a2 b2 a3 b3 a4 b4 a1 a2 a3 a4 b1 b2 b3 b4 a1 a2 a3 a4 b1 b2 b3 b4 td0 1-wire bus system the 1-wire bus is a system, which has a single bus ma ster and one or more slaves. in all instances, the ds2406 is a slave device. the bus ma ster is typically a microcontroller. the discussion of this bus system is broken down into three topics: hardware configuration, transac tion sequence, and 1-wire signaling (signal types and timing). a 1-wire protocol defines bus transactions in terms of the bus state during specified time slots that are initiated on the falling edge of sync pulses from the bus master. for a more detailed protocol description, refer to chapter 4 of the book of ds19xx ibutton standards. hardware configuration the 1-wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. to facilitate this, each device attached to the 1-wire bus must have an open drain or 3-state outputs. the 1-wire port of the ds2406 is open drain with an internal circuit equivalent to that shown in figure 11. typical bus ma ster ports are shown in figure 12. if a bi-directional pin is not available, separate output and input pins can be tied togeth er. a multidrop bus consists of a 1- wire bus with multiple slaves attached. the 1-wi re bus has a maximum data rate of 16.3kbits/s. for normal communication excluding eprom programming the 1-wire bus requires only a pull-up resistor of approximately 5k for short line lengths. the idle state for the 1-wire bus is high. if, for any reason a transaction needs to be suspended, the bus must be left in the idle state if the transaction is to resume. if this does not occur and the bus is left low for more than 120s, one or more of the devices on th e bus may be reset. if the 1-wire bus remains low for more than 5ms any ds2406 that is not v cc powered may perform a power-on reset and switch off both pios. transaction sequence the sequence for accessing the ds2406 vi a the 1-wire port is as follows: initialization rom function command memory or channel access function command transaction/data
ds2406 18 of 31 ds2406 equivalent circuit figure 11 1-wire interface pio ground pio channel reset d "1" q q activity latch dq q 1-wire data channel flip-flop to pio- control 10 m typ. from pio- control r edge detector data rx tx 100 mosfet ground 5 a typ. bus master circuit figure 12 a) open drain 12v open drain port pin s d d s 470 pf d s pgm d s 2n7000 2n7000 2n7000 vp0300l or vp0106n3 or bss110 capacitor added to reduce coupling on data line due to programming signal switching v pup rx tx b) standard ttl ttl-equivalent port pins 5 k 12v (10 ma min.) to data connection of ds2406 programming pulse the diode and programming circuit are not required if one does not intend to program the eprom cell s v pup rx tx dd v 5 k to data connection of ds2406 dd v ds5000 or 8051- equivalent 5 k 10 k 10 k bus master bus master the interface is reduced to the pull-up resistor if one does not intend to program the eprom cells. 5k
ds2406 19 of 31 initialization all transactions on the 1-wire bus begin with an initialization sequence. the initialization sequence consists of a reset pulse transmitted by the bus master followed by a presence pulse(s) transmitted by the slave(s). the presence pulse lets the bus master know that the ds2406 is on the bus and is ready to operate. for more details, see the ?1-wire signaling? section. rom function commands once the bus master has detected a presence, it can issue one of the five rom function commands that the ds2406 supports. all rom function commands are 8 bits long. a list of these commands follows (refer to flowchart in figure 13). read rom [33h] this command allows the bus master to read the ds2406?s 8-bit family code, unique 48-bit serial number, and 8-bit crc. this command should only be used only if there is a single slave on the bus. if more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-and resu lt). the resultant family code and 48-bit serial number will be invalid. match rom [55h] the match rom command, followed by a 64-bit rom se quence, allows the bus master to address a specific ds2406 on a multidrop bus. only the ds2406 th at exactly matches the 64-bit rom sequence will respond to the subsequent memory function co mmand. all slaves that do not match the 64-bit rom sequence will wait for a reset pulse. this command can be used with a single or multiple devices on the bus. search rom [f0h] when a system is initially brought up, the bus ma ster might not know the number of devices on the 1-wire bus or their 64-bit rom codes. the sear ch rom command allows the bus master to use a process of elimination to identify the 64-bit rom codes of all slave devices on the bus. the search rom process is the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. the bus master performs this 3-step routine on each bit of the rom. after one complete pass, the bus mast er knows the 64-bit rom code of one device. additional passes will identify the rom codes of the remaining devices. see chapter 5 of the book of ds19xx ibutton standards for a comprehensive discussion of a search rom, including an actual example. skip rom [cch] this command can save time in a single drop bus system by allowing the bus master to access the memory and channel access functions without providing the 64-bit rom code. if more than one slave is present on the bus and, for example, a read comma nd is issued following the skip rom command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pull-downs will produce a wired-and result).
ds2406 20 of 31 rom functions flow chart figure 13 spare vertical 33h read rom ? command r y n cch skip rom ? command y n s family code ds2406 tx (1 byte) ds2406 tx crc byte serial number ds2406 tx (6 byte) 55h match rom ? command y n bit 63 match ? master tx bit 0 bit 1 match ? bit 0 match ? master tx bit 1 master tx bit 63 f0h search rom ? command y n bit 0 match ? master tx bit 0 ds2406 tx bit 0 ds2406 tx bit 0 master tx bit 1 ds2406 tx bit 1 ds2406 tx bit 1 bit 1 match ? bit 63 match ? master tx bit 63 ds2406 tx bit 63 ds2406 tx bit 63 ech conditional ? search y n bit 0 match ? master tx bit 0 ds2406 tx bit 0 ds2406 tx bit 0 master tx bit 1 ds2406 tx bit 1 ds2406 tx bit 1 bit 1 match ? bit 63 match ? master tx bit 63 ds2406 tx bit 63 ds2406 tx bit 63 condition fulfilled ? ds2406 tx presence pulse bus master tx reset pulse function command bus master tx rom function command bus master tx memory r (see figure 7)
ds2406 21 of 31 conditional search rom [ech] the conditional search rom command operates similarly to the search rom command except that only devices fulfilling the specified condition will par ticipate in the search. this command provides an efficient means for the bus master to identify devices in a multidrop system that have to signal a status change, e.g. the opening of a window in a building control application. the condition is specified by the bit functions css0 to css4 in status memory location 7. at power-on all these bits are 1s. they can be changed by mean s of the write status command. as long as the device remains powered up, the modified search conditions ar e available for use at any time. for the conditional search, one can specify the polarity (high or low; css0), the source (pio-pin, channel flip flop or activity latch; css1, css2), and the channel of interest (a, b or the logical or of a, b; css3, css4). table 2 shows all qualifying conditions and the required settings for css0 to css4. qualifying conditions for conditional search table 2 description conditional search select code channel select source select polarity condition channel css4 css3 css2 css1 css0 reserved don?t care 0 0 0/1 unconditional neither one 0 0 at least one of these bits needs to be 1 0 activity latch = 0 a 0101 0 activity latch = 1 a 0101 1 channel ff = 0 (transistor on) a 0110 0 channel ff = 1 (transistor off) a 0110 1 pio low a 0111 0 pio high a 0111 1 activity latch = 0 b 1001 0 activity latch = 1 b 1001 1 channel ff = 0 (transistor on) b 1010 0 channel ff = 1 (transistor off) b 1010 1 pio low b 1011 0 pio high b 1011 1 activity latch = 0a or b1101 0 activity latch = 1a or b1101 1 channel ff = 0 (transistor on) a or b1110 0 channel ff = 1 (transistor off) a or b1110 1 pio low a or b1111 0 pio high a or b1111 1
ds2406 22 of 31 the activity latch (figure 11) captures an event for interrogation by the bus master at a later time. this way, the bus master needs not interrogate devices con tinuously. the activity latch is set to 1 with the first negative or positive edge detected on the associated pio channel. it can be cleared with the channel access command if the alr bit of the channel control byte 1 is set. the activity latch is automatically cleared when the ds2406 powers up. in order to use the activity latch the output transistor of the selected channel should be non-conducting. othe rwise signals applied to the pi o pin will be shorted to ground by the low impedance of the output transistor. the channel select bits css3 and css4 specify the channel of interest. the sampling of the source within the selected channel will take place on co mpletion of the conditional search command byte. the channel selection codes are as follows: css4 css3 channel selection 0 0 neither channel selected 0 1 channel a only 1 0 channel b only 1 1 channel a or channel b if both css3 and css4 are 1, the logical values of the selected signal source of both channels are ored and the result is compared to specified polarity. if, for example, the specified polarity is 0, the signal source of both channels must be 0 for the device to respond to the conditional search. if both css3 and css4 are 0, neither channel is select ed. under this condition the device will always respond to the conditional search if the polarity bit css0 is 0, disr egarding the source selection. if neither channel is selected and css0 = 1, the device will only respond to the regular search rom command. the source selection for the conditiona l search is done through the source select bits css1 and css2. the codes for these bits are as follows: css2 css1 source selection 0 0 reserved 0 1 activity latch 1 0 channel flip flop 11pio status the setting css1 = 0, css2 = 0 is reserved for future use. if programmed with this setting the device will respond to conditional search command as follows: if css0 = 0 the device will always respond to a conditional search, if css0 = 1 the device will never respond to a conditional search. the conditional search polarity is specified by css0. if css0 is 0, the ds2406 will respond to a conditional search command if the status of the selected source for the specified channel is logic 0. if css0 is set to 1, the source level needs to be logic 1. for 1-channel versions of the ds2406 the channel b input will always be logic 0. for this reason css4 should not be set to 1 to avoid unwanted influence from channel b. the bus master can determine the availability of channel b from bit 6 of the channel info byte.
ds2406 23 of 31 1-wire signaling the ds2406 requires strict protocols to ensure data integrity. the prot ocol consists of five types of signaling on one line: reset sequence with reset pulse and presence pulse, write 0, write 1, read data, and program pulse. except for the presence pulse the bus master initiates all these signals. the initialization sequence required to begin any co mmunication with the ds2406 is shown in figure 14. a reset pulse followed by a presence pulse indicates the ds2406 is ready to send or receive data. the bus master transmits (tx) a reset pulse (t rstl , minimum 480s). the bus master then releases the line and goes into receive mode (rx). the 1-wire bus is pulled to a high state via the pull-up resistor. after detecting the rising edge on the data pin, the ds2406 waits (t pdh , 15-60s) and then transmits the presence pulse (t pdl , 60-240s). initialization procedure ?reset and presence pulses? figure 14 resistor master ds2406 master rx "presence pulse" 480 s t rstl < * 480 s t rsth < (includes recovery time) 15 s t pdh < 60 s 60 t pdl < 240 s master tx "reset pulse" v pullup v pullup min v ih min v il max 0v t rsth t rstl t pdh t pdl t r * in order not to mask interrupt signalin g by other devices on the 1-wire bus, t rstl + t r should always be less than 960s. in a pa rasitically powered environment t rstl should be limited to maximum 5ms. otherwise the ds 2406 may perform a power-on reset. read/write time slots the definitions of write and read time slots are illustrated in figure 15. the master initia tes all time slots by driving the data line low. the falling edge of the data line synchronizes the ds2406 to the master by triggering an internal delay circuit. during write time slots, the delay circuit determines when the ds2406 will sample the data line. for a read data time slot, if a ?0? is to be transmitted, the delay circuit determines how long the ds2406 will hold the data line low. if the data bit is a ?1?, the ds2406 will not hold the data line low at all.
ds2406 24 of 31 read/write timing diagram figure 15 write-one time slot 15s 60s ds2406 sampling window v pullup v pullup min v ih min v il max 0v t slot t rec t low1 60 s t slot < 120 s 1 s t low1 < 15 s 1 s t rec < resistor master write-zero time slot 15s resistor master ds2406 60s t low0 sampling window 60 s t low0 < t slot < 120 s 1 s t rec < v pullup v pullup min v ih min v il max 0v t slot t rec
ds2406 25 of 31 read/write timing diagram (continued) figure 15 read-data time slot resistor master ds2406 master sampling window 60 s t slot < 120 s 1 s t lowr < 15 s 0 t release < 45 s 1 s t rec < t rdv = 15 s t su < 1 s v pullup v pullup min v ih min v il max 0v t slot t rec t lowr t su t rdv t release * the optimal sampling point for the master is as close as possible to the end time of the 15 s t rdv period without exceeding t rdv . for the case of a read-one time slot, this maximizes the amount of time for the pull-up resistor to recover the line to a high level. for a read-zero time slot it ensures that a read will occur before the fastest 1-wire devices(s) release the line (t release = 0). program pulse to copy data from the 8-bit scratchpad to the eprom data or status memory, a program pulse is applied to the data line after the bus master has confirmed that the crc for the current byte is correct. during programming, the bus master controls the transition from a state where the data line is idling high via the pull-up resistor to a state where the data line is actively driven to a programming voltage of 12v providing a minimum of 10ma of current to the ds2406. this programming voltage (figure 16) should be applied for 480s, after which the bus master should return the data line to the idle high state. note that due to the high voltage programming requirements for any 1-wire eprom device, it is not possible to multi-drop non-eprom ba sed 1-wire devices with the ds 2406 during programming. an internal diode within the non-eprom based 1- wire devices will attempt to clam p the data line at approximately 8v and could potentially damage these devices.
ds2406 26 of 31 program pulse timing diagram figure 16 resistor pull-up line type legend: bus master active high (12 v @ 10 ma) v pullup v pp gnd 480 s t rp t fp t dp t dv > 5 s > 5 s t pp normal 1-wire communication ends normal 1-wire communication resumes crc generation with the ds2406 there are two different types of crcs (cyclic redundancy checks). one crc is an 8-bit type. it is computed at the factory and lasered into the most significant byte of the 64-bit rom. the equivalent polynomial function of this crc is x 8 + x 5 + x 4 + 1. to determine whether the rom data has been read without error the bus master can compute the crc value from the first 56 bits of the 64-bit rom and compare it to the value read from the ds 2406. this 8-bit crc is received in the true form (non-inverted) when reading the rom. the other crc is a 16-bit type, generated according to the standardized crc16-polynomial function x 16 + x 15 + x 2 + 1. this crc is used for error detection when reading data memory, status memory, or when communicating with pio channels. it is the same type of crc as is used with nvram based ibuttons for error detection within the ibutton extended file structure. in contrast to the 8-bit crc, the 16-bit crc is always returned in the complemented (inverted) form. a crc-generator inside the ds2406 chip (figure 17) will calculate a new 16-bit crc as shown in the command flow chart of figure 7. the bus master may compare the crc value read from the device to the one it calculates from the data and decides whether to continue with an operation or to re-do the function that returned the crc error. when reading the data memory of the ds2406 with the read memory command, the 16-bit crc is only transmitted at the end of the memory. this crc is generated by clearing the crc generator, shifting in the command, low address, high addr ess, and every data byte startin g at the first addressed memory location and continuing until the end of the physical data memory is reached. when reading the status memory, the 16-bit crc is transmitted at the end of the 8-byte status memory page. the 16-bit crc will be generated by clearing the crc generator, shifting in the command byte, low address, high address, and th e data bytes beginning at the first addressed memory location and continuing until the last byte of the status memory is reached. when reading the data memory of the ds2406 with the extended read memory command, there are two situations where a 16-bit crc is generated. one 16-bit crc follows each redirection byte; another 16-bit crc is transmitted after the last byte of a memory data page is read. the crc at the end of the memory page is always the result of clearing the crc generator and shifting in the data bytes beginning at the first addressed memory location of the eprom data page until the last byte of this page. with the
ds2406 27 of 31 initial pass through the extended read memory flow chart the 16-bit crc value is the result of shifting the command byte into the cleared crc generator, followed by the two address bytes and the redirection byte. subsequent passes through the extended read memory flow chart will generate a 16-bit crc that is the result of clearing the crc generator and then shifting in only the redirection byte. when writing to the ds2406 (either data memory or status memory), the bus master receives a 16-bit crc to verify that the data transfer was correct be fore applying the programming pulse. with the initial pass through the write memory/status flow chart the 16-bit crc will be generated by clearing the crc- generator, shifting in the command, low address, hi gh address and the data byte. subsequent passes through the write memory/status fl ow chart due to the ds2406 automatically incrementing its address counter will generate a 16-bit crc that is the result of loading (not shifting) the new (incremented) address into the crc generator and then shifting in the new data byte. when communicating with a pio channel using th e channel access command, one can select whether and how often a 16-bit crc will be added to the data stream. this crc selection is specified in the channel control byte 1 and may be changed with every execution of the channel access command. depending on the crc selection, the device can generate a crc after every byte that follows the channel info byte, after each block of eight bytes or after each block of 32 bytes. if the crc is enabled, with the initial pass through the ch annel access flow chart the 16-bit crc will be generated by clearing the crc-generator, shifting in the command, channel control bytes 1 and 2, channel info byte and the specified amount of data bytes (1, 8, or 32). subse quent passes through the channel access flow chart will generate a 16-bit crc that is the result of clearing the crc generator and then shifting in the new data byte(s). this algorithm is valid for all accesse s to the pio channels, continuous reading or writing as well as toggling between read and write. the comparison of crc values and decision to continue with an operation are determined entirely by the bus master. there is no circuitry on the ds2406 that prevents a command sequence from proceeding if a crc error occurs. for more details on generating crc values including example implementations in both hardware and software, see the ?book of ds19xx ibutton standards?. crc-16 hardware description and polynomial figure 17 input data r polynomial = x 16 + x 15 + x 2 + 1 x 2 x 1 x 0 x 8 x 7 x 6 x 5 x 4 x 3 8th stage 7th stage 6th stage 5th stage 4th stage 3rd stage 2nd stage 1st stage s x 15 x 14 x 13 x 12 x 11 x 10 x 9 9th stage 10th stage 11th stage 12th stage 13th stage 14th stage 15th stage 16th stage crc output x 16
ds2406 28 of 31 absolute maximum ratings* voltage on data or pio-a to ground -0.5v to +13.0v voltage on v cc or pio-b to ground -0.5v to +6.5v operating temperature range -40c to +85c storage temperature range -55c to +125c soldering temperature see j-std-020a specifications * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. dc electrical characteristics data pin (v pup =2.8v to 6.0v; -40c to +85c) parameter symbol min typ max units notes 1-wire input high v ih 2.2 v 1, 6 1-wire input low v il -0.3 0.8 v 1, 13 1-wire output low @ 4ma v ol 0.4 v 1 1-wire output high v oh v pup 6.0 v 1, 2 input load current i l 5a3 programming voltage @ 10ma v pp 11.5 12.0 v dc electrical characteristics pio pins (v pup =2.8v to 6.0v; -40c to +85c) parameter symbol min typ max units notes logic 1 (a) v iha 2.2 12 v 1, 6 logic 0 (a) v ila -0.3 0.6 v 1 output sink current @ 4v (a) i sa see graph on page 30 ma 11, 12 output logic high (a) v oha v pupa 12.0 v 1, 2 logic 1 (b) v ihb 2.2 6.0 v 1, 6 logic 0 (b) v ilb -0.3 0.4 v 1 output sink current @ 4v (b) i sb see graph on page 30 ma output logic high (b) v ohb v pupb 6.0 v 1, 2 input resistance r i 71013 m 9 dc electrical characteristics v cc (v pup =2.8v to 6.0v; -40c to +85c) parameter symbol min typ max units notes logic 1 v ihc 2.8 6.0 v 1, 10 logic 0 v ilc -0.3 0.8 v 1 input current i cc 4.0 a 3
ds2406 29 of 31 capacitances (t a = 25c) parameter symbol min typ max units notes capacitance data pin c d 800 pf 7 capacitance pio-a pin c a 100 pf capacitance pio-b pin c b 25 pf capacitance v cc pin c c 10 pf ac electrical characteristics (v pup =2.8v to 6.0v; -40c to +85c) parameter symbol min typ max units notes time slot t slot 60 120 s write 1 low time t low1 115s16 write 0 low time t low0 60 120 s read low time t lowr 115s16 read data valid t rdv 15 s 15 release time t release 01545s read data setup 1-wire t su 1s 5 recovery time t rec 1s reset high time t rsth 480 s 4 reset low time t rstl 480 960 s 8 presence detect high t pdh 15 60 s presence detect low t pdl 60 240 s read data setup pio-a t sua 0.5 s read data setup pio-b t sub 0.5 s delay to program t dp 5s delay to verify t dv 5s program pulse width t pp 480 5000 s 14 program voltage rise time t rp 0.5 5.0 s program voltage fall time t fp 0.5 5.0 s definition of pio read data setup time 1-wire t sua, t sub pio-a, pio-b
ds2406 30 of 31 pio sink current 10 ma 20 ma 30 ma 40 ma 50 ma 60 ma 70 ma 80 ma 90 ma 100 ma i sa , i sb @ 0.4v v pup pio-b max. min. pio-a max. min. 4v 5v 6v 2.8v notes: 1. all voltages are referenced to ground. 2. v pup , v pupa , v pupb = external pull-up voltage. 3. input load is to ground. 4. an additional reset or communica tion sequence cannot begin until th e reset high time has expired. 5. read data setup time refers to the time the host must pull the 1-wire bus low to read a bit. data is guaranteed to be valid within 1s of this fallin g edge and will remain valid for 14s minimum (15s total from falling edge on 1-wire bus). 6. v ih is a function of the chip-internal supply voltage. th is voltage is determined by either the external pull-up resistor and v pup or the v cc supply, whichever is higher. without v cc supply, v ih for either pio pin should always be greater than or equal to v pup -0.3v. 7. capacitance on the data pin could be 800pf when power is first applied. if a 5k resistor is used to pull up the data line to v pup , 5s after power has been applied the parasite capacitance will not affect normal communications. 8. the reset low time (t rstl ) should be restricted to a maximum of 960 s to allow interrupt signaling; otherwise, it could mask or conceal interrupt pulses. 9. input resistance is to ground. 10. v cc must be at least 4.0v if it is to be connected during a programming pulse. 11. if the current at pio-a reaches 200ma the gate vo ltage of the output transi stor will be reduced to limit the sink current to 200ma. the user-supplied ci rcuitry should limit the current flow through the pio-transistor to no more than 100ma. otherwise the ds2406 may be damaged. 12. pio-a has a controlled turn-on output. the indicated currents are dc values. at v pup = 4.0v or higher the sink current typically reaches 80% of its dc value 1 s after turning on the transistor. 13. under certain low voltage conditions v ilmax may have to be reduced to as much as 0.5v to always guarantee a presence pulse. 14. the accumulative duration of the programming pul ses for each address must not exceed 5ms. 15. the optimal sampling point for the master is as close as possible to the end time of the 15 s t rdv period without exceeding t rdv . for the case of a read-one time slot, this maximizes the amount of time for the pull-up resistor to recover the line to a high level. for a read-zero time slot it ensures that a read will occur before the fastest 1-wire devices(s) release the line (t release = 0).
ds2406 31 of 31 16. the duration of the low pulse sent by the master should be a minimum of 1 s with a maximum value as short as possible to allow time for the pull-up resistor to recover the line to a high level before the 1-wire device samples in the case of a write 1 low time, or before the master samples in the case of a read low time.

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