View EL5375_1321568.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 ? fn7306.6 el5175, EL5375 550mhz differential line receivers the el5175 and EL5375 are single and triple high bandwidth amplifiers designed to extract the difference signal from noisy environments. they are primarily targeted for applications such as receiving signals from twisted-pair lines or any application where common mode noise injection is likely to occur. the el5175 and EL5375 are stable for a gain of one and requires two external resistors to set the voltage gain for each channel. the output common mode level is set by the reference pin (v ref ), which has a -3db band width of over 450mhz. generally, this pin is grounded but it can be tied to any voltage reference. the output can deliver a maximum of 60ma and is short circuit protected to withstand a temporary overload condition. the el5175 is available in the 8 ld soic and 8 ld msop packages and the EL5375 in the 24 ld qsop package. all are specified for operation over the full -40c to +85c temperature range. pinouts features ? differential input range 2.3v ? 550mhz 3db bandwidth ? 900v/s slew rate ? 60ma maximum output current ? single 5v or dual 5v supplies ? low power, 9.6ma per channel ? pb-free plus anneal available (rohs compliant) applications ? twisted-pair receivers ? differential line receivers ? vga over twisted-pair ? adsl/hdsl receivers ? differential to single-ended amplification ? reception of analog signals in a noisy environment 1 2 3 4 16 15 14 13 5 6 7 12 11 9 8 10 20 19 18 17 24 23 22 21 ref1 inp1 inn1 nc ref2 inp2 inn2 nc ref3 inp3 inn3 nc nc fb1 out1 nc vsp vsn nc fb2 out2 en fb3 out3 - + - + - + EL5375 (24 ld qsop) top view 1 2 3 4 8 7 6 5 - + out vs- vs+ en fb in+ in- ref el5175 (8 ld soic, msop) top view data sheet may 10, 2007 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-352-6832 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2004, 2005, 2007. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn7306.6 ordering information part number part marking tape & reel package pkg. dwg. # el5175is 5175is - 8 ld soic (150 mil) mdp0027 el5175is-t7 5175is 7? 8 ld soic (150 mil) mdp0027 el5175is-t13 5175is 13? 8 ld soic (150 mil) mdp0027 el5175isz (note) 5175isz - 8 ld soic (pb-free) (150 mil) mdp0027 el5175isz-t7 (note) 5175isz 7? 8 ld soic (pb-free) (150 mil) mdp0027 el5175isz-t13 (note) 5175isz 13? 8 ld soic (pb-free) (150 mil) mdp0027 el5175iy 5 - 8 ld msop (3.0mm) mdp0043 el5175iy-t7 5 7? 8 ld msop (3.0mm) mdp0043 el5175iy-t13 5 13? 8 ld msop (3.0mm) mdp0043 el5175iyz (note) baaab - 8 ld msop (pb-free) (3.0mm) mdp0043 el5175iyz-t7 (note) baaab 7? 8 ld msop (pb-free) (3.0mm) mdp0043 el5175iyz-t13 (note) baaab 13? 8 ld msop (pb-free) (3.0mm) mdp0043 EL5375iu EL5375iu - 24 ld qsop (150 mil) mdp0040 EL5375iu-t7 EL5375iu 7? 24 ld qsop (150 mil) mdp0040 EL5375iu-t13 EL5375iu 13? 24 ld qsop (150 mil) mdp0040 EL5375iuz (note) EL5375iuz - 24 ld qsop (pb-free) (150 mil) mdp0040 EL5375iuz-t7 (note) EL5375iuz 7? 24 ld qsop (pb-free) (150 mil) mdp0040 EL5375iuz-t13 (note) EL5375iuz 13? 24 ld qsop (pb-free) (150 mil) mdp0040 note: intersil pb-free plus anneal products employ special pb-free material sets; mo lding compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free p roducts are msl classified at pb-free peak reflow temper atures that meet or exceed the pb-free requirements of ipc/jedec j std-020. el5175, EL5375
3 fn7306.6 important note: all parameters having min/max specifications are guaranteed. typ values are for information purposes only. unles s otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a absolute maxi mum ratings (t a = +25c) thermal information supply voltage (v s + to v s -) . . . . . . . . . . . . . . . . . . . . . . . . . . . .12v maximum output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60ma operating junction temperature . . . . . . . . . . . . . . . . . . . . . . +135c ambient operating temperature . . . . . . . . . . . . . . . .-40c to +85c storage temperature range . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. electrical specifications v s + = +5v, v s - = -5v, t a = +25c, v in = 0v, r l = 500 , r f = 0, r g = open, c l = 2.7pf, unless otherwise specified. parameter description conditions min typ max unit ac performance bw -3db bandwidth a v =1, c l = 2.7pf 550 mhz a v =2, r f = 806, c l = 2.7pf 190 mhz a v =10, r f = 806, c l = 2.7pf 20 mhz bw 0.1db bandwidth a v =1, c l = 2.7pf 60 mhz sr slew rate v out = 3v p-p , 20% to 80%, r l = 100 600 v/s v out = 3v p-p , 20% to 80%, r l = 500 900 v/s t stl settling time to 0.1% v out = 2v p-p 10 ns t ovr output overdrive recovery time 20 ns gbwp gain bandwidth product 200 mhz v ref bw (-3db) v ref -3db bandwidth a v =1, c l = 2.7pf 450 mhz v ref sr v ref slew rate v out = 2v p-p , 20% to 80% 1000 v/s v n input voltage noise at f = 10khz 21 nv/ hz i n input current noise at f = 10khz 2.7 pa/ hz hd2 second harmonic distortion v out = 1v p-p , 5mhz -70 dbc hd2 second harmonic distortion v out = 1v p-p , 5mhz -66 dbc hd3 third harmonic distortion v out = 1v p-p , 5mhz -94 dbc hd3 third harmonic distortion v out = 1v p-p , 5mhz -84 dbc dg differential gain at 3.58mhz r l = 150 , a v =2 0.1 % d differential phase at 3.58mhz r l = 150 , a v =2 0.1 e s channel separation (EL5375) at f = 100khz 90 db input characteristics v os input referred offset voltage el5175 -3 40 mv EL5375 -3 30 mv i in input bias current (v in , v inb , v ref ) -25 -12.5 -6 a r in differential input resistance 150 k c in differential input capacitance 1pf dmir differential mode input range 2.1 2.3 2.5 v cmir common mode input range at v in +, v in - -4.3 +3.3 v v refin reference input voltage range v in + = v in - = 0v -3.6 3.3 v el5175, EL5375
4 fn7306.6 cmrr input common mode rejection ratio v in = 2.5v 75 95 db gain gain accuracy el5175, v in = 1v 0.979 0.994 1.009 v EL5375, v in = 1v 0.977 0.992 1.007 v output characteristics v out positive output voltage swing r l = 500 to gnd 3.3 3.54 v negative output voltage swing r l = 500 to gnd -3.95 -3.6 v i out (max) maximum output current r l = 10 40 67 ma r out output impedance 130 m supply v supply supply operating range v s + to v s -4.7511v i s (on) power supply current per channel - enabled 89.611ma i s (off) + positive power supply current - disabled en pin tied to 4.8v, el5175 80 100 a en pin tied to 4.8v, EL5375 1.7 5 a i s (off) - negative power supply current - disabled -150 -120 -90 a psrr power supply rejection ratio v s from 4.5v to 5.5v 45 56 db enable t en enable time 80 ns t ds disable time 1.2 s v ih en pin voltage for power-up v s + - 1.5 v v il en pin voltage for shut-down v s + - 0.5 v i ih-en en pin input current high per channel at v en = 5v 40 60 a i il-en en pin input current low per channel at v en = 0v -10 -3 a electrical specifications v s + = +5v, v s - = -5v, t a = +25c, v in = 0v, r l = 500 , r f = 0, r g = open, c l = 2.7pf, unless otherwise specified. (continued) parameter description conditions min typ max unit el5175, EL5375
5 fn7306.6 pin descriptions el5175 EL5375 pin name pin function 1 fb feedback input 2 in+ non-inverting input 3 in- inverting input 4 ref sets the common mode output voltage level to v ref 5en enabled when this pin is floating or the applied voltage v s + - 1.5 6 vs+ positive supply voltage 7 vs- negative supply voltage 8 out output voltage 1, 5, 9 ref1, 2, 3 reference input, controls common-mode output voltage 2, 6, 10 inp1, 2, 3 non-inverting inputs 3, 7, 11 inn1, 2, 3 inverting inputs 4, 8, 12, 18, 21, 24 nc no connect, grounded for best crosstalk performance 13, 16, 22 out1, 2, 3 non-inverting outputs 14, 17, 23 fb1, 2, 3 feedback from outputs 15 en enabled when this pin is floating or the applied voltage v s + - 1.5 19 vsn negative supply 20 vsp positive supply el5175, EL5375
6 fn7306.6 connection diagrams 1 2 3 4 16 15 14 13 5 6 7 12 11 9 8 10 20 19 18 17 24 23 22 21 ref1 inp1 inn1 nc ref2 inp2 inn2 nc ref3 inp3 inn3 nc nc fb1 out1 nc vsp vsn nc fb2 out2 en fb3 out3 r sr3 50 r sn3 50 r sp3 50 r sr2 50 r sn2 50 r sp2 50 r sr1 50 r sn1 50 r sp1 50 ref1 inp1 inn1 ref2 inp2 inn2 ref3 inp3 inn3 +5v c l2 2.7pf c l3 2.7pf out3 out1 r g r f r l1 500 c l1 2.7pf -5v out2 r g r f r l2 500 enable r l3 500 r g r f fb inp inn ref out vsn vsp en 1 2 3 4 8 7 6 5 inp inn ref r g r s2 50 r s3 50 en vout -5v +5v r s2 50 c l 2.7pf r l 500 r f= 0 el5175 el5175 el5175, EL5375
7 fn7306.6 typical performance curves figure 1. frequency response vs supply voltage f igure 2. frequency response vs supply voltage figure 3. frequency response vs various gain figure 4. frequency response vs c l figure 5. frequency response vs c l figure 6. frequency response for various r f a v =1 r l =500 c l =2.7pf 1m 10m 100m 1g frequency (hz) magnitude (db) 4 2 0 -2 -4 -6 v s =2.5v v s =5v a v =1 r l =100 c l =2.7pf 1m 10m 100m 1g frequency (hz) magnitude (db) 4 2 0 -2 -4 -6 v s =2.5v v s =5v v s =5v r l =500 c l =2.7pf 1m 10m 100m 1g frequency (hz) normalized gain (db) 4 2 0 -2 -4 -6 a v =10 a v =5 a v =2 a v =1 v s =5v r l =500 a v =1 1m 10m 100m 1g frequency (hz) magnitude (db) 5 3 1 -1 -3 -5 c l =2.7pf c l =15pf c l =10pf c l =0pf v s =2.5v r l =500 a v =1 1m 10m 100m 1g frequency (hz) magnitude (db) 5 3 1 -1 -3 -5 c l =2.7pf c l =15pf c l =10pf c l =0pf 1m 10m 100m 1g frequency (hz) normalized gain (db) 4 2 0 -2 -4 -6 v s =5v r l =500 a v =2 c l =2.7pf r f =1k r f =806 r f =500 r f =200 el5175, EL5375
8 fn7306.6 figure 7. frequency response for v ref figure 8. open loop gain figure 9. output impedance vs frequency figure 10. psrr vs frequency figure 11. cmrr vs frequency figure 12. voltage and current noise vs frequency typical performance curves (continued) 1m 10m 100m 1g frequency (hz) normalized gain (db) 4 2 0 -2 -4 -6 r l =500 a v =1 c l =2.7pf v s =2.5v v s =5v gain (db) 60 40 20 0 -20 -40 10k 100k 10m frequency (hz) 1m 100m 1g phase () 90 0 -90 -180 -270 -360 10k 100k 1m 100m frequency (hz) impedance ( ) 100 10 1 0.1 10m psrr (db) 30 10 -10 -50 -70 -90 10k 100k 10m frequency (hz) 1m 100m psrr+ psrr- -30 cmrr (db) 120 100 80 40 20 -90 1k 10k 10m frequency (hz) 1m 1g 60 100m 100k e n i n voltage noise (nv/ hz), current noise (pa/ hz) 1k 100 10 1 10 100 100k frequency (hz) 10k 10m 1m 1k el5175, EL5375
9 fn7306.6 figure 13. channel isolation vs frequency (EL5375 only) figure 14. harmonic distortion vs output voltage figure 15. harmonic distortion vs load resistance figure 16. harmonic distortion vs frequency figure 17. small signal transient response f igure 18. large signal transient response typical performance curves (continued) gain (db) 0 -20 -60 -80 -100 100k 1m frequency (hz) 100m 1g -40 10m ch1 ? ch2, ch2 ? ch3 ch1 ? ch3 v s =5v f=5mhz r l =500 1357 v op-p (v) distortion (db) -40 -50 -60 -70 -80 -100 h d 2 ( a v = 2 ) 246 -90 h d 2 ( a v = 1 ) h d 3 ( a v = 2 ) h d 3 ( a v = 1 ) hd2 (a v =2) h d 3 ( a v = 2 ) h d 3 ( a v = 1 ) 100 400 800 1k r load ( ) distortion (db) -50 -100 200 600 900 500 300 700 -60 -70 -80 -90 h d 2 ( a v = 1 ) v s =5v f=5mhz v op-p =1v (a v =1) v op-p =2v (a v =2) h d 2 ( a v = 2 ) 015 3540 r load ( ) distortion (db) -50 -100 525 20 10 30 -60 -70 -80 -90 v s =5v r l =500 v op-p =1v (a v =1) v op-p =2v (a v =2) h d 2 ( a v = 1 ) h d 3 ( a v = 2 ) h d 3 ( a v = 1 ) 10ns/div 50mv/div 10ns/div 0.5v/div el5175, EL5375
10 fn7306.6 simplified schematic figure 19. enabled response f igure 20. disabled response figure 21. package power dissipation vs ambient temperature figure 22. package power dissipation vs ambient temperature typical performance curves (continued) 100ns/div ch1 ch2 m=100ns ch1=200mv/div ch2=5v/div 400ns/div ch1 ch2 m=400ns ch1=200mv/div ch2=5v/div jedec jesd51-3 low effective thermal conductivity test board 870mw 625mw 486mw qsop24 ja =115c/w so8 ja =160c/w msop8 ja =206c/w 0 ambient temperature (c) 25 125 150 85 100 50 75 power dissipation (w) 1.2 1 0.2 0 0.6 0.4 0.8 jedec jesd51-7 high effective thermal conductivity test board 0 ambient temperature (c) power dissipation (w) 1.4 25 125 150 85 100 50 75 1.2 0.2 0 0.6 0.4 1 0.8 1.136w 909mw 870mw msop8 ja =115c/w so8 ja =110c/w qsop24 ja =88c/w r 2 r 1 r 4 r 3 r d2 r d1 q 8 fb q 4 v ref q 3 vin- q 2 vin+ q 1 q 6 v s + i 4 i 3 i 2 i 1 q 7 v b1 v s - 25 q 9 v b2 x1 v out c c el5175, EL5375
11 fn7306.6 description of operat ion and application information product description the el5175 and EL5375 are wide bandwidth, low power and single/differential ended to single ended output amplifiers. the el5175 is a single channel differential to single ended amplifier. the EL5375 is a triple channel differential to single ended amplifier. the el5175 and EL5375 are internally compensated for closed loop gain of +1 of greater. connected in gain of 1 and driving a 500 load, the el5175 and EL5375 have a -3db bandwidth of 550mhz. driving a 150 load at gain of 2, the bandwidth is about 130mhz. the bandwidth at the ref input is about 450mhz. the el5175 and EL5375 is available with a power down feature to reduce the power while the amplifier is disabled. input, output, and supply voltage range the el5175 and EL5375 have been designed to operate with a single supply voltage of 5v to 10v or a split supplies with its total voltage from 5v to 10v. the amplifiers have an input common mode voltage range from -4.3v to 3.3v for 5v supply. the differential mode input range (dmir) between the two inputs is about from -2.3v to +2.3v. the input voltage range at the ref pin is from -3.6v to 3.3v. if the input common mode or differential mode signal is outside the above-specified ranges, it will cause the output signal distorted. the output of the el5175 and EL5375 can swing from -3.9v to 3.5v at 500 load at 5v supply. as the load resistance becomes lower, the output swing is reduced respectively. over all gain settings the gain setting for the el5175 and EL5375 is similar to the conventional operational amplif ier. the output voltage is equal to the difference of the inputs plus v ref and then times the gain. figure 23. choice of feedback resistor and gain bandwidth product for applications that require a gain of +1, no feedback resistor is required. just short the out+ pin to fbp pin and out- pin to fbn pin. for gains greater than +1, the feedback resistor forms a pole with the parasitic capacitance at the inverting input. as this pole becomes smaller, the amplifier's phase margin is reduced. this causes ringing in the time domain and peaking in the frequency domain. therefore, r f has some maximum value that should not be exceeded for optimum performanc e. if a large value of r f must be used, a small capacitor in the few pico farad range in parallel with r f can help to reduce the ringing and peaking at the expense of reducing the bandwidth. the bandwidth of the el5175 and EL5375 depends on the load and the feedback network. r f and r g appear in parallel with the load for gains other than +1. as this combination gets smaller, the bandwidth falls off. consequently, r f also has a minimum value that should not be exceeded for optimum bandwidth performance. for gain of +1, r f = 0 is optimum. for the gains other than +1, optimum response is obtained with r f between 500 to 1k . for a v = 2 and r f = r g = 806 , the bw is about 190mhz and the frequency response is very flat. the el5175 and EL5375 have a gain bandwidth product of 200mhz. for gains 5, its bandwidth can be predicted by the following equation: driving capacitive loads and cables the el5175 and EL5375 can drive 15pf capacitance in parallel with 500 load to ground with less than 4.5db of peaking at gain of +1. if less peaking is desired in applications, a small series resistor (usually between 5 to 50 ) can be placed in series with each output to eliminate most peaking. however, this will reduce the gain slightly. if the gain setting is greater th an 1, the gain resistor r g can then be chosen to make up for any gain loss which may be created by the additional seri es resistor at the output. when used as a cable driver, double termination is always recommended for reflection-free performance. for those applications, a back-termination series resistor at the amplifier's output will isolate the amplifier from the cable and allow extensive capacitive drive. however, other applications may have high capacitive loads without a back-termination resistor. again, a small series resistor at the output can help to reduce peaking. disable/power-down the el5175 and EL5375 can be disabled and placed its outputs in a high impedance state. the turn off time is about 1.2s and the turn on time is about 80ns. when disabled, the amplifier's supply current is reduced to 80a for i s + and v o v ( in +v in -v ref + ) 1 r f r g -------- + ?? ?? ?? ? = - + - + g/b v o en v in + v in - v ref fb r g r f gain bw 200mhz = el5175, EL5375
12 fn7306.6 120a for i s - typically, thereby effe ctively eliminating the power consumption. the amplifier's power down can be controlled by standard cmos signal levels at the enable pin. the applied logic signal is relative to v s + pin. letting the en pin float or applying a signal that is less than 1.5v below v s + will enable the amplifier. the amplifier will be disabled when the signal at en pin is above v s + - 0.5v. if a ttl signal is used to control the enabled/disabled function, figure 22 could be used to convert the ttl signal to cmos signal. figure 24. output drive capability the el5175 and EL5375 have internal short circuit protection. its typical short circ uit current is 67ma. if the output is shorted indefinitely, the power dissipation could easily increase such that the part will be destroyed. maximum reliability is maintained if the output current never exceeds 60ma. this limit is set by the design of the internal metal interconnections. power dissipation with the high output drive capability of the el5175 and EL5375. it is possible to exceed the 135c absolute maximum junction temperature under certain load current conditions. therefore, it is important to calculate the maximum junction temperature for the application to determine if the load conditions or package types need to be modified for the amplifier to remain in the safe operating area. the maximum power dissipation allowed in a package is determined according to: ?t jmax = maximum junction temperature ?t amax = maximum ambi ent temperature ? ja = thermal resistance of the package assume the ref pin is tired to gnd for v s = 5v application, the maximum power dissipation actually produced by an ic is the total quiescent supply current times the total power supply voltage, plus the power in the ic due to the load, or: for sourcing: for sinking: where: ?v s = total supply voltage ?i smax = maximum quiescent supply current per channel ?v out = maximum output voltage of the application ?r load = load resistance ?i load = load current ? i = number of channels by setting the two pd max equations equal to each other, we can solve the output current and r load to avoid the device overheat. power supply bypassing and printed circuit board layout as with any high frequency device, a good printed circuit board layout is necessary for optimum performance. lead lengths should be as sort as possible. the power supply pin must be well bypassed to reduce the risk of oscillation. for normal single supply operation, where the v s - pin is connected to the ground plane, a single 4.7f tantalum capacitor in parallel with a 0. 1f ceramic capacitor from v s + to gnd will suffice. this same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. in this case, the v s - pin becomes the negative supply rail. for good ac performance, parasitic capacitance should be kept to minimum. use of wire wound resistors should be avoided because of their additional series inductance. use of sockets should also be avoided if possible. sockets add parasitic inductance and capacitance that can result in compromised performance. minimizing parasitic capacitance at the amplifier's inverting in put pin is very important. the feedback resistor should be placed very close to the inverting input pin. strip line design techniques are recommended for the signal traces. 1k 10k 5v en cmos/ttl pd max t jmax t amax ? ja -------------------------------------------- - = pd max v s i smax v s + ( v out ) v out r load ------------------- - i ? + = pd max v s i smax v out ( v s - ) i load ] i ? + [ = el5175, EL5375
13 fn7306.6 typical applications figure 25. twisted pair cable receiver as the signal is transmitted through a cable, the high frequency signal will be attenuated. one way to compensate this loss is to boost the high frequency gain at the receiver side. figure 26. compensated line receiver level shifter and signal summer the el5175 and EL5375 contains two pairs of differential pair input stages. it makes the inputs are all high impedance inputs. to take advantage of the two high impedance inputs, the el5175 and EL5375 can be used as a signal summer to add two signals together. like, one signal can be applied to v in +, the second signal can be applied to ref and v in - is ground. the output is equal to: also, the el5175 and EL5375 can be used as a level shifter by applying a level control signal to the ref input. 0 v fb v inb v ref el5175/ EL5375 el5173/ el5373 v out 50 50 z o = 100 v in 50 50 r 2 v fb v inb v ref el5175/ EL5375 v out v in 50 50 r 1 r 3 c 1 z o = 100 f a f c f gain (db) 1 + r 2 / r 1 1 + r 2 / (r 1 + r 3 ) v o v in ( +v ref ) gain + = el5175, EL5375
14 fn7306.6 el5175, EL5375 small outline package family (so) gauge plane a2 a1 l l1 detail x 4 4 seating plane e h b c 0.010 b m ca 0.004 c 0.010 b m ca b d (n/2) 1 e1 e n n (n/2)+1 a pin #1 i.d. mark h x 45 a see detail ?x? c 0.010 mdp0027 small outline package family (so) symbol inches tolerance notes so-8 so-14 so16 (0.150?) so16 (0.300?) (sol-16) so20 (sol-20) so24 (sol-24) so28 (sol-28) a 0.068 0.068 0.068 0.104 0.104 0.104 0.104 max - a1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 0.003 - a2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 0.001 - d 0.193 0.341 0.390 0.406 0.504 0.606 0.704 0.004 1, 3 e 0.236 0.236 0.236 0.406 0.406 0.406 0.406 0.008 - e1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 basic - l 0.025 0.025 0.025 0.030 0.030 0.030 0.030 0.009 - l1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 reference - n 8 14 16 16 20 24 28 reference - rev. m 2/07 notes: 1. plastic or metal protrusions of 0.006? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions ?d? and ?e1? are measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m - 1994
15 fn7306.6 el5175, EL5375 mini so package family (msop) 1 (n/2) (n/2)+1 n plane seating n leads 0.10 c pin #1 i.d. e1 e b detail x 3 3 gauge plane see detail "x" c a 0.25 a2 a1 l 0.25 c a b d a m b e c 0.08 c a b m h l1 mdp0043 mini so package family symbol millimeters tolerance notes msop8 msop10 a1.101.10 max. - a1 0.10 0.10 0.05 - a2 0.86 0.86 0.09 - b 0.33 0.23 +0.07/-0.08 - c0.180.18 0.05 - d 3.00 3.00 0.10 1, 3 e4.904.90 0.15 - e1 3.00 3.00 0.10 2, 3 e0.650.50 basic - l0.550.55 0.15 - l1 0.95 0.95 basic - n 8 10 reference - rev. d 2/07 notes: 1. plastic or metal protrusions of 0.15mm maximum per side are not included. 2. plastic interlead protrusions of 0.25mm maximum per side are not included. 3. dimensions ?d? and ?e1? are measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m-1994.
16 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn7306.6 el5175, EL5375 quarter size outline plast ic packages family (qsop) 0.010 c a b seating plane detail x e e1 1 (n/2) (n/2)+1 n pin #1 i.d. mark b 0.004 c c a see detail "x" a2 44 gauge plane 0.010 l a1 d b h c e a 0.007 c a b l1 mdp0040 quarter size outline plastic packages family symbol inches tolerance notes qsop16 qsop24 qsop28 a 0.068 0.068 0.068 max. - a1 0.006 0.006 0.006 0.002 - a2 0.056 0.056 0.056 0.004 - b 0.010 0.010 0.010 0.002 - c 0.008 0.008 0.008 0.001 - d 0.193 0.341 0.390 0.004 1, 3 e 0.236 0.236 0.236 0.008 - e1 0.154 0.154 0.154 0.004 2, 3 e 0.025 0.025 0.025 basic - l 0.025 0.025 0.025 0.009 - l1 0.041 0.041 0.041 basic - n 16 24 28 reference - rev. f 2/07 notes: 1. plastic or metal protrusions of 0.006? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions ?d? and ?e1? are measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m-1994.

▲Up To Search▲

Price & Availability of EL5375

	To Download EL5375 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .