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isplsi 2032v 3.3v high density programmable logic 2032v_10 1 use isplsi 2032ve for new designs features high density programmable logic 1000 pld gates 32 i/o pins, two dedicated inputs 32 registers high speed global interconnect wide input gating for fast counters, state machines, address decoders, etc. small logic block size for random logic 3.3v low voltage 2032 architecture interfaces with standard 5v ttl devices 60 ma typical active current fuse map compatible with 5v isplsi 2032 high performance e 2 cmos technology f max = 100 mhz maximum operating frequency t pd = 7.5 ns propagation delay electrically erasable and reprogrammable non-volatile 100% tested at time of manufacture in-system programmable 3.3v in-system programmability using boundary scan test access port (tap) open-drain output option for flexible bus interface capability, allowing easy implementation of wired-or or bus arbitration logic increased manufacturing yields, reduced time-to- market and improved product quality the ease of use and fast system speed of plds with the density and flexibility of fpgas enhanced pin locking capability three dedicated clock input pins synchronous and asynchronous clocks programmable output slew rate control flexible pin placement optimized global routing pool provides global interconnectivity ispdesignexpert ?logic compiler and com- plete isp device design systems from hdl synthesis through in-system programming superior quality of results tightly integrated with leading cae vendor tools productivity enhancing timing analyzer, explore tools, timing simulator and ispanalyzer pc and unix platforms functional block diagram global routing pool (grp) a0 a1 a3 input bus output routing pool (orp) a7 a6 a5 a4 input bus output routing pool (orp) a2 glb logic array dq dq dq dq 0139bisp/2000 description the isplsi 2032v is a high density programmable logic device that can be used in both 3.3v and 5v systems. the device contains 32 registers, 32 universal i/o pins, two dedicated input pins, three dedicated clock input pins, one dedicated global oe input pin and a global routing pool (grp). the grp provides complete interconnectivity between all of these elements. the isplsi 2032v features in-system programmability through the boundary scan test access port (tap). the isplsi 2032v offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. the basic unit of logic on the isplsi 2032v device is the generic logic block (glb). the glbs are labeled a0, a1 .. a7 (see figure 1). there are a total of eight glbs in the isplsi 2032v device. each glb is made up of four macrocells. each glb has 18 inputs, a programmable and/or/exclusive or array, and four outputs which can be configured to be either combinatorial or registered. inputs to the glb come from the grp and dedicated inputs. all of the glb outputs are brought back into the grp so that they can be connected to the inputs of any glb on the device. copyright ?2000 lattice semiconductor corp. all brand or product names are trademarks or registered trademarks of their respec tive holders. the specifications and information herein are subject to change without notice. lattice semiconductor corp., 5555 northeast moore ct., hillsboro, oregon 97124, u.s.a. september 2000 tel. (503) 268-8000; 1-800-lattice; fax (503) 268-8556; http://www.latticesemi.com
specifications isplsi 2032v 2 use isplsi 2032ve for new designs functional block diagram figure 1. isplsi 2032v functional block diagram the device also has 32 i/o cells, each of which is directly connected to an i/o pin. each i/o cell can be individually programmed to be a combinatorial input, output or bi- directional i/o pin with 3-state control. the signal levels are ttl compatible voltages and the output drivers can source 4 ma or sink 8 ma. each output can be pro- grammed independently for fast or slow output slew rate to minimize overall output switching noise. device pins can be safely driven to 5 volt signal levels to support mixed-voltage systems. eight glbs, 32 i/o cells, two dedicated inputs and two orps are connected together to make a megablock (see figure 1). the outputs of the eight glbs are connected to a set of 32 universal i/o cells by the orp. each isplsi 2032v device contains one megablock. the grp has as its inputs the outputs from all of the glbs and all of the inputs from the bi-directional i/o cells. all of these signals are made available to the inputs of the glbs. delays through the grp have been equalized to minimize timing skew. clocks in the isplsi 2032v device are selected using the dedicated clock pins. three dedicated clock pins (y0, y1, y2) or an asynchronous clock can be selected on a glb basis. the asynchronous or product term clock can be generated in any glb for its own clock. programmable open-drain outputs in addition to the standard output configuration, the outputs of the isplsi 2032v are individually program- mable, either as a standard totem-pole output or an open-drain output. the totem-pole output drives the specified voh and vol levels, whereas the open-drain output drives only the specified vol. the voh level on the open-drain output depends on the external loading and pull-up. this output configuration is controlled by a pro- grammable fuse. when this fuse is erased (jedec ??, the output is configured as a totem-pole output. when this fuse is programmed (jedec ??, the output is configured as an open-drain. the default configuration when the device is in bulk erased state is totem-pole configuration. the open-drain/totem-pole option is se- lectable through the ispdesignexpert software tools. global routing pool (grp) a0 a1 a3 input bus output routing pool (orp) a7 a6 a5 a4 input bus output routing pool (orp) a2 clk 0 clk 1 clk 2 goe 0 note: *y1 and reset are multiplexed on the same pin i/o 0 i/o 1 i/o 2 i/o 3 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 31 i/o 30 i/o 29 i/o 28 i/o 27 i/o 26 i/o 25 i/o 24 i/o 23 i/o 22 i/o 21 i/o 20 i/o 19 i/o 18 i/o 17 i/o 16 tdi/in 0 tdo/in 1 i/o 4 i/o 5 y0 y1* tck/y2 ispen tms/nc 0139b/2032v generic logic blocks (glbs)
specifications isplsi 2032v 3 use isplsi 2032ve for new designs storage temperature .............................. -65 to +150 c case temp. with power applied .............. -55 to 125 c max. junction temp. (t j ) with power applied ... 150 c 1. stresses above those listed under the absolute maximum ratings may cause permanent damage to the device. functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specifica tion is not implied (while programming, follow the programming specifications). dc recommended operating condition capacitance (t a =25 c, f=1.0 mhz) data retention specifications table 2-0008a-2032-isp parameter data retention minimum maximum units isplsi erase/reprogram cycles 20 10000 years cycles t a = 0 c to + 70 c t a = -40 c to + 85 c symbol table 2 - 0005/2032lv v cc v ih v il parameter supply voltage input high voltage input low voltage min. max. units 3.0 3.0 2.0 v 0.5 3.6 3.6 5.25 0.8 v v v v ss commercial industrial absolute maximum ratings 1 supply voltage v cc .................................. -0.5 to +5.6v input voltage applied ............................... -0.5 to +5.6v off-state output voltage applied ............ -0.5 to +5.6v c symbol table 2-0006/2032lv c parameter i/o capacitance 8 units typical test conditions 1 2 8 dedicated input capacitance pf pf v = 3.3v, v = 2.0v v = 3.3v, v = 2.0v cc cc i/o in c clock and global output enable capacitance 13 3 pf v = 3.3v, v = 2.0v cc y
specifications isplsi 2032v 4 use isplsi 2032ve for new designs switching test conditions input pulse levels table 2-0003/2032v/lv input rise and fall time 10% to 90% input timing reference levels output timing reference levels output load gnd to 3.0v 1.5v 1.5v see figure 2 3-state levels are measured 0.5v from steady-state active level. 1.5 ns output load conditions (see figure 2) dc electrical characteristics over recommended operating conditions figure 2. test load + 3.3v r 1 r 2 c l * device output test point * c l includes test fixture and probe capacitance. 0213a test condition r1 r2 cl a 316 ? 348 ? 35pf b 348 ? 35pf 316 ? 348 ? 35pf active high active low c 316 ? 348 ? 5pf 348 ? 5pf active low to z at v +0.5v ol active high to z at v -0.5v oh table 2 - 0004a v ol symbol 1. one output at a time for a maximum duration of one second. v = 0.5v was selected to avoid test problems by tester ground degradation. characterized but not 100% tested. 2. measured using two 16-bit counters. 3. typical values are at v = 3.3v and t = 25 c. 4. maximum i varies widely with specific device configuration and operating frequency. refer to power consumption section of this data sheet and thermal management section of the lattice semiconductor data book or cd-rom to estimate maximum i . table 2-0007/2032v 1 v oh i ih i il i il-isp parameter i il-pu i os 2, 4 i cc output low voltage output high voltage input or i/o high leakage current input or i/o low leakage current ispen input low leakage current i/o active pull-up current output short circuit current operating power supply current i = 8 ma i = -4 ma v v 5.25v 0v v v (max.) 0v v v 0v v v v = 3.3v, v = 0.5v v = 0.0v, v = 3.0v f = 1 mhz ol oh in il in il in il cc out toggle il ih condition min. typ. max. units 3 2.4 60 0.4 10 -10 50 -150 -150 -100 v v a a ma a a ma ma cc a out cc in cc cc (v - 0.2)v v v cc in cc
specifications isplsi 2032v 5 use isplsi 2032ve for new designs external timing parameters over recommended operating conditions t pd1 units -80 min. test cond. 1. unless noted otherwise, all parameters use the grp, 20 ptxor path, orp and y0 clock. 2. refer to timing model in this data sheet for further details. 3. standard 16-bit counter using grp feedback. 4. reference switching test conditions section. table 2-0030/2032v 1 4 3 1 tsu2 + tco1 ( ) -60 min. max. max. description # 2 parameter a 1 data propagation delay, 4pt bypass, orp bypass 10.0 15.0 ns t pd2 a 2 data propagation delay ns f max a 3 clock frequency with internal feedback 80.0 61.7 mhz f max (ext.) 4 clock frequency with external feedback mhz f max (tog.) 5 clock frequency, max. toggle mhz t su1 6 glb reg. setup time before clock, 4 pt bypass ns t co1 a 7 glb reg. clock to output delay, orp bypass ns t h1 8 glb reg. hold time after clock, 4 pt bypass 0.0 ns t su2 9 glb reg. setup time before clock 9.0 ns t co2 10 glb reg. clock to output delay ns t h2 11 glb reg. hold time after clock 0.0 ns t r1 a 12 ext. reset pin to output delay ns t rw1 13 ext. reset pulse duration 7.0 ns t ptoeen b 14 input to output enable ns t ptoedis c 15 input to output disable ns t goeen b 16 global oe output enable ns t goedis c 17 global oe output disable ns t wh 18 external synchronous clock pulse duration, high 5.0 ns t wl 19 external synchronous clock pulse duration, low 5.0 ns 64.5 100 7.0 6.5 7.5 14.0 15.0 15.0 10.0 10.0 15.0 51.3 71.4 9.0 0.0 11.0 0.0 8.0 7.0 7.0 20.0 8.5 9.5 16.0 18.0 18.0 12.0 12.0 -100 min. max. 7.5 100 0.0 7.0 0.0 5.0 4.0 4.0 83.3 125 5.5 5.0 6.5 12.0 13.0 13.0 7.5 7.5 12.0
specifications isplsi 2032v 6 use isplsi 2032ve for new designs internal timing parameters 1 over recommended operating conditions t io 1. internal timing parameters are not tested and are for reference only. 2. refer to timing model in this data sheet for further details. 3. the xor adjacent path can only be used by hard macros. table 2-0036/2032v inputs units -80 min. -60 min. max. max. description # 2 parameter 20 input buffer delay 0.6 ns t din 21 dedicated input delay 1.4 ns t grp 22 grp delay 2.1 ns glb t 1ptxor 25 1 product term/xor path delay 12.3 ns t 20ptxor 26 20 product term/xor path delay 12.3 ns t xoradj 27 xor adjacent path delay 14.4 ns t gbp 28 glb register bypass delay 1.3 ns t gsu 29 glb register setup time befor clock 0.2 ns t gh 30 glb register hold time after clock 8.0 ns t gco 31 glb register clock to output delay 1.6 ns 3 t gro 32 glb register reset to output delay 2.8 ns t ptre 33 glb product term reset to register delay 9.3 ns t ptoe 34 glb product term output enable to i/o cell delay 10.4 ns t ptck 35 glb product term clock delay 6.5 9.3 ns orp t ob 38 output buffer delay 2.2 ns t sl 39 output slew limited delay adder 12.2 ns 0.4 1.3 grp 1.2 t 4ptbpc 23 4 product term bypass path delay (combinatorial) 9.6 ns t 4ptbpr 24 4 product term bypass path delay (registered) 10.3 ns 9.2 9.5 11.3 0.3 5.8 7.5 0.2 5.4 1.6 2.5 5.6 8.5 3.8 5.6 t orp 36 orp delay 1.5 ns t orpbp 37 orp bypass delay 0.5 ns 1.4 0.4 outputs 2.2 12.2 t oen 40 i/o cell oe to output enabled 4.9 ns t odis 41 i/o cell oe to output disabled 4.9 ns 4.9 4.9 t goe 42 global output enable 7.1 ns 5.1 t gy0 43 clock delay, y0 to global glb clock line (ref. clock) 2.3 4.2 4.2 ns t gy1/2 44 clock delay, y1 or y2 to global glb clock line 2.3 4.2 4.2 ns clocks 2.3 2.3 t gr 45 global reset to glb 9.5 ns global reset 7.9 -100 min. max. 0.2 0.6 0.7 6.7 7.5 8.5 0.3 4.6 6.0 0.1 3.8 1.5 2.2 3.8 7.2 3.0 4.4 1.4 0.1 1.9 11.9 4.9 4.9 2.6 1.5 1.5 1.5 1.5 6.5
specifications isplsi 2032v 7 use isplsi 2032ve for new designs isplsi 2032v timing model glb reg delay i/o pin (output) orp delay feedback reg 4 pt bypass 20 pt xor delays control pts i/o pin (input) y0,1,2 grp glb reg bypass orp bypass dq rst re oe ck i/o delay i/o cell orp glb grp i/o cell #24 #25, 26, 27 #33, 34, 35 #43, 44 #36 reset ded. in #21 #20 #28 #29, 30, 31, 32 #38, 39 goe 0 #42 #40, 41 0491/2032 #22 comb 4 pt bypass #23 #37 #45 derivations of t su, t h and t co from the product term clock 1 = = = = t su 4.6 ns logic + reg su - clock (min) ( t io + t grp + t 20ptxor) + ( t gsu) - ( t io + t grp + t ptck(min)) (#20 + #22 + #26) + (#29) - (#20 + #22 + #35) (0.2 + 0.7 + 7.5) + (0.1) - (0.2 + 0.7 + 3.0) = = = = t h 0.7 ns clock (max) + reg h - logic ( t io + t grp + t ptck(max)) + ( t gh) - ( t io + t grp + t 20ptxor) (#20 + #22 + #35) + (#30) - (#20 + #22 + #26) (0.2 + 0.7 + 4.4) + (3.8) - (0.2 + 0.7 + 7.5) = = = = t co 10.1 ns clock (max) + reg co + output ( t io + t grp + t ptck(max)) + ( t gco) + ( t orp + t ob) (#20 + #22 + #35) + (#31) + (#36 + #38) (0.2 + 0.7 + 4.4) + (1.5) + (1.4 + 1.9) table 2-0042/2032v note: calculations are based on timing specifications for the isplsi 2032v-100.
specifications isplsi 2032v 8 use isplsi 2032ve for new designs power consumption power consumption in the isplsi 2032v device depends on two primary factors: the speed at which the device is operating and the number of product terms used. figure 3 shows the relationship between power and operating speed. figure 3. typical device power consumption vs fmax 0127a/2032v i cc can be estimated for the isplsi 2032v using the following equation: i cc (ma) = 15 + (# of pts * 0.78) + (# of nets * max freq * 0.004) where: # of pts = number of product terms used in design # of nets = number of signals used in device max freq = highest clock frequency to the device (in mhz) the i cc estimate is based on typical conditions (v cc = 3.3v, room temperature) and an assumption of two glb loads on average exists. these values are for estimates only. since the value of i cc is sensitive to operating conditions and the program in the device, the actual i cc should be verified. notes: configuration of two 16-bit counters typical current at 3.3v, 25 c 60 80 100 020 40 60 80 100 f max (mhz) i cc (ma) isplsi 2032v-100/-80/-60 90 70 40 50 power-up considerations when lattice 3.3v 2000v devices are used in mixed 5v/ 3.3v applications, some consideration needs to be given to the power-up sequence. when the i/o pins on the 3.3v isplsi devices are driven directly by 5v devices, a low impedance path can exist on the 3.3v device be- tween its i/o and vcc pins when the 3.3v supply is not present. this low impedance path can cause current to flow from the 5v device into the 3.3v isplsi device. the maximum current occurs when the signals on the i/o pins are driven high by the 5v devices. if a large enough current flows through the 3.3v i/o pins, latch-up can occur and permanent device damage may result. this latch-up condition occurs only during the power-up sequence when the 5v supply comes up before the 3.3v supply. the lattice 3.3v isplsi devices are guaranteed to withstand 5v interface signals within the device oper- ating vcc range of 3.0v to 3.6v. the recommended power-up options are as follows: option 1: ensure that the 3.3v supply is powered-up and stable before the 5v supply is powered up. option 2: ensure that the 5v device outputs are driven to a high impedance or logic low state during power-up.
specifications isplsi 2032v 9 use isplsi 2032ve for new designs pin description input/output pins these are the general purpose i/o pins used by the logic array. name table 2-0002a/2032v plcc pin numbers description 15, 19, 25, 29, 37, 41, 3, 7, 16, 20, 26, 30, 38, 42, 4, 8, 17, 21, 27, 31, 39, 43, 5, 9, i/o 0 - i/o 3 i/o 4 - i/o 7 i/o 8 - i/o 11 i/o 12 - i/o 15 i/o 16 - i/o 19 i/o 20 - i/o 23 i/o 24 - i/o 27 i/o 28 - i/o 31 18, 22, 28, 32, 40, 44, 6, 10 global output enable input pin. 2 goe 0 1, 23 gnd v cc 12, 34 vcc ground (gnd) input this pin performs two functions. when ispen is logic low, it functions as an input pin to load programming data into the device. tdi/in0 also is used as one of the two control pins for the isp state machine. when ispen is high, it functions as a dedicated input pin. dedicated clock input. this clock input is connected to one of the clock inputs of all the glbs on the device. this pin performs two functions: input dedicated in-system programming boundary scan enable input pin. this pin is brought low to enable the programming mode. the tms, tdi, tdo and tck controls become active. reset/y1 y0 tdi/in 0 i spen tms/nc 1 input when in isp mode, controls operation of isp state-machine. - dedicated clock input. this clock input is brought into the clock distribution network, and can optionally be routed to any glb and/or i/o cell on the device. output/input this pin performs two functions. when ispen is logic low, it functions as an output pin to read serial shift register data. when ispen is high, it functions as a dedicated input pin. tdo/in 1 input this pin performs two functions. when ispen is logic low, it functions as a clock pin for the serial shift register. when ispen is high, it functions as a dedicated clock input.this clock input is brought into the clock distribution network, and can optionally be routed to any glb and/or i/o cell on the device. tck/y2 - active low (0) reset pin which resets all of the glb and i/o registers in the device. 35 11 14 13 36 24 33 1. nc pins are not to be connected to any active signals, vcc or gnd.
specifications isplsi 2032v 10 use isplsi 2032ve for new designs pin description input this pin performs two functions. when ispen is logic low, it functions as an input pin to load programming data into the device. tdi/in0 also is used as one of the two control pins for the isp state machine. when ispen is high, it functions as a dedicated input pin. dedicated clock input. this clock input is connected to one of the clock inputs of all the glbs on the device. this pin performs two functions: input dedicated in-system programming boundary scan enable input pin. this pin is brought low to enable the programming mode. the tms, tdi, tdo and tck controls become active. input/output pins these are the general purpose i/o pins used by the logic array. name table 2-0002b/2032v tqfp pin numbers description 9, 13, 19, 23, 31, 35, 41, 1, 10, 14, 20, 24, 32, 36, 42, 2, 11, 15, 21, 25, 33, 37, 43, 3, i/o 0 - i/o 3 i/o 4 - i/o 7 i/o 8 - i/o 11 i/o 12 - i/o 15 i/o 16 - i/o 19 i/o 20 - i/o 23 i/o 24 - i/o 27 i/o 28 - i/o 31 12, 16, 22, 26, 34, 38, 44, 4 global output enable input pin. 40 goe 0 29 reset/y1 5 y0 8 tdi/in 0 7 ispen 30 tms/nc 1 input when in isp mode, controls operation of isp state-machine. 17, 39 gnd v cc 6, 28 vcc - dedicated clock input. this clock input is brought into the clock distribution network, and can optionally be routed to any glb and/or i/o cell on the device. output/input this pin performs two functions. when ispen is logic low, it functions as an output pin to read serial shift register data. when ispen is high, it functions as a dedicated input pin. 18 tdo/in 1 input this pin performs two functions. when ispen is logic low, it functions as a clock pin for the serial shift register.it is a dedicated clock input when ispen is logic high. this clock input is brought into the clock distribution network, and can optionally be routed to any glb and/or i/o cell on the device. tck/y2 ground (gnd) - active low (0) reset pin which resets all of the glb and i/o registers in the device. 27 1. nc pins are not to be connected to any active signals, vcc or gnd.
specifications isplsi 2032v 11 use isplsi 2032ve for new designs pin configuration isplsi 2032v 44-pin plcc pinout diagram pin configuration isplsi 2032v 44-pin tqfp pinout diagram i/o 18 i/o 17 i/o 16 tms/nc 1 reset/y1 vcc tck/y2 i/o 15 i/o 14 i/o 13 i/o 12 i/o 28 i/o 29 i/o 30 i/o 31 y0 vcc ispen tdi/in 0 i/o 0 i/o 1 i/o 2 i/o 27 i/o 26 i/o 25 i/o 24 goe 0 gnd i/o 23 i/o 22 i/o 21 i/o 20 i/o 19 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 gnd tdo/in 1 i/o 8 i/o 9 i/o 10 i/o 11 7 8 9 10 12 11 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 6 18 5 19 4 20 3 21 2 22 1 23 44 24 43 25 42 26 41 27 40 28 1. nc pins are not to be connected to any active signals, vcc or gnd. isplsi 2032v top view 0123/2032v i/o 18 i/o 17 i/o 16 tms/nc 1 reset/y1 vcc tck/y2 i/o 15 i/o 14 i/o 13 i/o 12 i/o 28 i/o 29 i/o 30 i/o 31 y0 vcc ispen tdi/in 0 i/o 0 i/o 1 i/o 2 i/o 27 i/o 26 i/o 25 i/o 24 goe 0 gnd i/o 23 i/o 22 i/o 21 i/o 20 i/o 19 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 gnd tdo/in 1 i/o 8 i/o 9 i/o 10 i/o 11 isplsi 2032v top view 1 2 3 4 6 5 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 44 12 43 13 42 14 41 15 40 16 39 17 38 18 37 19 36 20 35 21 34 22 0851/2032v/lv 1. nc pins are not to be connected to any active signals, vcc or gnd.
specifications isplsi 2032v 12 use isplsi 2032ve for new designs part number description isplsi 2032v ordering information device number 2032v isplsi xxxxx xx x xxx grade blank = commercial i = industrial x speed 100 = 100 mhz f max 80 = 80 mhz f max 60 = 60 mhz f max power l = low package j = plcc j44 = plcc t44 = tqfp device family 0212/2032v 60 44-pin plcc 15 isplsi 2032v-60lj44 60 15 44-pin tqfp isplsi 2032v-60lt44 table 2-0041a/2032v family f max (mhz) ordering number package t pd (ns) 100 44-pin plcc 7.5 isplsi 2032v-100lj44 100 44-pin tqfp 7.5 isplsi 2032v-100lt44 80 10 44-pin plcc isplsi 2032v-80lj44 isplsi 80 44-pin tqfp 10 isplsi 2032v-80lt44 commercial table 2-0041b/2032v family f max (mhz) ordering number package t pd (ns) isplsi 60 44-pin plcc 15 isplsi 2032v-60lj44i 60 44-pin tqfp 15 isplsi 2032v-60lt44i industrial

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