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d a t a sh eet objective speci?cation file under integrated circuits, ic02 1996 jan 26 integrated circuits tda8376; TDA8376A i 2 c-bus controlled pal/ntsc tv processors
1996 jan 26 2 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A contents 1 features 2 general description 3 quick reference data 4 ordering information 5 block diagram 6 pinning 7 functional description 7.1 video switches 7.2 integrated video filters, peaking and black stretcher 7.3 synchronization circuit 7.4 colour decoder 7.5 rgb output circuit and black-current stabilization 8i 2 c-bus specification 8.1 start-up procedure 8.2 inputs 8.2.1 input control bits 8.2.2 output control bits 9 limiting values 10 thermal characteristics 11 quality specification 11.1 latch-up 12 characteristics 13 test and application information 13.1 east-west output stage 13.2 adjustment of geometry control parameters 14 package outlines 15 soldering 15.1 introduction 15.2 sdip 15.2.1 soldering by dipping or by wave 15.2.2 repairing soldered joints 15.3 qfp 15.3.1 reflow soldering 15.3.2 wave soldering 15.3.3 repairing soldered joints 16 definitions 17 life support applications 18 purchase of philips i 2 c components
1996 jan 26 3 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A 1 features source selection with 2 cvbs inputs and a y/c (or extra cvbs) input output signals of the video switch circuit for the teletext decoder and a picture-in-picture (pip) processor video identification circuit which is independent of the synchronization for stable on screen display (osd) under no-signal conditions integrated chrominance trap with pre-shoot compensation and bandpass filters (automatically calibrated) integrated luminance delay line asymmetrical peaking in the luminance channel with a (defeatable) noise coring function black stretcher circuit in the luminance channel pal/ntsc colour decoder with automatic search system easy interfacing with the tda8395 (secam decoder) for multistandard applications rgb control circuit with black-current stabilization and white point adjustment; to obtain a good grey scale tracking the black-current ratio of the 3 guns depends on the white point adjustment two linear rgb inputs and fast blanking horizontal synchronization with two control loops and alignment-free horizontal oscillator vertical count-down circuit geometry correction by modulation of the vertical and e-w drive vertical and horizontal zoom possibility for 16 : 9 applications (TDA8376A only) i 2 c-bus control of various functions low dissipation (700 mw) small amount of peripheral components compared with competition ics y, u and v inputs and outputs. 2 general description the tda8376 and TDA8376A are alignment-free i 2 c-bus controlled video processors which contain a pal/ntsc colour decoder, luminance processor, sync processor, rgb-control and deflection processor. the circuits have been designed for use with the baseband chrominance delay line tda4665 and for dc-coupled vertical and east-west (e-w) output stages. both ics are pin compatible. the TDA8376A has a flexible horizontal and vertical zoom possibility for 16 : 9 applications. the supply voltage for the ics is 8 v. the ics are available in an sdip package with 52 pins and in a qfp package with 64 pins (see chapter 4). the pin numbers indicated in this document are referenced to the sdip52; sot247-1 package; unless otherwise indicated.
1996 jan 26 4 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A 3 quick reference data 4 ordering information symbol parameter min. typ. max. unit supply v p supply voltage - 8.0 - v i p supply current - 75 - ma input voltages v 9,13(p-p) cvbs input voltage (peak-to-peak value) - 1.0 - v v 27(p-p) s-vhs luminance input voltage (peak-to-peak value) - 1.0 - v v 6(p-p) s-vhs chrominance input voltage (burst amplitude) (peak-to-peak value) - 0.3 - v v i(p-p) rgb input voltage (peak-to-peak value) - 0.7 - v output voltages v 38(p-p) txt output voltage (peak-to-peak value) - 1.0 - v v 11(p-p) pip output voltage (peak-to-peak value) - 1.0 - v v 30(p-p) - (r - y) output voltage (peak-to-peak value) - 525 - mv v 29(p-p) - (b - y) output voltage (peak-to-peak value) - 675 - mv v 19,20,21(p-p) rgb output signal voltage amplitudes (peak-to-peak value) - 2.0 - v output currents i 40 horizontal output current 10 -- ma i 47,48 vertical output current 1 -- ma i 46 e-w drive output current 0.5 -- ma type number package name description version tda8376 sdip52 plastic shrink dual in-line package; 52 leads (600 mil) sot247-1 TDA8376Ah qfp64 plastic quad ?at package; 64 leads (lead length 1.95 mm); body 14 20 2.8 mm sot319-2
1996 jan 26 5 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A 5 block diagram d book, full pagewidth mge078 cvbs switch s-vhs switch band pass trap control dacs 16 x 6 bits 2 x 4 bits pal/ntsc decoder filter tuning vertical sync separator video identification black stretcher sync separator and 1st loop vco and control i 2 c-bus transceiver 35 34 33 4.4 mhz 3.6 mhz 6 7 11 38 12 36 2nd loop and horizontal output horizontal/ vertical divider delay, peaking and coring g-y matrix and sat control tda4665 ew geometry vertical geometry black current stabilizer rgb matrix and output rgb input and switch 46 bri contr white point 21 20 19 30 29 32 31 28 27 23 24 25 26 lumout lumin ri1 gi1 bi1 rgbin1 chroma cvbs/y pipo cvbs/txt cvbs ext dec ft det xtal2 xtal1 dec dig dec bg gnd2 gnd1 gnd3 ph1lf cvbs int 913 sw scl v p1 ( + 8 v) v p2 ( + 8 v) sda 34 44 45 42 10 51 837 43 41 39 40 hout sco fbi ph2lf ref ref hue sw sat ro go bo 22 bclin 18 blkin 51 2 50 48 47 49 ewd ehto vdr (p) vsc c blk vdr (n) sec ref 14 15 16 17 rgbin2 ri2 gi2 bi2 ryo byo byi ryi tda8376(a) i ref fig.1 block diagram (sdip52; sot247-1).
1996 jan 26 6 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A 6 pinning symbol pin description sdip52 qfp64 dec dig 1 11 decoupling digital supply c blk 2 12 black peak hold capacitor scl 3 13 i 2 c-bus serial clock input sda 4 14 i 2 c-bus serial data input/output dec bg 5 16 band gap decoupling chroma 6 17 chrominance input (s-vhs) cvbs/y 7 18 external cvbs/y input v p1 8 20 main supply voltage (+8 v) cvbs int 9 22 internal cvbs input gnd1 10 23 ground 1 pipo 11 25 picture-in-picture output dec ft 12 26 decoupling ?lter tuning cvbs ext 13 27 external cvbs input rgbin2 14 28 rgb insertion input 2 ri2 15 29 red input 2 gi2 16 30 green input 2 bi2 17 31 blue input 2 blkin 18 32 black-current input bo 19 34 blue output go 20 35 green output ro 21 36 red output bclin 22 37 beam current limiter input ri1 23 38 red input 1 gi1 24 39 green input 1 bi1 25 40 blue input 1 rgbin1 26 41 rgb insertion input 1 lumin 27 42 luminance input lumout 28 43 luminance output byo 29 44 - (b - y) signal output ryo 30 45 - (r - y) signal output byi 31 46 - (b - y) signal input ryi 32 47 - (r - y) signal input xtal1 33 49 3.58 mhz crystal connection xtal2 34 51 4.43/3.58 mhz crystal connection det 35 53 loop ?lter phase detector sec ref 36 54 secam reference output v p2 37 55 horizontal oscillator supply voltage (+8 v) cvbs/txt 38 56 cvbs/txt output
1996 jan 26 7 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A sco 39 57 sandcastle output hout 40 58 horizontal output fbi 41 59 ?yback input gnd2 42 24 ground 2 ph2lf 43 62 phase-2 ?lter ph1lf 44 63 phase-1 ?lter gnd3 45 60 ground 3 ewd 46 1 east-west drive output vdr (p) 47 3 vertical drive 1 positive output vdr (n) 48 4 vertical drive 2 negative output ehto 49 5 eht/overvoltage protection input vsc 50 7 vertical sawtooth capacitor i ref 51 8 reference current input n.c. 52 2 not connected n.c. - 6 not connected n.c. - 9 not connected n.c. - 10 not connected n.c. - 15 not connected n.c. - 19 not connected n.c. - 33 not connected n.c. - 48 not connected n.c. - 50 not connected n.c. - 52 not connected v p3 - 21 supply voltage 3 (+8 v) gnd4 - 61 ground 4 gnd5 - 64 ground 5 symbol pin description sdip52 qfp64
1996 jan 26 8 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A fig.2 pin configuration (sdip52). handbook, halfpage tda8376(a) mge076 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 dec dig c blk scl sda dec bg chroma cvbs/y v p1 cvbs int gnd1 pipo dec ft cvbs ext rgbin2 ri2 gi2 bi2 blkin bo go ro bclin ri1 gi1 bi1 rgbin1 n.c. i ref vsc ehto vdr (n) vdr (p) ewd gnd3 ph1lf ph2lf gnd2 fbi hout sco cvbs/txt v p2 sec ref det xtal2 xtal1 ryi byi ryo byo lumout lumin
1996 jan 26 9 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A fig.3 pin configuration (qfp64). handbook, full pagewidth tda8376(a) mge077 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ewd n.c. vdr (p) vdr (n) ehto n.c. vsc i ref n.c. n.c. dec dig c blk scl sda n.c. dec bg chroma cvbs/y n.c. xtal2 n.c. xtal1 n.c. ryi byi ryo byo lumout lumin rgbin1 bi1 gi1 ri1 bclin ro go bo n.c. 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 gnd5 ph1lf ph2lf gnd4 gnd3 fbi hout sco cvbs/txt v p2 sec ref det n.c. v p1 v p3 cvbs int gnd1 gnd2 pipo dec ft cvbs ext rgbin2 ri2 gi2 bi2 blkin
1996 jan 26 10 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A 7 functional description 7.1 video switches the circuit has two cvbs inputs and a super-video home system (s-vhs) input. the input can be chosen by the i 2 c-bus. the input selector also has a position in which cvbs ext is processed, unless there is a signal on the s-vhs input. when the input selector is in this position it switches to the s-vhs input if the s-vhs detector detects sync pulses on the s-vhs luminance input. the s-vhs detector output can be read by the i 2 c-bus. when the s-vhs option is not used the luminance input can be used as a second input for external cvbs signals. the choice is made via the cvs bit (see table 1). the video switch circuit has two outputs which can be programmed in a different way. the input signal for the decoder is also available on the txt output. therefore this signal can be used to drive the teletext decoder and the secam add-on decoder. the signal on the pip output can be chosen independent of the txt output. if s-vhs is selected for one of the outputs the luminance and chrominance signals are added so that a cvbs signal is obtained again. the circuit contains a video identification circuit which checks whether a video signal is available at the selected video input. this circuit is independent of the synchronization circuit. the information of this identification circuit can also be used to switch the phase-1 ( j 1 ) loop to a low gain when no signal is received so that a stable osd display is obtained. the video identification circuit can be switched on and off via the i 2 c-bus. 7.2 integrated video ?lters, peaking and black stretcher the circuit contains a chrominance bandpass and trap circuit. the chrominance trap filter in the luminance path is designed for a symmetrical step response behaviour. the filters are realized by gyrator circuits and they are automatically tuned by comparing the tuning frequency with the crystal frequency of the decoder. the luminance delay line and the delay for the peaking circuit are also realized by gyrator circuits. during secam reception the centre frequency of the chrominance trap is set to a value of approximately 4.2 mhz to obtain a better suppression of the secam carrier frequencies. the peaking function is achieved by two luminance delay cells each with a delay of 165 ns. the resulting peaking frequency is 3 mhz. the peaking is asymmetrical so that the overshoots in the direction of black are approximately two times higher than those in the direction of white. this provides a better picture impression than a symmetrical peaking. the circuit contains a coring circuit to prevent the noise content of the video signal being amplified by the peaking circuit. this coring circuit can be switched-off when required. it is possible to connect a colour transient improvement (cti) or picture signal improvement (psi) ic to the tda8376. the luminance signal which has passed the filter and delay line circuit is available externally. the output signal of the transient improvement circuit must be applied to the luminance input circuit. when the cti function is not required the two pins must be ac-coupled. the luminance signal below 50 ire can be stretched in accordance with the difference between the peak black level and the blanking level of the back-porch of the video signal. the black level stretcher can be switched-off by connecting pin 2 to the positive supply line. 7.3 synchronization circuit the sync separator is preceded by a controlled amplifier which adjusts the sync pulse amplitude to a fixed level. these pulses are fed to the slicing stage which is operating at 50% of the amplitude. the separated sync pulses are fed to the first phase detector and to the coincidence detector. this coincidence detector is only used to detect whether the line oscillator is synchronized and not for transmitter identification. the first phase-locked loop (pll) has a very high-statical steepness so that the phase of the picture is independent of the line frequency. to prevent the horizontal synchronization being disturbed by anti-copy signals such as macrovision the phase detector is gated during the vertical retrace period so that pulses during scan have no effect on the output voltage. the position of this pulse is asymmetrical and the width is approximately 22 m s. the horizontal output signal is generated by an oscillator which operates at twice the line frequency. its frequency is divided-by-two to lock the first control loop to the incoming signal. the time-constant of the loop can be forced by the i 2 c-bus (fast or slow). if required the ic can select the time-constant depending on the noise content of the incoming video signal. the free-running frequency of the oscillator is determined by a digital control circuit which is locked to the reference signal of the colour decoder. when the ic is switched on the horizontal output signal is suppressed and the oscillator is calibrated as soon as all subaddress bytes have been sent. when the frequency of the oscillator is correct the horizontal drive signal is switched on.
1996 jan 26 11 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A to obtain a smooth switching-on and switching-off behaviour of the horizontal output stage the horizontal output frequency is doubled during switch-on and switch-off (slow start/stop). during that time the duty factor of the output pulse has such a value that maximum safety is obtained for the output stage to protect the horizontal output transistor the horizontal drive is switched off when a power-on reset is detected. the drive signal is switched on again when the normal switch-on procedure is followed, i.e. all sub-address bytes must be sent and, after calibration, the horizontal drive signal will be released again via the slow start procedure. when the coincidence detector indicates an out-of-lock situation the calibration procedure is repeated. the circuit has a second control loop to generate the drive pulses for the horizontal driver stage. to prevent the horizontal output transistor being switched on during flyback the horizontal drive output is gated with the flyback pulse. the vertical sawtooth generator drives the vertical output and e-w correction drive circuits. the geometry processing circuits provide control of horizontal shift, e-w width, e-w parabola/width ratio, e-w corner/parabola ratio, trapezium correction, vertical shift, vertical slope, vertical amplitude, and the s-correction. all these controls can be set via the i 2 c-bus. the geometry processor has a differential current output for the vertical drive signal and a single-ended output for the e-w drive. both the vertical drive and the e-w drive outputs can be modulated for eht compensation. the eht compensation pin is also used for overvoltage protection. the TDA8376A geometry processor also offers the possibility for a flexible vertical and horizontal zoom mode for 16 : 9 applications. because of this feature an additional control can be added on the remote control so that the viewer can adjust the picture. in addition the de-interlace of the vertical output can be set via the i 2 c-bus. to avoid damage of the picture tube when the vertical deflection fails, the guard output current of the tda8350 can be supplied to the sandcastle output. when a failure is detected the rgb-outputs are blanked and a bit is set (ndf) in the status byte of the i 2 c-bus. when no vertical deflection output stage is connected this guard circuit will also blank the output signals. this can be overruled by the evg bit of subaddress 0a (see table 1). 7.4 colour decoder the colour decoder contains an alignment-free crystal oscillator, a killer circuit and the colour difference demodulators. the 90 phase shift for the reference signal is made internally. the demodulation angle and gain ratio for the colour difference signals for pal and ntsc are adapted to the standard. the colour decoder is very flexible. together with the secam decoder tda8395 an automatic multistandard decoder can be designed. in the automatic mode the secam identification is accepted only when the vertical frequency is 50 hz. in the forced mode the system can also identify signals with a vertical frequency of 60 hz. which standard the ic can decode depends on the external crystals. if a 4.4 mhz and a 3.5 mhz crystal are used pal 4.4, ntsc 4.4, ntsc 3.5 and pal 3.5 can be decoded. if two 3.5 mhz crystals are used pal n and m can be decoded. if one crystal is connected only pal/ntsc 4.4 or pal/ntsc 3.5 can be decoded. the crystal frequency of the decoder is used to tune the line oscillator. therefore the value of the crystal frequency must be given to the ic via the i 2 c-bus. for a reliable calibration of the horizontal oscillator it is very important that the crystal indication bits (xa and xb) are not corrupted (see table 6). for this reason the crystal bits (sxa and sxb) can be read in the output bytes so that the software can check the i 2 c-bus transmissions (see table 38). 7.5 rgb output circuit and black-current stabilization the colour-difference signals are matrixed with the luminance signal to obtain the rgb-signals. for the rgb-inputs linear amplifiers have been chosen so that the circuit is suited for signals coming from the scart connector. the rgb2 inputs (pins 14 to 17) have priority over the rgb1 inputs (pins 23 to 26). both fast blanking inputs can be blocked by i 2 c-bus controls. the contrast and brightness controls operate on internal and external signals.
1996 jan 26 12 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A the output signal has an amplitude of approximately 2 v black-to-white at nominal input signals and nominal settings of the controls. the black current stabilization is realized by feedback from the video output amplifiers to the rgb control circuit. the black current of the 3 guns of the picture tube is internally measured and stabilized. the black level control is active during 4 lines at the end of the vertical blanking. during the first line the leakage current is measured and the following 3 lines the 3 guns are adjusted to the required level. the maximum acceptable leakage current is 100 m a. the nominal value of the black current is 10 m a. the ratio of the currents for the various guns automatically tracks with the white point adjustment so that the background colour is the same as the adjusted white point. the input impedance of the black-current measuring pin is 15 k w . therefore the beam current during scan will cause the input voltage to exceed the supply voltage. the internal protection will start conducting so that the excessive current is bypassed. when the tv receiver is switched on the black current stabilization circuit is not active, the rgb outputs are blanked and beam current limiting input pin is short-circuited. only during the measuring lines will the outputs supply a voltage of 5 v to the video output stage so that it can be detected if the picture tube is warming up. these pulses are switched on after a waiting time of approximately 0.5 s. this ensures that the vertical deflection is activated so that the measuring pulses are not visible on the screen. as soon as the current supplied to the measuring input exceeds a value of 190 m a the stabilization circuit is activated. after a waiting time of approximately 0.8 s the blanking and the beam current limiting input pin are released. the remaining switch-on behaviour of the picture is determined by the external time constant of the beam current limiting network. 8i 2 c-bus specification valid subaddresses: 00 to 13 (tda8376) or 00 to 16 (TDA8376A); subaddress fe is reserved for test purposes. auto-increment mode is available for subaddresses. 8.1 start-up procedure read the status bytes until por = 0 and send all subaddress bytes. the horizontal output signal is switched on when the oscillator is calibrated. each time before the data in the ic is refreshed, the status bytes must be read. if por = 1, the procedure previously mentioned must be carried out to restart the ic. when this procedure is not followed the horizontal frequency may be incorrect after power-up or after a power dip. handbook, halfpage mla743 a6 a5 a4 a3 a2 a1 a0 10 00 1011/0 r/w fig.4 slave address (8a).
1996 jan 26 13 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A 8.2 inputs table 1 input status bits note 1. the bits exp and cl in subaddress 0c are only valid for the tda8376. for the TDA8376A these two bits must be set to logic 0. table 2 output status bits note 1. x = dont care. function subaddress (hex) data byte d7 d6 d5 d4 d3 d2 d1 d0 source select 00 ina inb inc ind foa fob xa xb decoder mode 01 forf fors dl stb poc cm2 cm1 cm0 hue 02 0 0 a5 a4 a3 a2 a1 a0 horizontal shift (hs) 03 0 0 a5 a4 a3 a2 a1 a0 e-w width (e-w) 04 0 0 a5 a4 a3 a2 a1 a0 e-w parabola/width (pw) 05 0 0 a5 a4 a3 a2 a1 a0 e-w corner parabola (cp) 06 0 0 a5 a4 a3 a2 a1 a0 e-w trapezium (tc) 07 0 0 a5 a4 a3 a2 a1 a0 vertical slope (vs) 08 ncin 0 a5 a4 a3 a2 a1 a0 vertical amplitude (va) 09 vid lbm a5 a4 a3 a2 a1 a0 s-correction (sc) 0a hco evg a5 a4 a3 a2 a1 a0 vertical shift (vsh) 0b sbl prd a5 a4 a3 a2 a1 a0 white point r 0c exp (1) cl (1) a5 a4 a3 a2 a1 a0 white point g 0d 0 cvs a5 a4 a3 a2 a1 a0 white point b 0e mat 0 a5 a4 a3 a2 a1 a0 peaking 0f yd3 yd2 yd1 yd0 a3 a2 a1 a0 brightness 10 rbl cor a5 a4 a3 a2 a1 a0 saturation 11 ie1 ie2 a5 a4 a3 a2 a1 a0 contrast 12 0 0 a5 a4 a3 a2 a1 a0 spare 13 0 0 000000 spare 14 0 0 000000 spare 15 0 0 000000 vertical zoom (vx, 76a) 16 0 0 a5 a4 a3 a2 a1 a0 function subaddress (hex) data byte d7 d6 d5 d4 d3 d2 d1 d0 output status bytes 00 por fsi sts sl xpr cd2 cd1 cd0 01 ndf in1 in2 ifi afa x (1) sxa sxb
1996 jan 26 14 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A 8.2.1 i nput control bits table 3 source select 1 table 4 source select 2 table 5 phase 1 ( j 1 ) time constant note 1. x = dont care. table 6 crystal indication xa and xb ina inb decoder and txt 0 0 cvbs int 0 1 cvbs ext 1 0 s-vhs 1 1 s-vhs (cvbs ext ) inc ind pip 0 0 cvbs int 0 1 cvbs ext 1 0 s-vhs 1 1 s-vhs (cvbs ext ) foa fob mode 0 0 normal 0 1 slow 1x (1) fast xa xb crystal 0 0 two 3.6 mhz 0 1 one 3.6 mhz (pin 33) 1 0 one 4.4 mhz (pin 34) 1 1 3.6 mhz (pin 33) and 4.4 mhz (pin 34) table 7 forced ?eld frequency note 1. when the forced mode is selected the divider will only switch to that position when the horizontal oscillator is not synchronized. table 8 interlace table 9 standby table 10 synchronization mode table 11 colour decoder mode forf fors field frequency 0 0 auto (60 hz when line not synchronized) 0 1 60 hz; note 1 1 0 50 hz; note 1 1 1 auto (50 hz when line not synchronized) dl status 0 interlace 1 de-interlace stb mode 0 standby 1 normal poc mode 0 active 1 not active cm2 cm1 cm0 decoder mode 0 0 0 not forced, own intelligence 0 0 1 forced ntsc 3.6 mhz 0 1 0 forced pal 4.4 mhz 0 1 1 forced secam 1 0 0 forced ntsc 4.4 mhz 1 0 1 forced pal 3.6 mhz (pin 33) 1 1 0 forced pal 3.6 mhz (pin 34) 1 1 1 no function
1996 jan 26 15 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A table 12 vertical divider mode table 13 video identi?cation mode table 14 long blanking mode table 15 eht tracking mode table 16 enable vertical guard (rgb blanking) table 17 service blanking table 18 overvoltage input mode table 19 vertical de?ection mode (tda8376 only) ncin vertical divider mode 0 normal operation 1 switched to search window vid video identification mode 0 j 1 loop switched on and off 1 not active lbm blanking mode 0 adapted to standard (50 or 60 hz) 1 ?xed in accordance with 50 hz standard hco tracking mode 0 eht tracking only on vertical 1 eht tracking on vertical and e-w evg vertical guard mode 0 not active 1 active sbl service blanking mode 0off 1on prd overvoltage mode 0 detection mode 1 protection mode exp cl vertical deflection mode 0 0 normal 0 1 compress 1 0 expand 1 1 expand and lift table 20 condition y/c input table 21 pal/ntsc matrix table 22 y-delay adjustment; note 1 note 1. for an equal delay of the luminance and chrominance signal the delay must be set at a value of 160 ns. this is only valid for a cvbs signal without group delay distortions. table 23 rgb blanking table 24 noise coring (peaking) table 25 enable fast blanking rgb1 table 26 enable fast blanking rgb2 cvs y-input mode 0 switched to y/c mode 1 switched to cvbs mode mat matrix 0 adapted to standard 1pal yd0 to yd3 y-delay yd3 yd3 160 ns + yd2 yd2 80 ns + yd1 yd1 40 ns + yd0 yd0 40 ns rbl rgb blanking 0 not active 1 active cor noise coring 0off 1on ie1 fast blanking 0 not active 1 active ie2 fast blanking 0 not active 1 active
1996 jan 26 16 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A 8.2.2 o utput control bits table 27 power-on reset table 28 field frequency indication table 29 s-vhs status table 30 phase 1 ( j 1 ) lock indication table 31 x-ray protection table 32 colour decoder mode por mode 0 normal 1 power-down fsi frequency 050hz 160hz sts s-vhs input 0 no signal 1 signal sl indication 0 not locked 1 locked xpr overvoltage 0 no overvoltage detected 1 overvoltage detected cd2 cd1 cd0 standard 0 0 0 no colour standard identi?ed 0 0 1 ntsc 3.6 mhz 0 1 0 pal 4.4 mhz 0 1 1 secam 1 0 0 ntsc 4.4 mhz 1 0 1 pal 3.6 mhz (pin 33) 1 1 0 pal 3.6 mhz (pin 34) 1 1 1 spare table 33 output vertical guard table 34 indication rgb1 insertion table 35 indication rgb2 insertion table 36 output video identi?cation table 37 ic version indication table 38 crystal indication sxa and sxb ndf vertical output stage 0ok 1 failure in1 rgb insertion 0 no (pin 26 low) 1 yes (pin 26 high) in2 rgb insertion 0 no (pin 14 low) 1 yes (pin 14 high) ifi video signal 0 no video signal identi?ed 1 video signal identi?ed afa ic 0 tda8376 1 TDA8376A sxa sxb crystal 0 0 two 3.6 mhz 0 1 one 3.6 mhz 1 0 one 4.4 mhz 1 1 3.6 and 4.4 mhz
1996 jan 26 17 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A 9 limiting values in accordance with the absolute maximum rating system (iec 134). notes 1. all pins are protected against esd by means of internal clamping diodes. 2. human body model (hbm): r = 1.5 k w ; c = 100 pf. 3. machine model (mm): r = 0 w ; c = 200 pf. 10 thermal characteristics 11 quality specification in accordance with snw-fq-611e . the number of the quality specification can be found in the quality reference handbook . the handbook can be ordered using the code 9398 510 63011. 11.1 latch-up at t amb =70 c all pins meet the following speci?cation. i trigger 3 100 ma or 3 1.5v dd(max) i trigger - 100 ma or - 0.5v dd(max) . symbol parameter conditions min. max. unit v p supply voltage - 9.0 v t stg storage temperature - 25 +150 c t amb operating ambient temperature 0 70 c t sol soldering temperature for 5 s - 260 c t j operating junction temperature - 150 c v es electrostatic handling all pins; notes 1 and 2 - 2000 +2000 v all pins; notes 1 and 3 - 200 +200 v symbol parameter value unit r th j-a thermal resistance from junction to ambient in free air sdip52 40 k/w qfp64 50 k/w
1996 jan 26 18 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A 12 characteristics v p =8v; t amb =25 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supplies m ain supply ( pin 8) v p1 supply voltage 7.2 8.0 8.8 v i p1 supply current - 75 - ma p tot total power dissipation - 650 - w h orizontal oscillator supply ( pin 37) v p2 supply voltage 7.2 8.0 8.8 v i p2 supply current - 6 - ma cvbs and s-vhs input switch i nternal and external cvbs inputs ( pins 9 and 13) v 9(p-p) cvbs input voltage (peak-to-peak value) note 1 - 1.0 1.4 v i 9 cvbs input current - 4 -m a ss cvbs suppression of non-selected cvbs input signal notes 2 and 3 50 -- db s-vhs input ( pins 6 and 7) v 7(p-p) luminance input voltage (peak-to-peak value) - 1.0 1.4 v i 7(p-p) luminance input current - 4 -m a v 6(p-p) chrominance input voltage (burst amplitude) (peak-to-peak value) note 4 - 0.3 0.45 v z i chrominance input impedance - 50 - k w txt and pip output signals ( pins 38 and 11) v o(p-p) output signal voltage amplitude (peak-to-peak value) - 1.0 - v z o output impedance -- 250 w v ts top sync voltage level - tbf - v
1996 jan 26 19 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A rgb inputs, colour difference inputs, luminance inputs and outputs rgb inputs ( pins 15 to 17 and 23 to 25); note 5 v i(p-p) input signal voltage amplitude for an output signal of 2 v (black-to-white) at nominal controls (peak-to-peak value) note 6 - 0.7 0.8 v v i(p-p) input signal voltage amplitude before clipping occurs (peak-to-peak value) note 2 1.0 -- v d v o difference between black level of internal and external signals at the outputs -- 20 mv i i input currents no clamping; note 7 - 0.1 -m a d t d delay difference for the three channels note 2 - 020ns f ast blanking ( pins 14 and 26) v i input voltage no data insertion -- 0.4 v data insertion 0.9 -- v v 14,26(max) maximum input pulse data insertion -- 3.0 v t d delay time from rgb input to rgb output data insertion; note 5 - 100 - ns d t d delay difference between data insertion to rgb output and rgb input to rgb output data insertion; note 5 - 50 - ns i 14,26 input current -- 0.2 ma ss int suppression of internal rgb signals notes 1 and 2; data insertion; f i = 0 to 5 mhz 55 -- db ss ext suppression of external rgb signals notes 1 and 2; no data insertion; f i = 0 to 5 mhz 55 -- db v 14 input voltage to insert black level at the rgb outputs to facilitate osd signals being applied to the outputs 4 -- v c olour difference input signals ( pins 31 and 32) v 32(p-p) input signal amplitude - (r - y) (peak-to-peak value) note 7 - 1.05 - v v 31(p-p) input signal amplitude - (b - y) (peak-to-peak value) note 7 - 1.35 - v i 31,32 input current for both inputs note 7 - 0.1 1.0 m a symbol parameter conditions min. typ. max. unit
1996 jan 26 20 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A l uminance inputs and outputs ( pins 27 and 28) v 28(p-p) output signal voltage amplitude (peak-to-peak value) top sync to white - 0.45 0.63 v v ts top sync voltage level - 2.5 - v z o output impedance - 250 -w v 27(p-p) input signal voltage amplitude (peak-to-peak value) - 0.45 - v i clamp clamping current during burst key pulse - 200 -m a i i input current no clamping -- 0.5 m a chrominance ?lters c hrominance trap circuit f trap trap frequency - f osc - mhz during secam reception - 4.2 - mhz qf trap quality factor note 8 - 2 - sr colour subcarrier rejection 20 -- db c hrominance band - pass circuit f c centre frequency - f osc - mhz qbp band-pass quality factor - 3 - delay line, peaking circuit and black stretcher y delay line t d delay time note 2 - 480 - ns t d1 tuning range delay time 8 steps - 160 - +160 ns b bandwidth of internal delay line note 2 5 -- mhz p eaking control ; note 9 f c(p) peaking centre frequency - 3 - mhz t w width of preshoot or overshoot at 50% of pulse; note 2 - 160 - ns os overshoot positive - 20 - % negative - 36 - % peaking control curve 16 steps see fig.5 g w wave gain - 1.8 - c oring stage s coring range - 15 - ire b lack level stretcher ( pin 2); note 10 bls max maximum black level shift 15 21 27 ire lsh level shift 100% of peak-white - 1 0 +1 ire 50% of peak-white - 1 - +3 ire 15% of peak-white 6 8 10 ire symbol parameter conditions min. typ. max. unit negative half wave gain positive half wave gain --------------------------------------------------------------
1996 jan 26 21 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A horizontal synchronization circuits s ync video input s( pins 7, 9 and 13) v 7,9,13 sync pulse voltage amplitude note 7 50 300 - mv sl hs slicing level for horizontal sync note 11 - 50 - % sl vs slicing level for vertical sync - 30 - % h orizontal oscillator f fr free running frequency - 15625 - hz d f fr spread of free running frequency -- 2% d f/ d v p frequency variation with respect to the supply voltage v p =8v 10%; note 2 - 0.2 0.5 % d f (max) maximum frequency variation with temperature t amb = 0 to 70 c; note 2 -- 80 hz f irst control loop ( filter connected to pin 44); note 12 f hr frequency holding range pll - 0.9 1.2 khz f cr frequency catching range pll note 2 0.6 0.9 - khz s/n signal-to-noise ratio of the video input signal at which the time constant is switched - 20 - db hys hysteresis at the switching point - 1 - db s econd control loop ( capacitor connected to pin 43) dj i / dj o control sensitivity - 150 -m s/ m s t cr control range from start of horizontal output to ?yback at nominal shift position 11 12 -m s t shift horizontal shift range 63 steps 2 --m s j dync control sensitivity for dynamic compensation - 5.3 -m s/v v 43 voltage to switch on the ?ash protection note 13 6 -- v i 43 input current during protection -- 1ma h orizontal output ( pin 40); note 14 v ol low level output voltage i ol =10ma -- 0.3 v i o(max) maximum allowed output current 10 -- ma v o(max) maximum allowed output voltage -- v p v d duty factor note 2 - 50 - % note 2; v hout = high; during switch-on/switch-off - 75 - % f switch frequency during switch-on and switch-off - 2f hout - hz t switch(on) switch-on time - 50 - ms t switch(off) switch-off time rgb drive maximum - 100 - ms rgb drive minimum - 50 - ms symbol parameter conditions min. typ. max. unit
1996 jan 26 22 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A f lyback pulse input ( pin 41) v hsw switching voltage level for horizontal blanking - 0.4 - v v j 2(sw) switching level for phase-2 loop - 4.0 - v v 41(max) maximum input voltage note 7 - 8.0 - v z i input impedance note 7 - 10 - m w s andcastle pulse output ( pin 39) v 39 output voltage during burst key 4.8 5.3 5.8 v during blanking 1.8 2.0 2.2 v t w pulse width burst key pulse 3.3 3.5 3.7 m s vertical blanking (50 hz) - 25 - lines vertical blanking (60 hz) - 21 - lines v clamp clamping voltage level for vertical guard detection - 2.7 - v i 39(min) minimum input current to activate guard detection -- 0.5 ma i 39(max) maximum allowable input current 2.5 -- ma t d delay of start of burst key to start of sync - 5.4 -m s vertical synchronization and geometry correction v ertical oscillator ; note 15 f fr free running frequency - 50/60 - hz f lock locking frequency range 45 - 64.5 hz divider value not locked - 625/525 - lines lr locking range 488 - 722 lines/ frame v ertical ramp generator ( pin 50) v 50(p-p) sawtooth voltage amplitude (peak-to-peak value) vs = 1fh; c = 100 nf; r = 39 k w - 3.5 - v i dis discharge current - 1 - ma i charge charge current set by external resistor note 16 - 19 -m a vs vertical slope control range 63 steps - 20 - +20 % d i 50 charge current increase f = 60 hz - 20 - % v 50l low level voltage of ramp - 2.07 - v v ertical drive outputs ( pins 47 and 48) i diff(p-p) differential output current (peak-to-peak value) va = 1fh - 0.95 - ma i cm common mode output current - 400 -m a v o output voltage 0 - 4.0 v symbol parameter conditions min. typ. max. unit
1996 jan 26 23 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A eht tracking / overvoltage protection ( pin 49); note 13 v 49 input voltage 1.2 - 2.8 v smr scan modulation range - 5 - +5 % j vert vertical sensitivity - 6.3 - %/v j ew e-w sensitivity when switched-on -- 6.3 - %/v i eq e-w equivalent output current +100 -- 100 m a v 49 overvoltage detection level - 3.9 - v d e - interlace ?rst ?eld delay - 0.5h - e-w width ; note 17 cr control range 63 steps tda8376 100 - 80 % TDA8376A 100 - 65 % i eq equivalent output current tda8376 0 - 400 m a TDA8376A 0 - 700 m a v o e-w output voltage range 1.0 - 8.0 v i o e-w output current range tda8376 0 - 900 m a TDA8376A 0 - 1200 m a e-w parabola / width cr control range 63 steps 0 - 22 % i eq equivalent output current e-w = 3fh; cp = 00h 0 - 440 m a e-w corner / parabola cr control range 63 steps - 43 - 0% i eq equivalent output current pw = 3fh; e-w = 3fh - 190 - 0 m a e-w trapezium cr control range 63 steps - 5 - +5 % i eq equivalent output current - 100 - +100 m a v ertical amplitude cr control range 63 steps 80 - 120 % i eqdiff(p-p) equivalent differential vertical drive output current (peak-to-peak value) sc = 00h 760 - 1140 m a v ertical shift cr control range 63 steps - 5 - +5 % i eqdiff(p-p) equivalent differential vertical drive output current (peak-to-peak value) - 50 - +50 m a s- correction cr control range 63 steps 0 - 30 % symbol parameter conditions min. typ. max. unit
1996 jan 26 24 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A v ertical expansion ( zoom ) mode (TDA8376A only ); note 18 output current variation compared with nominal scan: vef vertical expansion factor 0.75 - 1.38 % output current limiting and rgb blanking - 1.06 - % colour demodulation part c hrominance amplifier acc cr acc control range note 19 26 -- db d v variation in amplitude of the output signals over the acc range -- 2db thr on threshold colour killer on - 23 - 26 - 29 db hys off hysteresis colour killer off strong signal conditions; s/n 3 40 db; note 2 - +3 - db noisy input signals; note 2 - +1 - db r eference part phase-locked loop; note 20 f cr frequency catching range 360 600 - hz dj phase shift for a 400 hz deviation of the oscillator frequency note 2 -- 2 deg oscillator tc osc temperature coef?cient of the oscillator frequency note 2 -- tbf hz/k d f osc oscillator frequency deviation with respect to the supply note 2; v p =8v 10% -- tbf hz r i(min) minimum negative input resistance -- 1k w c l(max) maximum load capacitance -- 15 pf h ue control hue cr hue control range 63 steps; see fig.6 35 40 - deg d hue hue variation for 10% v p note 2 - 0 - deg d hue/ d t hue variation with temperature t amb = 0 to 70 c; note 2 - 0 - deg symbol parameter conditions min. typ. max. unit
1996 jan 26 25 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A d emodulators ( pins 29 and 30) v 30(p-p) - (r - y) output voltage amplitude (peak-to-peak value) note 21 - 0.525 - v v 29(p-p) - (b - y) output voltage amplitude (peak-to-peak value) note 21 - 0.675 - v g gain ratio between both demodulators g(b - y) and g(r - y) 1.60 1.78 1.96 d v spread of voltage amplitude ratio pal/ntsc note 2 - 1 - +1 db z o output impedance - (r - y)/ - (b - y) output note 2 - 500 -w b bandwidth of demodulators - 3 db; notes 7 and 21 - 650 - khz v 29,30(p-p) residual carrier output (peak-to-peak value) f=f osc ; - (r - y) output -- 5mv f=f osc ; - (b - y) output -- 5mv f=2f osc ; - (r - y) output -- 5mv f=2f osc ; - (b - y) output -- 5mv v 30(p-p) h/2 ripple at - (r - y) output (peak-to-peak value) -- 25 mv d v o / d t variation of output voltage amplitude with temperature note 2 - 0.1 - %/k d v o / d v p variation of output voltage amplitude with supply voltage note 2 -- 0.1 db j e phase error in the demodulated signals -- 5 deg c olour difference matrices in control circuit pal or (secam mode with tda8395); - (r - y) and - (b - y) not affected (g - y)/(r - y) ratio of demodulated signals -- 0.51 10% - (g - y)/(b - y) ratio of demodulated signals -- 0.19 25% - ntsc mode; the colour-difference matrix results in the following signals (nominal hue setting) - (b - y) - (b - y) signal - (b - y) - (r - y) - (r - y) signal 1.39(r - y) - 0.07(b - y) - (g - y) - (g - y) signal - 0.46(r - y) - 0.15(b - y) symbol parameter conditions min. typ. max. unit
1996 jan 26 26 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A r eference signal output for tda8395 ( pin 36); note 22 f ref reference frequency - 4.43 - mhz v 36(p-p) output voltage amplitude (peak-to-peak value) 0.2 0.25 0.3 v v o output voltage level pal/ntsc identi?ed - 1.5 - v no pal/ntsc identi?ed; secam (by tda8395) identi?ed - 5.0 - v i 36 required current to stop pal/ntsc identi?cation circuit during secam 150 --m a control part s aturation control ; note 6 sat cr saturation control range 63 steps; see fig.7 52 -- db c ontrast control ; note 6 con cr contrast control range 63 steps - 20 - db tracking between the three channels over a control range of 10 db see fig.8 -- 0.5 db b rightness control bri cr brightness control range 63 steps; see fig.9 - 0.7 - v rgb output signals ( pins 19, 20 and 21) v 19,20,21(p-p) output voltage amplitude (peak-to-peak value) at nominal luminance input signal, nominal contrast and white-point adjustment; note 6 tbf 2.0 tbf v at maximum white point setting - 3.0 - v v bwmax(p-p) maximum voltage amplitude (black-to-white) note 23 - 2.6 - v at maximum white point setting - 3.6 - v v red(p-p) output voltage amplitude for the red channel (peak-to-peak value) at nominal settings for contrast and saturation control and no luminance signal to the input (r - y, pal) tbf 2.1 tbf v v blank blanking level at the rgb outputs 0.7 0.8 0.9 v i bias internal bias current of npn emitter follower output transistor - 1.5 - ma i o available output current - 5 - ma z o output impedance - 150 -w cr bl control range of the black-current stabilization nominal brightness and white-point adjustment (with respect to the measuring pulse); v blk = 2.5 v -- 1v symbol parameter conditions min. typ. max. unit
1996 jan 26 27 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A v bl black level shift with picture content note 2 -- 20 mv v o output voltage of the 4-l pulse after switch-on - 4.2 - v d bl/ d t variation of black level with temperature note 2 - 1.0 - mv/k d bl relative variation in black level between the three channels during variations of note 2 supply voltage ( 10%) nominal controls -- tbf mv saturation (50 db) nominal contrast -- tbf mv contrast (20 db) nominal saturation -- tbf mv brightness ( 0.5 v) nominal controls -- tbf mv temperature (range 40 c) -- tbf mv s/n signal-to-noise ratio of the output signals rgb input; note 24 60 -- db cvbs input; note 24 50 -- db v res(p-p) residual voltage at the rgb outputs (peak-to-peak value) at f osc -- 15 mv at 2f osc plus higher harmonics in rgb outputs -- 15 mv b bandwidth of output signals rgb input; at - 3db 8 -- mhz cvbs input; at - 3 db; f osc = 3.58 mhz - 2.8 - mhz cvbs input; at - 3 db; f osc = 4.43 mhz - 3.5 - mhz s-vhs input; at - 3db 5 -- mhz w hite - point adjustment i 2 c-bus setting for nominal gain hex code - 20h - g inc(max) maximum increase of the gain hex code 3fh 40 50 60 % g dec(max) maximum decrease of the gain hex code 00h 40 50 60 % b lack - current stabilization ( pin 18); note 25 i bias bias current for the picture tube cathode nominal white point setting - 10 -m a i leak acceptable leakage current - 100 -m a i scan(max) maximum current during scan - 0.3 - ma symbol parameter conditions min. typ. max. unit
1996 jan 26 28 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A notes 1. signal with negative-going sync. amplitude includes sync pulse amplitude. 2. this parameter is not tested during production but is guaranteed by the design and qualified by means of matrix batches which are made in the pilot production period. 3. this parameter is measured at nominal settings of the various controls. 4. indicated is a signal for a colour bar with 75% saturation (chrominance : burst ratio = 2.2 : 1). 5. the rgb1 inputs (pins 14 to 17) have priority over the rgb2 inputs (pins 23 to 25). 6. nominal contrast is specified with the dac in position 20h. nominal saturation as maximum - 10 db. in the nominal brightness setting the black level at the outputs is identical to the level of the black-current measuring pulses. 7. this parameter is not tested during production and is just given as application information for the designer of the television receiver. 8. the - 3 db bandwidth of the circuit can be calculated by means of the following equation: 9. valid for a signal amplitude on the y-input of 0.7 v black-to-white (100 ire) with a rise time (10% to 90%) of 70 ns and the video switch in the y/c mode. during production the peaking function is not tested by measuring the overshoots but by measuring the frequency response of the y output. 10. for video signals with a black level which deviates from the back-porch blanking level the signal is stretched to the blanking level. the amount of correction depends on the ire value of the signal (see fig.10). the black level is detected by the capacitor connected to pin 2. the black level stretcher can be made inoperative by connecting pin 2 to the positive supply line. the values given are valid only when the luminance input signal (pins 7, 9 and 13) has a value of 1 v (p-p). 11. the slicing level is independent of sync pulse amplitude. the given percentage is the distance between the slicing level and the black level (back porch). b eam current limiting ( pin 22); note 23 v cr contrast reduction starting voltage - 3.5 - v v diffcr voltage difference for full contrast reduction - 2.0 - v v br brightness reduction starting voltage - 2.5 - v v diffbr voltage difference for full brightness reduction - 1.0 - v v bias internal bias voltage - 4.5 - v i ch(int) internal charge current - 25 -m a i disch discharge current due to peak-white limiting - 200 -m a symbol parameter conditions min. typ. max. unit f 3db C f osc 1 1 2q ------- - C ? ?? =
1996 jan 26 29 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A 12. to obtain a good performance for both weak signal and vcr playback the time constant of the first control loop is switched depending on the input signal condition and the condition of the i 2 c-bus. therefore the circuit contains a noise detector and the time constant is switched to slow when too much noise is present in the signal. in the fast mode during the vertical retrace time the phase detector current is increased 50% so that phase errors due to head-switching of the vcr are corrected as soon as possible. switching between the two modes can be automatically or overruled by the i 2 c-bus. the circuit contains a video identification circuit which is independent of first loop. this identification circuit can be used to close or open the first control loop when a video signal is present or not present on the input. this enables a stable on screen display (osd) when just noise is present at the input. the coupling of the video identification circuit with the first loop can be defeated via the i 2 c-bus. to prevent that the horizontal synchronization being disturbed by anti-copy guard signals like macrovision the phase detector is gated during the vertical retrace period so that pulses during scan have no effect on the output voltage. the width of the gate pulse is approximately 22 m s, the phase position around the sync pulse is asymmetrical. during weak signal conditions (noise detector active) the gating is active during the complete scan period and the width of the gate pulse is reduced to 5.7 m s so that the effect of the noise is reduced to a minimum. the output current of the phase detector in the various conditions are shown in table 39. 13. the ics have two protection inputs. the protection on pin 43 is intended to be used as flash protection. when this protection is activated the horizontal drive pulse is switched-off immediately and then switched on again via the slow start procedure. the protection on pin 49 is intended for overvoltage (x-ray) protection. when this protection is activated the horizontal drive can be switched-off (via the slow stop procedure). it is also possible to continue the horizontal drive and to set the protection bit (xpr) in the output bytes of the i 2 c-bus. the choice between the two modes of operation is made via the prd bit. 14. during switch-on the horizontal output starts with the double frequency and with a duty factor of 75% (v hout = high). after approximately 50 ms the frequency is changed to the normal value. because of the high frequency the peak currents in the horizontal output transistor are limited. also during switch-off the frequency is switched to the double value and the rgb drive is set to maximum so that the eht capacitor is discharged. after approximately 100 ms the rgb drive is set to minimum and 50 ms later the horizontal drive is switched-off. 15. the timing pulses for the vertical ramp generator are obtained from the horizontal oscillator via a divider circuit. this divider circuit has 3 modes of operation: a) search mode large window. this mode is switched on when the circuit is not synchronized or when a non-standard signal (number of lines per frame in the 50 hz mode is between 311 and 314 and in the 60 hz mode between 261 and 264). in the search mode the divider can be triggered between line 244 and line 361 (approximately 45 to 64.5 hz). b) standard mode narrow window. this mode is switched on when more than 15 successive vertical sync pulses are detected in the narrow window. when the circuit is in the standard mode and a vertical sync pulse is missing the retrace of the vertical ramp generator is started at the end of the window. consequently, the disturbance of the picture is very small. the circuit will switch back to the search window when, for 6 successive vertical periods, no sync pulses are found within the window. c) standard tv-norm (divider ratio 525 (60 hz) or 625 (50 hz). when the system is switched to the narrow window it is checked whether the incoming vertical sync pulses are in accordance with the tv-norm. when 15 standard tv-norm pulses are counted the divider system is switched to the standard divider ratio mode. in this mode the divider is always reset at the standard value even if the vertical sync pulse is missing. when 3 vertical sync pulses are missed the system switches back to the narrow window and when also in this window no sync pulses are found (condition 3 missing pulses) the system switches over to the search window. the vertical divider requires some waiting time during channel-switching of the tuner. when a fast reaction of the divider is required during channel-switching the system can be forced to the search window by means of the ncin bit in subaddress 08.
1996 jan 26 30 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A 16. conditions: frequency is 50 hz; normal mode; vs = 1fh. 17. the e-w output current range of the TDA8376A is higher than that of the tda8376 because of the horizontal zoom function of the TDA8376A. the output range percentages mentioned for e-w control parameters are based on the assumption that 400 m a variation in e-w output current is equivalent to 20% variation in picture width. 18. the TDA8376A has a zoom adjustment possibility for the vertical and horizontal deflection. for this reason an extra dac has been added in the vertical amplitude control which controls the vertical scan amplitude between 75 to 138% of the nominal scan. at an amplitude of 106% of the nominal scan the output current is limited and the blanking of he rgb outputs is activated. this is illustrated in fig.21. in addition to the variation of the vertical amplitude the vertical slope control range is also increased. this allows variation of the position of the bottom part of the picture independent of the upper part. the nominal scan height must be adjusted at a position of 19h of the vertical zoom dac. 19. at a chrominance input voltage of 660 mv (p-p) [colour bar with 75% saturation i.e. burst signal amplitude 300 mv (p-p)] the dynamic range of the acc is +6 and - 20 db. 20. all frequency variations are referenced to a 3.58 or 4.43 mhz carrier frequency. all oscillator specifications are measured with the philips crystal series 9922 520 with a series capacitance of 18 pf. the oscillator circuit is rather insensitive to the spurious responses of the crystal. provided the resonance resistance of the third overtone is higher than that of the fundamental frequency the oscillator will operate at the correct frequency. the typical crystal parameters for the crystals are: a) load resonance frequency f 0 (c l = 20 pf) = 4.433619 or 3.579545 mhz b) motional capacitance c m = 20.6 ff (4.43 mhz crystal) or 14.7 ff (3.58 mhz crystal) c) parallel capacitance c 0 = 5 pf for both crystals. the minimum detuning range can only be specified if both the ic and the crystal tolerances are known and the figures given in are therefore valid for the specified crystal series. in this, tolerances of the crystal with respect to nominal frequency, motional capacitance and ageing have been taken into account and have been counted for by gaussic addition. whenever different typical crystal parameters are used the following equation might be helpful for calculating the impact on the detuning capabilities: detuning range: the resulting detuning range should be corrected for temperature shift and supply deviation of both the ic and the crystal. the actual series capacitance in the application should be c l = 18 pf to account for parasitic capacitances on and off chip. for 3-normal applications with two crystals connected to one pin the maximum parasitic capacitance of the crystal pin should not exceed 15 pf. 21. the - (r - y) and - (b - y) signals are demodulated with a phase difference of the reference carrier of 90 and a gain ratio . the matrixing to the required signals is achieved in the control part. 22. the subcarrier output signal can be supplied to the tda8395 but it can also be used as drive signal for external comb filters. for this reason the signal is continuously available at the output. only when secam has been identified the subcarrier signal is available only during the vertical retrace time. this is to avoid cross-talk between the secam input signal and the subcarrier signal. an external dc load on this pin is not allowed because this current will disturb the reliability of the communication between the tda8376/TDA8376A and the tda8395. 23. at nominal setting of the gain control. when this amplitude is exceeded the peak-white limiting circuit will reduce the contrast. the control voltage is generated via the external capacitor connected to the beam-current limiting input. 24. signal-to-noise ratio (s/n) is specified as peak-to-peak signal with respect to rms noise (bandwidth 5 mhz). 25. this is a current input. the indicated value of the nominal bias current is obtained at the nominal setting of the gain (white point) control. the actual value of the bias current depends on the gain control setting of each channel. as a result the black-current of each gun is adapted to the white point setting so that the background colour will follow the white point adjustment. c m 1 c 0 c l ------ - + ? ? ?? 2 -------------------------- by C () C ry C () C ----------------------- - 1.78 =
1996 jan 26 31 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A table 39 output current of the phase detector in the various conditions note 1. only during vertical retrace, pulse width 22 m s. in other conditions the pulse width is 5.7 m s and the gating is continuous. i 2 c-bus commands ic conditions j -1 current/mode vid poc foa fob ident coin noise scan v-retr gating mode - 0 0 0 yes yes yes 30 30 yes (1) auto - 0 0 0 yes no no 180 270 no auto - 0 0 1 yes yes yes 30 30 yes slow - 0 0 1 yes yes no 180 270 yes fast - 01 - yes -- 180 270 no fast 00 -- no -- 6 6 no osd - 1 -------- off mla738 - 1 50 30 10 10 30 50 (%) 048c10 f dac (hex) fig.5 peaking control curve. overshoot in direction black. mla739 - 1 50 30 10 10 30 50 (deg) 0 10203040 dac (hex) fig.6 hue control curve.
1996 jan 26 32 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A mla740 - 1 250 25 0 (%) 0 10203040 dac (hex) 50 75 100 125 150 175 200 225 fig.7 saturation control curve. fig.8 contrast control curve. mla741 - 1 90 50 10 (%) 0 10203040 dac (hex) 20 30 40 60 70 80 100 mla742 - 1 0.7 0.35 0 0.35 0.7 0 (v) 0 10203040 dac (hex) fig.9 brightness control curve. relative variation with respect to the measuring pulse. fig.10 i/o relationship of the black level stretcher. (1) maximum black level shift. (2) level shift at 15% of peak white. handbook, halfpage a a b 100 output (ire) 60 20 - 20 80 40 0 input (ire) 20 0 100 mge079 40 60 80 (1) (2) b
1996 jan 26 33 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A 13 test and application information fig.11 application diagram. handbook, full pagewidth mge080 sda xtal2 34 33 38 4 3 15 16 17 14 23 24 25 26 36 30 29 32 31 39 21 20 19 18 22 46 47 48 40 41 xtal1 scl ri2 gi2 bi2 rgbin2 ri1 gi1 bi1 ro go bo blkin bclin ewd vdr (p) sec ref vdr (n) hout byo 3.6 mhz 4.4 mhz ryo ryi cvbs/ txt byi sco fbi to text decoder rgbin1 cvbs int cvbs ext cvbs/y chroma pipo 9 13 7 6 11 tda8395 tda8376(a) tda4665 13.1 east-west output stage in order to obtain correct tracking of the vertical and horizontal eht-correction, the e-w output stage should be dimensioned as illustrated in fig.12. resistor r ew determines the gain of the e-w output stage. resistor r c determines the reference current for both the vertical sawtooth generator and the geometry processor. the preferred value of r c is 39 k w which results in a reference current of 100 m a (v ref = 3.9 v the value of r ew must be: example: with v ref = 3.9 v r c =39k w and v scan = 120 v then r ew = 68 k w. r ew r c v scan 18 v ref ---------------------- - =
1996 jan 26 34 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A fig.12 east-west output stage. handbook, full pagewidth mge081 tda8376(a) horizontal deflection stage diode modulator ew output stage ewd 100 nf (5%) 39 k w (2%) 46 50 51 r c c saw r ew v dd v scan v ew i ref v ref fig.13 control range of vertical amplitude. va = 0, 31h and 63h; vsh = 31h; sc = 0. handbook, halfpage 0 600 200 - 200 - 600 - 400 0 400 t mge082 1/2 t i vert ( m a) time fig.14 control range of vertical slope. vs = 0, 31h and 63h; va = 31h; vhs = 31h; sc = 0. handbook, halfpage 0t 900 500 - 300 - 700 100 700 - 100 - 500 300 mge083 1/2 t time i vert ( m a)
1996 jan 26 35 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A fig.15 control range of vertical shift. vsh = 0, 31h and 63h; va = 31h; sc = 0. handbook, halfpage 0 600 200 - 200 - 600 - 400 0 400 t mge084 1/2 t time i vert ( m a) fig.16 control range of s-correction. sc = 0, 31h and 63h; va = 31h; vhs = 31h. picture height does not change with setting of s-correction for nominal vertical amplitude (va = 31h). handbook, halfpage 0 600 200 -200 -600 -400 0 400 t mge085 1/2 t time i vert ( m a) fig.17 control range of e-w width. ew = 0, 31h and 63h; pw = 31h; cp = 31h. handbook, halfpage 0 1200 800 400 0 200 600 1000 t mge086 1/2 t time i ew ( m a) fig.18 control range of e-w parabola/width ratio. pw = 0, 31h and 63h; ew = 31h; cp = 31h. handbook, halfpage 0 900 700 500 300 400 600 800 t time mge087 1/2 t i ew ( m a)
1996 jan 26 36 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A fig.19 control range of e-w corner/parabola ratio. cp = 0, 31h and 63h; ew = 31h; pw = 63h. handbook, halfpage 0 900 700 500 300 400 600 800 t time mge088 1/2 t i ew ( m a) fig.20 control range of e-w trapezium correction. tc = 0, 31h and 63h; ew = 31h; pw = 31h. handbook, halfpage 0 600 500 400 650 550 450 350 t time mge089 1/2 t i ew ( m a) fig.21 sawtooth waveform and blanking pulse. TDA8376A only. handbook, full pagewidth 60 70 50 40 30 138% 75% 20 10 0 - 10 - 20 - 30 - 40 - 50 - 60 bottom picture top picture vertical position (%) 100% 1/2 t time blanking for expansion 138% t mge090
1996 jan 26 37 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A 13.2 adjustment of geometry control parameters the deflection processor of the tda8376/TDA8376A offers nine control parameters for picture alignment: vertical picture alignment C s-correction C vertical amplitude C vertical slope C vertical shift horizontal picture alignment C horizontal shift C e-w width C e-w parabola/width C e-w corner/parabola C e-w trapezium correction. it is important to notice that the tda8376/ TDA8376A is designed for use with a dc-coupled vertical deflection stage. this is the reason why a vertical linearity alignment is not necessary (and therefore not available). for a particular combination of picture tube type, vertical output stage and e-w output stage it is determined which are the required values for the settings of s-correction, e-w parabola/width ratio and e-w corner/parabola ratio. these parameters can be preset via the i 2 c-bus, and do not need any additional adjustment. the remainder of the parameters are preset with the mid-value of their control range (i.e. 1fh), or with the values obtained by previous tv-set adjustments. the vertical shift control is intended for compensation of off-sets in the external vertical output stage or in the picture tube. it can be shown that without compensation these off-sets will result in a certain linearity error, especially with picture tubes that need large s-correction. the total linearity error is in first order approximation proportional to the value of the off-set, and to the square of the s-correction required. the necessity to use the vertical shift alignment depends on the expected off-sets in vertical output stage and picture tube, on the required value of the s-correction, and on the demands upon vertical linearity. for adjustment of the vertical shift and vertical slope independent of each other, a special service blanking mode can be entered by setting the sb-bit high. in this mode the rgb-outputs are blanked during the second half of the picture. there are two different methods for alignment of the picture in vertical direction. both methods make use of the service blanking mode. the first method is recommended for picture tubes that have a marking for the middle of the screen. with the vertical shift control the last line of the visible picture is positioned exactly in the middle of the screen. after this adjustment the vertical shift should not be changed. the top of the picture is placed by adjustment of the vertical amplitude, and the bottom by adjustment of the vertical slope. the second method is recommended for picture tubes that have no marking for the middle of the screen. for this method a video signal is required in which the middle of the picture is indicated (e.g. the white line in the circle test pattern). with the vertical slope control the beginning of the blanking is positioned exactly on the middle of the picture. then the top and bottom of the picture are placed symmetrical with respect to the middle of the screen by adjustment of the vertical amplitude and vertical shift. after this adjustment the vertical shift has the correct setting and should not be changed. if the vertical shift alignment is not required vsh should be set to its mid-value (i.e. vsh = 1fh). then the top of the picture is placed by adjustment of the vertical amplitude and the bottom by adjustment of the vertical slope. after the vertical picture alignment the picture is positioned in the horizontal direction by adjustment of the e-w width and the horizontal shift. finally (if necessary) the left and right-hand sides of the picture are aligned in parallel by adjusting the e-w trapezium control. to obtain the full range of the vertical zoom function of the TDA8376A the adjustment of the vertical geometry should be carried out at a nominal setting of the zoom dac at position 19h.
1996 jan 26 38 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A 14 package outlines unit b 1 cee m h l references outline version european projection issue date iec jedec eiaj mm dimensions (mm are the original dimensions) sot247-1 90-01-22 95-03-11 b max. w m e e 1 1.3 0.8 0.53 0.40 0.32 0.23 47.9 47.1 14.0 13.7 3.2 2.8 0.18 1.778 15.24 15.80 15.24 17.15 15.90 1.73 5.08 0.51 4.0 m h c (e ) 1 m e a l seating plane a 1 w m b 1 d a 2 z 52 1 27 26 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. (1) (1) d (1) z e a max. 12 a min. a max. sdip52: plastic shrink dual in-line package; 52 leads (600 mil) sot247-1
1996 jan 26 39 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.05 2.90 2.65 0.25 0.50 0.35 0.25 0.14 14.1 13.9 1 18.2 17.6 1.2 0.8 7 0 o o 0.2 0.1 0.2 1.95 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.0 0.6 sot319-2 95-02-04 97-08-01 d (1) (1) (1) 20.1 19.9 h d 24.2 23.6 e z 1.2 0.8 d e q e a 1 a l p detail x l (a ) 3 b 19 y c e h a 2 d z d a z e e v m a 1 64 52 51 33 32 20 x pin 1 index b p d h b p v m b w m w m 0 5 10 mm scale qfp64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm sot319-2 a max. 3.20
1996 jan 26 40 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A 15 soldering 15.1 introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). 15.2 sdip 15.2.1 s oldering by dipping or by wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joint for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg max ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 15.2.2 r epairing soldered joints apply a low voltage soldering iron (less than 24 v) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. 15.3 qfp 15.3.1 r eflow soldering reflow soldering techniques are suitable for all qfp packages. the choice of heating method may be influenced by larger plastic qfp packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. for more information, refer to the drypack chapter in our quality reference handbook (order code 9397 750 00192). reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary from 50 to 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheat for 45 minutes at 45 c. 15.3.2 w ave soldering wave soldering is not recommended for qfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. even with these conditions, do not consider wave soldering the following packages: qfp52 (sot379-1), qfp100 (sot317-1), qfp100 (sot317-2), qfp100 (sot382-1) or qfp160 (sot322-1). during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.3.3 r epairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1996 jan 26 41 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A 16 definitions 17 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 18 purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1996 jan 26 42 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A notes
1996 jan 26 43 philips semiconductors objective speci?cation i 2 c-bus controlled pal/ntsc tv processors tda8376; TDA8376A notes
philips semiconductors C a worldwide company argentina: ierod, av. juramento 1992 - 14.b, (1428) buenos aires, tel. (541)786 7633, fax. (541)786 9367 australia: 34 waterloo road, north ryde, nsw 2113, tel. (02)805 4455, fax. (02)805 4466 austria: triester str. 64, a-1101 wien, p.o. box 213, tel. (01)60 101-1236, fax. (01)60 101-1211 belgium: postbus 90050, 5600 pb eindhoven, the netherlands, tel. (31)40-2783749, fax. (31)40-2788399 brazil: rua do rocio 220 - 5 th floor, suite 51, cep: 04552-903-s?o paulo-sp, brazil, p.o. box 7383 (01064-970), tel. (011)821-2333, fax. (011)829-1849 canada: philips semiconductors/components: tel. (800) 234-7381, fax. (708) 296-8556 chile: av. santa maria 0760, santiago, tel. (02)773 816, fax. (02)777 6730 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. (852)2319 7888, fax. (852)2319 7700 colombia: iprelenso ltda, carrera 21 no. 56-17, 77621 bogota, tel. (571)249 7624/(571)217 4609, fax. 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(0039)2 6752 2557 japan: philips bldg 13-37, kohnan 2 -chome, minato-ku, tokyo 108, tel. (03)3740 5130, fax. (03)3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. (02)709-1412, fax. (02)709-1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. (03)750 5214, fax. (03)757 4880 mexico: 5900 gateway east, suite 200, el paso, tx 79905, tel. 9-5(800)234-7381, fax. (708)296-8556 netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. (040)2783749, fax. (040)2788399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. (09)849-4160, fax. (09)849-7811 norway: box 1, manglerud 0612, oslo, tel. (022)74 8000, fax. (022)74 8341 pakistan: philips electrical industries of pakistan ltd., exchange bldg. st-2/a, block 9, kda scheme 5, clifton, karachi 75600, tel. (021)587 4641-49, fax. (021)577035/5874546 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. (63) 2 816 6380, fax. (63) 2 817 3474 portugal: philips portuguesa, s.a., rua dr. antnio loureiro borges 5, arquiparque - miraflores, apartado 300, 2795 linda-a-velha, tel. (01)4163160/4163333, fax. (01)4163174/4163366 singapore: lorong 1, toa payoh, singapore 1231, tel. (65)350 2000, fax. (65)251 6500 south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430, johannesburg 2000, tel. (011)470-5911, fax. (011)470-5494 spain: balmes 22, 08007 barcelona, tel. (03)301 6312, fax. (03)301 42 43 sweden: kottbygatan 7, akalla. s-164 85 stockholm, tel. (0)8-632 2000, fax. (0)8-632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. (01)488 2211, fax. (01)481 77 30 taiwan: philips taiwan ltd., 23-30f, 66, chung hsiao west road, sec. 1. taipeh, taiwan roc, p.o. box 22978, taipei 100, tel. (886) 2 382 4443, fax. (886) 2 382 4444 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, thailand, tel. (66) 2 745-4090, fax. (66) 2 398-0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. (0 212)279 27 70, fax. (0212)282 67 07 ukraine: philips ukraine, 2a akademika koroleva str., office 165, 252148 kiev, tel. 380-44-4760297, fax. 380-44-4766991 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. (0181)730-5000, fax. (0181)754-8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. (800)234-7381, fax. (708)296-8556 uruguay: coronel mora 433, montevideo, tel. (02)70-4044, fax. (02)92 0601 internet: http://www.semiconductors.philips.com/ps/ for all other countries apply to: philips semiconductors, international marketing and sales, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, telex 35000 phtcnl, fax. +31-40-2724825 scds47 ? philips electronics n.v. 1996 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. printed in the netherlands 537021/1100/01/pp44 date of release: 1996 jan 26 document order number: 9397 750 00592

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