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dm9095 twisted-pair medium attachment unit 1 final version: dm9095-ds-f02 august 21, 2000 general description the dm9095 twisted-pair media attachment unit (tpmau) is designed to allow ethernet connections to use existing twisted-pair wiring plants through an ethernet attachment unit interface (aui). the dm9095 provides the electrical interface between the aui and the twisted-pair wire. the dm9095?s functions include level-shifted data pass-through from one transmission media to another, co llision detection, trans mitt ing pre- distortion generation, receiving squelch function, selectable signal-quality-error (sqe) test generation, a link- integrity strapping option, and automatic correction of polarity reversal on the twisted pair input. the dm9095 also includes led drivers for transmit, receive, jabber, co llision, reversed polarity detect and link status. the dm9095 is an advanced cmos device available in 28-pin plcc pack ages. block diagram aui data receiver aui data squelch operation mode selection aui current driver collision current driver crystal oscillator loopback control led drivers collision control jabber do + do - md0 md1 md2 di - tp pre-distortion driver link integrity auto-polarity detection tp data receiver tp data squelch di + ci + ci - osc1 tpo + dtpo + dtpo - tpo- li- ap tpi + tpi - rled cled xled jled
dm9095 twisted-pair medium attachment unit final 2 version: dm9095-ds-f02 august 21, 2000 features compatible with or exceeds i eee 802.3 standards for aui and 10base-t interfaces internal pre-distortion generator for tp driver smart squelch circuitry on all received data selectable heartbeat function selectable line-integrity test with led indication led indicator for transmit, receive, jabber, and collision advanced analog cmos process using single 5v supply lower tp threshold option for long length application selectable auto-polarity detection and correction function with led indication automatic aui/rj45 selection power-down mode full esd protection pin configuration : DM9095L DM9095L 4 3 2 1 28 27 26 mdo do- do+ gnd vdd tpi+ tpi- li- di+ di- ci+ ci- vdd ap 5 6 7 8 9 10 11 12 13 14 15 16 17 18 jled osc1 gnd cled rled xled vdd 25 24 23 22 21 20 19 md1 md2 gnd tpo- dtpo- dtpo+ tpo+
dm9095 twisted-pair medium attachment unit 3 final version: dm9095-ds-f02 august 21, 2000 pin description pin no. pin name i/o description 1 gnd - ground 2 3 do+ do- i transmitter input. a balanced differential line receiver input pair from the aui circuit that receives 10 mbits/s manchester-encoded data and applies the data to the tp cable. 4 md0 i operation mode selection pin. pulled high interna lly. 5 li- link-integrity enable. the pin is a dual function pin that determines whether the link integrity function should be realized. when this pin, which is internally pulled-high, is configured as an input pin and t ied low, the link integr ity test function is enabled. while configured as an output pin, the pin drives low for link-fail state and drives high for link-pass sta te. the output pin can drive an led status indi cator, as in figure 3(b) (page 6). 6 7 di+ di- o receiver outputs. a balanced output current driver pair to the aui transceiver cable with the 10 mbits/s manchester-encoded data received from the twisted-pair of the network. 8 9 ci+ ci- o collision outputs. balanced differential line driver outputs which send a 10mhz oscillation signal to the manchester encoder/decoder in the event of a c ollision, j abber interrupt, or heartbeat test. 10 vdd - +5v power s upply 11 ap i/o auto polarity. this pin is a dual funct ion pin which determines if the auto-polarity function should be enabled. the f unction is enabled if the pin is high. the pin is also capable of driving an led if the function is enabled. 12 jled o jabber indicator. normally off. it indicates a time-out transmission onto tp network. it turns on if the watc hdog timer has timed out and the twis ted-pair driver has been disabled. 13 osc1 i crystal pin. this pin is a 20mhz frequency-reference ter minal for internal chip timing. 14 gnd - ground
dm9095 twisted-pair medium attachment unit final 4 version: dm9095-ds-f02 august 21, 2000 pin description (continued) pin no. pin name i/o description 15 lced o collision indicator. normally off. it indicates a collision has been detected by the mau. it turns on the led if a co llision occurs. 16 rled o receive indicator. normally on. it indicates a reception from the tp network is in progress. w hen li- is disabl ed, rled will turn off if the mau receives a packet. w hen li- is enabled, rled will turn off as l ong as the link is bro ken. 17 xled o transmit indicator. normally on. it indicates that a transmiwwion onto the tp network is in progress by turning off. 18 vdd o +5v power s upply 19 20 21 22 tpo+ dtpo+ dtpo- tpo- o tp driver outputs. these four outputs provide the tp drivers with pre-distortion capab ility. the tpo+ /tpo- outputs generate 10mbits/s manchester-encoded data. the dtpo+ /dtpo- outputs are one-half bit time delayed and inverted with respect to tpo+ /tpo-. 23 gnd - ground 24 md2 i operation mode selection pin. pulled high internally 25 md1 i operation mode selection pin. pulled high internally 26 27 tpi- tpi+ i tp receive input. a differential receiver tied to the receive transformer pair of the twisted-pair wire. the receive pair of the twisted-pair medium is driven with 10mbi ts/s manchester-encoded data. 28 vdd o + 5v power s upply
dm9095 twisted-pair medium attachment unit 5 final version: dm9095-ds-f02 august 21, 2000 overview the dm9095 provides the interface between an aui and a tp wire. the receive, transmit, and co llision detection functions of the dm9095 are designed to meet the ieee 802.3 10base-t draft standard. the receive section transfers 10mbits/s manchester-encoded data from the twisted-pair to the aui, while the transmit section transfers data from the aui cable to the tp wire. the collision- detection function sends a 10mhz square wave onto the aui_ci circuits after sensing data being simultaneously transmitted and received. in addition to the these functions, there are three optional operating functions. enabling the link-integrity function causes a pulse to be transmitted in the absence of data transmission. the receiver recognized link-integrity pulses and connects the twisted-pair link. the link- integrity pin can be configured as an input or as an output. when the link-integrity pin is configured as an input, the function is enabled for proper setting. when the link- integrity pin is configured as an output, the function is enabled and the status of the link is indicated. if the heartbeat function is enabled, it allows the sqe-test sequence to be transmitted to the dte after every successful transmission on the tp wire. the option also enables normal or extended line length to be selected. when standard tp squelch levels are implemented, normal line length is used. when the tp squelch thresholds are lowered, extended line length is used. the device also contains an auto-polarity function which can be determined if the receive twisted-pair has been wired with polarity reversal. if the twisted-pair is wired with polarity reversal, the device automatically corrects for this error condition. also, the auto-polarity function can be used with an led to display the polarity of the receive twisted-pair wire. when power-down mode is set, the device shuts down, and the supply current is reduced to less t han 10 a. the dm9095 automatically pulls aui-di, aui_ci, and aui-do into high impedance state if the twisted-pair link is not connected. the function is used to provide the encoder/decoder chip to use coaxial mau. the dm9095 also includes four drivers capable of driving four leds to indicate the status of the receive, transmit, collision, and jabber functions. also, when configured correctly, two additional leds can display auto-polarity and link-integrity status.
dm9095 twisted-pair medium attachment unit final 6 version: dm9095-ds-f02 august 21, 2000 figure 3 (a). typical system application for external tpmau in mode 5 (where link integrity test is enabled, auto-polarity is disabled. li- is input pin)
dm9095 twisted-pair medium attachment unit 7 final version: dm9095-ds-f02 august 21, 2000 figure 3 (b). typical system application for internal tpmau in mode 6 (where link integrity test is enabled and auto polarity function is enabled. li- is output pin) d m9095
dm9095 twisted-pair medium attachment unit final 8 version: dm9095-ds-f02 august 21, 2000 figure 4. typical loading conditions for di and ci note: 1. possible filters are the pulse engineering inc. or an equi valent. 2. the 1:1 2kv isolation tr ansformer can be a pulse engineering or equivalent. 3. the filters and isolation transformer can be combined into one package. a possible source is valor electronics or an equi valent. figure 5. example of transmit circuit
dm9095 twisted-pair medium attachment unit 9 final version: dm9095-ds-f02 august 21, 2000 function description transmit functions the dm9095 receives transmit data from do + /do - and transfers it to the tp network. the input must be transformer-coupled to the aui circuit. the receiver is able to pass differential signals as small as 300mv peak and as large as 1315mv. dc biasing is provided with internal common-mode, the common-mode is set to nominal 2.5v. an internal analog delay line is used to generate the pre- distortion signals at dtpo + and dtpo -. the dtpo + / dtpo - signal delays 50ns after tpo + / tpo -. a delay lock loop, referenced to the crystal clock, is used to generate the internal delay line. all tp output driver pins are driver low as a result of any of the following: there is an aui idl pulse of at least 200ns duration; the output driver is jabbered; the link-integrity option is enabled and there is a link failure; or an idl pulse is not detected at the end of a packet and the input dose not exceed the detection threshold of 500ns 100ns. when the driver dete cts that it has finished sending an idl pulse onto the tp, a timer of not more than 500ns is started. while this timer is active, activity on the do + / do - inputs is ignored. receive functions the tp receiver is connected to a band-limiting filter, whose input is transformer-coupled to the twisted-pair tpi + / tpi - pins. the receiver is able to resolve differential signals as small as 350mv peak. common-mode input voltage is provided with internal common-mode, with the common- mode set to nominal 2.5v. the receiver squelch circuit prevents noise on the twisted-pair cable from falsely triggering the receiver in the absence of true data. the receiver will not be activated for si gnals at the buffer input having a peak amplitude below 300mv, a continuous frequency below 2 mhz, or a single cycle duration within the pass band of the receive filter. this driver differentially drives a current onto the load connected between the di + and di - pins. the current through the load results in an output voltage between 0.6v and 1.2v, measured differentially between the two pins. as in figure 4, it shows the typical loading for di + / di - driver. when the driver detects that it has finished sending an idl pulse onto the aui, a timer of not more than 500ns is started. while this timer is active, activity on the tpi + / tpi - inputs is ignored, and the aui driver discharges the current stored on the inductive load. collision functions a collision state ex ists whenever there are valid i nputs to the dm9095 from the network and from the dte simultaneously and the device is not in a link-integrity failure state. the dm9095 reports co llisions to the aui by s ending a 10 mhz signal over the ci + / ci - pair. the co llision report signal is output no more than 9 bt after the chip detects a collision. if tpi + / tpi - become active while there is activity on the do + / do - pair, the loopback data on tpi + / tpi - switches from transmit data to receive data within 13 bt 3 bt. if a collision c ondition exits with tpi + / tpi - having gone idle while do + / do ? are st ill active, sqe continues for 7 bt 2 bt. if a collision c ondition exits with do + / do ? having gone idle while tpi + / tpi ? are still active, sqe may cont inue for up to 9 bt. jabber functions jabber is a self-interrupt function that keeps a damaged node from continously transmitting onto the network. the chip contains a nominal w indow of 50ms, during which time a normal data link frame can be transmitted. if a frame length exceeds this duration, the jabber function inhibits transmission and sends a co llision si gnal on the ci + / ci ? pair. when activity on the do + / do ? pair has ceased, the chip continues to present the cso signal to the ci + / ci ? pair for 0.5s 50%. the transmission of link-integrity pulses from the tp drivers is not inhibited when the dm9095 is jabbed and the link integrity func tion is enabled. sqe test functions when the do + / do ? pair has gone idle after a successful transmission and the heartbeat function is enabled, the chip presents the cso signal to the ci + / ci ? pair. after a successful transmission onto the network media, the chip presents the cso signal within 11 bt 5 bt of the end of activity on the do + / do ? pair. the cso signal is presented for 10 bt 5 bt, after which the chip presents an idl on the ci + / ci ? pair and returns to the idle state.
dm9095 twisted-pair medium attachment unit final 10 version: dm9095-ds-f02 august 21, 2000 link integrity functions in the absence of receive traffic, the twisted-pair recei ver on the chip can detect periodic link-integrity pulse is a 100ns high signal with pre-distortion followed by a return to idle. the chip provides a link-integrity reception window, during which a link pulse is expected in the absence of receive traffic. the link-integrity window nominally opens 6.5ms after the receipt of a link-integrity pulse or the end of a data frame. the window closes nominally 104ms after the receipt of a link-integrity pulse or the end of a data frame. if a link pulse is received before the link-integrity reception window opens, it is ignored. if no link-integrity pulse is received while the link-integrity reception window is open, there is a link failure. the rled indicator is turned off, and the chip?s transmit, loopback, and receive functions are disabled. if a link-integrity pulse or receive traffic is received while the link-integrity reception window is open, the timers involved are reset. once the dm9095 has detected a link failure, one of two events must occur before the dm9095 re-enables transmission and reception of data. the first possible event is the reception of two consecutive link-integrity pulses that both fall within the link-integrity reception window and are separated by at least a nominal 6.5ms. the second possible event is the reception of a data packet from the twisted pair. with either of these events, the tpmau enters a wait state and continues to disable loopback, transmit, and receive functions. this continues until the dm9095 determines that there is no traffic going in either the transmit or receive direction and then enters the idle state. when the link integrity func tion is enabled, the dm9095 also transmits link-integrity pulses onto the transmit twisted-pair link. in the absence of transmit traffic, a link-integrity pulse is transmitted at a nominal rate of once per 16ms. link-integrity pulses continue to be transmitted when the part is jabbed by the watchdog timer or there is link-integrity failure. auto-polarity detection and correction functions the dm9095 can determine if the receive twisted pair has been wired with a polarity reversal. if so, the dm9095 automatically corrects for this error condition, when the correction function is enabled. also, the ap pin itself can be connected to an led to display the status of the polarity of the receive twisted pair. when enabled, the dm9095 powers up the function in the normal state and determines if the receive wires are reversed. the dm9095 examines either the idl pulse at the end of each receive packet or the link pulse when the link integrity function is enabled and uses this information to sense the polarity. if the dm9095 determines that the incoming idl pulse is of the proper polarity, it remains in normal state. if the dm9095 detects two consecutive reverse idl pulses or two reverse link pulses, it enters reverse state. if the dm9095 determines that the polarity of the link is reversed, it internally corrects for the polarity, ensuring that all follow-on packets are sent up the aui with the correct polarity. automatic aui and rj45 c onnector selection functions the chip provides the designer of a 10base-t ethernet interface card with the ability to design a card wit hout having to provide a switch or jumper array to change between aui and twisted-pair connections. the dm9095 provides automatic changeover whenever the external cable connection is changed. when the link integrity function is enabled and twis ted-pair c able is di sconnected, all incoming receive signals disappear and the device places the ci + / ci ? and di + / di ? outputs in their high-impedance state. in addition, do + / do ? i nputs are high-impedance i nputs. power-down mode function the power-down function is ideal for embedded, laptop computer applications. in power-down mode, the chip pulls within 10ua. when the device is reactivated from power-down mode, normal transceiver operation will resume after the 3.2ms calibration sequence is completed. power-on reset function the dm9095 uses a power-on reset sequence to place itself into a known digital state, to allow the analog sections to stabilize, and to calibrate the internal delay line. depending on the power-down condition, initialization requires the following lengths of time: power-on reset: 3.2 ms power-down mode: 3.2 ms
dm9095 twisted-pair medium attachment unit 11 final version: dm9095-ds-f02 august 21, 2000 crystal oscillator an external ttl-level clock can be applied to the osc1 pin which is crystal oscillator i nput. a resistor should be added in series with the clock source to limit the amplitude of the voltage swing seen by the pin. a 500 resistor works well in most cases. led status functions the led drivers require an external resistor in series with the led, which is in turn connected to vdd. the driver pulls the pin low to light the led and can sink up to 15ma of drive current from the resistor with an output impedance of less than 50 . the dm9095 provides three types led drivers, as follows. output led drivers: the led outputs xled, rled, jled, and cled are output led drivers. these signals are used for status information only. xled drives high when the dm9095 is transmitting a packet. xled is not asserted if the dm9095 has detected a jabber function or is in a link-fail state. rled drives high when the dm9095 is receiving a packet. rled is not asserted when the dm9095 is in a link-fail state. jled drives low when the dm9095 has detected a jabber condition. cled drives low when the dm9095 has detected a co llision c ondition. sampled led driver: the ap pin is used to set the configuration of the dm9095 and drive the led st atus indicators. every 26ms, the pin is configured as an input pin for 6.5 s. during this time, it is sampled by the dm9095. outside the sampling window, the driver is placed in an output state and used to drive the led indicators. ap is driven low to indicate that a reversed twisted pair has been detected on the receive circuit and corrected. if ap is tied low, dm9095 disables the auto-polarity function; when ap is pulled high externally, the function is enabled. input / output led driver: li-pin is an input/output pin, depending on the mode selection. when configured as an input pin, li-controls the link integrity test option. if li- is connected to gnd, the link integrity function is enabled. if li- is connected to v dd or left floating (internal pull-high), the link integrity function is disabled. when configured as an output pin, the pin drives low for link-fail state and drives high for link-pass state. the output pin can drive an led status indicator. power there are six power connections to the dm9095, including three vdd and three gnd connections. pins 1 and 28 are used for analog supplies, including squelch circuits, receiver, and the internal delay circuit. pins 10 and 14 are used for digital circuits, the i/o buffer, the control logic for analog circu its, and the crystal oscillator circuit. pins 18 and 23 are used for the twisted pair driver output buffer. operating modes the mode selection pins are used to select one of eight operating modes. these modes are summarized in the table below. the modes referred to in the table are the following: heartbeat: a yest means that the heartbeat function is enabled; a no means the heartbeat function is disabled. line length: ?ext ended? indicates that tp receive squelch thresholds have been lowered to 300mv for use with longer line lengths; normal indicates that the standard 10base-t tp receive squelch threshold of 450mv w ill be used. li-: the li- pin can be configured to be an input pin, whereby the link-integrity function can be enabled or disabled. the li- pin can also be configured as an output pin to indicate the status of the link, where the link-integrity is enabled. mode description mode md0 md1 md2 heartbeat line length li- application 0000 no ext ended i long wire tp 1001 no normal inormal wire tp 2010 no normal oli pin led output 3011 poer-down mode 4100 yes ext ended i long wire tp 5101 yes normal inormal wire tp 6110 yes normal oli pin led output 7111 power-down mode
dm9095 twisted-pair medium attachment unit final 12 version: dm9095-ds-f02 august 21, 2000 ac electrical characteristics symbol parameter min. typ. max. unit transmit timing t td transmit delay from do to tpo 0 200 ns t tlb loopback delay from do to di 0 500 ns t tpdy dtpo - to tpo + and dtpo + to tpo - delay 47 53 ns t toff do + high to idle time 200 ns t tidl tpo + high to idle time 250 350 ns receive timing t rd receive delay from tpi to di 0 500 ns t roff tpi + high to idle time 200 ns t ridl di + high to idle time 250 350 ns collision timing t cb collision turn-on time 0 900 ns t ce collision turn-off time 0 900 ns t clb loopback delay when switching from do to tpi 1000 1600 ns t cidl ci + high to idle time 250 350 ns t cph collision high-pulse width 40 50 60 ns t cp collision period 80 100 120 ns jabber timing t jmt maximum transmit time for tpo 45 50 55 ms t jcb time from jabber to enable ci output 0 900 ns t ju unjab time 250 450 750 ms
dm9095 twisted-pair medium attachment unit 13 final version: dm9095-ds-f02 august 21, 2000 ac electrical characteristics (continued) symbol parameter min. typ. max. unit link integrity timing t lp transmitted link integrity pulse period 8 16 24 ms t lpwt link integrity pulse width for tpo + 80 100 120 ns t lpwd link integrity pulse width for dtpo 40 50 60 ns heartbeat timing t hd heartbeat turn-on time 600 1600 ns t hcs heartbeat active time for ci output 500 1500 ns led timing t xset xled turn-off time 10 s t xoff xled off time 90 110 ms t xon xled minimum on time 4 8 ms t roff rled off time 90 110 ms t ron rled minimum on time 4 8 ms t rlfset rled turn-off time for link fail 50 150 ms t rlfoff rled off time for link fail t rlfon rled on time for link success 0.5 1.5 s t cset cled turn-on time 10 s t con cled nominal on time 10 20 ms t jset jled turn-on time 10 s t jon jled on time 250 750 ms
dm9095 twisted-pair medium attachment unit final 14 version: dm9095-ds-f02 august 21, 2000 timing waveforms
dm9095 twisted-pair medium attachment unit 15 final version: dm9095-ds-f02 august 21, 2000
dm9095 twisted-pair medium attachment unit final 16 version: dm9095-ds-f02 august 21, 2000 timing waveforms (continued)
dm9095 twisted-pair medium attachment unit 17 final version: dm9095-ds-f02 august 21, 2000 timing waveforms (continued) figure 10. transmitted link integrity pulse timing
dm9095 twisted-pair medium attachment unit final 18 version: dm9095-ds-f02 august 21, 2000 timing waveforms (continued)
dm9095 twisted-pair medium attachment unit 19 final version: dm9095-ds-f02 august 21, 2000 timing waveforms (continued)
dm9095 twisted-pair medium attachment unit final 20 version: dm9095-ds-f02 august 21, 2000 package information plcc 28l outline dimensions unit: inch/mm note: 1. dimension d & e do not include resin fin. 2. dimensions g d & g e are for pc board surface mount pad pi tch design reference only.
dm9095 twisted-pair medium attachment unit 21 final version: dm9095-ds-f02 august 21, 2000 ordering information part number pin count p ackage DM9095L 28 plcc disclaimer the information appearing in this publication is believed to be accurate. integrated circuits sold by d avicom semiconductor are covered by the warranty and patent indemnification pro visions st ipulated in the terms of sale only. davicom makes no warranty, express, statutory, implied or by description regarding the information in this publication or regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. further, davicom makes no warranty of merchantability or fitness for any purpose. davicom deserves the right to halt production or alter the spe cificat ions and prices at any time without notice. accordingly, the reader is cautioned to verify that the data s heets and other information in this publication are current before placing orders. pr oducts descri bed herein are intended for use in normal commer cial applications. applications involving unusual environmental or reliability requirements, e.g. m ilitary equipment or medical life support equipment, are specifically not recommended without additional processing by davicom for such applications. please note that application circuits illustrated in this document are for reference purposes only. davicom?s terms and conditions printed on the order acknowledgment govern all sales by davicom. davicom will not be bound by any terms inconsistent with these unless d avicom agrees otherwise in w riting. acceptance of the buyer?s orders shall be based on these terms. company overview davicom semiconductor, inc. develops and manufactures integrated circuits for integration into data communication products. our mission is to design and produce ic products that re the industry?s best value for data, audio, video, and interne t/intr anet applications. to achieve this goal, we have built an organization that is able to develop chipsets in response to the evolving technology requirements of our customers while st ill delivering pr oducts that meet their cost requirements. products we offer only produ cts that satisfy high performance requirements and which are compatible with major hardware and software standards. our currently available and soon to be released pr oducts are ba sed on our proprietary designs and deliver high quality, high performance chipsets that comply with modem communication standards and ethernet networking standards. contact windows for additional information about davicom pr oducts, contact the sales department at: headquarters hsin-chu office: 3f, no. 7-2, industry e. rd., ix, science-based park, hsin-chu city, taiwan, r.o.c. tel: 886-3-5798797 fax: 886-3-5798858 taipei sales & marketing office: 8f, no. 3, lane 235, bao-chiao rd., hsin-tien, taipei, taiwan, r.o.c. tel: 886-2-29153030 fax: 886-2-29157575 email: sales@davicom.com.tw davicom usa sunnyvale, california 1135 kern ave., sunnyvale, ca94085, u.s.a. tel: 1-408-7368600 fax: 1-408-7368688 email: sales@davicom8.com warning conditions beyond those listed for the absolute maximum may destroy or damage the products. in addition, conditions for sustai ned periods at near the limit s of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and/or function .

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