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isplsi 2128ve 3.3v in-system programmable superfast? high density pld 2128ve_11 1 features ? superfast high density in-system programmable logic ? 6000 pld gates ? 128 and 64 i/o pin versions, eight dedicated inputs ? 128 registers ? high speed global interconnect ? wide input gating for fast counters, state machines, address decoders, etc. ? small logic block size for random logic ? 100% functional, jedec and pinout compatible with isplsi 2128v devices ? 3.3v low voltage 2128 architecture ? interfaces with standard 5v ttl devices ? high performance e 2 cmos ? technology ? f max = 250mhz maximum operating frequency ? t pd = 4.0ns propagation delay ? electrically erasable and reprogrammable ? non-volatile ? 100% tested at time of manufacture ? unused product term shutdown saves power ? in-system programmable ? 3.3v in-system programmability (isp?) using boundary scan test access port (tap) ? open-drain output option for flexible bus interface capability, allowing easy implementation of wired- or bus arbitration logic ? increased manufacturing yields, reduced time-to- market and improved product quality ? reprogram soldered devices for faster prototyping ? 100% ieee 1149.1 boundary scan testable ? the ease of use and fast system speed of plds with the density and flexibility of fpgas ? enhanced pin locking capability ? three dedicated clock input pins ? synchronous and asynchronous clocks ? programmable output slew rate control ? flexible pin placement ? optimized global routing pool provides global interconnectivity functional block diagram* description the isplsi 2128ve is a high density programmable logic device available in 128 and 64 i/o-pin versions. the device contains 128 registers, eight dedicated input pins, three dedicated clock input pins, two dedi- cated global oe input pins and a global routing pool (grp). the grp provides complete interconnectivity between all of these elements. the isplsi 2128ve features in-system programmability through the bound- ary scan test access port (tap) and is 100% ieee 1149.1 boundary scan testable. the isplsi 2128ve offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable sys- tems. the basic unit of logic on the isplsi 2128ve device is the generic logic block (glb). the glbs are labeled a0, a1 .. d7 (see figure 1). there are a total of 32 glbs in the isplsi 2128ve device. each glb is made up of four macrocells. each glb has 18 inputs, a programmable and/or/exclusive or array, and four outputs which can be configured to be either combinatorial or registered. inputs to the glb come from the grp and dedicated inputs. all of the glb outputs are brought back into the grp so that they can be connected to the inputs of any glb on the device. global routing pool (grp) output routing pool (orp) output routing pool (orp) output routing pool (orp) output routing pool (orp) output routing pool (orp) output routing pool (orp) clk 0 output routing pool (orp) output routing pool (orp) clk 1 clk 2 logic array glb dq dq dq dq 0139a/2128v e c7 c6 c5 c4 c3 c2 c1 c0 d3 d2 d1 d0 d7 d6 d5 d4 b4 b5 b6 b7 b0 b1 b2 b3 a0 a1 a2 a3 a4 a5 a6 a7 *128 i/o version shown copyright ? 2002 lattice semiconductor corp. all brand or product names are trademarks or registered trademarks of their respec tive holders. the specifications and information herein are subject to change without notice. lattice semiconductor corp., 5555 northeast moore ct., hillsboro, oregon 97124, u.s.a. january 2002 t el. (503) 268-8000; 1-800-lattice; fax (503) 268-8556; http://www.latticesemi.com
specifications isplsi 2128ve 2 functional block diagram figure 1. isplsi 2128ve functional block diagram (128-i/o and 64-i/o versions) the 128-i/o 2128ve contains 128 i/o cells, while the 64- i/o version contains 64 i/o cells. each i/o cell is directly connected to an i/o pin and can be individually pro- grammed to be a combinatorial input, output or bi-directional i/o pin with 3-state control. the signal levels are ttl compatible voltages and the output drivers can source 4ma or sink 8ma. each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. device pins can be safely driven to 5v signal levels to support mixed-voltage systems. eight glbs, 32 or 16 i/o cells, two dedicated inputs and two or one orps are connected together to make a megablock (see figure 1). the outputs of the eight glbs are connected to a set of 32 or 16 universal i/o cells by the two or one orps. each isplsi 2128ve device contains four megablocks. the grp has as its inputs, the outputs from all of the glbs and all of the inputs from the bi-directional i/o cells. all of these signals are made available to the inputs of the glbs. delays through the grp have been equalized to minimize timing skew. clocks in the isplsi 2128ve device are selected using the dedicated clock pins. three dedicated clock pins (y0, y1, y2) or an asynchronous clock can be selected on a glb basis. the asynchronous or product term clock can be generated in any glb for its own clock. programmable open-drain outputs in addition to the standard output configuration, the outputs of the isplsi 2128ve are individually program- mable, either as a standard totem-pole output or an open-drain output. the totem-pole output drives the specified voh and vol levels, whereas the open-drain output drives only the specified vol. the voh level on the open-drain output depends on the external loading and pull-up. this output configuration is controlled by a pro- grammable fuse. the default configuration when the device is in bulk erased state is totem-pole configuration. the open-drain/totem-pole option is selectable through the lattice software tools. global routing pool (grp) 0139b/2128ve megablock reset input bus d3 d2 d1 d0 d7 d6 d5 d4 output routing pool (orp) output routing pool (orp) i/o 127 i/o 126 i/o 125 i/o 124 i/o 123 i/o 122 i/o 121 i/o 120 i/o 119 i/o 118 i/o 117 i/o 116 i/o 115 i/o 114 i/o 113 i/o 112 i/o 111 i/o 110 i/o 109 i/o 108 i/o 107 i/o 106 i/o 105 i/o 104 i/o 103 i/o 102 i/o 101 i/o 100 i/o 99 i/o 98 i/o 97 i/o 96 in 7 c7 c6 c5 c4 c3 c2 c1 c0 output routing pool (orp) output routing pool (orp) input bus in 5 in 4 i/o 91 i/o 90 i/o 89 i/o 88 i/o 87 i/o 86 i/o 85 i/o 84 i/o 83 i/o 82 i/o 81 i/o 80 i/o 79 i/o 78 i/o 77 i/o 76 i/o 75 i/o 74 i/o 73 i/o 72 i/o 71 i/o 70 i/o 69 i/o 68 i/o 67 i/o 66 i/o 65 i/o 64 i/o 95 i/o 94 i/o 93 i/o 92 output routing pool (orp) output routing pool (orp) input bus clk 0 i/o 32 i/o 33 i/o 34 i/o 35 i/o 36 i/o 37 i/o 38 i/o 39 i/o 40 i/o 41 i/o 42 i/o 43 i/o 44 i/o 45 i/o 46 i/o 47 i/o 48 i/o 49 i/o 50 i/o 51 i/o 52 i/o 53 i/o 54 i/o 55 i/o 56 i/o 57 i/o 58 i/o 59 i/o 60 i/o 61 i/o 62 i/o 63 y0 y1 y2 tdo/in 2 tck/in 3 b4 b5 b6 b7 b0 b1 b2 b3 output routing pool (orp) output routing pool (orp) a0 a1 a2 a3 a4 a5 a6 a7 bscan i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 16 i/o 17 i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 i/o 0 i/o 1 i/o 2 i/o 3 goe 0 goe 1 clk 1 clk 2 input bus tdi/in 0 tms/in 1 in 6 generic logic blocks (glbs) global routing pool (grp) 0139b/2128ve.64io megablock reset input bus d3 d2 d1 d0 d7 d6 d5 d4 output routing pool (orp) i/o 63 i/o 62 i/o 61 i/o 60 i/o 59 i/o 58 i/o 57 i/o 56 i/o 55 i/o 54 i/o 53 i/o 52 i/o 51 i/o 50 i/o 49 i/o 48 in 7* c7 c6 c5 c4 c3 c2 c1 c0 output routing pool (orp) input bus in 5* in 4* i/o 43 i/o 42 i/o 41 i/o 40 i/o 39 i/o 38 i/o 37 i/o 36 i/o 35 i/o 34 i/o 33 i/o 32 i/o 47 i/o 46 i/o 45 i/o 44 output routing pool (orp) input bus clk 0 y0 y1 y2 tdo/in 2 tck/in 3 b4 b5 b6 b7 b0 b1 b2 b3 output routing pool (orp) a0 a1 a2 a3 a4 a5 a6 a7 bscan i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 16 i/o 17 i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 i/o 0 i/o 1 i/o 2 i/o 3 goe 0 goe 1 clk 1 clk 2 input bus tdi/in 0 tms/in 1 *not available on 84-plcc device in 6* generic logic blocks (glbs)
specifications isplsi 2128ve 3 absolute maximum ratings 1 supply voltage v cc .................................. -0.5 to +5.4v input voltage applied ............................... -0.5 to +5.6v off-state output voltage applied ............ -0.5 to +5.6v storage temperature ................................ -65 to 150 c case temp. with power applied .............. -55 to 125 c max. junction temp. (t j ) with power applied ... 150 c 1. stresses above those listed under the ?absolute maximum ratings? may cause permanent damage to the device. functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specifica tion is not implied (while programming, follow the programming specifications). dc recommended operating condition erase reprogram specifications capacitance (t a =25 c, f=1.0 mhz) c symbol table 2-0006/2128ve c parameter i/o capacitance 6 units typical test conditions 1 2 8 dedicated input capacitance pf pf v = 3.3v, v = 0.0v v = 3.3v, v = 0.0v cc cc i/o in c clock and global output enable capacitance 10 3 pf v = 3.3v, v = 0.0v cc y table 2-0008/2128ve parameter minimum maximum units erase/reprogram cycles 10,000 ? cycles t a = 0 c to + 70 c t a = -40 c to + 85 c symbol table 2-0005/2128ve v cc v ih v il parameter supply voltage input high voltage input low voltage min. max. units 3.0 3.0 2.0 v ? 0.5 3.6 3.6 5.25 0.8 v v v v ss commercial industrial
specifications isplsi 2128ve 4 switching test conditions figure 2. test load input pulse levels table 2 - 0003/2128ve input rise and fall time input timing reference levels output timing reference levels output load gnd to 3.0v 1.5ns 10% to 90% 1.5v 1.5v see figure 2 3-state levels are measured 0.5v from steady-state active level. dc electrical characteristics over recommended operating conditions output load conditions (see figure 2) test condition r1 r2 cl a 316 ? 348 ? 35pf b 348 ? 35pf 316 ? 348 ? 35pf active high active low c 316 ? 348 ? 5pf 348 ? 5pf active low to z at v +0.5v ol active high to z at v -0.5v oh table 2-0004/2128ve v ol symbol 1. one output at a time for a maximum duration of one second. v = 0.5v was selected to avoid test problems by tester ground degradation. characterized but not 100% tested. 2. measured using eight 16-bit counters. 3. typical values are at v = 3.3v and t = 25 c. 4. maximum i varies widely with specific device configuration and operating frequency. refer to the power consumption section of this data sheet and thermal management section of the lattice semiconductor data book or cd-rom to estimate maximum i . table 2-0007/2128ve 1 v oh i ih i il i il-isp parameter i il-pu i os 2, 4 i cc output low voltage output high voltage input or i/o high leakage current input or i/o low leakage current bscan input low leakage current i/o active pull-up current output short circuit current operating power supply current i = 8 ma i = -4 ma 0v v v (max.) 0v v v 0v v v v = 3.3v, v = 0.5v v = 0.0v, v = 3.0v f = 1 mhz ol oh in il in il in il cc out clock il ih condition min. typ. max. units 3 ? 2.4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 195 0.4 ? 10 10 -10 -150 -150 -100 ? v v a a a a a ma ma cc a out cc cc (v - 0.2)v v v v v 5.25v cc cc in in cc + 3.3v r 1 r 2 c l * device output test point * c l includes test fixture and probe capacitance. 0213a/2128ve
specifications isplsi 2128ve 5 use 2128ve-250 for new designs external timing parameters over recommended operating conditions t pd1 units test cond. 1. unless noted otherwise, all parameters use a grp load of four, 20 ptxor path, orp and y0 clock. 2. standard 16-bit counter using grp feedback. 3. reference switching test conditions section. table 2-0030a/2128ve v.1.0 1 3 2 1 tsu2 + tco1 ( ) description # parameter a1 data propagation delay, 4pt bypass, orp bypass ns t pd2 a2 data propagation delay ns f max a3 clock frequency with internal feedback mhz f max (ext.) ? 4 clock frequency with external feedback mhz f max (tog.) ? 5 clock frequency, max. toggle mhz t su1 ? 6 glb reg. setup time before clock, 4 pt bypass ns t co1 a7 glb reg. clock to output delay, orp bypass ns t h1 ? 8 glb reg. hold time after clock, 4 pt bypass ns t su2 ? 9 glb reg. setup time before clock ns t co2 a1 0 glb reg. clock to output delay ns t h2 ? 11 glb reg. hold time after clock ns t r1 a1 2 ext. reset pin to output delay, orp bypass ns t rw1 ? 13 ext. reset pulse duration ns t ptoeen b1 4 input to output enable ns t ptoedis c1 5 input to output disable ns t goeen b1 6 global oe output enable ns t goedis c1 7 global oe output disable ns t wh ? 18 external synchronous clock pulse duration, high ns t wl ? 19 external synchronous clock pulse duration, low ns -180 min. max. ? 5.0 ? 180 ? ? ? ? ? 0.0 4.5 ? 0.0 ? 4.0 ? ? ? ? 2.5 ? 2.5 ? 125 200 3.5 3.5 ? ? 4.5 ? 7.0 ? 10.0 10.0 5.0 5.0 7.5 -250 min. max. ? 4.0 ? 250 ? ? ? ? ? 0.0 3.3 ? 0.0 ? 3.5 ? ? ? ? 1.8 ? 1.8 ? 158 277 2.5 3.0 ? ? 3.7 ? 6.0 ? 6.0 6.0 4.0 4.0 6.0
specifications isplsi 2128ve 6 external timing parameters over recommended operating conditions t pd1 units test cond. 1. unless noted otherwise, all parameters use a grp load of four, 20 ptxor path, orp and y0 clock. 2. standard 16-bit counter using grp feedback. 3. reference switching test conditions section. table 2-0030b/2128ve v.1.0 1 3 2 1 tsu2 + tco1 ( ) description # parameter a1 data propagation delay, 4pt bypass, orp bypass ns t pd2 a2 data propagation delay ns f max a3 clock frequency with internal feedback mhz f max (ext.) ?4 clock frequency with external feedback mhz f max (tog.) ?5 clock frequency, max. toggle mhz t su1 ?6 glb reg. setup time before clock, 4 pt bypass ns t co1 a7 glb reg. clock to output delay, orp bypass ns t h1 ?8 glb reg. hold time after clock, 4 pt bypass ns t su2 ?9 glb reg. setup time before clock ns t co2 a1 0 glb reg. clock to output delay ns t h2 ?1 1 glb reg. hold time after clock ns t r1 a1 2 ext. reset pin to output delay, orp bypass ns t rw1 ?1 3 ext. reset pulse duration ns t ptoeen b1 4 input to output enable ns t ptoedis c1 5 input to output disable ns t goeen b1 6 global oe output enable ns t goedis c1 7 global oe output disable ns t wh ?1 8 external synchronous clock pulse duration, high ns t wl ?1 9 external synchronous clock pulse duration, low ns -135 min. -100 min. max. max. ? 7.5 ? 10.0 ?? 135 ? 100 ? ?? ?? ?? ?? 0.0 ? 6.0 ? ?? 0.0 ? ?? 5.0 ? ?? ?? ?? ?? 3.5 ? ? 3.5 ? ? 100 143 5.0 4.0 ? ? 5.0 ? 9.0 ? 12.0 12.0 7.0 7.0 10.0 77 100 6.5 0.0 8.0 0.0 6.5 5.0 5.0 13.0 5.0 6.0 12.5 15.0 15.0 9.0 9.0
specifications isplsi 2128ve 7 use 2128ve-250 for new designs internal timing parameters 1 over recommended operating conditions t io 1. internal timing parameters are not tested and are for reference only. 2. refer to timing model in this data sheet for further details. 3. the xor adjacent path can only be used by hard macros. table 2-0036a/2128ve v.1.0 inputs units description # 2 parameter 20 input buffer delay ns t din 21 dedicated input delay ns t grp 22 grp delay ns glb t 1ptxor 25 1 product term/xor path delay ns t 20ptxor 26 20 product term/xor path delay ns t xoradj 27 xor adjacent path delay ns t gbp 28 glb register bypass delay ns t gsu 29 glb register setup time before clock ns t gh 30 glb register hold time after clock ns t gco 31 glb register clock to output delay ns 3 t gro 32 glb register reset to output delay ns t ptre 33 glb product term reset to register delay ns t ptoe 34 glb product term output enable to i/o cell delay ns t ptck 35 glb product term clock delay ns orp t ob 38 output buffer delay ns t sl 39 output slew limited delay adder ns grp t 4ptbpc 23 4 product term bypass path delay (combinatorial) ns t 4ptbpr 24 4 product term bypass path delay (registered) ns t orp 36 orp delay ns t orpbp 37 orp bypass delay ns outputs t oen 40 i/o cell oe to output enabled ns t odis 41 i/o cell oe to output disabled ns t goe 42 global output enable ns t gy0 43 clock delay, y0 to global glb clock line (ref. clock) ns t gy1/2 44 clock delay, y1 or y2 to global glb clock line ns clocks t gr 45 global reset to glb -180 min. max. 0.5 1.1 0.6 3.4 3.4 3.4 0.0 ? ? 0.3 0.6 4.3 5.9 4.0 1.6 2.0 1.9 2.4 1.4 0.4 3.0 3.0 2.0 1.2 1.4 4.4 ? ? ? ? ? ? ? 1.2 2.3 ? ? ? ? 1.0 ? ? ? ? ? ? ? ? ? 1.2 1.4 ? -250 min. max. 0.5 0.7 0.2 2.8 2.8 2.8 0.0 ? ? 0.2 0.3 3.7 2.9 3.6 1.4 2.0 1.5 2.0 1.1 0.4 2.4 2.4 1.6 1.0 1.2 3.9 ? ? ? ? ? ? ? 0.8 1.7 ? ? ? ? 0.8 ? ? ? ? ? ? ? ? ? 1.0 1.2 ?ns global reset
specifications isplsi 2128ve 8 internal timing parameters 1 over recommended operating conditions t io 1. internal timing parameters are not tested and are for reference only. 2. refer to timing model in this data sheet for further details. 3. the xor adjacent path can only be used by hard macros. table 2-0036b/2128ve v.1.0 inputs units description # 2 parameter 20 input buffer delay ns t din 21 dedicated input delay ns t grp 22 grp delay ns glb t 1ptxor 25 1 product term/xor path delay ns t 20ptxor 26 20 product term/xor path delay ns t xoradj 27 xor adjacent path delay ns t gbp 28 glb register bypass delay ns t gsu 29 glb register setup time before clock ns t gh 30 glb register hold time after clock ns t gco 31 glb register clock to output delay ns 3 t gro 32 glb register reset to output delay ns t ptre 33 glb product term reset to register delay ns t ptoe 34 glb product term output enable to i/o cell delay ns t ptck 35 glb product term clock delay ns orp t ob 38 output buffer delay ns t sl 39 output slew limited delay adder ns grp t 4ptbpc 23 4 product term bypass path delay (combinatorial) ns t 4ptbpr 24 4 product term bypass path delay (registered) ns t orp 36 orp delay ns t orpbp 37 orp bypass delay ns outputs t oen 40 i/o cell oe to output enabled ns t odis 41 i/o cell oe to output disabled ns t goe 42 global output enable ns t gy0 43 clock delay, y0 to global glb clock line (ref. clock) ns t gy1/2 44 clock delay, y1 or y2 to global glb clock line ns clocks t gr 45 global reset to glb ns global reset -135 min. -100 min. max. max. ? ? ? ? ? ? ? 1.7 4.8 ? ? ? ? 2.6 ? ? ? ? ? ? ? ? ? 2.4 2.6 ? 0.7 2.5 1.8 6.2 6.2 6.2 1.0 ? ? 0.3 3.1 7.1 9.1 5.6 1.6 2.0 5.2 4.7 1.7 0.7 3.4 3.4 5.6 2.4 2.6 7.1 0.5 1.7 1.2 4.7 4.7 4.7 0.5 ? ? 0.3 1.1 6.1 6.9 4.6 1.6 2.0 3.7 3.7 1.5 0.5 3.4 3.4 3.6 1.6 1.8 5.8 ? ? ? ? ? ? ? 1.2 3.8 ? ? ? ? 1.6 ? ? ? ? ? ? ? ? ? 1.6 1.8 ?
specifications isplsi 2128ve 9 isplsi 2128ve timing model glb reg delay i/o pin (output) orp delay feedback reg 4 pt bypass 20 pt xor delays control pts i/o pin (input) y0,1,2 grp glb reg bypass orp bypass dq rst re oe ck i/o delay i/o cell orp glb grp i/o cell #24 #25, 26, 27 #33, 34, 35 #43, 44 #36 reset ded. in #21 #20 #28 #29, 30, 31, 32 #38, 39 goe 0 #42 #40, 41 0491/2032 #22 comb 4 pt bypass #23 #37 #45 derivations of t su, t h and t co from the product term clock = = = = t su 2.8ns logic + reg su - clock (min) ( t io + t grp + t 20ptxor) + ( t gsu) - ( t io + t grp + t ptck(min)) (#20 + #22 + #26) + (#29) - (#20 + #22 + #35) (0.5 + 0.2 + 2.8) + (0.8) - (0.5 + 0.2 + 0.8) = = = = t h clock (max) + reg h - logic ( t io + t grp + t ptck(max)) + ( t gh) - ( t io + t grp + t 20ptxor) (#20 + #22 + #35) + (#30) - (#20 + #22 + #26) (0.5 + 0.2 + 3.6) + (1.7) - (0.5 + 0.2 + 2.8) = = = = t co note: calculations are based upon timing specifications for the isplsi 2128ve-250l. clock (max) + reg co + output ( t io + t grp + t ptck(max)) + ( t gco) + ( t orp + t ob) (#20 + #22 + #35) + (#31) + (#36 + #38) (0.5 + 0.2 + 3.6) + (0.2) + (1.1 + 1.4) table 2-0042/2128ve v.1.0 2.5ns 7.0ns
specifications isplsi 2128ve 10 power consumption power consumption in the isplsi 2128ve device de- pends on two primary factors: the speed at which the device is operating and the number of product terms used. figure 3 shows the relationship between power and operating speed. figure 3. typical device power consumption vs fmax 0127/2128ve i cc can be estimated for the isplsi 2128ve using the following equation: i cc = 8 + (# of pts * 0.669) + (# of nets * max freq * 0.0026) where: # of pts = number of product terms used in design # of nets = number of signals used in device max freq = highest clock frequency to the device (in mhz) the i cc estimate is based on typical conditions (v cc = 3.3v, room temperature) and an assumption of two glb loads on average exists. these values are for estimates only. since the value of i cc is sensitive to operating conditions and the program in the device, the actual i cc should be verified. 150 100 250 050 100 150 200 250 f max (mhz) i cc (ma) notes: configuration of eight 16-bit counters typical current at 3.3v, 25? c 300 350 200 isplsi 2128ve
specifications isplsi 2128ve 11 signal descriptions reset active low (0) reset pin resets all the registers in the device. goe 0, goe1 global output enable input pins. y0, y1, y2 dedicated clock input ? these clock inputs are connected to one of the clock inputs of all the glbs in the device. bscan input ? dedicated in-system programming boundary scan enable input pin. this pin is brought low to enable the programming mode. the tms, tdi, tdo and tck controls become active. tdi/in 0 input ? this pin performs two functions. when bscan is logic low, it functions as a serial data input pin to load programming data into the device. when bscan is high, it functions as a dedicated input pin. tck/in 3 input ? this pin performs two functions. when bscan is logic low, it functions as a clock pin for the boundary scan state machine. when bscan is high, it functions as a dedicated input pin. tms/in 1 input ? this pin performs two functions. when bscan is logic low, it functions as a mode control pin for the boundary scan state machine. when bscan is high, it functions as a dedicated input pin. tdo/in 2 output/input ? this pin performs two functions. when bscan is logic low, it functions as an output pin to read serial shift register data. when bscan is high, it functions as a dedicated input pin. in 4 - in 7 dedicated input pins to the device. gnd ground (gnd) vcc vcc nc 1 no connect i/o input/output pins ? these are the general purpose i/o pins used by the logic array. signal name description 1. nc pins are not to be connected to any active signals, vcc or gnd.
specifications isplsi 2128ve 12 signal locations l a n g i s l l a b - 8 0 2 a g b p fa g b p f a g b p f a g b p fa g b p f n i p - 6 7 1 p f q tp f q t p f q t p f q tp f q t n i p - 0 6 1 p f q pp f q p p f q p p f q pp f q p l l a b - 0 0 1 a g b a ca g b a c a g b a c a g b a ca g b a c n i p - 0 0 1 p f q tp f q t p f q t p f q tp f q t t e s e r 3 h1 29 12 d1 1 1 e o g , 0 e o g1 h , 6 1 j3 2 , 0 1 11 2 , 0 0 11 e , 9 f3 1 , 2 6 2 y , 1 y , 0 y4 1 j , 4 1 h , 2 h8 0 1 , 3 1 1 , 0 28 9 , 3 0 1 , 8 18 f , 6 f , 3 e0 6 , 5 6 , 0 1 n a c s b 1 j5 23 25 e5 1 0 n i / i d t3 j6 24 22 f6 1 3 n i / k c t5 1 j7 0 17 90 1 g9 5 1 n i / s m t8 p6 60 65 j7 3 2 n i / o d t9 c4 5 10 4 16 b7 8 7 n i - 4 n i, 8 t , 9 a , 6 1 h 4 h , 7 6 , 5 5 1 , 4 1 1 9 1 , 1 6 , 1 4 1 , 4 0 1 7 1 1 d , 5 k , 6 a , 9 e9 , 8 3 , 8 8 , 6 6 d n g, 7 g , 3 1 d , 4 d , 0 1 g , 9 g , 8 g , 9 h , 8 h , 7 h , 8 j , 7 j , 0 1 h , 7 k , 0 1 j , 9 j , 0 1 k , 9 k , 8 k 3 1 n , 4 n , 7 8 , 8 6 , 6 4 , 4 2 , 3 5 1 , 4 3 1 , 9 0 1 5 7 1 , 9 7 , 2 6 , 2 4 , 2 2 , 9 3 1 , 2 2 1 , 9 9 9 5 1 6 k , 9 g , 1 f , 7 b6 8 , 1 6 , 9 3 , 4 1 c c v, 2 1 d , 6 d , 5 d , 4 f , 3 1 e , 4 e , 3 1 l , 4 l , 3 1 f , 5 n , 3 1 m , 4 m 2 1 n , 1 1 n , 5 6 , 3 4 , 2 2 , 2 , 1 3 1 , 1 1 1 , 0 9 6 5 1 , 9 5 , 9 3 , 0 2 , 2 , 9 1 1 , 1 0 1 , 2 8 2 4 1 4 j , 0 1 f , 2 e , 5 a9 8 , 3 6 , 6 3 , 2 1 c n 1 , 5 1 a , 3 a , 2 a , 2 b , 1 b , 6 1 a , 5 1 b , 4 1 b , 3 b , 3 c , 2 c , 6 1 b , 4 1 d , 5 1 c , 4 1 c , 3 p , 2 p , 1 p , 5 1 p , 4 1 p , 3 1 p , 3 r , 2 r , 1 r , 6 1 r , 5 1 r , 4 1 r , 5 1 t , 2 t , 1 t 6 1 t , 6 3 , 7 2 , 8 1 , 9 , 8 7 , 9 6 , 4 6 , 5 5 , 2 1 1 , 6 0 1 , 7 9 , 3 4 1 , 4 2 1 , 5 1 1 6 6 1 , 7 5 1 , 2 5 1 2 0 1, 4 c , 3 c , 8 a , 7 e , 8 d , 6 d , 3 g , 4 f , 0 1 e 3 k , 8 h , 7 h , 5 g , 1 3 , 5 2 , 1 2 , 4 , 4 6 , 4 5 , 0 5 , 4 4 , 4 9 , 1 8 , 5 7 , 1 7 0 0 1 . d n g r o c c v , s l a n g i s e v i t c a y n a o t d e t c e n n o c e b o t t o n e r a s n i p c n . 1
specifications isplsi 2128ve 13 i/o locations i/o 0 j2 28 25 g1 17 i/o 1 j4 29 26 f3 18 i/o 2 k1 30 27 e4 19 i/o 3 k3 31 28 h1 20 i/o 4 k2 32 29 g2 22 i/o 5 k4 33 30 j1 23 i/o 6 l1 34 31 h2 24 i/o 7 l2 35 32 k1 26 i/o 8 l3 37 33 j2 27 i/o 9 m1 38 34 k2 28 i/o 10 m2 39 35 h3 29 i/o 11 m3 40 36 j3 30 i/o 12 n1 41 37 g4 32 i/o 13 n2 42 38 h4 33 i/o 14 n3 44 40 k4 34 i/o 15 p4 45 41 h5 35 i/o 16 t3 47 43 f5 40 i/o 17 r4 48 44 j6 41 i/o 18 t4 49 45 k7 42 i/o 19 p5 50 46 h6 43 i/o 20 r5 51 47 k8 45 i/o 21 n6 52 48 g6 46 i/o 22 t5 53 49 j7 47 i/o 23 r6 54 50 k9 48 i/o 24 p6 56 51 j8 49 i/o 25 t6 57 52 k10 51 i/o 26 n7 58 53 j9 52 i/o 27 r7 59 54 j10 53 i/o 28 p7 60 55 h9 55 i/o 29 t7 61 56 h10 56 i/o 30 n8 62 57 g7 57 i/o 31 r8 63 58 g8 58 i/o 32 t9 70 63 d10 67 i/o 33 p9 71 64 e8 68 i/o 34 r9 72 65 f7 69 i/o 35 n9 73 66 c10 70 i/o 36 t10 74 67 d9 72 i/o 37 p10 75 68 b10 73 i/o 38 r10 76 69 c9 74 i/o 39 n10 77 70 a10 76 i/o 40 t11 79 71 b9 77 i/o 41 p11 80 72 a9 78 i/o 42 r11 81 73 c8 79 i/o 43 t12 82 74 b8 80 i/o 44 p12 83 75 d7 82 i/o 45 r12 84 76 c7 83 i/o 46 t13 85 77 a7 84 i/o 47 r13 86 78 c6 85 i/o 48 t14 88 80 e6 90 i/o 49 n14 89 81 b5 91 i/o 50 p16 91 83 a4 92 i/o 51 n15 92 84 c5 93 i/o 52 n16 93 85 a3 95 i/o 53 m14 94 86 d5 96 i/o 54 m15 95 87 b4 97 i/o 55 m16 96 88 a2 98 i/o 56 l15 98 89 b3 99 i/o 57 l14 99 90 a1 1 i/o 58 l16 100 91 b2 2 i/o 59 k13 101 92 b1 3 i/o 60 k15 102 93 c2 5 i/o 61 k14 103 94 c1 6 i/o 62 k16 104 95 d4 7 i/o 63 j13 105 96 d3 8 208 176 160 100 100 signal fpbga tqfp pqfp cabga tqfp i/o 64 h15 116 105 ? ? i/o 65 h13 117 106 ? ? i/o 66 g16 118 107 ? ? i/o 67 g14 119 108 ? ? i/o 68 g15 120 109 ? ? i/o 69 g13 121 110 ? ? i/o 70 f16 122 111 ? ? i/o 71 f14 123 112 ? ? i/o 72 f15 125 113 ? ? i/o 73 e16 126 114 ? ? i/o 74 e14 127 115 ? ? i/o 75 e15 128 116 ? ? i/o 76 d16 129 117 ? ? i/o 77 c16 130 118 ? ? i/o 78 d15 132 120 ? ? i/o 79 a14 133 121 ? ? i/o 80 c13 135 123 ? ? i/o 81 b13 136 124 ? ? i/o 82 a13 137 125 ? ? i/o 83 c12 138 126 ? ? i/o 84 b12 139 127 ? ? i/o 85 d11 140 128 ? ? i/o 86 a12 141 129 ? ? i/o 87 c11 142 130 ? ? i/o 88 b11 144 131 ? ? i/o 89 d10 145 132 ? ? i/o 90 a11 146 133 ? ? i/o 91 b10 147 134 ? ? i/o 92 c10 148 135 ? ? i/o 93 d9 149 136 ? ? i/o 94 a10 150 137 ? ? i/o 95 b9 151 138 ? ? i/o 96 a8 158 143 ? ? i/o 97 c8 159 144 ? ? i/o 98 b8 160 145 ? ? i/o 99 d8 161 146 ? ? i/o 100 a7 162 147 ? ? i/o 101 c7 163 148 ? ? i/o 102 b7 164 149 ? ? i/o 103 d7 165 150 ? ? i/o 104 a6 167 151 ? ? i/o 105 c6 168 152 ? ? i/o 106 b6 169 153 ? ? i/o 107 a5 170 154 ? ? i/o 108 c5 171 155 ? ? i/o 109 b5 172 156 ? ? i/o 110 a4 173 157 ? ? i/o 111 b4 174 158 ? ? i/o 112 c4 176 160 ? ? i/o 113 a1 1 1 ? ? i/o 114 c1 3 3 ? ? i/o 115 d3 4 4 ? ? i/o 116 d2 5 5 ? ? i/o 117 d1 6 6 ? ? i/o 118 e3 7 7 ? ? i/o 119 e2 8 8 ? ? i/o 120 e1 10 9 ? ? i/o 121 f3 11 10 ? ? i/o 122 f2 12 11 ? ? i/o 123 f1 13 12 ? ? i/o 124 g4 14 13 ? ? i/o 125 g2 15 14 ? ? i/o 126 g3 16 15 ? ? i/o 127 g1 17 16 ? ? 208 176 160 100 100 signal fpbga tqfp pqfp cabga tqfp
specifications isplsi 2128ve 14 signal configuration isplsi 2128ve 208-ball fpbga signal diagram nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 gnd vcc vcc gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd vcc vcc gnd vcc vcc vcc gnd vcc vcc vcc in 5 in 4 y2 vcc goe 0 tck/ in 3 y1 i/o 79 i/o 82 i/o 86 i/o 90 i/o 94 i/o 96 i/o 100 i/o 104 i/o 107 i/o 110 i/o 111 i/o 109 i/o 106 i/o 102 i/o 98 i/o 95 i/o 91 i/o 88 i/o 84 i/o 81 i/o 77 i/o 76 i/o 73 i/o 75 i/o 74 vcc i/o 70 i/o 72 i/o 71 i/o 66 i/o 68 i/o 64 i/o 65 i/o 63 i/o 62 i/o 58 i/o 56 i/o 57 vcc i/o 55 i/o 54 i/o 53 i/o 52 i/o 51 i/o 49 i/o 48 i/o 46 i/o 43 i/o 40 i/o 36 i/o 32 i/o 29 i/o 25 i/o 22 i/o 18 i/o 47 i/o 45 i/o 42 i/o 38 i/o 34 i/o 31 i/o 27 i/o 23 i/o 20 i/o 17 i/o 16 i/o 60 i/o 61 i/o 59 i/o 67 i/o 69 i/o 78 i/o 80 i/o 83 i/o 87 i/o 97 tdo/ in 2 i/o 101 i/o 103 i/o 99 i/o 93 i/o 89 i/o 85 i/o 105 i/o 108 i/o 112 i/o 114 i/o 117 i/o 116 i/o 115 i/o 120 i/o 119 i/o 118 vcc in 7 y0 in 6 i/o 44 i/o 50 i/o 41 i/o 37 i/o 33 tms/ in 1 i/o 28 i/o 24 i/o 39 i/o 35 i/o 30 i/o 26 i/o 21 i/o 19 i/o 15 bscan reset i/o 123 i/o 122 i/o 121 i/o 127 goe 1 i/o 125 i/o 126 i/o 124 i/o 2 i/o 4 i/o 3 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 5 i/o 1 tdi/ in 0 i/o 0 i/o 92 i/o 113 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a b c d e f g h j k l m n p r t a b c d e f g h j k l m n p r t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1. ncs are not to be connected to any active signals, vcc or gnd. note: ball a1 indicator dot on top side of package. 208 bga/2128ve isplsi 2128ve bottom view
specifications isplsi 2128ve 15 pin configuration isplsi 2128ve 176-pin tqfp pinout diagram isplsi 2128ve top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 i/o 113 vcc i/o 114 i/o 115 i/o 116 i/o 117 i/o 118 i/o 119 1 nc i/o 120 i/o 121 i/o 122 i/o 123 i/o 124 i/o 125 i/o 126 i/o 127 1 nc in 7 y0 reset vcc goe 1 gnd bscan tdi/in 0 1 nc i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 1 nc i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 vcc i/o 14 i/o 112 gnd i/o 111 i/o 110 i/o 109 i/o 108 i/o 107 i/o 106 i/o 105 i/o 104 nc 1 i/o 103 i/o 102 i/o 101 i/o 100 i/o 99 i/o 98 i/o 97 i/o 96 nc 1 vcc in 5 tdo/in 2 gnd nc 1 i/o 95 i/o 94 i/o 93 i/o 92 i/o 91 i/o 90 i/o 89 i/o 88 nc 1 i/o 87 i/o 86 i/o 85 i/o 84 i/o 83 i/o 82 i/o 81 i/o 80 gnd i/o 79 i/o 78 vcc i/o 77 i/o 76 i/o 75 i/o 74 i/o 73 i/o 72 nc 1 i/o 71 i/o 70 i/o 69 i/o 68 i/o 67 i/o 66 i/o 65 i/o 64 nc 1 in 4 y1 nc 1 vcc goe 0 gnd y2 tck/in 3 nc 1 i/o 63 i/o 62 i/o 61 i/o 60 i/o 59 i/o 58 i/o 57 i/o 56 nc 1 i/o 55 i/o 54 i/o 53 i/o 52 i/o 51 i/o 50 vcc i/o 49 i/o 15 gnd i/o 16 i/o 17 i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 nc 1 i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 nc 1 vcc tms/in 1 in 6 gnd nc 1 i/o 32 i/o 33 i/o 34 i/o 35 i/o 36 i/o 37 i/o 38 i/o 39 nc 1 i/o 40 i/o 41 i/o 42 i/o 43 i/o 44 i/o 45 i/o 46 i/o 47 gnd i/o 48 176-tqfp/2128ve 1. nc pins are not to be connected to any active signals, vcc or gnd.
specifications isplsi 2128ve 16 pin configuration isplsi 2128ve 160-pin pqfp pinout diagram isplsi 2128ve top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 i/o 113 vcc i/o 114 i/o 115 i/o 116 i/o 117 i/o 118 i/o 119 i/o 120 i/o 121 i/o 122 i/o 123 i/o 124 i/o 125 i/o 126 i/o 127 in 7 y0 reset vcc goe 1 gnd bscan tdi/in 0 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 vcc i/o 14 i/o 112 gnd i/o 111 i/o 110 i/o 109 i/o 108 i/o 107 i/o 106 i/o 105 i/o 104 i/o 103 i/o 102 i/o 101 i/o 100 i/o 99 i/o 98 i/o 97 i/o 96 vcc in 5 tdo/in 2 gnd i/o 95 i/o 94 i/o 93 i/o 92 i/o 91 i/o 90 i/o 89 i/o 88 i/o 87 i/o 86 i/o 85 i/o 84 i/o 83 i/o 82 i/o 81 i/o 80 gnd i/o 79 i/o 78 vcc i/o 77 i/o 76 i/o 75 i/o 74 i/o 73 i/o 72 i/o 71 i/o 70 i/o 69 i/o 68 i/o 67 i/o 66 i/o 65 i/o 64 in 4 y1 nc 1 vcc goe 0 gnd y2 tck/in 3 i/o 63 i/o 62 i/o 61 i/o 60 i/o 59 i/o 58 i/o 57 i/o 56 i/o 55 i/o 54 i/o 53 i/o 52 i/o 51 i/o 50 vcc i/o 49 i/o 15 gnd i/o 16 i/o 17 i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 vcc tms/in 1 in 6 gnd i/o 32 i/o 34 i/o 34 i/o 35 i/o 36 i/o 37 i/o 38 i/o 39 i/o 40 i/o 41 i/o 42 i/o 43 i/o 44 i/o 45 i/o 46 i/o 47 gnd i/o 48 1. nc pins are not to be connected to any active signal, vcc or gnd. 160-pqfp/2128ve
specifications isplsi 2128ve 17 signal configuration isplsi 2128ve 100-ball cabga signal diagram 10 987654321 a b c d e f g h j k a b c d e f g h j k 10 987654321 i/o 39 i/o 41 i/o 46 i/o 50 i/o 52 i/o 55 i/o 57 nc 1 in 5 vcc i/o 35 i/o 38 i/o 42 i/o 45 i/o 47 i/o 51 i/o 60 i/o 61 nc 1 nc 1 tck/ in 3 i/o 31 i/o 30 i/o 21 i/o 12 i/o 4 i/o 0 nc 1 gnd nc 1 i/o 29 i/o 28 i/o 19 i/o 13 i/o 10 i/o 15 i/o 6 i/o 3 nc 1 nc 1 i/o 27 i/o 26 i/o 24 i/o 22 i/o 17 i/o 11 tms/ in 1 i/o 8 i/o 5 vcc i/o 25 1 ncs are not to be connected to any active signals, vcc or gnd. note: ball a1 indicator dot on top side of package. i/o 23 i/o 20 i/o 18 i/o 14 i/o 9 i/o 7 gnd nc 1 in 6 goe 0 i/o 34 i/o 16 i/o 1 tdi/ in 0 nc 1 gnd 100-bga/2128ve vcc y2 y1 i/o 32 i/o 36 i/o 44 i/o 53 i/o 62 i/o 63 nc 1 in 7 nc 1 reset i/o 33 i/o 48 i/o 2 goe 1 nc 1 vcc y0 in 4 nc 1 bscan i/o 37 i/o 40 i/o 43 i/o 54 i/o 49 tdo/ in 2 i/o 56 i/o 58 i/o 59 gnd isplsi 2128ve bottom view
specifications isplsi 2128ve 18 pin configuration isplsi 2128ve 100-pin tqfp pinout diagram i/o 57 i/o 58 i/o 59 1 nc i/o 60 i/o 61 i/o 62 i/o 63 in 7 y0 reset vcc goe 1 gnd bscan tdi/in 0 i/o 0 i/o 1 i/o 2 i/o 3 1 nc i/o 4 i/o 5 i/o 6 1 nc nc 1 i/o 38 i/o 37 i/o 36 nc 1 i/o 35 i/o 34 i/o 33 i/o 32 in 4 y1 nc 1 vcc goe 0 gnd y2 tck/in 3 i/o 31 i/o 30 i/o 29 i/o 28 nc 1 i/o 27 i/o 26 i/o 25 nc 1 i/o 56 i/o 55 i/o 54 i/o 53 i/o 52 nc 1 i/o 51 i/o 50 i/o 49 i/o 48 vcc in 5 tdo/in 2 gnd i/o 47 i/o 46 i/o 45 i/o 44 nc 1 i/o 43 i/o 42 i/o 41 i/o 40 i/o 39 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 1 nc i/o 12 i/o 13 i/o 14 i/o 15 vcc tms/in 1 in 6 gnd i/o 16 i/o 17 i/o 18 i/o 19 1 nc i/o 20 i/o 21 i/o 22 i/o 23 i/o 24 1 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 58 isplsi 2128ve top view 1. nc pins are not to be connected to any active signals, vcc or gnd. 100-tqfp/2128ve
specifications isplsi 2128ve 19 part number description isplsi 2128ve ordering information device number isplsi 2128ve xxx x xxxx grade blank = commercial i = industrial x speed 250 = 250 mhz f max 180 = 180 mhz f max* 135 = 135 mhz f max 100 = 100 mhz f max *use isplsi 2128ve-250 for new designs package ? device family 0212/2128ve q160 = 160-pin pqfp t176 = 176-pin tqfp b208 = 208-ball fpbga t100 = 100-pin tqfp b100 = 100-ball cabga power l = low 180 180 176-pin tqfp 5.0 5.0 isplsi 2128ve-180lt176* 160-pin pqfp isplsi 2128ve-180lq160* table 2-0041a/2128ve 135 7.5 100-pin tqfp isplsi 2128ve-135lt100 family f max (mhz) ordering number package t pd (ns) isplsi 128 128 180 5.0 208-ball fpbga isplsi 2128ve-180lb208* 128 250 250 176-pin tqfp 4.0 4.0 isplsi 2128ve-250lt176 160-pin pqfp isplsi 2128ve-250lq160 128 128 250 4.0 208-ball fpbga isplsi 2128ve-250lb208 128 180 100-pin tqfp 5.0 isplsi 2128ve-180lt100* 64 180 5.0 100-ball cabga isplsi 2128ve-180lb100* 64 250 100-pin tqfp 4.0 isplsi 2128ve-250lt100 64 250 4.0 100-ball cabga isplsi 2128ve-250lb100 64 64 i/os 135 100-ball cabga 7.5 isplsi 2128ve-135lb100 64 135 7.5 176-pin tqfp isplsi 2128ve-135lt176 128 135 160-pin pqfp 7.5 isplsi 2128ve-135lq160 128 135 208-ball fpbga 7.5 isplsi 2128ve-135lb208 128 commercial 100 100-pin tqfp 10 isplsi 2128ve-100lt100 64 100 10 100-ball cabga isplsi 2128ve-100lb100 64 100 100 176-pin tqfp 10 10 isplsi 2128ve-100lt176 160-pin pqfp isplsi 2128ve-100lq160 128 128 100 10 208-ball fpbga isplsi 2128ve-100lb208 128 *use isplsi 2128ve-250 for new designs 135 100-pin tqfp 7.5 isplsi 2128ve-135lt100i table 2-0041b/2128ve family f max (mhz) ordering number package t pd (ns) isplsi 64 135 176-pin tqfp 7.5 isplsi 2128ve-135lt176i 128 i/os industrial

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