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  page 1 phone: 360.260.2468 l sales: 800.736.0194 l fax: 360.260.2469 email: sales@usdigital.com l website: www.usdigital.com 11100 ne 34th circle l vancouver, washington 98682 usa ls7166 encoder to microprocessor interface chip chips the ls7166 is an lsi monolithic cmos building block useful in motion control applications. the 24-bit multi-mode counter register and logic enables a microproces- sor to track the speed, direction, and position of an optical incremental shaft encoder. in addition to an 8-bit data bus, programmable realtime inputs and outputs are provided for hardware based control functions and status indication. note: us digital has already designed the ics on this data sheet into various products. please see the pc7166 , ad4-a and ad6 data sheets. features: ? x4 or x1 resolution multiplication. ? preloadable 24-bit up/down counter. ? choice of two 20-pin packages: soic surface mount or dip (600mil). ? x1 or x2 or x4 resolution multiplier. ? binary or bcd. ? divide-by-n. ? 24-bit comparator register. ? 4 control registers. ? readable status register. ? 8-bit tri-state i/o bus. ? dc to 10 mhz count frequency. ? latched counter outputs. ? input/output ttl & cmos compatible. ? 5 volt operation. ? 200 ua supply current. ? no external clock required. block diagram of counter & registers: ordering information: description: parameter min. max. units operating temperature 0 70 c storage temperature -65 150 c voltage at any input -.5 vcc+.5 volts supply voltage (vcc) 7 volts absolute maximum ratings: technical data, rev. 01.22.01, january 2001 all information subject to change without notice. dip package (300mil): LS7166-DIP surface mount package: ls7166-soic price: $11.65 / 1 $9.35 / 25 $7.45 / 100 $6.35 / 500 $5.40 / 1k
page 2 phone: 360.260.2468 l sales: 800.736.0194 l fax: 360.260.2469 email: sales@usdigital.com l website: www.usdigital.com 11100 ne 34th circle l vancouver, washington 98682 usa ls7166 encoder to microprocessor interface chip chips 4 useful bits. initializes the 24-bit counter and sets operating modes. select this register by making bit-6 low and bit-7 high. control functions may be combined. bit-0: low level selects binary count mode. high level selects bcd count mode. bit-1: this bit must be reset low for normal operation. bit-2: low level selects normal wrap-around count mode. high level selects divide-by-n mode (24-bit counter is reloaded from the preset register upon carry or borrow). bit-3: this bit must be reset low for normal operation. bits 4 & 5: the functions of hardware pins 16 & 17 are defined by these two bits. pin 16 can be defined as any of the following: bit-5 bit-4 pin 16 function 0 0 carry - low true 0 1 carry toggle flip flop (starts out low) 1 0 carry - high true 1 1 24-bit comparator/counter match - low true pin 17 is also defined the the same two bits as follows: bit-5 bit-4 pin 17 function 0 0 borrow - low true 0 1 borrow toggle flip flop (starts out low) 1 0 borrow - high true 1 1 24-bit comparator/counter match - high true output control register (write only): readtime hardware output pin description: carry or match (output) (pin 16): the function of this pin is defined by bits 4 and 5 of the output control register as follows: bit-5 bit-4 pin function 0 0 carry - low true 0 1 carry toggle flip flop (starts out low) 1 0 carry - high true 1 1 24-bit comparator / counter match - low true borrow or match (output) (pin 17): the function of this pin is also defined by bits 4 and 5 of the output control register as follows: bit-5 bit-4 pin function 0 0 borrow - low true 0 1 borrow toggle flip flop (starts out low) 1 0 borrow - high true 1 1 24-bit comparator/counter match - high true note that the functions of pins 16 and 17 are defined by the same 2 bits of the output control register. they are inseparably linked together. the toggle flip flops are triggered by the trailing edges of the associated carry, borrow, or compare match. thus there is a 1-clock delay between the input and output of each flip flop. unless otherwise specified, assume the longest prop delay from any input to any output is <110ns. bits 5, 6 and 7 are always high. bit-0: borrow toggle flip-flip. toggles every time the 24-bit counter underflows generating a borrow. bit-1: carry toggle flip-flip. toggles every time the 24-bit counter overflows generating a carry. trailing edge triggered. bit-2: compare toggle flip flop. toggles every time the 24-bit counter equals the 24-bit preset register. trailing edge triggered. bit-3: sign bit. set low when a borrow occurs. set high when a carry occurs. level triggered. bit-4: up/down counter direction. reset low when counting down, set high when counting up. leading edge triggered. bits 5, 6 and 7 are always high. status register (read only, control): parameter min. max. units notes supply voltage 4.5 5.5 volts supply current - 200 a @ 5.0v input low voltage - 0.8 volts input high voltage 2.0 - volts output low voltage - 0.4 volts @4ma sink output high voltage 2.5 - volts @ 200a source input current - 15 n a leakage current output source current 200 - a @v oh = 2.5v output sink current 4 - ma @v ol = 0.4v data bus off-state leakage current - 15 na a & b (inputs) (pins 6 & 7): connect to a & b quadrature outputs of the encoder. the quadrature code will be decoded and used to clock and steer the 24-bit counter. it can be programmed to generate one clock once per quadrature cycle, once per 1/ 2 cycle or once per 1/4th cycle (x1, x2 or x4 mode). maximum count frequency is 10 mhz. a/b enable or counter reset (input) (pin 4): active low. minimum low pulse width is 60ns. the function of this pin is defined by bit-4 of the input control register. when bit-4 is low, a low level on this pin will reset the 24-bit counter. when bit-4 is high, a low level on this pin will enable the a & b inputs. load counter or load latch (input) (pin 3): active low. minimum low pulse width is 60ns. the function of this pin is defined by bit-5 of the input control register. when bit-5 is low, a low level on this pin will transfer the contents of the 24-bit preset register to the 24- bit counter. when bit-5 is high, a low level on this pin will transfer the contents of the 24-bit counter to the 24-bit counter output latch. realtime hardware input pin descriptions: data bus (pins 8-15): three-state, 8-bits. used to pass data to and from the internal registers in single and multiple-byte transfers. bits 6 & 7 are used as address bits to select the desired control registers during write operations. chip select (input) (pin 2): active low, enables the chip to read or write on the data bus. read (input) (pin 19): active low, enables the status register or 1-byte of the 24-bit output latch to be read on the data bus. write (input) (pin 1): active low, during chip select, latches the data bus into the internal registers. control-hi/data-lo (input) (pin 18): used to address various resistors during read and write cycles. a high level during a read cycle selects the status register. a high level during a write cycle selects 1 of the 4 control registers. a low level during a write cycle selects one byte of the preset register. a low level during a read cycle selects one byte of the counter output latch. microprocessor bus pin descriptions: dc electrical characteristics:
page 3 phone: 360.260.2468 l sales: 800.736.0194 l fax: 360.260.2469 email: sales@usdigital.com l website: www.usdigital.com 11100 ne 34th circle l vancouver, washington 98682 usa ls7166 encoder to microprocessor interface chip chips defines the operating mode of this chip. select this register by making bit-6 high and bit-7 low. bits 0, 1 & 2: these bits must be reset low for normal operation. bit-3: reset low to disable the a & b inputs. set high to enable the a & b inputs. bit-4: the function of hardware pin 4 is defined by this bit. when bit-4 is low, a low level on pin 4 will reset the 24-bit counter. when bit-4 is high, a high level on pin 4 will disable the a & b inputs. bit-5: the function of hardware pin 3 is defined by this bit. when bit-5 is low, a low level on pin 3 will transfer the contents of the 24-bit preset register to the 24-bit counter. when bit-5 is high, a low level on pin 3 will transfer to contents of the 24-bit counter to the 24-bit counter output latch. selects the quadrature count mode. select this register by making bit-6 high and bit-7 high. it can be programmed to generate one clock once per quadrature cycle, once per 1/2 cycle or once per 1/4th cycle (x1, x2 or x4 mode). for example, a 500 cycle/rev encoder can provide 500, 1000 or 2000 counts/rev. bits-0 & 1: bit-1 bit-0 quadrature count mode 0 0 not valid 0 1 x1 mode 1 0 x2 mode 1 1 x4 mode bits-3 & 5: these bits do not matter. writing to 1 of the 4 control registers: set control/data high. bits 6 & 7 are used as address bits to select one of these 4 registers. only bits 0-5 are stored. notes: d7 & d6 are the most significant bits of the data bus. c/d is control/data pin 18. rd is read pin 19. wr is write pin 1. cs is chip select pin 2. x means "don't care". write cycle timing: allow at least 15ns setup time for valid data, chip select and control/data before asserting write. make the write pulse at least 60ns long. hold the data bus, chip select and control/data stable at least 50ns after deasserting write. read cycle timing: the data bus will become valid within 110ns after asserting chip select, control/data and read. the 24-bit preset register is the input port for the 24-bit counter. the data is first written into the preset register in 3 write cycles (least significant byte 1st). the address pointer is automatically incremented with each write cycle. sequence: ? reset the address pointer by setting bit-0 of the master control register high. ? load byte 0 (lsb) into this register & increment address ? load byte 1 into this register & increment address ? load byte 2 (msb) into this register & increment address ? transfer the 3-byte preset register to the 24-bit counter by setting bit-3 high of the master control register. preset register (write only, data): input control register (write only): quadrature control register (write only): register access: the 24-bit counter value at any instant can be accessed by transferring its contents to the 24-bit counter output latch. note that only good stable data will be passed from the counter to the output latch even if the counter bits are in the midst of a transition. this chip will internally stretch the latch pulse if necessary until the counter has stabilized. the 3 bytes are then read from the output latch (least significant byte 1st). the address pointer is automati- cally incremented with each read cycle. sequence: ? reset the address pointer and transfer the counter value to the output latch by setting bits 0 and 1 of the master control register high. these bits will automatically reset to zero after the read sequence. ? read byte 0 (lsb) and increment address ? read byte 1 and increment address ? read byte 2 (msb) and increment address counter output latch (read only, data): performs register reset and load operations. select this register by making bits 6 and 7 low. writing a non-zero byte to this register does not require a follow-up write of an all-zeros byte to terminate an operation. control functions may be combined. all bits are high true. bit-0: reset the 3-byte address pointer, in preparation for a 3-byte (24-bit) write sequence of the preset register or read sequence of the output latch. bit-1: transfer the 24-bit counter contents to the 24-bit output latch. bit-2: reset the 24-bit counter, the borrow toggle flip-flop and the carry toggle flip-flop and set the sign bit high. bit-3: transfer the 24-bit preset register to the 24-bit counter. bit-4: reset the comparator match toggle flip-flop. bit-5: master reset. reset the 24-bit counter, the input control register, the output control register, the quadrature register, the borrow toggle flip- flop, the carry toggle flip-flop, the comparator toggle flip-flop and the 3- byte address pointer. note: master reset does not reset the counter perfectly. the counter will be either 1, 0 or -1 after a master reset. to reliably reset the counter to 0, do a reset counter command with bit-2 as shown above. master control register (write only): d7 d6 c/d rd wr cs function xxxxx1 disable chip for read or write 0011 0 write to master control register 0111 0 write to input control register 1011 0 write to output control register 1111 0 write to quadrature control register x x 0 1 0 write to preset register, then increment address counter x x 0 1 0 read output latch, then increment address counter x x 1 1 0 read output status register


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