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regarding the change of names mentioned in the document, such as mitsubishi electric and mitsubishi xx, to renesas technology corp. the semiconductor operations of hitachi and mitsubishi electric were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although mitsubishi electric, mitsubishi electric corporation, mitsubishi semiconductors, and other mitsubishi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. note : mitsubishi electric will continue the business operations of high frequency & optical devices and power devices. renesas technology corp. customer support dept. april 1, 2003 to all our customers
mitsubishi 8-bit single-chip microcomputer 740 family / 38000 series 3800 group users manual
notes regarding these materials these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customer? application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-party? rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. all information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these materials. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further details on these materials or the products contained therein. keep safety first in your circuit designs! mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
preface this users manual describes mitsubishis cmos 8- bit microcomputers 3800 group. after reading this manual, the user should have a through knowledge of the functions and features of the 3800 group, and should be able to fully utilize the product. the manual starts with specifications and ends with application examples. for details of software, refer to the series melps 740 users manual. for details of development support tools, refer to the development support tools for micro- computers data book.
before using this users manual this users manual consists of the following three chapters. refer to the chapter appropriate to your conditions, such as hardware design or software development. chapter 3 also includes necessary information for systems development. be sure to refer to this chapter. 1. organization l chapter 1 hardware this chapter describes features of the microcomputer and operation of each peripheral function. l chapter 2 application this chapter describes usage and application examples of peripheral functions, based mainly on setting examples of related registers. l chapter 3 appendix this chapter includes necessary information for systems development using the microcomputer, electric characteristics, a list of registers, the masking confirmation (mask rom version), and mark specifications which are to be submitted when ordering. 2. structure of register the figure of each register structure describes its functions, contents at reset, and attributes as follows : note 2. bit attributes??????the attributes of control register bits are classified into 3 bytes : read-only, write-only and read and write. in the figure, these attributes are represented as follows : : bit in which nothing is arranged 0 1 : name function at reset rw b 0 1 2 3 4 0 0 0 0 0 5 5 5 6 7 1 [ b0 b1 b2 b3 b4 b5 b6 b7 contents immediately after reset release bit attributes (note 1) processor mode bits stack page selection bit nothing arranged for these bits. these are write disabled bits. when these bits are read out, the contents are ?. fix this bit to ?. main clock (x in -x out ) stop bit internal system clock selection bit 0 0 : single-chip mode 1 0 : 1 1 : not available b1 b0 0 : 0 page 1 : 1 page 0 : operating 1 : stopped 0 : x in -x out selected 1 : x cin -x cout selected : bit that is not used for control of the corresponding function 0 note 1. contents immediately after reset release 0??at reset release 1??at reset release undefinedundefined or reset release contents determined by option at reset release [ rread read enabled 5 read disabled wwrite write enabled 5 write disabled (note 2) [ cpu mode register (cpum) [address : 3b 16 ] bits
list of groups ha ving the similar functions 3800 group, one of the cmos 8-bit microcomputer 38000 series presented in this users manual is provided with standard functions. the basic functions of the 3800, 3802, 3806 and 3807 groups having the same functions are shown below. for the detailed functions of each group, refer to the related data book and users manual. list of groups having the same functions notes 1: extended operating temperature version available 2: high-speed version available 3: extended operating temperature version and high-speed versio n available ] . rom expansion prescaler : 3 timer : 4 <8-bit> function group pin (package type) timer a-d converter d-a converter clock generating circuit serial i/o remarks one time prom eprom ram mask rom memory type ] 24k 512 384 32k 8k 16k 32k 16k (note 1) 8k (note 1) 16k (note 1) 32k (note 1) 384 384 640 8k (note 1) 24k 384 384 640 16k (note 1) 32k (note 1) 32k (note 1) 32k 1024 pwm output 512 16k 16k 16k 3800 gr oup 64 pin ? 64p4b ? 64p6n-a ? 64p6d-a 1 circuit prescaler : 3 timer : 4 <8-bit> uart or clock synchronous 5 1 3802 gr oup 64 pin ? 64p4b ? 64p6n-a 8-bit 5 8-channel 8-bit 5 2-channel uart or clock synchronous 5 1 clock synchronous 5 1 1 circuit 1 circuit prescaler : 3 timer : 4 <8-bit> uart or clock synchronous 5 1 clock synchronous 5 1 3806 gr oup 3807 gr oup 80 pin ? 80p6n-a 2 circuit 8-bit 5 13-channel 8-bit 5 4-channel uart or clock synchronous 5 1 clock synchronous 5 1 timer : 3 <8-bit> timer x/y : 2 timer a/b : 2 <16-bit> 80 pin ? 80p6n-a ? 80p6s-a ? 80p6d-a 12k (note 1) 16k (note 1) 24k (note 3 ) 24k 32k (note 3 ) 48k (note 3 ) 1024 512 384 384 1024 24k (note 2) 48k (note 3) 8-bit 5 8-channel 8-bit 5 2-channel as of september 1995 real time port output analog comparator watchdog timer 48k (note 2)
i table of contents 3800 group user's manual table of contents chapter 1. hardware description ................................................................................................................................ 1-2 features ...................................................................................................................................... 1-2 applications .............................................................................................................................. 1-2 pin configuration .................................................................................................................. 1-2 functional block ................................................................................................................... 1-4 pin description ........................................................................................................................ 1-5 part numbering ....................................................................................................................... 1-6 group expansion .................................................................................................................... 1-7 group expansion (extended operating temperature version) ................... 1-9 functional description .................................................................................................... 1-10 central processing unit (cpu) ............................................................................................ 1-10 memory .................................................................................................................................... 1-14 i/o ports .................................................................................................................................. 1-16 interrupts ................................................................................................................................. 1-18 timers ...................................................................................................................................... 1-20 serial i/o ................................................................................................................................. 1-22 reset circuit ........................................................................................................................... 1-26 clock generating circuit ....................................................................................................... 1-28 processor modes .................................................................................................................... 1-29 notes on programming ..................................................................................................... 1-31 processor status register .................................................................................................... 1-31 interrupts ................................................................................................................................. 1-31 decimal calculations .............................................................................................................. 1-31 timers ...................................................................................................................................... 1-31 multiplication and division instructions ............................................................................... 1-31 ports ......................................................................................................................................... 1-31 serial i/o ................................................................................................................................. 1-31 instruction execution time .................................................................................................... 1-31 memory expansion mode and microprocessor mode ....................................................... 1-31 data required for mask orders ................................................................................ 1-32 rom programming method .............................................................................................. 1-32 functional description supplement ......................................................................... 1-33 interrupt ................................................................................................................................... 1-33 timing after interrupt ............................................................................................................. 1-34
ii 3800 group user's manual table of contents chapter 2. application 2.1 i/o port ............................................................ ............................................................ ............. 2 - 2 2.1.1 memory map of i/o port ............................................................ ................................... 2 - 2 2.1.2 related registers ............................................................ ................................................ 2 - 3 2.1.3 handling of unused pins ............................................................ ................................... 2 - 4 2.2 timer ............................................................ ............................................................ ................. 2 - 5 2.2.1 memory map of timer ............................................................ ........................................ 2 - 5 2.2.2 related registers ............................................................ ................................................ 2 - 6 2.2.3 timer application examples ............................................................ ............................ 2-11 2.3 serial i/o ............................................................ ............................................................ ........ 2-23 2.3.1 memory map of serial i/o ............................................................ ............................... 2-23 2.3.2 related registers ............................................................ .............................................. 2-24 2.3.3 serial i/o connection examples ............................................................ ..................... 2-28 2.3.4 setting of serial i/o transfer data format ............................................................ ..... 2-30 2.3.5 serial i/o application examples ............................................................ ..................... 2-31 2.4 processor mode ............................................................ ....................................................... 2-49 2.4.1 memory map of processor mode ............................................................ ................... 2-49 2.4.2 related register ............................................................ ................................................ 2-49 2.4.3 processor mode application examples ............................................................ .......... 2-50 2.5 reset ............................................................ ............................................................ ............... 2-54 2.5.1 connection example of reset ic ............................................................ .................... 2-54 chapter 3. appendix 3.1 electrical characteristics ............................................................ ......................................... 3 - 2 3.1.1 absolute maximum ratings ............................................................ ................................ 3 - 2 3.1.2 recommended operating conditions ............................................................ ................ 3 - 2 3.1.3 electrical characteristics ............................................................ .................................... 3 - 3 3.1.4 timing requirements and switching characteristics .................................................. 3 - 4 3.1.5 absolute maximum ratings (extended operating temperatu re version) .................. 3 - 8 3.1.6 recommended operating conditions(extended operating te mperature version) .... 3 - 8 3.1.7 electrical characteristics (extended operating tempera ture version) ...................... 3 - 9 3.1.8 timing requirements and switching characteristics (extended operating temperature version) .......................................................... 3-10 3.1.9 timing diagram ............................................................ ................................................. 3-12 3.2 standard characteristics ............................................................ ........................................ 3-15 3.2.1 power source current characteristic examples ........................................................ 3-15 3.2.2 port standard characteristic examples ............................................................ .......... 3-16 3.3 notes on use ............................................................ ............................................................ 3-18 3.3.1 notes on interrupts ............................................................ .......................................... 3-18 3.3.2 notes on the serial i/o ............................................................ ................................... 3-18 3.3.3 notes on the reset pin ............................................................ ................................ 3-19 3.3.4 notes on input and output pins ............................................................ ..................... 3-20
iii table of contents 3800 group user's manual 3.3.5 notes on memory expansion mode and microprocessor mode ............................ 3-21 3.3.6 notes on built-in prom .............................................................................................. 3-22 3.4 countermeasures against noise ...................................................................................... 3-24 3.4.1 shortest wiring length .................................................................................................. 3-24 3.4.2 connection of a bypass capacitor across the vss line and the vcc line ............ 3-25 3.4.3 consideration for oscillator ......................................................................................... 3-26 3.4.4 setup for i/o ports ....................................................................................................... 3-26 3.4.5 providing of watchdog timer function by software .................................................. 3-27 3.5 list of registers ................................................................................................................... 3-28 3.6 mask rom ordering method ............................................................................................. 3-37 3.7 mark specification form ..................................................................................................... 3-51 3.8 package outline .................................................................................................................... 3-53 3.9 machine instructions .......................................................................................................... 3-56 3.10 list of instruction codes ................................................................................................. 3-66 3.11 sfr memory map .............................................................................................................. 3-67 3.12 pin configuration ............................................................................................................... 3-68
3800 group user?s manual i list of figures list of figures chapter 1 hardware fig. 1 pin configuration of m38002m4-xxxfp/m38003m6-xxxhp ....................................... 1 - 2 fig. 2 pin configuration of m38002m4-xxxsp ............................................................ ............. 1 - 3 fig. 3 functional block diagram ............................................................ ...................................... 1 - 4 fig. 4 part numbering ............................................................ ....................................................... 1 - 6 fig. 5 memory expansion plan ............................................................ ........................................ 1 - 7 fig. 6 memory expansion plan (extended operating temperature version) .......................... 1 - 9 fig. 7 740 family cpu register structure ............................................................ .................... 1-10 fig. 8 register push and pop at interrupt generation and sub routine call ........................ 1-11 fig. 9 structure of cpu mode register ............................................................ ........................ 1-13 fig. 10 memory map diagram ............................................................ ........................................ 1-14 fig. 11 memory map of special function register (sfr) ....................................................... 1-15 fig. 12 port block diagram (single-chip mode) ............................................................ ........... 1-17 fig. 13 interrupt control ............................................................ .................................................. 1-19 fig. 14 structure of interrupt-related registers ............................................................ ............ 1-19 fig. 15 structure of timer xy register ............................................................ .......................... 1-20 fig. 16 block diagram of timer x, timer y, timer 1, and time r 2 ........................................ 1-21 fig. 17 block diagram of clock synchronous serial i/o ......................................................... 1-22 fig. 18 operation of clock synchronous serial i/o function .................................................. 1-22 fig. 19 block diagram of uart serial i/o ............................................................ ................... 1-23 fig. 20 operation of uart serial i/o function ............................................................ ........... 1-24 fig. 21 structure of serial i/o control registers ............................................................ .......... 1-25 fig. 22 example of reset circuit ............................................................ .................................... 1-26 fig. 23 internal status of microcomputer after reset ............................................................ .. 1-26 fig. 24 timing of reset ............................................................ ................................................... 1-27 fig. 25 ceramic resonator circuit ............................................................ .................................. 1-28 fig. 26 external clock input circuit ............................................................ ............................... 1-28 fig. 27 block diagram of clock generating circuit ............................................................ ...................... 1-28 fig. 28 memory maps in various processor modes ............................................................ ... 1-29 fig. 29 structure of cpu mode register ............................................................ ...................... 1-29 fig. 30 onw function timing ............................................................ .......................................... 1-30 fig. 31 programming and testing of one time prom version ........................................... 1-32 fig. 32 timing chart after an interrupt occurs ............................................................ ............ 1-34 fig. 33 time up to execution of the interrupt processing rou tine ....................................... 1-34 chapter 2 application fig. 2.1.1 memory map of i/o port related registers ............................................................ ... 2 - 2 fig. 2.1.2 structure of port pi (i=0, 1, 2, 3, 4, 5, 6, 7) .......................................................... 2 - 3 fig. 2.1.3 structure of port pi direction register (i=0, 1, 2, 3, 4, 5, 6, 7) ........................... 2 - 3 fig. 2.2.1 memory map of timer related registers ............................................................ ......... 2 - 5 fig. 2.2.2 structure of prescaler 12, prescaler x, prescaler y .............................................. 2 - 6 fig. 2.2.3 structure of timer 1 ............................................................ ........................................ 2 - 6 fig. 2.2.4 structure of timer 2, timer x, timer y ............................................................ ....... 2 - 7 fig. 2.2.5 structure of timer xy mode register ............................................................ ........... 2 - 8 fig. 2.2.6 structure of interrupt request register 1 ............................................................ ...... 2 - 9
ii 3800 group users manual list of figures fig. 2.2.7 structure of interrupt request register 2 ................................................................... 2-9 fig. 2.2.8 structure of interrupt control register 1 .................................................................. 2-10 fig. 2.2.9 structure of interrupt control register 2 .................................................................. 2-10 fig. 2.2.10 connection of timers and setting of division ratios [clock function] ................ 2-12 fig. 2.2.11 setting of related registers [clock function] ......................................................... 2-13 fig. 2.2.12 control procedure [clock function] ........................................................................ 2-14 fig. 2.2.13 example of a peripheral circuit .............................................................................. 2-15 fig. 2.2.14 connection of the timer and setting of the division ratio [piezoelectric buzzer output] .......... 2-15 fig. 2.2.15 setting of related registers [piezoelectric buzzer output] ................................... 2-16 fig. 2.2.16 control procedure [piezoelectric buzzer output] .................................................. 2-16 fig. 2.2.17 a method for judging if input pulse exists ........................................................... 2-17 fig. 2.2.18 setting of related registers [measurement of frequency] ................................... 2-18 fig. 2.2.19 control procedure [measurement of frequency] ................................................... 2-19 fig. 2.2.20 connection of the timer and setting of the division ratio [measurement of pulse width] ........... 2-20 fig. 2.2.21 setting of related registers [measurement of pulse width] ................................ 2-21 fig. 2.2.22 control procedure [measurement of pulse width] ................................................ 2-22 fig. 2.3.1 memory map of serial i/o related registers ........................................................... 2-23 fig. 2.3.2 structure of transmit/receive buffer register ........................................................ 2-24 fig. 2.3.3 structure of serial i/o status register .................................................................... 2-24 fig. 2.3.4 structure of serial i/o control register ................................................................... 2-25 fig. 2.3.5 structure of uart control register ......................................................................... 2-25 fig. 2.3.6 structure of baud rate generator ............................................................................ 2-26 fig. 2.3.7 structure of interrupt edge selection register ....................................................... 2-26 fig. 2.3.8 structure of interrupt request register 1 ................................................................ 2-27 fig. 2.3.9 structure of interrupt control register 1 ................................................................. 2-27 fig. 2.3.10 serial i/o connection examples (1) ...................................................................... 2-28 fig. 2.3.11 serial i/o connection examples (2) ...................................................................... 2-29 fig. 2.3.12 setting of serial i/o transfer data format ............................................................ 2-30 fig. 2.3.13 connection diagram [communication using a clock synchronous serial i/o] 2-31 fig. 2.3.14 timing chart [communication using a clock synchronous serial i/o] ............. 2-31 fig. 2.3.15 setting of related registers at a transmitting side [communication using a clock synchronous serial i/o] .................................. 2-32 fig. 2.3.16 setting of related registers at a receiving side [communication using a clock synchronous serial i/o] .................................. 2-33 fig. 2.3.17 control procedure at a transmitting side [communication using a clock synchronous serial i/o] .................................. 2-34 fig. 2.3.18 control procedure at a receiving side[communication using a clock synchronous serial i/o] . 2-35 fig. 2.3.19 connection diagram [output of serial data] ......................................................... 2-36 fig. 2.3.20 timing chart [output of serial data] ...................................................................... 2-36 fig. 2.3.21 setting of serial i/o related registers [output of serial data] ............................ 2-37 fig. 2.3.22 setting of serial i/o transmission data [output of serial data] .......................... 2-37 fig. 2.3.23 control procedure of serial i/o [output of serial data] ...................................... 2-38 fig. 2.3.24 connection diagram [cyclic transmission or reception of block data between microcomputers] 2-39 fig. 2.3.25 timing chart [cyclic transmission or reception of block data between microcomputers] ........ 2-40 fig. 2.3.26 setting of related registers [cyclic transmission or reception of block data between microcomputers] . 2-40 fig. 2.3.27 control in the master unit ....................................................................................... 2-41 fig. 2.3.28 control in the slave unit ......................................................................................... 2-42 fig. 2.3.29 connection diagram [communication using uart] ............................................ 2-43 fig. 2.3.30 timing chart [communication using uart] ......................................................... 2-43
3800 group users manual iii list of figures fig. 2.3.31 setting of related registers at a transmitting side [communication using uart] ........................ 2-45 fig. 2.3.32 setting of related registers at a receiving side [communication using uart] ............................ 2-46 fig. 2.3.33 control procedure at a transmitting side [communication using uart] ......... 2-47 fig. 2.3.34 control procedure at a receiving side [communication using uart] .............. 2-48 fig. 2.4.1 memory map of processor mode related register ................................................ 2-49 fig. 2.4.2 structure of cpu mode register .............................................................................. 2-49 fig. 2.4.3 expansion example of rom and ram .................................................................. 2-50 fig. 2.4.4 read-cycle (oe access, sram) .............................................................................. 2-51 fig. 2.4.5 read-cycle (oe access, eprom) ........................................................................... 2-51 fig. 2.4.6 write-cycle (w control, sram) ................................................................................ 2-52 fig. 2.4.7 application example of the onw function ............................................................. 2-53 fig. 2.5.1 example of poweron reset circuit ........................................................................... 2-54 fig. 2.5.2 ram back-up system ................................................................................................ 2-54
iv 3800 group users manual list of figures chapter 3 appendix fig. 3.1.1 circuit for measuring output switching characteristics ......................................... 3-11 fig. 3.1.2 timing diagram (in single-chip mode) .................................................................... 3-12 fig. 3.1.3 timing diagram (in memory expansion mode and microprocessor mode) (1) 3-13 fig. 3.1.4 timing diagram (in memory expansion mode and microprocessor mode) (2) 3-14 fig. 3.2.1 power source current characteristic example ....................................................... 3-15 fig. 3.2.2 power source current characteristic example (in wait mode) ............................. 3-15 fig. 3.2.3 standard characteristic example of cmos output port at p-channel drive(1). 3-16 fig. 3.2.4 standard characteristic example of cmos output port at p-channel drive(2). 3-16 fig. 3.2.5 standard characteristic example of cmos output port at n-channel drive(1) 3-17 fig. 3.2.6 standard characteristic example of cmos output port at n-channel drive(2) 3-17 fig. 3.3.1 structure of interrupt control register 2 .................................................................. 3-18 fig. 3.4.1 wiring for the reset pin ........................................................................................ 3-24 fig. 3.4.2 wiring for clock i/o pins ........................................................................................... 3-25 fig. 3.4.3 wiring for the v pp pin of the one time prom and the eprom version ....... 3-25 fig. 3.4.4 bypass capacitor across the v ss line and the v cc line ..................................... 3-25 fig. 3.4.5 wiring for a large current signal line ..................................................................... 3-26 fig. 3.4.6 wiring to a signal line where potential levels change frequently ...................... 3-26 fig. 3.4.7 stepup for i/o ports .................................................................................................. 3-26 fig. 3.4.8 watchdog timer by software .................................................................................... 3-27 fig. 3.5.1 structure of port pi (i=0, 1, 2, 3, 4, 5, 6, 7) ........................................................ 3-28 fig. 3.5.2 structure of port pi direction register (i=0, 1, 2, 3, 4, 5, 6, 7) ......................... 3-28 fig. 3.5.3 structure of transmit/receive buffer register ....................................................... 3-29 fig. 3.5.4 structure of serial i/o status register .................................................................... 3-29 fig. 3.5.5 structure of serial i/o control register ................................................................... 3-30 fig. 3.5.6 structure of uart control register ......................................................................... 3-30 fig. 3.5.7 structure of baud rate generator ............................................................................ 3-31 fig. 3.5.8 structure of prescaler 12, prescaler x, prescaler y ........................................... 3-31 fig. 3.5.9 structure of timer 1 .................................................................................................. 3-32 fig. 3.5.10 structure of timer 2, timer x, timer y .............................................................. 3-32 fig. 3.5.11 structure of timer xy mode register ................................................................... 3-33 fig. 3.5.12 structure of interrupt edge selection register ..................................................... 3-34 fig. 3.5.13 structure of cpu mode register ............................................................................ 3-34 fig. 3.5.14 structure of interrupt request register 1 .............................................................. 3-35 fig. 3.5.15 structure of interrupt request register 2 .............................................................. 3-35 fig. 3.5.16 structure of interrupt control register 1 ............................................................... 3-36 fig. 3.5.17 structure of interrupt control register 2 ............................................................... 3-36
3800 group users manual i list of tables list of tables chapter 1 hardware table 1 pin description ................................................................................................................. 1-5 table 2 list of supported products ............................................................................................. 1-8 table 3 list of supported products (extended operating temperature version) .................. 1-9 table 4 push and pop instructions of accumulator or processor status register .............. 1-11 table 5 set and clear instructions of each bit of processor status register ...................... 1-12 table 6 list of i/o port functions .............................................................................................. 1-16 table 7 interrupt vector addresses and priority ...................................................................... 1-18 table 8 functions of ports in memory expansion mode and microprocessor mode ........ 1-29 table 9 programming adapter ................................................................................................... 1-32 table 10 interrupt sources, vector addresses and interrupt priority .................................... 1-33 chapter 2 application table 2.1.1 handling of unused pins (in single-chip mode) ................................................... 2-4 table 2.1.2 handling of unused pins ( in memory expansion mode and microprocessor mode ) ....... 2-4 table 2.2.1 function of cntr 0 /cntr 1 edge switch bit .......................................................... 2-8 table 2.3.1 setting examples of baud rate generator values and transfer bit rate values .................... 2-44 chapter 3 appendix table 3.1.1 absolute maximum ratings ...................................................................................... 3-2 table 3.1.2 recommended operating conditions ...................................................................... 3-2 table 3.1.3 electrical characteristics .......................................................................................... 3-3 table 3.1.4 timing requirements (1) .......................................................................................... 3-4 table 3.1.5 timing requirements (2) .......................................................................................... 3-4 table 3.1.6 switching characteristics (1) ................................................................................... 3-5 table 3.1.7 switching characteristics (2) ................................................................................... 3-5 table 3.1.8 timing requirements in memory expansion mode and microprocessor mode (1) ...................... 3-6 table 3.1.9 switching characteristics in memory expansion mode and microprocessor mode (1) ............... 3-6 table 3.1.10 timing requirements in memory expansion mode and microprocessor mode (2) .................... 3-7 table 3.1.11 switching characteristics in memory expansion mode and microprocessor mode (2) ............ 3-7 table 3.1.12 absolute maximum ratings (extended operating temperature version) .......... 3-8 table 3.1.13 recommended operating conditions ( extended operating temperature version ) ...... 3-8 table 3.1.14 electrical characteristics (extended operating temperature version) .............. 3-9 table 3.1.15 timing requirements (extended operating temperature version) .................. 3-10 table 3.1.16 switching characteristics (extended operating temperature version) ............ 3-10 table 3.1.17 timing requirements in memory expansion mode and microprocessor mode (extended operating temperature version) ................................................... 3-11 table 3.1.18 switching characteristics in memory expansion mode and microprocessor mode (extended operating temperature version) ................................................... 3-11
ii 3800 group users manual list of tables table 3.3.1 programming adapter ............................................................................................. 3-22 table 3.3.2 setting of programming adapter switch ............................................................... 3-22 table 3.3.3 setting of prom programmer address ................................................................ 3-23 table 3.5.1 function of cntr 0 /cntr 1 edge switch bit ........................................................ 3-33
chapter 1 chapter 1 hardware description features applications pin configuration functional block pin description part numbering group expansion functional description notes on programming data required for mask orders rom programming method functional description supplement
1-2 hardware 3800 group users manual description/features/applications/pin configuration pin configuration (top view) fig. 1 pin configuration of m38002m4-xxxfp/m38003m6-xxxhp package type : 64p6n-a/64p6d-a 64-pin plastic-molded qfp description the 3800 group is the 8-bit microcomputer based on the 740 fam- ily core technology. the 3800 group is designed for office automation equipment, household appliances and include four timers, serial i/o function. the various microcomputers in the 3800 group include variations of internal memory size and packaging. for details, refer to the section on part numbering. for details on availability of microcomputers in the 3800 group, re- fer to the section on group expansion. features ? basic machine-language instructions ....................................... 71 ? the minimum instruction execution time ............................ 0.5 m s (at 8 mhz oscillation frequency) ? memory size rom .................................................................. 8 k to 32 k bytes ram ................................................................. 384 to 1024 bytes ? programmable input/output ports ............................................. 58 ? interrupts .................................................. 15 sources, 15 vectors ? timers ............................................................................. 8 bit 5 4 ? serial i/o ....................... 8-bit 5 1 (uart or clock-synchronized) ? clock generating circuit ....................... internal feedback resistor (connect to external ceramic resonator or quartz-crystal oscillator) ? power source voltage ..................................................3.0 to 5.5 v (extended operating temperature version : 4.0 to 5.5 v) ? power dissipation ............................................................... 32 mw ? memory expansion possible ? operating temperature range .................................... C20 to 85 c (extended operating temperature version : C40 to 85 c) applications office automation, factory automation, household appliances, and other consumer applications, etc. m38002m4-xxxfp m38003m6-xxxhp 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p3 3 /reset out p3 4 / f p3 5 /sync p3 7 /rd p3 6 /wr p3 2 /onw p6 4 p6 6 p6 7 p7 0 p7 1 v cc p3 0 p3 1 p6 3 p6 5 p6 2 p6 1 p6 0 p5 7 p5 6 p5 5 /cntr 1 p5 4 /cntr 0 p5 3 /int 5 p5 2 /int 4 p5 1 /int 3 p5 0 /int 2 p4 7 /s rdy p4 6 /s clk p4 3 /int 1 p4 4 /r x d p4 5 /t x d p2 4 /db 4 p2 3 /db 3 p2 2 /db 2 p2 0 /db 0 p2 1 /db 1 p2 5 /db 5 cnv ss p4 1 p4 0 x in x out v ss p2 7 /db 7 p2 6 /db 6 p4 2 /int 0 reset p0 0 /ad 0 p0 1 /ad 1 p0 2 /ad 2 p0 3 /ad 3 p0 4 /ad 4 p0 5 /ad 5 p0 6 /ad 6 p0 7 /ad 7 p1 0 /ad 8 p1 1 /ad 9 p1 2 /ad 10 p1 3 /ad 11 p1 4 /ad 12 p1 7 /ad 15 p1 6 /ad 14 p1 5 /ad 13
hardw are 1-3 3800 group users manual pin configuration pin configura tion (t op view) fig. 2 pin configuration of m38002m4-xxxsp package type : 64p4b 64-pin shrink plastic-molded dip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p6 4 p6 6 p6 7 p7 0 p7 1 v cc p6 3 p6 5 p6 2 p6 1 p6 0 p5 7 p5 6 p5 5 /cntr 1 p5 4 /cntr 0 p5 3 /int 5 p5 2 /int 4 p5 1 /int 3 p5 0 /int 2 p4 7 /s rdy p4 6 /s clk p4 3 /int 1 p4 4 /r x d p4 5 /t x d cnv ss p4 1 p4 0 x in x out v ss p4 2 /int 0 reset p2 4 /db 4 p2 3 /db 3 p2 2 /db 2 p2 0 /db 0 p2 1 /db 1 p2 5 /db 5 p2 7 /db 7 p2 6 /db 6 p3 3 /reset out p3 4 / f p3 5 /sync p3 7 /rd p3 6 /wr p3 2 /onw p3 0 p3 1 p0 0 /ad 0 p0 1 /ad 1 p0 2 /ad 2 p0 3 /ad 3 p0 4 /ad 4 p0 5 /ad 5 p0 6 /ad 6 p0 7 /ad 7 p1 0 /ad 8 p1 1 /ad 9 p1 2 /ad 10 p1 3 /ad 11 p1 4 /ad 12 p1 7 /ad 15 p1 6 /ad 14 p1 5 /ad 13 m38002m4-xxxsp
1-4 hardware 3800 group users manual functional block fig. 3 functional block diagram functional block diagram (package : 64p4b) functional block cntr 1 cntr 0 int 2 to int 5 ram rom cpu a x y s pc h pc l ps v ss 32 reset 27 v cc 1 26 cnv ss p0(8) 49 50 51 52 53 54 55 56 p1(8) 41 43 45 47 42 44 46 48 p2(8) 33 35 37 39 34 36 38 40 p3(8) 57 59 61 63 58 60 62 64 p4(8) 20 22 24 28 21 23 25 29 p5(8) 12 14 16 18 13 15 17 19 p7(2) 3 2 p6(8) 4 6 10 5911 x in 30 x out 31 reset input clock generating circuit clock input clock output prescaler 12 (8) timer 1 (8) timer 2 (8) i/o port p4 i/o port p0 i/o port p1 i/o port p2 i/o port p3 i/o port p5 i/o port p7 i/o port p6 7 8 serial i/o(8) int 0, int 1 prescaler x (8) timer x (8) prescaler y (8) timer y (8) cpu data bus
hardware 1-5 3800 group users manual ? 8-bit cmos i/o port with the same function as port p0 ? cmos compatible input level ? cmos 3-state output structure pin v cc v ss cnv ss reset x in x out p0 0 C p0 7 p1 0 C p1 7 p2 0 C p2 7 p3 0 C p3 7 p4 0 , p4 1 p4 2 /int 0 , p4 3 /int 1 p4 4 /r x d, p4 5 /t x d, p4 6 /s clk , p4 7 /s rdy p5 0 /int 2 C p5 3 /int 5 p5 4 /cntr 0 , p5 5 /cntr 1 p5 6 , p5 7 p6 0 C p6 7 p7 0 , p7 1 function ? apply voltage of 3.0 v to 5.5 v to v cc , and 0 v to v ss . (extended operating temperature version : 4.0 v to 5.5 v) ? this pin controls the operation mode of the chip. ? normally connected to v ss . ? if this pin is connected to v cc , the internal rom is inhibited and external memory is accessed. ? reset input pin for active l ? input and output signals for the internal clock generating circuit. ? connect a ceramic resonator or quartz-crystal oscillator between the x in and x out pins to set the oscillation frequency. ? if an external clock is used, connect the clock source to the x in pin and leave the x out pin open. ? the clock is used as the oscillating source of system clock. ? 8 bit cmos i/o port ? i/o direction register allows each pin to be individually programmed as either input or output. ? at reset this port is set to input mode. ? in modes other than single-chip, these pins are used as address, data, and control bus i/o pins. ? cmos compatible input level ? cmos 3-state output structure ? 8-bit cmos i/o port with the same function as port p0 ? cmos compatible input level ? cmos 3-state output structure pin description table 1. pin description pin description name power source cnv ss reset input clock input clock output i/o port p0 i/o port p1 i/o port p2 i/o port p3 i/o port p4 i/o port p5 i/o port p6 i/o port p7 function except a port function ? external interrupt input pins ? serial i/o i/o pins ? external interrupt input pins ? timer x and timer y i/o pins ? 8-bit cmos i/o port with the same function as port p0 ? cmos compatible input level ? cmos 3-state output structure ? 2-bit cmos i/o port with the same function as port p0 ? cmos compatible input level ? cmos 3-state output structure
1-6 hardw are 3800 group users manual part numbering fig. 4 part numbering p ar t numbering m3800 2 m 4 - xxx sp product package type sp : 64p4b package fp : 64p6n-a package hp : 64p6d-a package ss : 64s1b package fs : 64d0 package rom number omitted in some types. rom/prom size 1 2 3 4 5 6 7 8 : 4096 bytes : 8192 bytes : 12288 bytes : 16384 bytes : 20480 bytes : 24576 bytes : 28672 bytes : 32768 bytes the first 128 bytes and the last 2 bytes of rom are reserved areas ; they cannot be used. memory type m e s : mask rom version : eprom or one time prom version : external rom ram size 0 1 2 3 4 5 6 7 : 192 bytes : 256 bytes : 384 bytes : 512 bytes : 640 bytes : 768 bytes : 896 bytes : 1024 bytes normally, using hyphen when electrical characteristic, or division of quality identification code using alphanumeric character C : standard d : extended operating temperature version
hardware 1-7 3800 group users manual group expansion group expansion mitsubishi plans to expand the 3800 group as follows: (1) support for mask rom, one time prom, eprom, and external rom versions rom/prom capacity ................................... 8 k to 32 k bytes ram capacity .............................................. 384 to 1024 bytes (2) packages 64p4b ............................................ shrink plastic molded dip 64p6n-a ............................. 0.8 mm pitch plastic molded qfp 64p6d-a ............................. 0.5 mm pitch plastic molded qfp 64s1b ......................... shrink ceramic dip (eprom version) 64d0 ................ 0.8 mm pitch ceramic lcc (eprom version) memory expansion plan fig. 5 memory expansion plan m38002m2/e2 m38002m4/e4 m38003m6 m38002s m38007m8/e8 mass product being planned mass product mass product mass product external rom rom size (bytes) 32k 28k 24k 20k 16k 12k 8k 192 256 384 512 640 768 896 1024 ram size (bytes) m38004m8/e8 mass product note : products under development or planning: the development schedule and specifications may be revised without notice.
1-8 hardware 3800 group users manual remarks mask rom version one time prom version one time prom version (blank) mask rom version one time prom version one time prom version (blank) mask rom version one time prom version one time prom version (blank) eprom version mask rom version one time prom version one time prom version (blank) eprom version mask rom version mask rom version mask rom version mask rom version one time prom version one time prom version (blank) eprom version mask rom version one time prom version one time prom version (blank) eprom version external rom type external rom type product m38002m2-xxxsp m38002e2-xxxsp m38002e2sp m38002m2-xxxfp m38002e2-xxxfp m38002e2fp m38002m4-xxxsp m38002e4-xxxsp m38002e4sp m38002e4ss m38002m4-xxxfp m38002e4-xxxfp m38002e4fp m38002e4fs m38003m6-xxxsp m38003m6-xxxfp m38003m6-xxxhp m38004m8-xxxsp m38004e8-xxxsp m38004e8sp m38004e8ss m38004m8-xxxfp m38004e8-xxxfp m38004e8fp m38004e8fs m38002ssp m38002sfp group expansion currently supported products are listed below. ram size (bytes) package table 2. list of supported products as of september 1995 8192 (8062) 16384 (16254) (p) rom size (bytes) rom size for user in ( ) 24576 (24446) 32768 (32638) 0 384 384 512 640 384 64p4b 64p6n-a 64p4b 64s1b-e 64p6n-a 64d0 64p4b 64p6n-a 64p6d-a 64p4b 64s1b-e 64p6n-a 64d0 64p4b 64p6n-a
hardware 1-9 3800 group users manual product name m38002m2dxxxsp m38002m2dxxxfp m38002m4dxxxsp m38002e4dxxxsp m38002e4dsp m38002m4dxxxfp m38002e4dxxxfp m38002e4dfp m38004m8dxxxsp m38004m8dxxxfp remarks mask rom version mask rom version mask rom version one time prom version one time prom version (blank) mask rom version one time prom version one time prom version (blank) mask rom version mask rom version group expansion group expansion (extended operating temperature version) mitsubishi plans to expand the 3800 group (extended operating temperature version) as follows: (1) support for mask rom, one time prom, and eprom versions rom/prom capacity ................................... 8 k to 32 k bytes ram capacity ................................................ 384 to 640 bytes (2) packages 64p4b ............................................ shrink plastic molded dip 64p6n-a ............................. 0.8 mm pitch plastic molded qfp memory expansion plan (extended operating temperature version) fig. 6 memory expansion plan (extended operating temperature version) currently supported products are listed below. ram size (bytes) 8192 (8062) as of september 1995 package 64p4b 64p6n-a table 3. list of supported products (extended operating temperature version) m38002m4d/e4d mass product m38002m2d mass product m38004m8d mass product rom size (bytes) 32k 28k 24k 20k 16k 12k 8k 4k 192 256 384 512 640 768 896 1024 ram size (bytes) (p) rom size (bytes) rom size for user in ( ) 16384 (16254) 32768 (32638) 384 384 1024 64p4b 64p6n-a 64p4b 64p6n-a
1-10 hardware 3800 group users manual functional description central processing unit (cpu) the 3800 group uses the standard 740 family instruction set. re- fer to the table of 740 family addressing modes and machine in- structions or the series 740 users manual for de- tails on the instruction set. machine-resident 740 family instructions are as follows: the fst and slw instruction cannot be used. the stp, wit, mul, and div instruction can be used. the central processing unit (cpu) has the six registers. accumulator (a) the accumulator is an 8-bit register. data operations such as data transfer, etc., are executed mainly through the accumulator. index register x (x), index register y (y) both index register x and index register y are 8-bit registers. in the index addressing modes, the value of the operand is added to the contents of register x or register y and specifies the real ad- dress. when the t flag in the processor status register is set to 1, the value contained in index register x becomes the address for the second operand. stack pointer (s) the stack pointer is an 8-bit register used during subroutine calls and interrupts. the stack is used to store the current address data and processor status when branching to subroutines or interrupt routines. the lower eight bits of the stack address are determined by the contents of the stack pointer. the upper eight bits of the stack ad- dress are determined by the stack page selection bit. if the stack page selection bit is 0, then the ram in the zero page is used as the stack area. if the stack page selection bit is 1, then ram in page 1 is used as the stack area. the stack page selection bit is located in the sfr area in the zero page. note that the initial value of the stack page selection bit varies with each microcomputer type. also some microcom- puter types have no stack page selection bit and the upper eight bits of the stack address are fixed. the operations of pushing register contents onto the stack and popping them from the stack are shown in fig. 8. program counter (pc) the program counter is a 16-bit counter consisting of two 8-bit registers pc h and pc l . it is used to indicate the address of the next instruction to be executed. fig. 7 740 family cpu register structure functional description x y s pc l c nvtbd i z a b0 b0 b7 b7 b15 b0 b7 b0 b7 b0 b7 b0 b7 accumulator index register x index register y stack pointer program counter processor status register (ps) carry flag zero flag interrupt disable flag decimal mode flag break flag index x mode flag overflow flag negative flag pc h
hardware 1-11 3800 group users manual fig. 8 register push and pop at interrupt generation and subroutine call table 4. push and pop instructions of accumulator or processor status register accumulator processor status register push instruction to stack pha php pop instruction from stack pla plp functional description on-going routine execute jsr m(s) ? (pc h ) (s) ? (s e 1) m(s) ? (pc l ) (s) ? (s e 1) subroutine (s) ? (s + 1) (pc l ) ? m(s) (s) ? (s + 1) (pc h ) ? m(s) execute rts (s) ? (s e 1) m(s) ? (ps) (s) ? (s e 1) interrupt service routine (s) ? (s + 1) (ps) ? m(s) (s) ? (s + 1) (pc l ) ? m(s) execute rti (s) ? (s + 1) (pc h ) ? m(s) m(s) ? (pc h ) (s) ? (s e 1) m(s) ? (pc l ) interrupt request (note 1) store return address on stack (note 2) restore return address restore contents of processor status register i flag 0 to 1 fetch the jump vector store contents of processor status register on stack store return address on stack (note 2) notes 1 : the condition to enable the interrup t ? interrupt enable bit is 1 interrupt disable flag is 0 2 : when an interrupt occurs, the address of the next instruction to be executed is stored in the stack area. when a subroutine is called, the address one before the next instruction to be executed is stored in the stack area. restore return address
1-12 hardware 3800 group users manual processor status register (ps) the processor status register is an 8-bit register consisting of flags which indicate the status of the processor after an arithmetic op- eration. branch operations can be performed by testing the carry (c) flag, zero (z) flag, overflow (v) flag, or the negative (n) flag. in decimal mode, the z, v, n flags are not valid. after reset, the interrupt disable (i) flag is set to 1, but all other flags are undefined. since the index x mode (t) and decimal mode (d) flags directly affect arithmetic operations, they should be initialized in the beginning of a program. (1) carry flag (c) the c flag contains a carry or borrow generated by the arith- metic logic unit (alu) immediately after an arithmetic opera- tion. it can also be changed by a shift or rotate instruction. (2) zero flag (z) the z flag is set if the result of an immediate arithmetic op- eration or a data transfer is 0, and cleared if the result is anything other than 0. (3) interrupt disable flag (i) the i flag disables all interrupts except for the interrupt gener- ated by the brk instruction. interrupts are disabled when the i flag is 1. when an interrupt occurs, this flag is automatically set to 1 to prevent other interrupts from interfering until the current in- terrupt is serviced. (4) decimal mode flag (d) the d flag determines whether additions and subtractions are executed in binary or decimal. binary arithmetic is executed when this flag is 0; decimal arithmetic is executed when it is 1. decimal correction is automatic in decimal mode. only the adc and sbc instructions can be used for decimal arith- metic. (5) break flag (b) the b flag is used to indicate that the current interrupt was generated by the brk instruction. the brk flag in the pro- cessor status register is always 0. when the brk instruc- tion is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to 1. the saved processor status is the only place where the break flag is ever set. (6) index x mode flag (t) when the t flag is 0, arithmetic operations are performed between accumulator and memory, e.g. the results of an op- eration between two memory locations is stored in the accu- mulator. when the t flag is 1, direct arithmetic operations and direct data transfers are enabled between memory loca- tions, i.e. between memory and memory, memory and i/o, and i/o and i/o. in this case, the result of an arithmetic op- eration performed on data in memory location 1 and memory location 2 is stored in memory location 1. the address of memory location 1 is specified by index register x, and the address of memory location 2 is specified by normal address- ing modes. (7) overflow flag (v) the v flag is used during the addition or subtraction of one byte of signed data. it is set if the result exceeds + 127 to C128. when the bit instruction is executed, bit 6 of the memory location operated on by the bit instruction is stored in the overflow flag. (8) negative flag (n) the n flag is set if the result of an arithmetic operation or data transfer is negative. when the bit instruction is executed, bit 7 of the memory location operated on by the bit instruction is stored in the negative flag. functional description table 5. set and clear instructions of each bit of processor status register set instruction clear instruction c flag sec clc z flag i flag sei cli d flag sed cld b flag t flag set clt v flag clv n flag
hardware 1-13 3800 group users manual cpu mode register the cpu mode register is allocated at address 003b 16 . the cpu mode register contains the stack page selection bit. fig. 9 structure of cpu mode register functional description cpu mode register ( cpum : address 003b 16 ) b7 b0 stack page selection bit 0 : 0 page 1 : 1 page not used (return 0 when read) processor mode bits b1 b0 0 0 : single-chip mode 0 1 : memory expansion mode 1 0 : microprocessor mode 1 1 : not available
1-14 hardware 3800 group users manual memory special function register (sfr) area the special function register area in the zero page contains con- trol registers such as i/o ports and timers. ram ram is used for data storage and for stack area of subroutine calls and interrupts. rom the first 128 bytes and the last 2 bytes of rom are reserved for device testing and the rest is user area for storing programs. interrupt vector area the interrupt vector area contains reset and interrupt vectors. zero page the 256 bytes from addresses 0000 16 to 00ff 16 are called the zero page area. the internal ram and the special function regis- ters (sfr) are allocated to this area. the zero page addressing mode can be used to specify memory and register addresses in the zero page area. access to this area with only 2 bytes is possible in the zero page addressing mode. special page the 256 bytes from addresses ff00 16 to ffff 16 are called the special page area. the special page addressing mode can be used to specify memory addresses in the special page area. ac- cess to this area with only 2 bytes is possible in the special page addressing mode. fig. 10 memory map diagram functional description 0100 16 0000 16 0040 16 0440 16 ff00 16 ffdc 16 fffe 16 ffff 16 192 256 384 512 640 768 896 1024 xxxx 16 00ff 16 013f 16 01bf 16 023f 16 02bf 16 033f 16 03bf 16 043f 16 4096 8192 12288 16384 20480 24576 28672 32768 f000 16 e000 16 d000 16 c000 16 b000 16 a000 16 9000 16 8000 16 f080 16 e080 16 d080 16 c080 16 b080 16 a080 16 9080 16 8080 16 yyyy 16 zzzz 16 ram rom reserved area sfr area not used interrupt vector area rom area reserved rom area (128 bytes) zero page special page ram area ram capacity (bytes) address xxxx 16 rom capacity (bytes) address yyyy 16 reserved rom area address zzzz 16
hardware 1-15 3800 group users manual fig. 11 memory map of special function register (sfr) functional description 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 port p0 (p0) port p0 direction register (p0d) port p1 (p1) port p1 direction register (p1d) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p3 direction register (p3d) port p4 (p4) port p4 direction register (p4d) port p5 (p5) port p5 direction register (p5d) port p6 (p6) port p6 direction register (p6d) port p7 (p7) port p7 direction register (p7d) transmit/receive buffer register (tb/rb) serial i/o status register (siosts) serial i/o control register (siocon) uart control register (uartcon) baud rate generator (brg) interrupt control register 2(icon2) prescaler y (prey) timer y (ty) interrupt edge selection register (intedge) cpu mode register (cpum) interrupt request register 1(ireq1) interrupt request register 2(ireq2) interrupt control register 1(icon1) prescaler 12 (pre12) timer 2 (t2) prescaler x (prex) timer x (tx) timer 1 (t1) timer xy mode register (tm)
1-16 hardware 3800 group users manual pin p0 0 C p0 7 p1 0 C p1 7 p2 0 C p2 7 p3 0 C p3 7 p4 0 ,p4 1 p4 2 /int 0 , p4 3 /int 1 p4 4 /r x d, p4 5 /t x d, p4 6 /s clk , p4 7 /s rdy p5 0 /int 2 , p5 1 /int 3 , p5 2 /int 4 , p5 3 /int 5 p5 4 /cntr 0 , p5 5 /cntr 1 p5 6 ,p5 7 p6 0 C p6 7 p7 0 , p7 1 name port p0 port p1 port p2 port p3 port p4 port p5 port p6 port p7 input/output input/output, individual bits input/output, individual bits input/output, individual bits input/output, individual bits input/output, individual bits input/output, individual bits input/output, individual bits input/output, individual bits i/o format cmos 3-state output cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output cmos compatible input level non-port function address low-order byte output address high-order byte output data bus i/o control signal i/o external interrupt input serial i/o function i/o external interrupt input timer x and timer y function i/o ref.no. (1) (2) (3) (4) (5) (6) (2) (7) (1) table 6. list of i/o port functions related sfrs cpu mode register cpu mode register cpu mode register cpu mode register interrupt edge selection register serial i/o control register uart control register interrupt edge selection register timer xy mode register note 1 : for details of the functions of ports p0 to p3 in modes other than single-chip mode, and how to use double-function ports as func- tion i/o ports, refer to the applicable sections. 2 : make sure that the input level at each pin is either 0 v or v cc during execution of the stp instruction. when an input level is at an intermediate potential, a current will flow from v cc to v ss through the input-stage gate. i/o ports direction registers the 3800 group has 58 programmable i/o pins arranged in eight i/o ports (ports p0 to p7). the i/o ports have direction registers which determine the input/output direction of each individual pin. each bit in a direction register corresponds to one pin, each pin can be set to be input port or output port. when 0 is written to the bit corresponding to a pin, that pin be- comes an input pin. when 1 is written to that bit, that pin be- comes an output pin. if data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. pins set to input are floating. if a pin set to input is written to, only the port output latch is written to and the pin remains floating. functional description
hardware 1-17 3800 group users manual fig. 12 port block diagram (single-chip mode) functional description (1) ports p0, p1, p2, p3, p4 0 , p4 1 , p5 6 , p5 7 , p6, p7 direction register data bus port latch (2) ports p4 2 , p4 3 , p5 0 C p5 3 direction register data bus port latch interrupt input (3) port p4 4 direction register data bus port latch serial i/o input serial i/o enable bit receive enable bit (4) port p4 5 direction register data bus port latch serial i/o output serial i/o enable bit transmit enable bit p4 5 /t x d p-channel output disable bit (5) port p4 6 direction register data bus port latch serial i/o clock output serial i/o mode selection bit serial i/o enable bit serial i/o enable bit serial i/o synchronous clock selection bit serial i/o external clock input (6) port p4 7 direction register data bus port latch serial i/o ready output serial i/o enable bit s rdy output enable bit serial i/o mode selection bit (7) ports p5 4 , p5 5 direction register data bus port latch pulse output mode timer output counter input interrupt input
1-18 hardware 3800 group users manual interrupts interrupts occur by fifteen sources: eight external, six internal, and one software. interrupt control each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software in- terrupt set by the brk instruction. an interrupt occurs if the corre- sponding interrupt request and enable bits are 1 and the inter- rupt disable flag is 0. interrupt enable bits can be set or cleared by software. interrupt request bits can be cleared by software, but cannot be set by software. the brk instruction cannot be disabled with any flag or bit. the i (interrupt disable) flag disables all interrupts except the brk in- struction interrupt. interrupt operation when an interrupt is received, the contents of the program counter and processor status register are automatically stored into the stack. the interrupt disable flag is set to inhibit other interrupts from interfering.the corresponding interrupt request bit is cleared and the interrupt jump destination address is read from the vector table into the program counter. notes on use when the active edge of an external interrupt (int 0 to int 5 , cntr 0 , or cntr 1 ) is changed, the corresponding interrupt re- quest bit may also be set. therefore, please take following se- quence; (1) disable the external interrupt which is selected. (2) change the active edge selection. (3) clear the interrupt request bit which is selected to 0. (4) enable the external interrupt which is selected. functional description interrupt source reset (note 2) int 0 int 1 serial i/o reception serial i/o transmission timer x timer y timer 1 timer 2 cntr 0 cntr 1 int 2 int 3 int 4 int 5 brk instruction low fffc 16 fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffdc 16 high fffd 16 fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdd 16 table 7. interrupt vector addresses and priority priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 interrupt request generating conditions at reset at detection of either rising or falling edge of int 0 input at detection of either rising or falling edge of int 1 input at completion of serial i/o data reception at completion of serial i/o transfer shift or when transmission buffer is empty at timer x underflow at timer y underflow at timer 1 underflow at timer 2 underflow at detection of either rising or falling edge of cntr 0 input at detection of either rising or falling edge of cntr 1 input at detection of either rising or falling edge of int 2 input at detection of either rising or falling edge of int 3 input at detection of either rising or falling edge of int 4 input at detection of either rising or falling edge of int 5 input at brk instruction execution remarks non-maskable external interrupt (active edge selectable) external interrupt (active edge selectable) valid when serial i/o is selected valid when serial i/o is selected stp release timer underflow external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) non-maskable software interrupt note 1 : vector addresses contain interrupt jump destination addresses. 2 : reset function in the same way as an interrupt with the highest priority. vector addresses (note 1)
hardware 1-19 3800 group users manual fig. 13 interrupt control fig. 14 structure of interrupt-related registers functional description b7 b0 b7 b0 b7 b0 b7 b0 b7 b0 interrupt edge selection register int 0 active edge selection bit int 1 active edge selection bit int 2 active edge selection bit int 3 active edge selection bit int 4 active edge selection bit int 5 active edge selection bit not used (return ??when read) (intedge : address 003a 16 ) interrupt request register 1 int 0 interrupt request bit int 1 interrupt request bit serial i/o receive interrupt request bit serial i/o transmit interrupt request bit timer x interrupt request bit timer y interrupt request bit timer 1 interrupt request bit timer 2 interrupt request bit interrupt control register 1 int 0 interrupt enable bit int 1 interrupt enable bit serial i/o receive interrupt enable bit serial i/o transmit interrupt enable bit timer x interrupt enable bit timer y interrupt enable bit timer 1 interrupt enable bit timer 2 interrupt enable bit (ireq1 : address 003c 16 ) (icon1 : address 003e 16 ) interrupt request register 2 cntr 0 interrupt request bit cntr 1 interrupt request bit int 2 interrupt request bit int 3 interrupt request bit int 4 interrupt request bit int 5 interrupt request bit not used (return ??when read) (ireq2 : address 003d 16 ) interrupt control register 2 cntr 0 interrupt enable bit cntr 1 interrupt enable bit int 2 interrupt enable bit int 3 interrupt enable bit int 4 interrupt enable bit int 5 interrupt enable bit not used (return ??when read) (do not write ??to this bit) 0 : no interrupt request issued 1 : interrupt request issued 0 : interrupts disabled 1 : interrupts enabled (icon2 : address 003f 16 ) 0 : falling edge active 1 : rising edge active interrupt disable flag (i) interrupt request interrupt request bit interrupt enable bit brk instruction reset
1-20 hardw are 3800 group users manual timer s the 3800 g roup has f our timers: timer x, timer y , timer 1, and timer 2. all timers are count do wn. when the timer reaches 00 16 , an un- derflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is cont inued. when a timer underflows, the interrupt request bit correspon ding to that timer is set to 1. the division ratio of each timer or prescaler is given by 1/ (n + 1), where n is the value in the corresponding timer or prescaler latch. timer 1 and timer 2 the count source of prescaler 12 is the oscillation frequenc y di- vided b y 16. the output of prescaler 12 is counted b y timer 1 and timer 2, and a timer underflow sets the interrupt request bi t. timer x and timer y timer x and timer y can each be selected in one of f our oper ating modes b y setting the timer xy mode register . timer mode the timer counts f(x in )/16 in timer mode. pulse output mode timer x (or timer y) counts f(x in )/16. whene v er the contents of the timer reach 00 16 , the signal output from the cntr 0 (or cntr 1 ) pin is inverted. if the cntr 0 (or cntr 1 ) active edge switch bit is 0, output begins at h. if it is 1, output starts at l. when using a timer in th is mode, set the corresponding port p5 4 ( or port p5 5 ) direction register to out- put mode. event counter mode operation in event counter mode is the same as in timer mode , except the timer counts signals input through the cntr 0 or cntr 1 pin. pulse width measurement mode if the cntr 0 (or cntr 1 ) active edge selection bit is 0, the timer counts at the oscillation frequency divided by 16 while the cntr 0 (or cntr 1 ) pin is at h. if the cntr 0 (or cntr 1 ) active edge switch bit is 1, the count continues during the time that the cntr 0 (or cntr 1 ) pin is at l. in all of these modes, the count can be stopped by setting t he timer x (timer y) count stop bit to 1. ev er y time a timer underflows, the corresponding interrupt request bit is set. fig. 15 structure of timer xy register functional description timer x count stop bit 0: count start 1: count stop timer xy mode register (tm : address 0023 16) timer y operating mode bit 0 0: timer mode 0 1: pulse output mode 1 0: event counter mode 1 1: pulse width measurement mode cntr 1 active edge switch bit 0: interrupt at falling edge count at rising edge in event counter mode 1: interrupt at rising edge count at falling edge in event counter mode b7 cntr 0 active edge switch bit 0: interrupt at falling edge count at rising edge in event counter mode 1: interrupt at rising edge count at falling edge in event counter mode b0 timer x operating mode bit 0 0: timer mode 0 1: pulse output mode 1 0: event counter mode 1 1: pulse width measurement mode b1b0 b5b4 timer y count stop bit 0: count start 1: count stop
hardware 1-21 3800 group users manual fig. 16 block diagram of timer x, timer y, timer 1, and timer 2 functional description timer x latch (8) timer x (8) prescaler x latch (8) prescaler x (8) oscillator divider f(x in ) 1/16 cntr 0 active edge switch bit p5 4 /cntr 0 pin port p5 4 direction register 0 1 event counter mode timer x count stop bit cntr 0 active edge switch bit port p5 4 latch pulse output mode pulse width measurement mode timer mode pulse output mode 1 0 timer x latch write pulse pulse output mode to timer x interrupt request bit to cntr 0 interrupt request bit data bus timer y latch (8) timer y (8) prescaler y latch (8) prescaler y (8) cntr 1 active edge switch bit p5 5 /cntr 1 pin port p5 5 direction register 0 1 event counter mode timer y count stop bit cntr 1 active edge switch bit port p5 5 latch pulse output mode pulse width measurement mode timer mode pulse output mode 1 0 timer y latch write pulse pulse output mode to timer y interrupt request bit to cntr 1 interrupt request bit data bus q q r toggle flip- flop t q q r toggle flip- flop t timer 2 latch (8) timer 1 latch (8) prescaler 12 latch (8) prescaler 12 (8) timer 2 (8) timer 1 (8) data bus to timer 2 interrupt request bit to timer 1 interrupt request bit
1-22 3800 group users manual serial i/o serial i/o can be used as either cloc k synchronous or asynchro- nous (u ar t) ser ial i/o . a dedicated timer is also pro vided f or baud rate generation. cloc k sync hr onous serial i/o mode cloc k synchronous ser ial i/o mode can be selected b y setting the mode selection bit of the ser ial i/o control register to 1. f or cloc k synchronous ser ial i/o , the tr ansmitter and the receiv er must use the same clock. if an internal clock is used, trans fer is star ted b y a wr ite signal to the tb/rb (address 0018 16 ). fig. 17 bloc k dia gram of c loc k sync hr onous serial i/o fig. 18 operation of c loc k sync hr onous serial i/o function functional description 1/4 x in 1/4 f/f p4 6 /s clk1 serial i/o status register serial i/o control register p4 7 /s rdy p4 4 /r x d p4 5 /t x d f(x in ) receive buffer address 0018 16 receive shift register receive buffer full flag (rbf) receive interrupt request (ri) clock control circuit shift clock serial i/o synchronous clock selection bit frequency division ratio 1/(n+1) baud rate generator address 001c 16 brg count source selection bit clock control circuit falling-edge detector transmit buffer data bus address 0018 16 shift clock transmit shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) transmit interrupt source selection bit address 0019 16 data bus address 001a 16 transmit shift register d 7 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 rbf = 1 tsc = 1 tbe = 0 tbe = 1 tsc = 0 transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) serial output txd serial input rxd write pulse to receive/transmit buffer (address 0018 16 ) overrun error (oe) detection notes 1 : the transmit interrupt (ti) can be selected to occur either when the transmit buffer has emptied (tbe=1) or after the transmit shift operation has ended (tsc=1), by setting the t ransmit interrupt source selection bit (tic) of the serial i /o control register. 2 : if data is written to the transmit buffer when tsc=0, the t ransmit clock is generated continuously and serial data is output continuously from the txd pin. 3 : the receive interrupt (ri) is set when the receive buffer f ull flag (rbf) becomes 1 . receive enable signal s rdy hardware
hardware 1-23 3800 group users manual asynchronous serial i/o (uart) mode clock asynchronous serial i/o mode (uart) can be selected by clearing the serial i/o mode selection bit of the serial i/o control register to 0. eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. the transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. since the shift reg- ister cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the re- ceive buffer. the transmit buffer can also hold the next data to be transmitted, and the receive buffer can hold a character while the next charac- ter is being received. fig. 19 block diagram of uart serial i/o functional description f(x in ) 1/4 oe pe fe 1/16 1/16 data bus receive buffer address 0018 16 receive shift register receive buffer full flag (rbf) receive interrupt request (ri) baud rate generator frequency division ratio 1/(n+1) address 001c 16 st/sp/pa generator transmit buffer data bus transmit shift register address 0018 16 transmit shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) address 0019 16 stdetector sp detector uart control register address 001b 16 character length selection bit address 001a 16 brg count source selection bit transmit interrupt source selection bit serial i/o synchronous clock selection bit clock control circuit character length selection bit 7 bits 8 bits serial i/o control register p4 6 /s clk serial i/o status register p4 4 /r x d p4 5 /t x d
1-24 hardware 3800 group users manual fig. 20 operation of uart serial i/o function serial i/o control register (siocon) 001a 16 the serial i/o control register consists of eight control bits for the serial i/o function. uart control register (uartcon) 001b 16 the uart control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial i/o is selected and set the data format of an data transfer. one bit in this register (bit 4) is always valid and sets the output structure of the p4 5 /t x d pin. serial i/o status register (siosts) 0019 16 the read-only serial i/o status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial i/o function and various errors. three of the flags (bits 4 to 6) are valid only in uart mode. the receive buffer full flag (bit 1) is cleared to 0 when the receive buffer is read. if there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer, and the receive buffer full flag is set. a write to the serial i/o status reg- ister clears all the error flags oe, pe, fe, and se (bit 3 to bit 6, re- spectively). writing 0 to the serial i/o enable bit sioe (bit 7 of the serial i/o control register) also clears all the status flags, in- cluding the error flags. all bits of the serial i/o status register are initialized to 0 at reset, but if the transmit enable bit (bit 4) of the serial i/o control register has been set to 1, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become 1. transmit buffer/receive buffer register (tb/ rb) 0018 16 the transmit buffer and the receive buffer are located at the same address. the transmit buffer is write-only and the receive buffer is read-only. if a character bit length is 7 bits, the msb of data stored in the receive buffer is 0. baud rate generator (brg) 001c 16 the baud rate generator determines the baud rate for serial trans- fer. the baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate genera- tor. functional description tsc=0 tbe=1 rbf=0 tbe=0 tbe=0 rbf=1 rbf=1 st d 0 d 1 sp d 0 d 1 st sp tbe=1 tsc=1 st d 0 d 1 sp d 0 d 1 st sp transmit or receive clock transmit buffer write signal generated at 2nd bit in 2-stop-bit mode 1 start bit 7 or 8 data bits 1 or 0 parity bit 1 or 2 stop bit (s) 1: error flag detection occurs at the same time that the rbf flag becomes "1" (at 1st stop bit, during reception). 2: the transmit interrupt (ti) can be selected to occur when either the tbe or tsc flag becomes "1", depending on the setting of the transmit interrupt source selection bit (tic) of the serial i/o control register. 3: the receive interrupt (ri) is set when the rbf flag becomes "1". 4: after data is written to the transmit buffer when tsc=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to tsc=0. notes ] ] serial output t x d serial input r x d receive buffer read signal
hardw are 1-25 3800 group users manual b7 b7 transmit buffer empty flag (tbe) 0: buffer full 1: buffer empty receive buffer full flag (rbf) 0: buffer empty 1: buffer full transmit shift completion flag (tsc) 0: transmit shift in progress 1: transmit shift completed overrun error flag (oe) 0: no error 1: overrun error parity error flag (pe) 0: no error 1: parity error framing error flag (fe) 0: no error 1: framing error summing error flag (se) 0: (oe) u (pe) u (fe)=0 1: (oe) u (pe) u (fe)=1 not used (returns "1" when read) serial i/o status register (siosts : address 0019 16 ) serial i/o control register (siocon : address 001a 16 ) b0 b0 brg count source selection bit (css) 0: f(x in ) 1: f(x in )/4 serial i/o synchronous clock selection bit (scs) 0: brg output divided by 4 when clock synchronous serial i/o is selected, brg output divided by 16 when uart is selected. 1: external clock input when clock synchronous serial i/o is selected, external clock input divided by 16 when uart is selected. s rdy output enable bit (srdy) 0: p4 7 pin operates as ordinaly i/o pin 1: p4 7 pin operates as s rdy output pin transmit interrupt source selection bit (tic) 0: interrupt when transmit buffer has emptied 1: interrupt when transmit shift operation is completed transmit enable bit (te) 0: transmit disabled 1: transmit enabled receive enable bit (re) 0: receive disabled 1: receive enabled serial i/o mode selection bit (siom) 0: clock asynchronous (uart) serial i/o 1: clock synchronous serial i/o serial i/o enable bit (sioe) 0: serial i/o disabled (pins p4 4 to p4 7 operate as ordinary i/o pins) 1: serial i/o enabled (pins p4 4 to p4 7 operate as serial i/o pins) b7 uart control register (uartcon : address 001b 16 ) character length selection bit (chas) 0: 8 bits 1: 7 bits parity enable bit (pare) 0: parity checking disabled 1: parity checking enabled parity selection bit (pars) 0: even parity 1: odd parity stop bit length selection bit (stps) 0: 1 stop bit 1: 2 stop bits p4 5 /t x d p-channel output disable bit (poff) 0: cmos output (in output mode) 1: n-channel open drain output (in output mode) not used (return "1" when read) b0 fig. 21 structure of serial i/o contr ol register s functional description
1-26 hardware 3800 group users manual 3.0v (note 1) 0.6v (note 2) 0v 0v power source voltage reset input voltage v cc reset v ss m51953al 4 5 1 3 0.1 m f 3800 group note 1 : extended operating temperature version : 4.0v note 2 : extended operating temperature version : 0.8v reset circuit to reset the microcomputer, the reset pin should be held at an l level for 2 m s or more. then the reset pin is returned to an h level (the power source voltage should be between 3.0 v and 5.5 v, and between 4.0 v and 5.5 v for extended operating tempera- ture version), reset is released. internal operation does not begin until after 8 to 13 x in clock cycles are completed. after the reset is completed, the program starts from the address contained in ad- dress fffd 16 (high-order byte) and address fffc 16 (low-order byte). make sure that the reset input voltage is less than 0.6 v for v cc of 3.0 v (extended operating temperature version: the reset input voltage is less than 0.8 v for v cc of 4.0 v). fig. 23 internal status of microcomputer after reset fig. 22 example of reset circuit functional description 0 note. 5 : undefined ] : the initial values of cm 1 are determined by the level at the cnv ss pin. the contents of all other registers and ram are undefined after a reset, so they must be initialized by software. register contents (0001 16 ) ? ? ? timer 2 port p0 direction register port p1 direction register port p2 direction register port p3 direction register port p4 direction register port p5 direction register port p6 direction register port p7 direction register serial i/o status register timer xy mode register serial i/o control register uart control register timer 1 (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (0003 16 ) ? ? ? (0005 16 ) ? ? ? (0007 16 ) ? ? ? (0009 16 ) ? ? ? (000b 16 ) ? ? ? (000d 16 ) ? ? ? (000f 16 ) ? ? ? (0019 16 ) ? ? ? (001a 16 ) ? ? ? (001b 16 ) ? ? ? (0020 16 ) ? ? ? (0021 16 ) ? ? ? (0022 16 ) ? ? ? (0023 16 ) ? ? ? (0024 16 ) ? ? ? (0025 16 ) ? ? ? (0026 16 ) ? ? ? (0027 16 ) ? ? ? (003a 16 ) ? ? ? (003b 16 ) ? ? ? (003c 16 ) ? ? ? (003d 16 ) ? ? ? (003e 16 ) ? ? ? address prescaler 12 prescaler x timer x prescaler y timer y interrupt edge selection register cpu mode register interrupt request register 1 interrupt request register 2 interrupt control register 1 interrupt control register 2 processor status register program counter 00 16 00 16 00 16 00 16 000000 0 ] 00 16 ff 16 ff 16 ff 16 ff 16 00 16 ff 16 01 16 ff 16 00 16 00 16 00 16 111000 0 0 0 100 0 0 0 00 16 00 16 00 16 contents of address fffc 16 55555 1 5 5 (ps) (pc h ) (pc l ) contents of address fffd 16 00 16 00 16 00 16 (003f 16 ) ???
hardware 1-27 3800 group users manual fig. 24 timing of reset functional description reset data f address sync x in : 8 to 13 clock cycles x in ? ? ? ? ? fffc fffd ad h , ad l ? ? ? ? ? ad l ad h 1: f(x in ) and f( f ) are in the relationship: f(x in )=2 f( f ). 2: a question mark (?) indicates an undefined status that depends on the previous status. reset address from the vector table notes ? ? reset out (internal reset)
1-28 hardware 3800 group users manual clock generating circuit an oscillation circuit can be formed by connecting a resonator be- tween x in and x out . to supply a clock signal externally, input it to the x in pin and make the x out pin open. oscillation control stop mode if the stp instruction is executed, the internal clock f stops at h. timer 1 is set to 01 16 and prescaler 12 is set to ff 16 . oscillator restarts when an external interrupt is received, but the internal clock f remains at h until timer 1 underflows. this allows time for the clock circuit oscillation to stabilize. if oscillator is restarted by a reset, no wait time is generated, so keep the reset pin at l level until oscillation has stabilized. wait mode if the wit instruction is executed, the internal clock f stops at an h level, but the oscillator itself does not stop. the internal clock restarts if a reset occurs or when an interrupt is received. since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. to ensure that interrupts will be received to release the stp or wit state, interrupt enable bits must be set to 1 before the stp or wit instruction is executed. when the stp status is released, prescaler 12 and timer 1 will start counting and reset will not be released until timer 1 underflows, so set the timer 1 interrupt enable bit to 0 before the stp instruction is executed. fig. 27 block diagram of clock generating circuit fig. 26 external clock input circuit fig. 25 ceramic resonator circuit functional description c out x in x out c in x in x out open external oscillation circuit vss vcc 1/8 x out x in r sq stp instruction wit instruction r s q r s q reset stp instruction timer 1 onw control prescaler 12 1/2 f output internal clock f rd rf onw pin single-chip mode reset interrupt request interrupt disable flag (i) ff 16 01 16 reset or stp instruction
hardw are 1-29 3800 group users manual processor modes single-chip mode, memory expansion mode, and microprocessor mode can be selected by changing the contents of the process or mode bits cm 0 and cm 1 (bits 0 and 1 of address 003b 16 ). in memory expansion mode and microprocessor mode, memory can be expanded externally through ports p0 to p3. in these mode s, ports p0 to p3 lose their i/o port functions and become bus pins. fig. 28 memor y maps in v arious processor modes fig. 29 structure of cpu mode register single-chip mode select this mode by resetting the microcomputer with cnv ss con- nected to v ss . memory expansion mode select this mode by setting the processor mode bits to 01 in soft- ware with cnv ss connected to v ss . this mode enab les e xter nal memory expansion while maintaining the validity of the inter nal rom. internal rom will take precedence over external memory if addresses conflict. microprocessor mode select this mode by resetting the microcomputer with cnv ss con- nected to v cc , or by setting the processor mode bits to 10 in software with cnv ss connected to v ss . in microprocessor mode, the internal rom is no longer valid and external memory must be used. functional description port name port p0 port p1 port p2 port p3 function outputs low-order byte of address. outputs high-order byte of address. operates as i/o pins for data d 7 to d 0 (including instruction codes). p3 0 and p3 1 function only as output pins (except that the port latch cannot be read). p3 2 is the onw input pin. p3 3 is the reset out output pin. (note) p3 4 is the f output pin. p3 5 is the sync output pin. p3 6 is the wr output pin, and p3 7 is the rd output pin. note : if cnv ss is connected to v ss , the microcomputer goes to single-chip mode after a reset, so this pin cannot be used as the reset out output pin. t able 8. functions of por ts in memor y e xpansion mode and microprocessor mode 0000 16 0040 16 0008 16 0000 16 yyyy 16 ffff 16 0008 16 0040 16 ffff 16 internal ram reserved area internal rom memory expansion mode the shaded areas are external memory areas. sfr area : yyyy 16 is the start address of internal rom. sfr area microprocessor mode ] internal ram reserved area 0440 16 ] 0440 16 b0 cpu mode register (cpum : address 003b 16 ) processor mode bits 0 0 : single-chip mode 0 1 : memory expansion mode 1 0 : microprocessor mode 1 1 : not available stack page selection bit 0 : 0 page 1 : 1 page b7 not used (return 0 when read) b1 b0
1-30 hardware 3800 group users manual bus control with memory expansion the 3800 group has a built-in onw function to facilitate access to external memory and i/o devices in memory expansion mode or microprocessor mode. if an l level signal is input to the onw pin when the cpu is in a read or write state, the corresponding read or write cycle is ex- tended by one cycle of f . during this extended period, the rd or wr signal remains at l. this extension period is valid only for writing to and reading from addresses 0000 16 to 0007 16 and 0440 16 to ffff 16 in microprocessor mode, 0040 16 to yyyy 16 in memory expansion mode, and only read and write cycles are ex- tended. fig. 30 onw function timing functional description f read cycle write cycle dummy cycle write cycle read cycle dummy cycle ad 15 to ad 0 period during which onw input signal is received during this period, the onw signal must be fixed at either h or l. at all other times, the input level of the onw signal has no affect on operations. the bus cycles is not extended for an address in the area 0008 16 to 043f 16, regardless of whether the onw signal is received. ] : ] ] ] onw wr rd
hardware 1-31 3800 group users manual notes on programming notes on programming processor status register the contents of the processor status register (ps) after a reset are undefined, except for the interrupt disable flag (i) which is 1. af- ter a reset, initialize flags which affect program execution. in particular, it is essential to initialize the index x mode (t) and the decimal mode (d) flags because of their effect on calculations. interrupts the contents of the interrupt request bits do not change immedi- ately after they have been written. after writing to an interrupt re- quest register, execute at least one instruction before executing a bbc or bbs instruction. decimal calculations to calculate in decimal notation, set the decimal mode flag (d) to 1, then execute an adc or sbc instruction. only the adc and sbc instructions yield proper decimal results. after executing an adc or sbc instruction, execute at least one instruction before executing a sec, clc, or cld instruction. in decimal mode, the values of the negative (n), overflow (v), and zero (z) flags are invalid. the carry flag can be used to indicate whether a carry or borrow has occurred. initialize the carry flag before each calculation. clear the carry flag before an adc and set the flag before an sbc. timers if a value n (between 0 and 255) is written to a timer latch, the fre- quency division ratio is 1/(n + 1). multiplication and division instructions the index x mode (t) and the decimal mode (d) flags do not af- fect the mul and div instruction. the execution of these instructions does not change the contents of the processor status register. ports the contents of the port direction registers cannot be read. the following cannot be used: ? the data transfer instruction (lda, etc.) ? the operation instruction when the index x mode flag (t) is 1 ? the addressing mode which uses the value of a direction regis- ter as an index ? the bit-test instruction (bbc or bbs, etc.) to a direction register ? the read-modify-write instruction (ror, clb, or seb, etc.) to a direction register use instructions such as ldm and sta, etc., to set the port direc- tion registers. serial i/o in clock synchronous serial i/o, if the receive side is using an ex- ternal clock and it is to output the s rdy signal, set the transmit en- able bit, the receive enable bit, and the s rdy output enable bit to 1. serial i/o continues to output the final bit from the t x d pin after transmission is completed. instruction execution time the instruction execution time is obtained by multiplying the fre- quency of the internal clock f by the number of cycles needed to execute an instruction. the number of cycles required to execute an instruction is shown in the list of machine instructions. the frequency of the internal clock f is half of the x in frequency. when the onw function is used in modes other than single-chip mode, the frequency of the internal clock f may be one fourth the x in frequency. memory expansion mode and microproces- sor mode execute the ldm or sta instruction for writing to port p3 (address 0006 16 ) in memory expansion mode and microprocessor mode. set areas which can be read out and write to port p3 (address 0006 16 ) in a memory, using the read-modify-write instruction (seb, clb).
1-32 hardware 3800 group users manual data required for mask orders/rom programming method data required for mask orders the following are necessary when ordering a mask rom produc- tion: 1. mask rom order confirmation form 2. mark specification form 3. data to be written to rom, in eprom form (three identical copies) rom programming method the built-in prom of the blank one time prom version and built- in eprom version can be read or programmed with a general- purpose prom programmer using a special programming adapter. set the address of prom programmer in the user rom area. the prom of the blank one time prom version is not tested or screened in the assembly process and following processes. to en- sure proper operation after programming, the procedure shown in figure 31 is recommended to verify programming. fig. 31 programming and testing of one time prom version table 9. programming adapter package 64p4b, 64s1b 64p6n-a 64d0 name of programming adapter pca4738s-64a pca4738f-64a pca4738l-64a programming with prom programmer screening (caution) (150 c for 40 hours) verification with prom programmer functional check in target device the screening temperature is far higher than the storage temperature. never expose to 150 c exceeding 100 hours. caution :
hardware 1-33 3800 group users manual functional description supplement functional description supplement interrupt 3800 group permits interrupts on the basis of 15 sources. it is vec- tor interrupts with a fixed priority system. accordingly, when two or more interrupt requests occur during the same sampling, the higher-priority interrupt is accepted first. this priority is determined by hardware, but variety of priority processing can be performed by software, using an interrupt enable bit and an interrupt disable flag. for interrupt sources, vector addresses and interrupt priority, refer to table 10. table 10. interrupt sources, vector addresses and interrupt priority note: reset functions in the same way as an interrupt with the highest priority. priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 remarks non-maskable external interrupt (active edge selectable) external interrupt (active edge selectable) valid when serial i/o is selected valid when serial i/o is selected stp release timer underflow external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) non-maskable software interrupt vector addresses fffd 16 fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdd 16 fffc 16 fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffdc 16 high-order low-order interrupt sources reset (note) int 0 interrupt int 1 interrupt serial i/o receive interrupt serial i/o transmit interrupt timer x interrupt timer y interrupt timer 1 interrupt timer 2 interrupt cntr 0 interrupt cntr 1 interrupt int 2 interrupt int 3 interrupt int 4 interrupt int 5 interrupt brk instruction interrupt
1-34 hardware 3800 group users manual functional description supplement timing after interrupt the interrupt processing routine begins with the machine cycle fol- lowing the completion of the instruction that is currently in execu- tion. figure 32 shows a timing chart after an interrupt occurs, and fig- ure 33 shows the time up to execution of the interrupt processing routine. fig. 32 timing chart after an interrupt occurs fig. 33 time up to execution of the interrupt processing routine : cpu operation code fetch cycle : vector address of each interrupt : jump destination address of each interrupt : ?0 16 ?or ?1 16 sync b l , b h a l , a h sps f data bus not used pc h pc l ps a l a h address bus s , sps s-2 , sps s-1, sps pc b l b h a l , a h sync rd wr interrupt processing routine generation of interrupt request main routine 7 to 23 cycles (at performing 8.0 mhz, 1.75 m s to 5.75 m s) 2 cycles 5 cycles start of interrupt processing 0 to 16 cycles waiting time for post-processing of pipeline stack push and vector fetch [ : at execution of div instruction (16 cycles) [
chapter 2 chapter 2 application 2.1 i/o port 2.2 timer 2.3 serial i/o 2.4 processor mode 2.5 reset
2-2 3800 group users manual application 2.1 i/o port 2.1 i/o port 2.1.1 memory map of i/o port fig. 2.1.1 memory map of i/o port related registers 0009 16 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 port p0 (p0) port p0 direction register (p0d) port p1 (p1) port p1 direction register (p1d) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p3 direction register (p3d) port p4 (p4) port p4 direction register (p4d) port p5 (p5) port p5 direction register (p5d) port p6 (p6) port p6 direction register (p6d) port p7 (p7) port p7 direction register (p7d)
application 2.1 i/o port 2-3 3800 group users manual 2.1.2 related registers fig. 2.1.2 structure of port pi (i = 0, 1, 2, 3, 4, 5, 6, 7) port pi b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name port pi 0 port pi 1 port pi 2 port pi 3 port pi 4 port pi 5 port pi 6 port pi 7 in output mode write read l port latch in input mode write : port latch read : value of pins l ? ? ? ? ? ? ? ? port pi (pi) (i = 0, 1, 2, 3, 4, 5, 6, 7) [address : 00 16 , 02 16 , 04 16 , 06 16 , 08 16 , 0a 16 , 0c 16 , 0e 16 ] note : ( note ) port p7 register [address : 0e 16 ] port p7 is a 2-bit port (p7 0 , p7 1 ). accordingly, when bits 2 to 7 are read out, the contents are ?. fig. 2.1.3 structure of port pi direction register (i = 0, 1, 2, 3, 4, 5, 6, 7) port pi direction register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name port pi direction register 0 0 0 0 0 0 0 0 port pi direction register (pid) (i =0, 1, 2, 3, 4, 5, 6, 7) [address : 01 16 , 03 16 , 05 16 , 07 16 , 09 16 , 0b 16 , 0d 16 , 0f 16 ] 0 : port pi 0 input mode 1 : port pi 0 output mode 0 : port pi 1 input mode 1 : port pi 1 output mode 0 : port pi 2 input mode 1 : port pi 2 output mode 0 : port pi 3 input mode 1 : port pi 3 output mode 0 : port pi 4 input mode 1 : port pi 4 output mode 0 : port pi 5 input mode 1 : port pi 5 output mode 0 : port pi 6 input mode 1 : port pi 6 output mode 0 : port pi 7 input mode 1 : port pi 7 output mode 5 5 5 5 5 5 5 5 note : ( note ) port p7 direction register [address : 0f 16 ] port p7 is a 2-bit port (p7 0 , p7 1 ). accordingly, these bits do not have a direction register function. ( note ) ( note ) ( note ) ( note ) ( note )
2-4 3800 group users manual applica tion 2.1 i/o port p3 0 , p3 1 p4, p5, p6, p7 onw reset out f sync x out ? set to the input mode and connect to v cc or v ss through a resistor of 1 k to 10 k . ? set to the output mode and open at l or h. open (only when using external clock). handling 2.1.3 handling of unused pins table 2.1.1 handling of unused pins (in single-chip mode) name of pins/ports p0, p1, p2, p3, p4, p5, p6, p7 x out name of pins/ports handling table 2.1.2 handling of unused pins (in memory expansion mod e and microprocessor mode) open ? set to the input mode and connect to v cc or v ss through a resistor of 1 k to 10 k . ? set to the output mode and open at l or h. connect to v cc through a resistor of 1 k to 10 k . open open open open (only when using external clock).
2-5 3800 group users manual applica tion 2.2 timer 2.2 timer 2.2.1 memory map of timer fig. 2.2.1 memory map of timer related registers 00 3 c 16 00 2 0 16 00 2 1 16 00 2 2 16 00 2 3 16 00 2 4 16 00 2 5 16 00 2 6 16 00 2 7 16 003d 16 003e 16 003f 16 prescaler 12 (pre12) timer 1 (t1) timer 2 (t2) timer xy mode register (tm) prescaler x (prex) timer x (tx) prescaler y (prey) timer y (ty) interrupt request register 1 (ireq1) interrupt request register 2 (ireq2) interrupt control register 1 (icon1) interrupt control register 2 (icon2)
application 2.2 timer 2-6 3800 group users manual 2.2.2 related registers fig. 2.2.2 structure of prescaler 12, prescaler x, prescaler y fig. 2.2.3 structure of timer 1 prescaler 12, prescaler x, prescaler y b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 prescaler 12 (pre12), prescaler x (prex), prescaler y (prey) [address : 20 16 , 24 16 , 26 16 ] the count value of each prescaler is set. the value set in this register is written to both the prescaler and the prescaler latch at the same time. when the prescaler is read out, the value (count value) of the prescaler is read out. l l l b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 1 0 0 0 0 0 0 0 timer 1 (t1) [address : 21 16 ] the count value of the timer 1 is set. the value set in this register is written to both the timer 1 and the timer 1 latch at the same time. when the timer 1 is read out, the value (count value) of the timer 1 is read out. l l l timer 1
2-7 3800 group users manual application 2.2 timer fig. 2.2.4 structure of timer 2, timer x, timer y timer 2, timer x, timer y b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 timer 2 (t2), timer x (tx), timer y (ty) [address : 22 16 , 25 16 , 27 16 ] the count value of each timer is set. the value set in this register is written to both the timer and the timer latch at the same time. when the timer is read out, the value (count value) of the timer is read out. l l l
application 2.2 timer 2-8 3800 group users manual operating mode of timer x/timer y timer mode pulse output mode event counter mode pulse width measurement mode table. 2.2.1 function of cntr 0 /cntr 1 edge switch bit fig. 2.2.5 structure of timer xy mode register function of cntr 0 /cntr 1 edge switch bit (bits 2 and 6) 0 1 0 1 0 1 0 1 ? generation of cntr 0 /cntr 1 interrupt request : falling edge (no effect on timer count) ? generation of cntr 0 /cntr 1 interrupt request : rising edge (no effect on timer count) ? start of pulse output : from h level ? generation of cntr 0 /cntr 1 interrupt request : falling edge ? start of pulse output : from l level ? generation of cntr 0 /cntr 1 interrupt request : rising edge ? timer x/timer y : count of rising edge ? generation of cntr 0 /cntr 1 interrupt request : falling edge ? timer x/timer y : count of falling edge ? generation of cntr 0 /cntr 1 interrupt request : rising edge ? timer x/timer y : measurement of h level width ? generation of cntr 0 /cntr 1 interrupt request : falling edge ? timer x/timer y : measurement of l level width ? generation of cntr 0 /cntr 1 interrupt request : rising edge a a aa aa function timer xy mode register b7 b6 b5 b4 b3 b2 b1 b0 b at reset r w 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 timer xy mode register (tm) name timer x operating mode bit cntr 0 active edge switch bit timer y operating mode bit cntr 1 active edge switch bit 0 0 : timer mode 0 1 : pulse output mode 1 0 : event counter mode 1 1 : pulse width measurement mode 0 0 : timer mode 0 1 : pulse output mode 1 0 : event counter mode 1 1 : pulse width measurement mode it depends on the operating mode of the timer x (refer to table 2.2.1). it depends on the operating mode of the timer y (refer to table 2.2.1). b5 b4 timer x count stop bit [address : 23 16 ] b1 b0 timer y count stop bit 0 : count start 1 : count stop 0 : count start 1 : count stop
2-9 3800 group users manual application 2.2 timer fig. 2.2.7 structure of interrupt request register 2 fig. 2.2.6 structure of interrupt request register 1 interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 0 0 0 0 interrupt request reigster 2 (ireq2) [address : 3d 16 ] name cntr 0 interrupt request bit cntr 1 interrupt request bit int 2 interrupt request bit 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request int 3 interrupt request bit [ [ [ [ 5 6 0 0 : no interrupt request 1 : interrupt request nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are ?. int 5 interrupt request bit [ [ ??is set by software, but not ?. 4 0 0 : no interrupt request 1 : interrupt request int 4 interrupt request bit [ 0 7 0 5 5 interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw interrupt request reigster 1 (ireq1) [address : 3c 16 ] name [ ??is set by software, but not ?. aaaaaa aaaaaa aaaaaa aaaaaa timer y interrupt request bit aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa 4 5 6 7 0 0 0 0 timer x interrupt request bit timer 1 interrupt request bit 0 : no interrupt request 1 : interrupt request aaaaaaa aaaaaaa aaaaaaa aaaaaaa timer 2 interrupt request bit 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request [ [ [ [ [ [ [ [ 0 0 0 0 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request int 0 interrupt request bit int 1 interrupt request bit serial i/o receive interrupt request bit serial i/o transmit interrupt request bit 0 1 2 3
application 2.2 timer 2-10 3800 group users manual fig. 2.2.8 structure of interrupt control register 1 fig. 2.2.9 structure of interrupt control register 2 interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 0 0 0 0 interrupt control reigster 2 (icon2) [address : 3f 16 ] name cntr 0 interrupt enable bit cntr 1 interrupt enable bit int 2 interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled int 3 interrupt enable bit 5 6 0 0 : interrupt disabled 1 : interrupt enabled fix these bits to ?. int 5 interrupt enable bit 4 0 0 : interrupt disabled 1 : interrupt enabled int 4 interrupt enable bit 0 0 0 7 0 aaaaaa aaaaaa timer y interrupt enable bit aaaaaa aaaaaa interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 0 0 0 0 interrupt control register 1 (icon1) [address : 3e 16 ] name int 0 interrupt enable bit int 1 interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa 4 5 6 7 0 0 0 0 timer x interrupt enable bit timer 1 interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled aaaaaaa aaaaaaa aaaaaaa aaaaaaa timer 2 interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled serial i/o transmit interrupt enable bit serial i/o receive interrupt enable bit
2-11 3800 group users manual applica tion 2.2 timer 2.2.3 timer application examples (1) basic functions and uses [function 1] c ont r o l o f e vent i n t e r val ( t i m er x , t i m e r y , ti m e r 1 , ti m e r 2) t h e t i me r c o u n t s t o p b i t i s s e t to 0 a fte r s e tti n g a c o u n t v a l u e to a ti me r. t h e n a ti me r i n te rru p t r eque s t o c c u r s a f t er a c er t ai n per i od. [ u se] ? g ener at i on of an out pu t s i gn al t i m i ng ? g ener at i on of a w a i t i ng t i m e [ funct i o n 2 ] c ont r o l of c ycl i c oper a t i o n ( t i m e r x , t i me r y , t i me r 1 , t i m e r 2 ) the v a l ue of a t i m er l at c h i s au t o m at i c a l l y w r i t t e n t o a c o r r es p ondi ng t i m er ev er y t i m e a t i m er und er f l o w s , a nd eac h c y c l i c t i m er i nt er r u pt r eq ues t oc c ur s . [ u se] ? g ene r at i on o f c y c l i c i nt er r upt s ? c l oc k f un c t i on ( m ea s ur em ent of 2 50m s ec o nd) a ppl i c at i o n ex am pl e 1 ? c ont r ol o f a m ai n r ou t i ne c y c l e [ funct i on 3 ] o u t p ut of r e ct angul ar w ave f o r m ( t i m er x , ti m e r y ) th e o ut p ut l e v e l o f t he c n t r p i n i s i nv er t ed ev er y t i m e a t i m er u nde r f l ow s ( p u l s e ou t put m ode ) . [ u se] ? a pi ez o el ec t r i c buz z er o ut put a ppl i c at i o n ex am pl e 2 ? g ene r at i on o f t he r em ot e- c on t r ol c a r r i er w av ef or m s [ funct i on 4] c ount of e x t e r n a l pul se ( t i m er x , ti m e r y ) e x t er nal pul s es i nput t o t he c n t r pi n ar e s el ec t ed as a t i m er c ount s our c e ( e v ent c ount er m ode ) . [ u se] ? m eas u r e m e nt of f r e quen c y a ppl i c at i o n ex am pl e 3 ? d i v i s i on of e x t er nal pul s es . ? g e n e r a t i o n o f i n t e r r u p t s i n a cycl e b a se d o n a n e xt e r n a l p u l se . ( c ount of a r eel pul s e) [ funct i on 5 ] m easur e m e nt of e x t e r n a l pul se w i d t h ( t i m e r x , ti m e r y ) the h or l l ev el w i dt h of ex t e r na l pu l s es i nput t o c n tr pi n i s m eas ur ed ( p ul s e w i dt h m eas ur em ent m ode ) . [ u se] ? m eas u r e m e nt of ex t e r na l pu l s e f r e quenc y ( m ea s ur em ent of p ul s e w i dt h of fg pu l s e ] gener- ated by motor) application example 4 ? measurement of external pulse duty (when the frequency is fixed) ] fg pulse : pulse used for detecting the motor speed to control the motor speed.
application 2.2 timer 2-12 3800 group users manual (2) timer application example 1 : clock function (measurement of 250 ms) outline : the input clock is divided by a timer so that the clock counts up every 250 ms. specifications : ? the clock f(x in ) = 4.19 mhz (2 22 hz) is divided by a timer. ? the clock is counted at intervals of 250 ms by the timer x interrupt. figure 2.2.10 shows a connection of timers and a setting of division ratios, figures 2.2.11 show a setting of related registers, and figure 2.2.12 shows a control procedure. fig. 2.2.10 connection of timers and setting of division ratios [clock function] timer x interrupt request bit 1/16 0 or 1 1/256 1/256 f(x in ) = 4.19 mhz fixed prescaler x timer x 250 ms 0 : no interrupt request 1 : interrupt request 1/4 the clock is divided by 4 by software. 1 second
application 2.2 timer 2-13 3800 group users manual fig. 2.2.11 setting of related registers [clock function] 255 prex prescaler x (address : 24 16 ) 255 tx timer x (address:25 16 ) set ?ivision ratio ?1 timer x interrupt enable bit : interrupt enabled icon1 interrupt control register 1 (address : 3e 16 ) timer x interrupt request bit (becomes ??every 250 ms) ireq1 interrupt request register 1 (address : 3c 16 ) 0 timer x operating mode bits : timer mode tm timer xy mode register (address : 23 16 ) 0 0 1 timer x count stop bit : count stop set to ??at starting to count. 1 b7 b0 b7 b0 b7 b0 b7 b0 b7 b0
2-14 3800 group users manual applica tion 2.2 timer control procedure : figure 2.2.12 shows a control procedure. fig. 2.2.12 control procedure [clock function] reset initialization sei tm icon1 prex tx tm cli .... .... .... .... (address : 23 16 ) (address : 3e 16 ), bit4 (address : 24 16 ) (address : 25 16 ) (address : 23 16 ), bit3 xxxx 1 x 00 2 1 256 C 1 256 C 1 0 l l l l l l l x : this bit is not used in this application. set it to 0 or 1. its value can be disregarded. timer x interrupt processing routine clt ( note 2 ) cld ( note 3 ) push register to stack rti y n clock stop? clock count up (1/4 second-year) pop registers check if the clock has already been set. count up the clock. pop registers which is pushed to stack main processing prex tx ireq1 .... (address : 24 16 ) (address : 25 16 ) (address : 3c 16 ), bit4 256 C 1 256 C 1 0 [processing for completion of setting clock] ( note 1 ) note 1: this processing is performed only at completing to set the clock. when restarting the clock from zero second after completing to set the clock, re-set timers. l l l l l note 2: when using the index x mode flag (t). note 3: when using the decimal mode flag (d). push the register used in the interrupt processing routine into the stack. timer x : timer mode timer x interrupt : enabled set division ratio C 1 to the prescaler x and timer x. timer x count : operating interrupts : enabled all interrupts : disabled
application 2.2 timer 2-15 3800 group users manual (3) timer application example 2 : piezoelectric buzzer output outline : the rectangular waveform output function of a timer is applied for a piezoelectric buzzer output. specifications : ? the rectangular waveform resulting from dividing clock f(x in ) = 4.19 mhz into about 2 khz (2048 hz) is output from the p5 4 /cntr 0 pin. ? the level of the p5 4 /cntr 0 pin fixes to h while a piezoelectric buzzer output is stopped. figure 2.2.13 shows an example of a peripheral circuit, and figure 2.2.14 shows a connection of the timer and setting of the division ratio. fig. 2.2.13 example of a peripheral circuit fig. 2.2.14 connection of the timer and setting of the division ratio [piezoelectric buzzer output] 244 m s 244 m s 3800 group pipipi.... p5 4 /cntr 0 set a division ratio so that the underflow output cycle of the timer x becomes this value. the ??level is output while a piezoelectric buzzer output is stopped. cntr 0 output 1/16 1/2 f(x in ) = 4.19 mhz fixed timer x fixed 1/64 cntr 0 1 prescaler x
2-16 3800 group users manual applica tion 2.2 timer fig. 2.2.15 setting of related registers [piezoelectric buzz er output] control procedure : figure 2.2.16 shows a control procedure. fig. 2.2.16 control procedure [piezoelectric buzzer output] 0 63 tx timer x (address : 25 16 ) set division ratio C 1 01 0 cntr 0 active edge switch bit : output from the h level timer x count stop bit : count stop set to 0 at starting to count. timer x operating mode bits : pulse output mode tm timer xy mode register (address : 23 16 ) b7 b0 1 b7 b0 prex prescaler x (address : 24 16 ) b7 b0 initialization p5 p5d icon1 tm tx prex .... .... .... 0 xxxx 1001 2 64 C 1 1 C 1 (address : 0a 16 ), bit4 (address : 0b 16 ) (address : 3e 16 ), bit4 (address : 23 16 ) (address : 25 16 ) (address : 24 16 ) a piezoelectric buzzer is requested? reset y n main processing tm (address : 23 16 ), bit3 0 during stopping outputting a piezoelectric buzzer during outputting a piezoelectric buzzer output unit l tm (address : 23 16 ), tx (address : 25 16 ) 64 C1 x : this bit is not used in this application. set it to 0 or 1. its value can be disregarded. l timer x interrupts : disabled the cntr 0 output is stopped at this point (stop outputting a piezoelectric buzzer). set division ratio C 1 to the prescaler x and timer x. l l l the piezoelectric buzzer request occured in the main processing is processed in the output unit. 1 xxx 1 xxxx 2 bit3 1
applica tion 2.2 timer 2-17 3800 group users manual (4) timer application example 3 : measurement of frequency outline : the following two values are compared for judging if the fre quency is within a certain range. ? a value counted a pulse which is input to p5 5 /cntr 1 pin by a timer. ? a referance value specifications : ? the pulse is input to the p5 5 /cntr 1 pin and counted by the timer y. ? a count value is read out at the interval of about 2 ms (t imer 1 interrupt interval : 244 m s 5 8). when the count value is 28 to 40, it is regarded the i nput pulse as a valid. ? because the timer is a down-counter, the count value is comp ared with 227 to 215 ]? . ] 227 to 215 = 255 (initialized value of counter) C 28 to 40 ( the number of valid value). figure 2.2.17 shows a method for judging if input pulse exis ts, and figure 2.2.18 shows a setting of related registers. input pulse 71.4 m s or more (14 khz or less) 71.4 m s (14 khz) 50 m s(20 khz) 50 m s or less (20 khz or more) invalid valid invalid 2 ms 71.4 m s = 28 counts 2 ms 50 m s = 40 counts ? ? ? ? ? ? ? ? ? ? ? ? fig 2.2.17 a method for judging if input pulse exists
2-18 3800 group users manual application 2.2 timer fig. 2.2.18 setting of related registers [measurement of frequency] 0 prey prescaler y (address : 26 16 ) set ?ivision ratio ?1 255 ty timer y (address : 27 16 ) set ?55?to this register immediately before counting pulse. (after a certain time, this value is decreased by the number of input pulses) 1 timer y interrupt enable bit : interrupt disabled icon1 interrupt control register 1 (address : 3e 16 ) 0 judgment of timer y interrupt request bit (when this bit is set to ??at reading out the count value of the timer y (address : 27 16 ), 256 pulses or more are input (at setting 255 to the timer y).) ireq1 interrupt request register 1 (address : 3c 16 ) 1 cntr 1 active edge switch bits : count at falling edge timer y count stop bit : count stop set to ??at starting to count. timer y operating mode bit : event counter mode tm timer xy mode register (address : 23 16 ) b7 b0 0 1 prescaler 12 (address : 20 16 ) b7 b0 63 pre12 7 t1 timer 1 (address : 21 16 ) b7 b0 b7 b0 b7 b0 b7 b0 0 timer 1 interrupt enable bit : interrupt enabled b7 b0 1
applica tion 2.2 timer 2-19 3800 group users manual control procedure : figure 2.2.19 shows a control procedure. fig. 2.2.19 control procedure [measurement of frequency] rti (a) ty (address : 27 16 ) ty ireq1 (address : 27 16 ) (address : 3c 16 ), bit5 256 C 1 0 0 fpulse 0 fpulse 1 processing for a result of judgment 214 (a) 228? < < compare the count value read with the reference value. store the comparison result in flag fpulse. out of range in range l l l l l l pop registers pop registers which is pushed to stack. l read the count value. store the count value in the accumulator (a). initialize the count value. set the timer y interrupt request bit to 0. reset initialization sei tm pre12 t1 prey ty icon1 tm cli .... .... .... (address : 23 16 ) (address : 20 16 ) (address : 21 16 ) (address : 26 16 ) (address : 27 16 ) (address : 3e 16 ), bit6 (address : 23 16 ), bit7 1110 xxxx 2 64C1 8C1 1C1 256C1 1 1 timer 1 interrupt processing routine ireq1 (address : 3c 16 ), bit5? l l l l l l l set the division ratio so that the timer 1 interrupt occurs every 2 ms. timer 1 interrupt : enabled l note 1: when using the index x mode flag (t). note 2: when using the decimal mode flag (d). push the register used in the interrupt processing routine into the stack. l x : this bit is not used in this application. set it to 0 or 1. its value can be disregarded. 0 when the count value is 256 or more, the processing is performed as out of range. timer y : event counter mode (count at falling edge of pulse input from cntr 1 pin) all interrupts : disabled timer y count : start interrupts : enabled clt ( note 1 ) cld ( note 2 ) push register to stack
2-20 3800 group users manual application 2.2 timer (5) timer application example 4 : measurement of pulse width of fg pulse generated by motor outline : the h level width of a pulse input to the p5 4 /cntr 0 pin is counted by timer x. an underflow is detected by timer x interrupt and an end of the input pulse h level is detected by cntr 0 interrupt. specifications : ? the h level width of a fg pulse input to the p5 4 /cntr 0 pin is counted by timer x. (example : when the clock frequency is 4.19 mhz, the count source would be 3.8 m s that is obtained by dividing the clock frequency by 16. measurement can be made up to 250 ms in the range of ffff 16 to 0000 16 .) figure 2.2.20 shows a connection of the timer and a setting of the division ratio, and figure 2.2.21 shows a setting of related registers. fig. 2.2.20 connection of the timer and setting of the division ratio [measurement of pulse width] f(x in ) = 4.19 mhz fixed prescaler x timer x timer x interrupt request bit 250 ms 0 : no interrupt request 1 : interrupt request 1/16 0 or 1 1/256 1/256
application 2.2 timer 2-21 3800 group users manual fig. 2.2.21 setting of related registers [measurement of pulse width] 01 cntr 0 active edge switch bit : count ??level width timer x operating mode bits : pulse width measurement mode timer x count stop bit : count stop set to ??at starting to count. tm timer xy mode register (address : 23 16 ) b7 b0 1 1 255 prex prescaler x (address : 24 16 ) set ?ivision ratio ?1 255 tx timer x (address : 25 16 ) 1 timer x interrupt enable bit : interrupt enabled icon1 interrupt control register 1 (address : 3e 16 ) b7 b0 b7 b0 b7 b0 1 cntr 0 interrupt enable bit : interrupt enabled icon2 interrupt control register 2 (address : 3f 16 ) 0 cntr 0 interrupt request bit (this bit is set to ??at completion of inputting ??level signal.) ireq2 interrupt request register 2 (address : 3d 16 ) b7 b0 b7 b0 timer x interrupt request bit (this bit is set to ??at underflow of timer x.) ireq1 interrupt request register (address : 3c 16 ) 0 b7 b0
2-22 3800 group users manual applica tion 2.2 timer fig. 2.2.22 control procedure [measurement of pulse width] figure 2.2.22 shows a control procedure. initialization all interrupts : disabled l l l l l l sei tm prex tx icon1 ireq1 icon2 ireq2 tm cli .... .... .... (address : 23 16 ) (address : 24 16 ) (address : 25 16 ) (address : 3e 16 ), bit4 (address : 3c 16 ), bit4 (address : 3f 16 ), bit0 (address : 3d 16 ), bit0 (address : 23 16 ), bit3 256C1 256C1 1 0 1 0 0 l x : this bit is not used in this application. set it to 0 or 1. its value can be disregarded. timer x interrupt processing routine processing for error rti error occurs l cntr 0 interrupt processing routine clt ( note 1 ) cld ( note 2 ) push register to stack rti pop registers l l a count value is read out and stored to ram. set the division ratio so that the timer x interrupt occurs every 250 ms. l l (a) result of pulse width measurement lowCorder 8-bit (a) result of pulse width measurement highCorder 8-bit prex (address : 24 16 ) tx (address : 25 16 ) prex inversion of (a) tx 256 C 1 inversion of (a) 256 C 1 push the register used in the interrupt processing routine into the stack. pop registers which is pushed to stack . timer x : pulse width measurement mode interrupts : enabled (count h level width of pulse input from cntr 0 pin.) set the division ratio so that the timer x interrupt occurs every 250 ms. timer x interrupt : enabled cntr 0 interrupt : enabled timer x count : start l note 1: when using the index x mode flag (t). note 2: when using the decimal mode flag (d). xxxx 1011 2 reset
2-23 3800 group users manual applica tion 2.3 serial i/o 2.3 serial i/o 2.3.1 memory map of serial i/o fig. 2.3.1 memory map of serial i/o related registers 0018 16 0019 16 001a 16 001b 16 001c 16 transmit/receive buffer register (tb/rb) serial i/o status register (siosts) serial i/o control register (siocon) uart control register (uartcon) baud rate generator (brg) 003f 16 003a 16 003c 16 003d 16 003e 16 interrupt edge selection register (intedge) interrupt request register 1 (ireq1) interrupt request register 2 (ireq2) interrupt control register 2 (icon2) interrupt control register 1 (icon1)
2-24 3800 group users manual applica tion 2.3 serial i/o 2.3.2 related registers fig. 2.3.2 structure of transmit/receive buffer register fig. 2.3.3 structure of serial i/o status register transmit/receive buffer register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 6 7 transmit/receive buffer register (tb/rb) [address : 18 16 ] a transmission data is written to or a receive data is read out from this buffer register. ? at writing : a data is written to the transmit buffer regi ster. ? at reading : a content of the receive buffer register is r ead out. ? ? ? ? ? 5 ? ? ? note : a content of the transmit buffer register cannot be read out . a data cannot be written to the receive buffer register. b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 1 serial i/o status reigster (siosts) [address : 19 16 ] name transmit buffer empty flag (tbe) 0 : (oe) (pe) (fe) = 0 1 : (oe) (pe) (fe) = 1 overrun error flag (oe) 0 : buffer full 1 : buffer empty nothing is allocated for this bit. it is a write disabled bi t. when this bit is read out, the value is 0. receive buffer full flag (rbf) transmit shift register shift completion flag (tsc) parity error flag (pe) framing error flag (fe) summing error flag (se) 0 : buffer empty 1 : buffer full 0 : transmit shift in progress 1 : transmit shift completed 0 : no error 1 : overrun error 0 : no error 1 : parity error 0 : no error 1 : framing error 5 5 5 5 5 5 5 5 serial i/o status register
2-25 3800 group users manual applica tion 2.3 serial i/o fig. 2.3.4 structure of serial i/o control register fig. 2.3.5 structure of uart control register b7 b6 b5 b4 b3 b2 b1 b0 uart control register (uartcon) [address : 1b 16 ] uart control register 0 0 0 0 0 1 5 character length selection bit (chas) 0 : 8 bits 1 : 7 bits parity enable bit (pare) 0 : parity checking disabled 1 : parity checking enabled stop bit length selection bit (stps) 0 : 1 stop bit 1 : 2 stop bits p4 5 /txd p-channel output disable bit (poff) nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 1. parity selection bit (pars) 0 : even parity 1 : odd parity 1 5 1 5 at reset b name function rw 0 1 2 3 4 5 6 7 in output mode 1 : n-channel open-drain output 0 : cmos output b7 b6 b5 b4 b3 b2 b1 b0 serial i/o control register 0 0 0 0 0 : transmit buffer empty 1 : transmit shift operating completion 0 : f ( x i n ) 1 : f ( x i n ) / 4 serial i/o synchronous clock selection bit (scs) at selecting clock synchronous serial i/o 0 : brg output divided by 4 1 : external clock input at selecting uart 0 : brg output divided by 16 1 : external clock input divided by 16 transmit interrupt source selection bit (tic) s rdy output enable bit (srdy) 0 : i/o port (p47) 1 : s rdy output pin at reset b name function rw 0 1 2 3 0 0 0 : transmit disabled 1 : transmit enabled transmit enable bit (te) receive enable bit (re) 0 : receive disabled 1 : receive enabled 4 5 0 0 serial i/o enable bit (sioe) serial i/o mode selection bit (siom) 0 : uart 1 : clock synchronous serial i/o 0 : serial i/o disabled (p4 4 Cp4 7 : i/o port) 1 : serial i/o enabled (p4 4 Cp4 7 : serial i/o function pin) 6 7 brg count source selection bit (css) serial i/o control register (siocon) [address : 1a 16 ]
2-26 3800 group users manual applica tion 2.3 serial i/o b baud rate generator (brg) [ address : 1c 16 ] b7 b6 b5 b4 b3 b2 b1 b0 baud rate generator ? a count value of baud rate generator is set. ? ? ? ? ? ? ? function at reset w 0 1 2 3 4 5 6 7 r fig. 2.3.6 structure of baud rate generator fig. 2.3.7 structure of interrupt edge selection register interrupt edge selection register (intedge) [address : 3a 16 ] interrupt edge selection register int 0 interrupt edge selection bit 0 : falling edge active 1 : rising edge active 0 int 1 interrupt edge selection bit 0 : falling edge active 1 : rising edge active int 3 interrupt edge selection bit 0 : falling edge active 1 : rising edge active nothing is allocated for these bits. these are write disable d bits. when these bits are read out, the values are 0. 0 int 4 interrupt edge selection bit 0 : falling edge active 1 : rising edge active int 5 interrupt edge selection bit 0 : falling edge active 1 : rising edge active 0 5 0 0 0 0 0 int 2 interrupt edge selection bit 0 : falling edge active 1 : rising edge active at reset b name function rw 0 1 2 3 4 5 6 7 5 b7 b6 b5 b4 b3 b2 b1 b0
2-27 3800 group users manual application 2.3 serial i/o timer x interrupt request bit serial i/o receive interrupt request bit interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 0 0 0 0 interrupt request reigster 1 (ireq1) [address : 3c 16 ] name int 0 interrupt request bit int 1 interrupt request bit 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request serial i/o transmit interrupt request bit [ [ [ [ timer y interrupt request bit 4 5 6 7 0 0 0 0 timer 1 interrupt request bit 0 : no interrupt request 1 : interrupt request timer 2 interrupt request bit 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request [ [ [ [ [ ??is set by software, but not ?. timer x interrupt request bit fig. 2.3.8 structure of interrupt request register 1 fig. 2.3.9 structure of interrupt control register 1 timer y interrupt enable bit interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 0 0 0 0 interrupt control register 1 (icon1) [address : 3e 16 ] name int 0 interrupt enable bit int 1 interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 4 5 6 7 0 0 0 0 timer x interrupt enable bit timer 1 interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled timer 2 interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled serial i/o transmit interrupt enable bit serial i/o receive interrupt enable bit
2-28 3800 group users manual application 2.3 serial i/o 2.3.3 serial i/o connection examples (1) control of peripheral ic equipped with cs pin there are connection examples using a clock synchronous serial i/o mode. figure 2.3.10 shows connection examples of a peripheral ic equipped with the cs pin. fig. 2.3.10 serial i/o connection examples (1) port cs clk in out (4) connecting ics 3800 group peripheral ic 1 peripheral ic 2 port s clk t x d r x d cs clk in out (2) transmission and reception 3800 group peripheral ic (e prom etc.) 2 (3) transmission and reception (pins r x d and t x d are connected) (pins in and out in peripheral ic are connected) cs clk in out 3800 group peripheral ic (e prom etc.) 2 [ 2 ?ort?is an output port controlled by software. note: port s clk t x d cs clk data (1) only transmission (using the r x d pin as an i/o port) 3800 group peripheral ic (osd controller etc.) [ 1 [ 1: select an n-channel open-drain output control of t x d pin. 2: use such out pin of peripheral ic as an n-channel open- drain output in high impedance during receiving data. port s clk t x d r x d s clk t x d r x d port cs clk in out
2-29 3800 group users manual application 2.3 serial i/o (2) connection with microcomputer figure 2.3.11 shows connection examples of the other microcomputers. fig. 2.3.11 serial i/o connection examples (2) (4) using uart s clk t x d r x d clk in out (2) selecting an external clock 3800 group microcomputer (3) using the s rdy siganl output function (selecting an external clock) s rdy s clk t x d r x d rdy clk in out 3800 group microcomputer clk in out (1) selecting an internal clock 3800 group microcomputer r x d t x d s clk t x d r x d r x d t x d 3800 group microcomputer
2-30 3800 group users manual applica tion 2.3 serial i/o 2.3.4 setting of serial i/o transfer data format a clock synchronous or clock asynchronous (uart) is selected as a data format of the serial i/o. figure 2.3.12 shows a setting of serial i/o transfer data fo rmat. fig. 2.3.12 setting of serial i/o transfer data format 1st-8data-1sp st lsb serial i/o uart clock synchronous serial i/o 1st-7data-1sp st lsb 1st-8data-1par-1sp st lsb 1st-7data-1par-1sp st lsb 1st-8data-2sp st lsb 1st-7data-2sp st lsb 1st-8data-1par-2sp st lsb 1st-7data-1par-2sp st lsb msb sp msb sp msb par sp msb par sp msb 2sp msb 2sp msb par 2sp msb par 2sp lsb first st : start bit sp : stop bit par : parity bit
2-31 3800 group users manual application 2.3 serial i/o 2.3.5 serial i/o application examples (1) communication using a clock synchronous serial i/o (transmit/receive) outline : 2-byte data is transmitted and received through the clock synchronous serial i/o. the s rdy signal is used for communication control. figure 2.3.13 shows a connection diagram, and figure 2.3.14 shows a timing chart. fig. 2.3.13 connection diagram [communication using a clock synchronous serial i/o] specifications : ? the serial i/o is used (clock synchronous serial i/o is selected) ? synchronous clock frequency : 125 khz (f(x in ) = 4 mhz is divided by 32) ? the s rdy (receivable signal) is used. ? the receiving side outputs the s rdy signal at intervals of 2 ms (generated by timer), and 2-byte data is transferred from the transmitting side to the receiving side. p4 2 / int 0 s clk1 t x d 3800 group s rdy s clk r x d 3800 group transmitting side receiving side fig. 2.3.14 timing chart [communication using a clock synchronous serial i/o] ??? d 0 d 4 d 2 d 1 d 6 d 5 d 7 d 3 d 0 d 4 d 2 d 1 d 6 d 5 d 7 d 3 d 0 d 1 ??? ??? t x d s clk s rdy 2 ms
2-32 3800 group users manual applica tion 2.3 serial i/o serial i/o status register (address : 19 16 ) siosts baud rate generator (address : 1c 16 ) brg set division ratio C 1 transmit buffer empty flag ? check to be transferred data from the transmit buffer regi ster to transmit shift register. ? writable the next transmission data to the transmit buffer register at being set to 1. transmitting side transmit shift register shift completion flag check a completion of transmitting 1-byte data with this f lag 1 : transmit shift completed serial i/o control register (address : 1a 16 ) siocon brg counter source selection bit : f(x in ) serial i/o synchronous clock selection bit : brg/4 transmit enable bit : transmit enabled receive enable bit : receive disabled serial i/o mode selection bit : clock synchronous serial i/o serial i/o enable bit : serial i/o enabled interrupt edge selection register (address : 3a 16 ) intedge int 0 active edge selection bit : select int 0 falling edge b7 b0 b7 b0 11 0 1 00 b7 b0 7 b7 b0 0 fig. 2.3.15 setting of related registers at a transmitting s ide [communication using a clock synchronous serial i/o]
2-33 3800 group users manual applica tion 2.3 serial i/o fig. 2.3.16 setting of related registers at a receiving side [communication using a clock synchronous serial i/o] b7 b0 receiving side serial i/o control register (address : 1a 16 ) siocon serial i/o synchronous clock selection bit : external clock s rdy output enable bit : use the s rdy output transmit enable bit : transmit enabled set this bit to 1, using s rdy output. receive enable bit : receive enabled serial i/o mode selection bit : clock synchronous serial i/o serial i/o enable bit : serial i/o enabled serial i/o status register (address : 19 16 ) siosts receive buffer full flag check a completion of receiving 1-byte data with this flag. 1 : at completing to receive 0 : at reading out a receive buffer b7 b0 1 111 11
2-34 3800 group users manual applica tion 2.3 serial i/o control procedure : figure 2.3.17 shows a control procedure at a transmitting s ide, and figure 2.3.18 shows a control procedure at a receiving side. fig. 2.3.17 control procedure at a transmitting side [commun ication using a clock synchronous serial i/o] reset initialization siocon brg intedge ..... tb/rb (address : 18 16 ) the first byte of a transmission data write a transmission data the transmit buffer empty flag is set to 0 by this writing. detect int 0 falling edge ireq1 (address : 3c 16 ), bit0 ? 1 0 check to be transfered data from the transmit buffer register to the transmit shift register. (transmit buffer empty flag) siosts (address : 19 16 ), bit0? 1 0 tb/rb (address : 18 16 ) write a transmission data the transmit buffer empty flag is set to 0 by this writing. the second byte of a transmission data check to be transfered data from the transmit buffer register to the transmit shift register. (transmit buffer empty flag) siosts (address : 19 16 ), bit0? 1 0 check a shift completion of the transmit shift register (transmit shift register shift completion flag) siosts (address : 19 16 ), bit2? 1 0 ireq1 (address : 3c 16 ), bit0 0 l x : this bit is not used in this application. set it to 0 or 1. its value can be disregarde d. l l l l l l (address : 1a 16 ) (address : 1c 16 ) (address : 3a 16 ), bit0 8C1 0 1101 xx 00 2
2-35 3800 group users manual applica tion 2.3 serial i/o fig. 2.3.18 control procedure at a receiving side [communica tion using a clock synchronous serial i/o] reset initialization siocon (address : 1a 16 ) 1111 x 11 x 2 ..... tb/rb (address : 18 16 ) dummy data s rdy output s rdy signal is output by writing data to the tb/rb. using the s rdy , the transmit enabled bit (bit4) of the siocon is set to 1. an interval of 2 ms is generated by a timer. pass 2 ms? y n check a completion of receiving (receive buffer full flag) siosts (address : 19 16 ), bit1? 1 0 read out reception data from tb/rb (address : 18 16 ) receive the first byte data. a receive buffer full flag is set to 0 by reading data. check a completion of receiving (receive buffer full flag) siosts (address : 19 16 ), bit1? 1 0 read out reception data from tb/rb (address : 18 16 ) receive the second byte data. a receive buffer full flag is set to 0 by reading data. x : this bit is not used in this application. set it to 0 or 1. its value can be disregarded . l l l l l l l
2-36 3800 group users manual applica tion 2.3 serial i/o (2) output of serial data (control of a peripheral ic) outline : 4-byte data is transmitted and received through the clock sy nchronous serial i/o. the cs signal is output to a peripheral ic through the port p5 3 . fig. 2.3.19 connection diagram [output of serial data] specifications : ? the serial i/o is used. (clock synchronous serial i/o is s elected) ? synchronous clock frequency : 125 khz (f(x in ) = 4 mhz is divided by 32) ? transfer direction : lsb first ? the serial i/o1 interrupt is not used. ? the port p5 3 is connected to the cs pin (l active) of the peripheral ic for a transmission control (the output level of the port p5 3 is controlled by software). figre 2.3.20 shows an output timing chart of serial data. fig. 2.3.20 timing chart [output of serial data] p5 3 s clk t x d cs peripheral ic 3800 group data cs clk clk data cs do 0 do 1 do 2 do 3 clk data
2-37 3800 group users manual application 2.3 serial i/o figure 2.3.21 shows a setting of serial i/o related registers, and figure 2.3.22 shows a setting of serial i/o transmission data. fig. 2.3.22 setting of serial i/o transmission data [output of serial data] fig. 2.3.21 setting of serial i/o related registers [output of serial data] set a transmission data. check that transmission of the previous data is completed before writing data (bit 3 of the interrupt request register 1 is set to ??. tb/rb transmit/receive buffer register (address : 18 16 ) b7 b0 serial i/o synchronous clock selection bit : brg/4 s rdy output enable bit : not use the s rdy signal output function 0 serial i/o transmit interrupt enable bit : interrupt disabled icon1 interrupt control register 1 (address : 3e 16 ) serial i/o transmit interrupt request bit using this bit, check the completion of transmitting 1-byte base data. ??: transmit shift completion ireq1 interrupt request register 1 (address : 3c 16 ) 00 1 siocon serial i/o control register (address : 1a 16 ) 0 0 11 brg count source selection bit : f(x in ) transmit interrupt source selection bit : transmit shift operating completion transmit enable bit : transmit enabled 1 receive enable bit : receive disabled b7 b0 0 b7 b0 b7 b0 serial i/o mode selection bit : clock synchronous serial i/o serial i/o enable bit : serial i/o enabled 0 p4 5 /t x d p-channel output disable bit : cmos output uartcon uart control register (address : 1b 16 ) b7 b0 7 set ?ivision ratio ?1 brg baud rate generator (address : 1c 16 ) b7 b0
2-38 3800 group users manual applica tion 2.3 serial i/o control procedure : when the registers are set as shown in figure 2.3.21, the s erial i/o can transmit 1-byte data simply by writing data to the transmit buffer re gister. thus, after setting the cs signal to l, write the transmis sion data to the receive buffer register on a 1-byte base, and return the cs signal to h when the desired number of bytes have been transmitted. figure 2.3.23 shows a control procedure of serial i/o. fig. 2.3.23 control procedure of serial i/o [output of seria l data] set the serial i/o. set the cs signal output level to l. set the serial i/o transmit interrupt request bit to 0. write a transmission data. (start to transmit 1-byte data) check the completion of transmitting 1- byte data. use any of ram area as a counter for counting the number of transmitted bytes. check that transmission of the target number of bytes has been completed. return the cs signal output level to h when transmission of the target number of bytes is completed. reset p5 (address : 0a 16 ), bit3 0 0 n y 1 ireq1 (address : 3c 16 ), bit3? complete to transmit data? initialization siocon uartcon brg icon1 p5 p5d .... .... (address : 1a 16 ) (address : 1b 16 ), bit4 (address : 1c 16 ) (address : 3e 16 ), bit3 (address : 0a 16 ), bit3 (address : 0b 16 ) p5 (address : 0a 16 ), bit3 1 l l l l l l l l l x : this bit is not used in this application. set it to 0 or 1. its value can be disregarde d. l serial i/o transmit interrupt : disabled set the cs signal output port. (h level output) ireq1 (address : 3c 16 ), bit3 0 tb/rb (address : 18 16 ) a transmission data l 11011000 2 0 8C1 0 1 xxxx 1 xxx 2
application 2.3 serial i/o 2-39 3800 group users manual (3) cyclic transmission or reception of block data (data of a specified number of bytes) between microcomputers [without using an automatic transfer] outline : when a clock synchronous serial i/o is used for communication, synchronization of the clock and the data between the transmitting and receiving sides may be lost because of noise included in the synchronizing clock. thus, it is necessary to be corrected constantly. this heading adjustment is carried out by using the interval between blocks in this example. fig. 2.3.24 connection diagram [cyclic transmission or reception of block data between microcomputers] specifications : ? the serial i/o is used (clock synchronous serial i/o is selected). ? synchronous clock frequency : 131 khz (f(x in ) = 4.19 mhz is divided by 32) ? byte cycle: 488 m s ? number of bytes for transmission or reception : 8 byte/block ? block transfer cycle : 16 ms ? block transfer period : 3.5 ms ? interval between blocks : 12.5 ms ? heading adjustive time : 8 ms limitations of the specifications 1. reading of the reception data and setting of the next transmission data must be completed within the time obtained from byte cycle C time for transferring 1-byte data (in this example, the time taken from generating of the serial i/o receive interrupt request to generating of the next synchronizing clock is 431 m s). 2. heading adjustive time < interval between blocks must be satisfied. s clk master unit s clk slave unit t x d r x d t x d r x d
2.3 serial i/o 2-40 application 3800 group users manual the communication is performed according to the timing shown below. in the slave unit, when a synchronizing clock is not input within a certain time (heading adjustive time), the next clock input is processed as the beginning (heading) of a block. when a clock is input again after one block (8 byte) is received, the clock is ignored. figure 2.3.26 shows a setting of related registers. fig. 2.3.25 timing chart [cyclic transmission or reception of block data between microcomputers] d 0 byte cycle block transfer period block transfer cycle d 1 d 2 d 7 d 0 interval between blocks processing for heading adjustment heading adjustive time fig. 2.3.26 setting of related registers [cyclic transmission or reception of block data between microcomputers] transmit enabled siocon serial i/o control register (address : 1a 6 ) synchronous clock : brg/4 transmit interrupt source : transmit shift operating completion receive enabled clock synchronous serial i/o 0 1 1 110 0 master unit 1 serial i/o enabled brg count source : f(x in ) not use the s rdy output not be effected by external clock transmit enabled siocon serial i/o control register (address : 1a 16 ) not use the serial i/o transmit interrupt receive enabled clock synchronous serial i/o 1 1 1 1 slave unit 1 serial i/o enabled 0 synchronous clock : external clock not use the s rdy output uartcon uart control register (address : 1b 16 ) p4 5 /t x d pin : cmos output 0 both of units b7 b0 7 brg b7 b0 baud rate generator (address : 1c 16 ) set ?ivision ratio ?1 b7 b0 b7 b0
applica tion 2.3 serial i/o 2-41 3800 group users manual control procedure : control in the master unit after a setting of the related registers is completed as sho wn in figure 2.3.33, in the master unit transmission or reception of 1-byte data is started simply b y writing transmission data to the transmit buffer register. to perform the communication in the timing shown in figure 2 .3.25, therefore, take the timing into account and write transmission data. read out the reception data when the serial i/o transmit interrupt request bit is set to 1, or before the next tran smission data is written to the transmit buffer register. a processing example in the master unit using timer interrup ts is shown below. fig. 2.3.27 control in the master unit write a transmission data read a reception data n within a block transfer period? y y complete to transfer a block? n rti write the first transmission data (first byte) in a block count a block interval counter n start a block transfer? y generate a certain block interval by using a timer or other functions. l check the block interval counter and determine to start of a block transfer. l clt ( note 1 ) cld ( note 2 ) push register to stack note 1: when using the index x mode flag (t). note 2: when using the decimal mode flag (d). push the register used in the interrupt processing routine into the stack. l pop registers pop registers which is pushed to stack. l interrupt processing routine executed every 488 m s
2.3 serial i/o 2-42 applica tion 3800 group users manual control in the slave unit after a setting of the related registers is completed as sho wn in figure 2.3.26, the slave unit becomes the state which is received a synchronizing clock at all times, and the serial i/o receive interrupt request bit is set to 1 every time an 8-bit synchronous clock is received . by the serial i/o receive interrupt processing routine, the data to be transmitted next is written to the transmit buffer register after received data is read out. however, if no serial i/o receive interrupt occurs for more than a certain time (head adjustive time), the following processing will be performed. 1. the first 1 byte data of the transmission data in the blo ck is written into the transmit buffer register. 2. the data to be received next is processed as the first 1 byte of the received data in the block. figure 2.3.28 shows the control in the slave unit using a se rial i/o receive interrupt and any timer interrupt (for head adjustive). fig. 2.3.28 control in the slave unit write a transmission data read a reception data n within a block transfer period? y y a received byte counter 3 8? n rti write any data (ff 16 ) a received byte counter +1 heading adjustive counter initialized value ( note 3 ) serial i/o receive interrupt processing routine timer interrupt processing routine heading adjustive counter C 1 n heading adjustive counter = 0? y rti write the first transmission data (first byte) in a block a received byte counter 0 check the received byte counter to judge if a block has been transfered. in this example, set the value which is equal to the heading adjustive time divided by the timer interrupt cycle as the initialized value of the heading adjustive counter. for example: when the heading adjustive time is 8 ms and the timer interrupt cycle is 1 m s, set 8 as the initialized value. 3: l clt ( note 1 ) cld ( note 2 ) push register to stack push the register used in the interrupt processing routine into the stack. l clt ( note 1 ) cld ( note 2 ) push register to stack push the register used in the interrupt processing routine into the stack. l pop registers pop registers which is pushed to stack. l pop registers pop registers which is pushed to stack. l notes 1: when using the index x mode flag (t). 2: when using the decimal mode flag (d).
applica tion 2.3 serial i/o 2-43 3800 group user? manual (4) communication (transmit/receive) using an asynchronous s erial i/o (uart) point : 2-byte data is transmitted and received through an asynchron ous serial i/o. the port p4 0 is used for communication control. figure 2.3.29 shows a connection diagram, and figure 2.3.30 shows a timing chart. fig. 2.3.29 connection diagram [communication using uart] specifications : ?the serial i/o is used (uart is selected). ?transfer bit rate : 9600 bps (f(x in ) = 4.9152 mhz is divided by 512) ?communication control using port p4 0 (the output level of the port p4 0 is controlled by softoware.) ?2-byte data is transferred from the transmitting side to t he receiving side at inter- vals of 10 ms (generated by timer). fig. 2.3.30 timing chart [communication using uart] transmitting side p4 0 3800 group p4 0 3800 group receiving side t x d x d p4 0 t x d 10 ms d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st sp(2) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st sp(2) d 0 st r
2.3 serial i/o 2-44 application 3800 group users manual table 2.3.1 shows setting examples of baud rate generator (brg) values and transfer bit rate values, figure 2.3.31 shows a setting of related registers at a transmitting side, and figure 2.3.32 shows a setting of related registers at a receiving side. table 2.3.1 setting examples of baud rate generator values and transfer bit rate values brg setting value actual time (bps) brg setting value at f(x in ) = 4.9152 mh z 600 1200 2400 4800 9600 19200 38400 76800 31250 62500 600.96 1201.92 2403.85 4807.69 9615.38 20833.33 41666.67 83333.33 31250.00 62500.00 207(cf 16 ) 103(67 16 ) 51(33 16 ) 25(19 16 ) 12(0c 16 ) 5(05 16 ) 2(02 16 ) 5(05 16 ) 15(0f 16 ) 7(07 16 ) 600.00 1200.00 2400.00 4800.00 9600.00 19200.00 38400.00 76800.00 191(bf 16 ) 95(5f 16 ) 47(2f 16 ) 23(17 16 ) 11(0b 16 ) 5(05 16 ) 2(02 16 ) 5(05 16 ) 600.00 1200.00 2400.00 4800.00 9600.00 19200.00 38400.00 76800.00 127(7f 16 ) 63(3f 16 ) 31(1f 16 ) 15(0f 16 ) 7(07 16 ) 3(03 16 ) 1(01 16 ) 3(03 16 ) at f(x in ) = 8 mh z at f(x in ) = 7.3728 mh z transfer bit rate (bps) (note 1) brg count source (note 2) actual time (bps) actual time (bps) brg setting value f(x in )/4 f(x in )/4 f(x in )/4 f(x in )/4 f(x in )/4 f(x in )/4 f(x in )/4 f(x in ) f(x in ) f(x in ) transfer bit rate (bps) = (brg setting value + 1) 5 16 5 m f(x in ) notes 1: equation of transfer bit rate m: when bit 0 of the serial i/o control register (address : 1a 16 ) is set to 0, a value of m is 1. when bit 0 of the serial i/o control register (address : 1a 16 ) is set to 1, a value of m is 4. 2: a brg count source is selected by bit 0 of the serial i/o control register (address : 1a 16 ).
applica tion 2.3 serial i/o 2-45 3800 group users manual fig. 2.3.31 setting of related registers at a transmitting s ide [communication using uart] b7 b0 00 0 b7 b0 b7 b0 serial i/o status register (address : 19 16 ) siosts transmitting side baud rate generator (address : 1c 16 ) brg siocon brg count source selection bit : f(x in )/4 serial i/o synchronous clock selection bit : brg/16 transmit enable bit : transmit enabled receive enable bit : receive disabled serial i/o mode selection bit : asynchronous serial i/o(uart ) serial i/o enable bit : serial i/o enabled s rdy output enable bit : not use s rdy out uart control register (address : 1b 16 ) uartcon character length selection bit : 8 bits parity enable bit : parity checking disabled p4 5 /t x d p-channel output disable bit : cmos output stop bit length selection bit : 2 stop bits f(x in ) transfer bit rate 5 16 5 m C 1 transmit buffer empty flag ? check to be transferred data from the transmit buffer register to the transmit shift register. ? writable the next transmission data to the transmit buffer register at being set to 1. transmit shift register shift completion flag check a completion of transmitting 1-byte data with this fla g. 1 : transmit shift completed serial i/o control register (address : 1a 16 ) set when bit 0 of the serial i/o control register (address : 1a 16 ) is set to 0, a value of m is 1. when bit 0 of the serial i/o control register (address : 1a 16 ) is set to 1, a value of m is 4. [ [ 10 0 1 0 0 1 1 b7 b0 7
2.3 serial i/o 2-46 applica tion 3800 group users manual fig. 2.3.32 setting of related registers at a receiving side [communication using uart] b7 b0 b7 b0 b7 b0 siosts b7 b0 receive buffer full flag receiving side serial i/o status register (address : 19 16 ) brg 7 serial i/o control register (address : 1a 16 ) siocon uartcon check a completion of receiving 1-byte data with this flag. 1 : at completing to receive 0 : at reading out a content of the receive buffer registe r overrun error flag 1 : when data are ready to be transferred to the receive shift register in the state of storing data into the receive buffer register. parity error flag 1 : when parity error occurs at enabled parity. framing error flag 1 : when data can not be received at the timing of setting a stop bit. summing error flag 1 : when even one of the following errors occurs. ? overrun error ? parity error ? framing error brg count source selection bit : f(x in )/4 serial i/o synchronous clock selection bit : brg/16 transmit enable bit : transmit disabled receive enable bit : receive enabled serial i/o mode selection bit : asynchronous serial i/o(uart ) serial i/o enable bit : serial i/o enabled s rdy output enable bit : not use s rdy out uart control register (address : 1b 16 ) character length selection bit : 8 bits parity enable bit : parity checking disabled stop bit length selection bit : 2 stop bits baud rate generator (address : 1c 16 ) f(x in ) transfer bit rate 5 16 5 m C 1 set when bit 0 of the serial i/o control register (address : 1a 16 ) is set to 0, a value of m is 1. when bit 0 of the serial i/o control register (address : 1a 16 ) is set to 1, a value of m is 4. [ [ 10 10 0 0 1 00 1
applica tion 2.3 serial i/o 2-47 3800 group users manual control procedure : figure 2.3.33 shows a control procedure at a transmitting s ide, and figure 2.3.34 shows a control procedure at a receiving side. reset end of communication (address : 1a 16 ) (address : 1b 16 ) (address : 1c 16 ) (address : 08 16 ), bit0 (address : 09 16 ) p4 (address : 08 16 ), bit0 1 y n tb/rb (( address : 18 16 ) the second byte of a transmission data siosts (address : 19 16 ), bit0? 1 0 siosts (address : 19 16 ), bit2? 1 0 initialization siocon uartcon brg p4 p4d 8C1 .... tb/rb ( address : 18 16 ) the first byte of a transmission data p4 (address : 08 16 ), bit0 0 1 0 x : this bit is not used in this application. set it to 0 or 1. its value can be disregarde d. set port p4 0 for a communication control. an interval of 10 ms is generated by a timer. start of communication. write a transmission data the transmit buffer empty flag is set to 0 by this writing. write a transmission data the transmit buffer empty flag is set to 0 by this writing. check to be transferred data from the transmit buffer register to the transmit shift register. (transmit buffer empty flag) check to be transferred data from the transmit buffer register to the transmit shift register. (transmit buffer empty flag) check a shift completion of the transmit shift register. (transmit shift register shift completion flag) siosts (address : 19 16 ), bit0? 0 xxxxxxx 1 2 l l l l l l l l l l pass 10 ms? 1001 x 001 2 00001000 2 fig. 2.3.33 control procedure at a transmitting side [commun ication using uart]
2.3 serial i/o 2-48 applica tion 3800 group users manual fig. 2.3.34 control procedure at a receiving side [communica tion using uart] reset (address : 1a 16 ) (address : 1b 16 ) (address : 1c 16 ) (address : 09 16 ) check a completion of receiving. (receive buffer full flag) siosts (address : 19 16 ), bit1? 1 0 read out a reception data from rb (address : 18 16 ) siosts (address : 19 16 ), bit6? 0 1 initialization siocon uartcon brg p4d 1010 x 001 2 00001000 2 8 1 xxxxxxx 0 2 .... siosts (address : 19 16 ), bit1? 1 0 check an error falag. siosts (address : 19 16 ), bit6? 0 1 p4 (address : 08 16 ), bit0? 0 1 siocon (address : 1a 16 ) siocon (address : 1a 16 ) 0000 x 001 2 1010 x 001 2 read out a reception data from rb (address : 18 16 ) receive the first 1 byte data a receive buffer full flag is set to 0 by reading data. check a completion of receiving. (receive buffer full flag) receive the second byte data a receive buffer full flag is set to 0 by reading data. check an error flag. ? countermeasure for a bit slippage x : this bit is not used in this application. set it to 0 or 1. its value can be disregarde d. l l l l l l l processing for error
applica tion 2.4 processor mode 2-49 3800 group users manual 2.4 processor mode 2.4.1 memory map of processor mode fig. 2.4.1 memory map of processor mode related register 2.4.2 related register fig. 2.4.2 structure of cpu mode register 003b 16 cpu mode register (cpum) 5 5 5 5 3 2 0 1 cpu mode register (cpum) [adress : 3b 16 ] nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 0. 0 0 0 0 0 cpu mode register processor mode bits 00 : single-chip mode 01 : memory expansion mode 10 : microprocessor mode 11 : not available stack page selection bit 0 : 0 page 1 : 1 page 0 0 5 5 [ an initial value of bit 1 is determined by a level of the c nv ss pin. [ at reset b name function rw 4 5 6 7 b7 b6 b5 b4 b3 b2 b1 b0
applica tion 2.4 processor mode 2-50 3800 group users manual 2.4.3 processor mode application examples (1) application example of memory expansion in the case wher e the onw (one-wait) function is not used outline : the external memory is accessed in the microprocessor mode. at f(x in ) = 8 mhz, an available ram is given by the following : ? oe access time : ta (oe) 50 ns ? setup time for writing data : tsu (d) 65 ns for example, the m5m5256bp-10 whose address access is 100 ns is available. figure 2.4.3 shows an expansion example of a 32k byte rom an d a 32k byte ram. fig. 2.4.3 expansion example of rom and ram 3800 group cnv ss onw ad 15 8 8 8 ad 14 ad 0 db 0 db 7 rd wr m5m27c256ak-10 m5m5256bp-10 ce a 0 Ca 14 d 0 Cd 7 oe a 0 Ca 14 dq 1 Cdq 8 oe w 8mhz v cc = 5.0v 10 % 0000 16 8000 16 0440 16 0040 16 0008 16 ffff 16 external ram area (m5m5256bp) sfr area internal ram area external ram area (m5m5256bp) external rom area (m5m27c256ak) memory map 74f04 s C C 15 8 2 , p3 1 eprom sram 2 p3 0 p4 p5 p6 p7
applica tion 2.4 processor mode 2-51 3800 group users manual figure 2.4.4, figure 2.4.5 and figure 2.4.6 show a standard timing at 8 mhz (no-wait). fig. 2.4.4 read-cycle (oe access, sram) fig. 2.4.5 read-cycle (oe access, eprom) output enabled access time of m5m5256bp data bus setup time before rd of 3800 td(ahrd) rd pulse width of 3800 rd delay time after outputting address of 3800 50 ns (max) 65 ns (min) address (low-order) a 0 Ca 7 (port p0) address (high-order) a 8 Ca 14 (port p1) dq 1 Cdq 8 (port p2) s (a15) wr h level 125 ns - 10 ns (min) 125 ns - 35 ns (min) oe (rd of 3800) td(ahrd) t wl (rd) ta(oe) tsu(dbrd) : : t wl (rd) : ta(oe) : tsu(dbrd) rd delay time after outputting address of 3800 output enabled access time of m5m27c256ak data bus setup time before rd of 3800 50 ns (max) 65 ns (min) address (low-order) a 0C a 7 (port p0) address (high-order) a 8C a 14 (port p1) d 0C d 7 (port p2) wr h level ce 5.8 ns (max) t phl 125 ns - 10ns (min) 125 ns - 35 ns (min) oe (rd of 3800) td(ahrd) t wl (rd) ta(oe) tsu(db rd) rd pulse width of 3800 ta(oe) td(ah rd) t wl (rd) tsu(db rd) t phl : : : : : output delay time of 74f04 data data
applica tion 2.4 processor mode 2-52 3800 group users manual fig. 2.4.6 write-cycle (w control, sram) td(ah wr) w (wr of 3800) 65 ns (max) 35 ns (min) address (low-order) address (high-order) data dq 1 Cdq 8 (port p2) s (a15) oe (rd of 3800) h level 125 ns - 10 ns (min) 125 ns - 35 ns (min) td(ah wr) t wl (wr) td(wr db) tsu(d) : wr delay time after outputting address of 3800 : wr pulse width of 3800 t wl (wr) : data bus delay time after wr of 3800 td(wr db) : data setup time of m5m5256bp tsu(d) a 0 Ca 7 (port p0) a 8 Ca 14 (port p1)
applica tion 2.4 processor mode 2-53 3800 group users manual (2) application example of memory expansion in the case wher e the onw (one-wait) function is used outline : onw function is used when the external memory access is slow. if l level signal is input to the p3 2 / onw pin while the cpu is in the read or write status, the read or write cycle corresponding to 1 cycle of f is extended. in the extended period, the rd or wr signal is kept at the l level. the onw function operates only when data is read from or written into addresses 0000 16 to 0007 16 and addresses 0440 16 to ffff 16 . figure 2.4.7 shows an application example of the onw function. ____ fig. 2.4.7 application example of the onw function 3800 group cnv ss ad 15 8 p5 8 p6 onw ad 14 ad 0 db 0 db 7 rd wr m5m27c256ak-10 m5m5256bp-10 ce a 0 C a 14 d 0 C d 7 oe a 0 C a 14 dq 1 C dq 8 oe w 8mhz v cc = 5.0v 10 % external ram area (m5m5256bp) sfr area internal ram area external ram area (m5m5256bp) external rom area (m5m27c256ak) 0000 16 8000 16 0440 16 0040 16 0008 16 ffff 16 memory map 74f04 s C 15 8 8 p4 2 p3 0 , p3 1 eprom sram C 2 p7
application 2-54 2.5 reset 3800 group users manual 2.5 reset 2.5.1 connection example of reset ic figure 2.5.2 shows the system example which switch to the ram backup mode by detecting a drop of the system power source voltage with the int interrupt. fig. 2.5.1 example of poweron reset circuit fig. 2.5.2 ram back-up system system power source voltage +5 m62009l, m62009p, m62009fp 7 5 4 91 35 3 6 2 1 v cc 1 reset int gnd cd v1 v cc 2 3800 group v cc int reset + 40 v ss m62022l 3800 group reset 1 5 3 91 35 40 0.1 m f power source gnd delay capacity 4 output v ss v cc
chapter 3 chapter 3 appendix 3.1 electrical characteristics 3.2 standard characteristics 3.3 notes on use 3.4 countermeasures against noise 3.5 list of registers 3.6 mask rom ordering method 3.7 mark specification form 3.8 package outline 3.9 list of instruction codes 3.10 machine instructions 3.11 sfr memory map 3.12 pin configuration
3800 group users manual appendix 3.1 electrical characteristics 3-2 3.1 e lectrical c haracteristics 3.1.1 absolute maxim um ratings p o w er source v oltage input v oltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 input v oltage reset , x in input v oltage cnv ss output v oltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 , x out p o w er dissipation oper ating temper ature stor age temper ature v cc v i v i v i v o p d t opr t stg symbol p ar ameter conditions ratings C0.3 to 7.0 C 0.3 to v cc +0.3 C0.3 to v cc +0.3 C0.3 to 13 C0.3 to v cc +0.3 1000(note) C20 to 85 C40 to 125 v v v v v mw c c unit t a = 25 c all v oltages are based on v ss . output tr ansistors are cut off . t able 3.1.1 absolute maxim um ratings note : 300 mw in case of the flat package . t able 3.1.2 recommended operating conditions (v cc = 3.0 to 5.5 v , t a = C20 to 85 c , unless otherwise noted) 3.1.2 recommended operating conditions note 1: the minimum power source voltage is [v] (f(x in ) = xmhz) on the condition of 2 mhz < f(x in ) < 8 mhz. 2: the total output current is the sum of all the currents flo wing through all the applicab le por ts . the total a v er age current is an a v er- age v alue measured ov er 100 ms . the total peak current is the peak value of all the currents . 3: the peak output current is the peak current flowing in each port. 4: the average output current i ol(avg) , i oh(avg) in an average value measured over 100 ms. 5.5 5.5 v cc v cc 0.2 v cc 0.2 v cc 0.16 v cc C80 C80 80 80 C40 C40 40 40 C10 10 C5 5 8 6 v cc C16 p o w er source voltage (note 1) (f(x in ) 2 mhz) (f(x in ) = 8 mhz) p o w er source voltage h input v oltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 h input v oltage reset , x in , cnv ss l input v oltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 l input v oltage reset , cnv ss l input v oltage x in h total peak output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 (note 2) h total peak output current p4 0 Cp4 7 ,p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note 2) l total peak output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 (note 2) l total peak output current p4 0 Cp4 7 ,p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note 2) h total a v er age output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 (note 2) h total a v er age output current p4 0 Cp4 7 ,p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note 2) l total a v er age output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 (note 2) l total a v er age output current p4 0 Cp4 7 ,p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note 2) h peak output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note 3) l peak output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note 3) h a v er age output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note 4) l a v er age output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note 4) inter nal cloc k oscillation frequency (4.0 v vcc 5.5 v) inter nal cloc k oscillation frequency (3.0 v vcc 4.0 v) v cc v ss v ih v ih v il v il v il s i oh(peak) s i oh(peak) s i ol(peak) s i ol(peak) s i oh(a vg) s i oh(avg) s i ol(avg) s i ol(avg) i oh(peak) i ol(peak) i oh(avg) i ol(avg) f(x in ) symbol parameter limits min. v v v v v v v ma ma ma ma ma ma ma ma ma ma ma ma mhz unit 3.0 4.0 0.8 v cc 0.8 v cc 0 0 0 5.0 5.0 0 t y p . max. x+ 1 6 6
3-3 3800 group users manual appendix 3.1 electrical characteristics 2.0 1.0 5.0 5.0 C5.0 5.5 13 8 2.0 1 10 h output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note) l output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 ,p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 hysteresis cntr 0 , cntr 1 , int 0 Cint 5 hysteresis r x d, s clk hysteresis reset h input current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 h input current reset, cnv ss h input current x in l input current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 reset, cnv ss l input current x in ram hold voltage symbol parameter limits min. v unit table 3.1.3 electrical characteristics (v cc = 3.0 to 5.5 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) 3.1.3 electrical characteristics v cc C2.0 v cc C1.0 0.4 0.5 0.5 4 C4 6.4 4 0.8 1.5 1 0.2 0.1 typ. max. i oh = C10 ma v cc = 4.0 to 5.5 v i oh = C1.0 ma v cc = 3.0 to 5.5 v i ol = 10 ma v cc = 4.0 to 5.5 v i ol = 1.0 ma v cc = 3.0 to 5.5 v v i = v cc v i = v cc v i = v cc v i = v ss v i = v ss when clock stopped f(x in ) = 8 mhz, v cc = 5 v f(x in ) = 5 mhz, v cc = 5 v f(x in ) = 2 mhz, v cc = 3 v when wit instruction is executed with f(x in ) = 8 mhz, v cc = 5 v when wit instruction is executed with f(x in ) = 5 mhz, v cc = 5 v when wit instruction is executed with f(x in ) = 2 mhz, v cc = 3 v test conditions v t+ C v tC v t+ C v tC v t+ C v tC i ih i ih i ih i il i il v ram i cc v oh v ol v v v v m a m a m a m a m a v when stp instruction is executed with clock stopped, output transistors isolated. note : p4 5 is measured when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0. t a = 25 c t a = 85 c 2.0 power source current ma m a
3800 group users manual appendix 3.1 electrical characteristics 3-4 note: when bit 6 of address 001a 16 is 1. divide this value by four when bit 6 of address 001a 16 is 0. reset input l pulse width external clock input cycle time external clock input h pulse width external clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 to int 5 input h pulse width int 0 to int 5 input l pulse width serial i/o clock input cycle time (note) serial i/o clock input h pulse width (note) serial i/o clock input l pulse width (note) serial i/o input set up time serial i/o input hold time t w(reset) t c(x in ) t wh(x in ) t wl(x in ) t c(cntr) t wh(cntr) t wl(cntr) t wh(int) t wl(int) t c(s clk ) t wh(s clk ) t wl(s clk ) t su(r x dCs clk ) t h(s clk Cr x d) symbol parameter limits min. m s ns ns ns ns ns ns ns ns ns ns ns ns ns unit table 3.1.4 timing requirements (1) (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) 3.1.4 timing requirements and switching characteristics 2 125 50 50 200 80 80 80 80 800 370 370 220 100 typ. max. reset input l pulse width external clock input cycle time external clock input h pulse width external clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 to int 5 input h pulse width int 0 to int 5 input l pulse width serial i/o clock input cycle time (note) serial i/o clock input h pulse width (note) serial i/o clock input l pulse width (note) serial i/o input set up time serial i/o input hold time symbol parameter limits min. m s ns ns ns ns ns ns ns ns ns ns ns ns ns unit table 3.1.5 timing requirements (2) (v cc = 3.0 to 4.0 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) 2 500/ (3 v cc C8) 200/ (3 v cc C8) 200/ (3 v cc C8) 500 230 230 230 230 2000 950 950 400 200 typ. max. note: when bit 6 of address 001a 16 is 1 (clock synchronous mode). divide this value by four when bit 6 of address 001a 16 is 0 (uart mode). t w(reset) t c(x in ) t wh(x in ) t wl(x in ) t c(cntr) t wh(cntr) t wl(cntr) t wh(int) t wl(int) t c(s clk ) t wh(s clk ) t wl(s clk ) t su(r x dCs clk ) t h(s clk Cr x d)
3-5 3800 group users manual appendix 3.1 electrical characteristics serial i/o clock output h pulse width serial i/o clock output l pulse width serial i/o output delay time (note 1) serial i/o output valid time (note 1) serial i/o clock output rising time serial i/o clock output falling time cmos output rising time (note 2) cmos output falling time (note 2) 140 30 30 30 30 symbol parameter limits min. ns ns ns ns ns ns ns ns unit table 3.1.6 switching characteristics (1) (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) t c(s clk ) /2C30 t c(s clk ) /2C30 C30 10 10 typ. max. t wh(s clk ) t wl(s clk ) t d(s clk Ct x d) t v(s clk Ct x d) t r(s clk ) t f(s clk ) t r(cmos) t f(cmos) test conditions fig. 3.1.1 note1: when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0. 2: x out pin is excluded. serial i/o clock output h pulse width serial i/o clock output l pulse width serial i/o output delay time (note 1) serial i/o output valid time (note 1) serial i/o clock output rising time serial i/o clock output falling time cmos output rising time (note 2) cmos output falling time (note 2) 350 50 50 50 50 symbol parameter limits min. ns ns ns ns ns ns ns ns unit table 3.1.7 switching characteristics (2) (v cc = 3.0 to 4.0 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) t c(s clk ) /2C50 t c(s clk ) /2C50 C30 20 20 typ. max. t wh(s clk ) t wl(s clk ) t d(s clk Ct x d) t v(s clk Ct x d) t r(s clk ) t f(s clk ) t r(cmos) t f(cmos) test conditions fig. 3.1.1 note1: when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0. 2: x out pin is excluded.
3800 group users manual appendix 3.1 electrical characteristics 3-6 bef ore f onw input set up time after f onw input hold time bef ore f data bus set up time after f data bus hold time bef ore rd onw input set up time bef ore wr onw input set up time after rd onw input hold time after wr onw input hold time bef ore rd data b us set up time after rd data b us hold time t su(onwC f ) t h( f Conw) t su(dbC f ) t h( f Cdb) t su (onwCrd) t su (onwCwr) t h(rdConw) t h(wrConw) t su(dbCrd) t h(rdCdb) symbol parameter limits min. ns ns ns ns ns ns ns ns unit C20 C20 60 0 C20 C20 65 0 t y p . max. 40 45 20 10 70 65 200 200 symbol p ar ameter limits min. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns unit t c(x in ) C10 t c(x in ) C10 6 6 3 15 t c(x in ) C10 3t c(x in ) C10 t c(x in ) C35 t c(x in ) C40 0 0 10 0 2t c(x in ) 20 10 25 10 20 10 10 5 20 t c(x in ) C15 t c(x in ) C20 5 5 15 t y p . max. t c( f ) t wh( f ) t wl( f ) t d( f Cah) t v( f Cah) t d( f Cal) t v( f Cal) t d( f Csync) t v( f Csync) t d( f Cwr) t v( f Cwr) t d( f Cdb) t v( f Cdb) t wl(rd) t wl(wr) t d(ahCrd) t d(ahCwr) t d(alCrd) t d(alCwr) t v(rdCah) t v(wrCah) t v(rdCal) t v(wrCal) t d(wrCdb) t v(wrCdb) t d (resetCreset out ) t v( f Creset) t est conditions note : the reset out goes h in sync with the f all of the f cloc k that is an ywhere betw een about 8 cycle and 13 cycles after the reset input goes h. fig. 3.1.1 t able 3.1.8 timing requirements in memor y e xpansion mode and micropr ocessor mode (1) (v cc = 4.0 to 5.5 v , v ss = 0 v , t a = C20 to 85 c , unless otherwise noted) t able 3.1.9 switc hing c haracteristics in memor y e xpansion mode and micropr ocessor mode (1) (v cc = 4.0 to 5.5 v , v ss = 0 v , t a = C20 to 85 c , unless otherwise noted) f clock cycle time f cloc k h pulse width f cloc k l pulse width after f ad 15 Cad 8 dela y time after f ad 15 Cad 8 v alid time after f ad 7 Cad 0 dela y time after f ad 7 Cad 0 v alid time sync dela y time sync v alid time rd and wr dela y time rd and wr v alid time after f data bus dela y time after f data bus valid time rd pulse width, wr pulse width rd pulse width, wr pulse width (when one-w ait is v alid) after ad 15 Cad 8 rd dela y time after ad 15 Cad 8 wr dela y time after ad 7 Cad 0 rd dela y time after ad 7 Cad 0 wr dela y time after rd ad 15 Cad 8 v alid time after wr ad 15 Cad 8 v alid time after rd ad 7 Cad 0 v alid time after wr ad 7 Cad 0 v alid time after wr data bus dela y time after wr data bus valid time reset out output dela y time reset out output v alid time (note)
3-7 3800 group users manual appendix 3.1 electrical characteristics note: the reset out goes h in sync with the f all of the f cloc k that is an ywhere betw een about 8 cycle and 13 cycles after the reset input goes h. bef ore f onw input set up time after f onw input hold time bef ore f data bus set up time after f data bus hold time bef ore rd onw input set up time bef ore wr onw input set up time after rd onw input hold time after wr onw input hold time bef ore rd data b us set up time after rd data b us hold time t su(onwC f ) t h( f Conw) t su(dbC f ) t h( f Cdb) t su ( onw Crd) t su ( onw Cwr) th ( rd Conw) t h( wr Conw) t su(dbC rd ) t h( rd Cdb) symbol parameter limits min. ns ns ns ns unit C20 C20 180 0 C20 C20 185 0 t y p . max. f clock cycle time f cloc k h pulse width f cloc k l pulse width after f ad 15 Cad 8 dela y time after f ad 15 Cad 8 v alid time after f ad 7 Cad 0 dela y time after f ad 7 Cad 0 v alid time sync dela y time sync v alid time rd and wr dela y time rd and wr v alid time after f data bus dela y time after f data bus valid time rd pulse width, wr pulse width rd pulse width, wr pulse width (when one-w ait is v alid) after ad 15 Cad 8 rd dela y time after ad 15 Cad 8 wr dela y time after ad 7 Cad 0 rd dela y time after ad 7 Cad 0 wr dela y time after rd ad 15 Cad 8 v alid time after wr ad 15 Cad 8 v alid time after rd ad 7 Cad 0 v alid time after wr ad 7 Cad 0 v alid time after wr data bus dela y time after wr data bus valid time reset out output dela y time reset out output v alid time (note) 150 150 25 15 200 195 300 300 symbol parameter limits min. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns unit t c(x in ) C20 t c(x in ) C20 10 10 3 15 t c(x in ) C20 3t c(x in ) C20 t c(x in ) C145 t c(x in ) C145 5 5 10 0 2t c(x in ) 15 15 40 20 15 7 10 10 t y p . max. t c( f ) t wh( f ) t wl( f ) t d( f Cah) t v( f Cah) t d( f Cal) t v( f Cal) t d( f Csync) t v( f Csync) t d( f Cwr) t v( f Cwr) t d( f Cdb) t v( f Cdb) t wl(rd) t wl(wr) t d(ahCrd) t d(ahCwr) t d(alCrd) t d(alCwr) t v(rdCah) t v(wrCah) t v(rdCal) t v(wrCal) t d(wrCdb) t v(wrCdb) t d (resetCreset out ) t v( f Creset) t est conditions fig. 3.1.1 t able 3.1.10 timing requirements in memor y e xpansion mode and micropr ocessor mode (2) (v cc = 3.0 v , v ss = 0 v , t a = C20 to 85 c , unless otherwise noted) t able 3.1.11 switc hing c haracteristics in memor y e xpansion mode and micropr ocessor mode (2) (v cc = 3.0 v , v ss = 0 v , t a = C20 to 85 c , unless otherwise noted) ns ns ns ns ns
3800 group users manual appendix 3.1 electrical characteristics 3-8 3.1.5 absolute maxim um ratings (extended operating temperature ver sion) t able 3.1.12 absolute maxim um ratings (extended operating temperature ver sion) power source voltage input v oltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 input v oltage reset , x in input v oltage cnv ss output v oltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 , x out p o w er dissipation oper ating temper ature stor age temper ature symbol parameter conditions ratings C0.3 to 7.0 v unit t a = 25 c all v oltages are based on v ss . output tr ansistors are cut off . note 1: the total output current is the sum of all the currents flo wing through all the applicab le por ts . the total a v er age current is an a v er- age v alue measured ov er 100 ms . the total peak current is the peak value of all the currents . 2: the peak output current is the peak current flowing in each port. 3: the average output current i ol(avg) , i oh(avg) in an average value measured over 100 ms. 5.5 power source voltage p o w er source voltage h input v oltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 h input v oltage reset , x in , cnv ss l input v oltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 l input v oltage reset , cnv ss l input voltage x in h total peak output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 (note 1) h total peak output current p4 0 Cp4 7 ,p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note 1) l total peak output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 (note 1) l total peak output current p4 0 Cp4 7 ,p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note 1) h total a v er age output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 (note 1) h total a v er age output current p4 0 Cp4 7 ,p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note 1) l total a v er age output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 (note 1) l total a v er age output current p4 0 Cp4 7 ,p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note 1) h peak output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note 2) l peak output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note 2) h average output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note 3) l average output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note 3) internal clock oscillation frequency v cc v ss v ih v ih v il v il v il s i oh(peak) s i oh(peak) s i ol(peak) s i ol(peak) s i oh(a vg) s i oh(a vg) s i ol(a vg) s i ol(a vg) i oh(peak) i ol(peak) i oh(avg) i ol(avg) f(x in ) symbol parameter limits min. v v unit t able 3.1.13 recommended operating conditions (extended operating tempera ture version) (v cc = 4.0 to 5.5 v , t a = C40 to 85 c , unless otherwise noted) 3.1.6 recommended operating conditions (extended operating temperature ver sion) 4.0 5.0 0 t y p . max. v cc v i v i v i v o p d t opr t stg C0.3 to v cc +0.3 C0.3 to v cc +0.3 C0.3 to 13 C0.3 to v cc +0.3 1000(note) C40 to 85 C65 to 150 v v v v mw c c 0.8 v cc 0.8 v cc 0 0 0 v cc v cc 0.2 v cc 0.2 v cc 0.16 v cc C80 C80 80 80 C40 C40 40 40 C10 10 C5 5 8 v v v v v ma ma ma ma ma ma ma ma ma ma ma ma mhz note : 300 mw in case of the flat pac kage .
3-9 3800 group users manual appendix 3.1 electrical characteristics when stp instruction is executed with clock stopped, output transistors isolated. note : p4 5 is measured when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0. 2.0 5.0 5.0 C5.0 5.5 13 8 1 10 h output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 (note) l output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 ,p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 hysteresis cntr 0 , cntr 1 , int 0 Cint 5 hysteresis r x d, s clk hysteresis reset h input current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 h input current reset, cnv ss h input current x in l input current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 , p7 1 , reset, cnv ss l input current x in ram hold voltage symbol parameter limits min. unit table 3.1.14 electrical characteristics (extended operating temperature version) (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = C40 to 85 c, unless otherwise noted) 3.1.7 electrical characteristics (extended operating temperature version) v cc C2.0 0.4 0.5 0.5 4 C4 6.4 4 1.5 1 0.1 typ. max. i oh = C10 ma i ol = 10 ma v i = v cc v i = v cc v i = v cc v i = v ss v i = v ss when clock stopped f(x in ) = 8 mhz f(x in ) = 5 mhz when wit instruction is executed with f(x in ) = 8 mhz when wit instruction is executed with f(x in ) = 5 mhz t a = 25 c t a = 85 c 2.0 test conditions v t+ C v tC v t+ C v tC v t+ C v tC i ih i ih i ih i il i il v ram i cc v oh v ol v v v v v m a m a m a m a m a v power source current ma m a
3800 group users manual appendix 3.1 electrical characteristics 3-10 3.1.8 timing requirements and switching characteristics (extended operating temperature version) note: bit 6 of address 001a 16 is 1. divide this value by four bit 6 of address 001a 16 is 0. reset input l pulse width external clock input cycle time external clock input h pulse width external clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 to int 5 input h pulse width int 0 to int 5 input l pulse width serial i/o clock input cycle time (note) serial i/o clock input h pulse width (note) serial i/o clock input l pulse width (note) serial i/o input set up time serial i/o input hold time t w(reset) t c(x in ) t wh(x in ) t wl(x in ) t c(cntr) t wh(cntr) t wl(cntr) t wh(int) t wl(int) t c(s clk ) t wh(s clk ) t wl(s clk ) t su(r x dCs clk ) t h(s clk Cr x d) symbol parameter limits min. m s ns ns ns ns ns ns ns ns ns ns ns ns ns unit 2 125 50 50 200 80 80 80 80 800 370 370 220 100 typ. max. table 3.1.15 timing requirements (extended operating temperature version) (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = C40 to 85 c, unless otherwise noted) serial i/o clock output h pulse width serial i/o clock output l pulse width serial i/o output delay time (note 1) serial i/o output valid time (note 1) serial i/o clock output rise time serial i/o clock output fall time cmos output rise time (note 2) cmos output fall time (note 2) 140 30 30 30 30 symbol parameter limits min. ns ns ns ns ns ns ns ns unit t c(s clk ) /2C30 t c(s clk ) /2C30 C30 10 10 typ. max. t wh(s clk ) t wl(s clk ) t d(s clk Ct x d) t v(s clk Ct x d) t r(s clk ) t f(s clk ) t r(cmos) t f(cmos) test conditions fig. 3.1.1 note1: when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0. 2: x out pin is excluded. table 3.1.16 switching characteristics (extended operating temperature version) (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = C40 to 85 c, unless otherwise noted)
3-11 3800 group users manual appendix 3.1 electrical characteristics table 3.1.17 timing requirements in memory expansion mode and microprocessor mode (extended operating temperature version) (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = C40 to 85 c, unless otherwise noted) table 3.1.18 switching characteristics in memory expansion mode and microprocessor mode (extended operating temperature version) (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = C40 to 85 c, unless otherwise noted) before f onw input set up time after f onw input hold time before f data bus set up time after f data bus hold time before rd onw input set up time before wr onw input set up time after rd onw input hold time after wr onw input hold time before rd data bus set up time after rd data bus hold time t su(onwC f ) t h( f Conw) t su(dbC f ) t h( f Cdb) t su ( onw Crd) t su ( onw Cwr) t h( rd Conw) t h( wr Conw) t su(dbC rd ) t h( rd Cdb) symbol parameter limits min. ns ns ns ns ns ns ns ns unit C20 C20 60 0 C20 C20 65 0 typ. max. f clock cycle time f clock h pulse width f clock l pulse width after f ad 15 Cad 8 delay time after f ad 15 Cad 8 valid time after f ad 7 Cad 0 delay time after f ad 7 Cad 0 valid time sync delay time sync valid time rd and wr delay time rd and wr valid time after f data bus delay time after f data bus valid time rd pulse width, wr pulse width rd pulse width, wr pulse width (when one-wait is valid) after ad 15 Cad 8 rd delay time after ad 15 Cad 8 wr delay time after ad 7 Cad 0 rd delay time after ad 7 Cad 0 wr delay time after rd ad 15 Cad 8 valid time after wr ad 15 Cad 8 valid time after rd ad 7 Cad 0 valid time after wr ad 7 Cad 0 valid time after wr data bus delay time after wr data bus valid time reset out output delay time reset out output valid time (note) 40 45 20 10 70 65 200 200 symbol parameter limits min. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns unit t c(x in ) C10 t c(x in ) C10 6 6 3 15 t c(x in ) C10 3t c(x in ) C10 t c(x in ) C35 t c(x in ) C40 0 0 10 0 2t c(x in ) 20 10 25 10 20 10 10 5 20 t c(x in ) C15 t c(x in ) C20 5 5 15 typ. max. test conditions note : the reset out output goes h in sync with the fall of the f clock that is anywhere between about 8 cycle and 13 cycles after the reset input goes h. fig. 3.1.1 t c( f ) t wh( f ) t wl( f ) t d( f Cah) t v( f Cah) t d( f Cal) t v( f Cal) t d( f Csync) t v( f Csync) t d( f Cwr) t v( f Cwr) t d( f Cdb) t v( f Cdb) t wl(rd) t wl(wr) t d(ahCrd) t d(ahCwr) t d(alCrd) t d(alCwr) t v(rdCah) t v(wrCah) t v(rdCal) t v(wrCal) t d(wrCdb) t v(wrCdb) t d (resetCreset out ) t v( f Creset) fig. 3.1.1 circuit for measuring output switching characteristics measurement output pin 100pf cmos output
3800 group users manual appendix 3.1 electrical characteristics 3-12 3.1.9 timing diagram timing diagram fig. 3.1.2 timing diagram (in single-chip mode) 0.2 v cc t wl(int) 0.8 v cc t wh(int) 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 0.2 v cc t wl(x in ) 0.8 v cc t wh(x in) t c(x in ) x in 0.2 v cc 0.8 v cc t w(reset) reset t f t r 0.2 v cc t wl(cntr) 0.8 v cc t wh(cntr) t c(cntr) t d(s clk -t x d) t v(s clk -t x d) t c(s clk ) t wl(s clk ) t wh(s clk ) th (s clk- r x d) t su(s clk- r x d) t x d r x d s clk int 0 int 5 cntr 0 , cntr 1
3-13 3800 group users manual appendix 3.1 electrical characteristics timing dia gram in memor y expansion mode and micr opr ocessor mode (1) fig. 3.1.3 timing dia gram (in memor y e xpansion mode and micropr ocessor mode) (1) timing dia gram in micr opr ocessor mode t wl( f ) t wh( f ) t c( f ) f t d( f -ah) t d( f -al) t d( f -sync) t v( f -ah) t v( f -al) t v( f -sync) t d( f -wr) t v( f -wr) t su(onw- f ) t h( f -onw) t su(db- f ) t h( f -db) t d( f -db) t v( f -db) t d(reset- reset out ) ad 15 Cad 8 ad 7 Cad 0 sync rd,wr onw db 0 Cdb 7 db 0 Cdb 7 reset f reset out t v( f - reset out ) 0.5 v cc 0.8 v cc 0.2 v cc (at cpu reading) (at cpu writing) 0.5 v cc 0.5 v cc 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.5 v cc 0.5 v cc 0.5 v cc 0.5 v cc 0.5 v cc
3800 group users manual appendix 3.1 electrical characteristics 3-14 timing diagram in memory expansion mode and microprocessor mode (2) fig. 3.1.4 timing diagram (in memory expansion mode and microprocessor mode) (2) 0.5 v cc rd,wr 0.5 v cc ad 15 ?d 8 t d(ah-wr) t v(wr-ah) 0.5 v cc ad 7 ?d 0 t d(al-wr) t v(wr-al) 0.8 v cc 0.2 v cc db 0 ?b 7 0.5 v cc rd t su(db-rd) t h(rd-db) 0.5 v cc db 0 ?b 7 0.5 v cc wr t d(wr-db) t v(wr-db) t h(wr-onw) onw t su(onw-wr) t v(rd-ah) t d(ah-rd) t d(al-rd) t v(rd-al) t h(rd-onw) t su(onw-rd) t wl(rd) t wl(wr) (at cpu reading) (at cpu writing) t wl(rd) t wl(wr) 0.8 v cc 0.2 v cc
appendix 3.2 standard characteristics 3-15 3800 group users manual 3.2 standard characteristics 3.2.1 power source current characteristic examples figures 3.2.1 and figure 3.2.2 show power source current cha racteristic examples. fig. 3.2.1 power source current characteristic example [measuring condition : 25 c] fig. 3.2.2 power source current characteristic example (in w ait mode) [measuring condition : 25 c] 0 0 rectangular waveform 8 4 3 2 1 8 4 3 2 1 567 5 6 7 vcc = 5.5 v, ta = 25 vcc = 4.0 v, ta = 25 power source current (ma) vcc = 3.0 v, ta = 25 frequency f(x in ) (mhz) 0 0 8 4 3 2 1 8 4 3 2 1 56 7 5 6 7 rectangular waveform power source current (ma) frequency f(x in ) (mhz) vcc = 4.0 v, ta = 25 vcc = 3.0 v, ta = 25 vcc = 5.5 v, ta = 25
3-16 3800 group users manual appendix 3.2 standard characteristics 3.2.2 port standard characteristic examples figures 3.2.3, figure 3.2.4, figure 3.2.5 and figure 3.2.6 s how port standard characteristic examples. fig. 3.2.3 standard characteristic example of cmos output po rt at p-channel drive (1) [port p0 0 i oh Cv oh characteristic (p-channel drive)] fig. 3.2.4 standard characteristic example of cmos output po rt at p-channel drive (2) [port p0 0 i oh Cv oh characteristic (p-channel drive)] (pins with same characteristic : p0, p1, p2, p3, p4, p5, p6, p7) (pins with same characteristic : p0, p1, p2, p3, p4, p5, p6, p7) 0 v oh (v) i oh (ma) 0.5 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 C 5 C 10 C 15 C 20 C 25 C 30 C 35 C 40 C 45 C 50 5.5 vcc = 5.0 v, ta = 25 vcc = 4.0 v, ta = 25 vcc = 3.0 v, ta = 25 0 v oh (v) i oh (ma) 0.5 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 C 5 C 10 C 15 C 20 C 25 C 30 C 35 C 40 C 45 C 50 5.5 vcc = 4.0 v, ta = 90 vcc = 5.0 v, ta = 90 vcc = 3.0 v, ta = 90
appendix 3.2 standard characteristics 3-17 3800 group users manual fig. 3.2.5 standard characteristic example of cmos output po rt at n-channel drive (1) [port p0 0 i ol Cv ol characteristic (n-channel drive)] fig. 3.2.6 standard characteristic example of cmos output po rt at n-channel drive (2) [port p0 0 i ol Cv ol characteristic (n-channel drive)] (pins with same characteristic : p0, p1, p2, p3, p4, p5, p6, p7) (pins with same characteristic : p0, p1, p2, p3, p4, p5, p6, p7) 0 v ol (v) i ol (ma) 0.5 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5 10 15 20 25 30 35 40 45 50 vcc = 5.0 v, ta = 90 vcc = 4.0 v, ta = 90 vcc = 3.0 v, ta = 90 0 v ol (v) i ol (ma) 0.5 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5 10 15 20 25 30 35 40 45 50 55 60 vcc = 5.0 v, ta = 25 vcc = 4.0 v, ta = 25 vcc = 3.0 v, ta = 25
3800 group users manual 3-18 appendix 3.3 notes on use (1) sequence for switching an external interrupt detection edge clear an interrupt enable bit to 0 (interrupt disabled) switch the detection edge clear an interrupt request bit to 0 (no interrupt requ- est issued) set the interrupt enable bit to 1 ( interrupt enabled ) 3.3 notes on use 3.3.1 notes on interrupts when the external interrupt detection edge must be switched, make sure the following sequence. reason the interrupt circuit recognizes the switching of the detection edge as the change of external input signals. this may cause an unnecessary interrupt. (2) bits 7 and 6 of the interrupt control register 2 fix the bits 7 and 6 of the interrupt control register 2 (address:003f 16 ) to 0. figure 3.3.1 shows the structure of the interrupt control register 2. fig. 3.3.1 structure of interrupt control register 2 3.3.2 notes on the serial i/o (1) stop of data transmission as for the serial i/o that can be used as either a clock synchronous or an asynchronous (uart) serial i/o, clear the transmit enable bit to 0 (transmit disabled), and clear the serial i/o enable bit to 0 (serial i/o disabled)in the following cases : l when stopping data transmission during transmitting data in the clock synchronous serial i/o mode l when stopping data transmission during transmitting data in the uart mode l when stopping only data transmission during transmitting and receiving data in the uart mode reason since transmission is not stopped and the transmission circuit is not initialized even if the serial i/o enable bit is cleared to 0 (serial i/o disabled), the internal transmission is running (in this case, since pins txd, rxd, s clk , and s rdy function as i/o ports, the transmission data is not output). when data is written to the transmit buffer register in this state, the data is transferred to the transmit shift register and start tp be sjifted. when the serial i/o enable bit is set to 1 at this time, the data during internally shifting is output to the txd pin and ti may cause an operation failure to a microcomputer. (2) stop of data reception as for the serial i/o that can be used as either a clock synchronous or an asynchronous (uart) serial i/o, clear the receive enable bit to 0 (receive disabled), or clear the serial i/o enable bit to 0 (serial i/o disabled) in the following case : l when stopping data reception during receiving data in the clock synchronous serial i/o mode clear the receive enable bit to 0 (receive disabled) in the following cases : l when stopping data reception during receiving data in the uart mode l when stopping only data reception during transmitting and receiving data in the uart mode b7 b0 interrupt control register 2 address 003f 16 interrupt enable bits not used fix these bits to 0. 0 0
3800 group users manual 3-19 appendix 3.3 notes on use (3) stop of data transmission and reception in a clock synchronous serial i/o mode as for the serial i/o that can be used as either a clock synchronous or an asynchronous (uart) serial i/o, clear both the transmit enable bit and receive enable bit to 0 (transmit and receive disabled) at the same time in the following case: l when stopping data transmission and reception during transmitting and receiving data in the clock synchronous mode (when data is transmitted and received in the clock synchronous serial i/o mode, any one of data transmission and reception cannot be stopped.) reason in the clock synchronous serial i/o mode, the same clock is used for transmission and reception. if any one of transmission and reception is disabled, a bit error occurs because transmission and reception cannot be synchronized. in this mode, the clock circuit of the transmission circuit also operates for data reception. accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to 0 (transmit disabled). also, the transmission circuit is not initialized by clearing the serial i/o enable bit to 0 (serial i/o disabled) (refer to (1) ). (4) the s rdy pin on a receiving side when signals are output from the s rdy pin on the reception side by using an external clock in the clock synchronous serial i/o mode, set all of the receive enable bit, the s rdy output enable bit, and the transmit enable bit to 1 (transmit enabled). (5) stop of data reception in a clock synchronous serial i/o mode set the serial i/o control register again after the transmission and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to 0. clear both the transmit enable bit (te) and the receive enable bit (re) to 0 set the bits 0 to 3 and bit 6 of the serial i/o control register set both the transmit enable bit (te) and the receive enable bit (re) to 1 can be set with the ldm instruction at the same time (6) control of data transmission using the transmit shift completion flag the transmit shift completion flag changes from 1 to 0 with a delay of 0.5 to 1.5 shift clocks. when checking the transmit shift completion flag after writing a data to the transmit buffer register for controlling a data transmission, note this delay. (7) control of data transmission using an external clock when an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to 1 at h level of the s clk input signal. also, write data to the transmit buffer register at h level of the s clk input signal. 3.3.3 notes on the reset pin when a rising time of the reset signal is long, connect a ceramic capacitor or others across the reset pin and the v ss pin. and use a 1000 pf or more capacitor for high frequency use. when connecting the capacitor, make sure the following : l make the length of the wiring which is connected to a capacitor the shortest possible. l make sure to check the operation of application products on the user side. reason if the several nanosecond or several ten nanosecond impulse noise enters the reset pin, a microcomputer may malfunction.
3800 group users manual 3-20 appendix 3.3 notes on use 3.3.4 notes on input and output pins (1) fix of a port input level in stand-by state fix input levels of an input and an i/o port for getting effect of low-power dissipation in stand-by state*, especially for the i/o ports of the n-channel open-drain. pull-up (connect the port to v cc ) or pull-down (connect the port to v ss ) these ports through a resistor. when determining a resistance value, make sure the following: l external circuit l variation of output levels during the ordinary operation * stand-by state : the stop mode by executing the stp instruction the wait mode by executing the wit instruction reason even when setting as an output port with its direction register, in the following state : l n-channel......when the content of the port latch is 1 the transistor becomes the off state, which causes the ports to be the high-impedance state. make sure that the level becomes undefined depending on external circuits. accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of an input and an i/o port are undefined. this may cause power source current. (2) modify of the content of i/o port latch when the content of the port latch of an i/o port is modified with the bit managing instruction*, the value of the unspecified bit may be changed. reason the bit managing instruction is read-modify-write instruction for reading and writing data by a byte unit. accordingly, when this instruction is executed on one bit of the port latch of an i/o port, the following is executed to all bits of the port latch. l as for a bit which is set as an input port : the pin state is read in the cpu, and is written to this bit after bit managing. l as for a bit which is set as an output port : the bit value is read in the cpu, and is written to this bit after bit managing. make sure the following : l even when a port which is set as an output port is changed for an input port, its port latch holds the output data. l even when a bit of a port latch which is set as an input port is not speccified with a bit managing instruction, its value may be changed in case where content of the pin differs from a content of the port latch. * bit managing instructions : seb and clb instruction
3800 group users manual 3-21 appendix 3.3 notes on use 3.3.5 notes on memory expansion mode and microprocessor mode (1) writing data to the port latch of port p3 in the memory expansion or the microprocessor mode, ports p3 0 and p3 1 can be used as the output port. use the ldm or sta instruction for writing data to the port latch (address 000 6 16 ) of port p3. when using a read-modify-write instruction (the seb or the clb instruction), allocate the read and the write enabled memory at address 0006 16 . reason in the memory expansion or microprocessor mode, address 0006 16 is allocated in the external area. accordingly, l data is read from the external memory. l data is written to both the port latch of the port p3 and th e external memory. accordingly, when executing a read-modify-write instruction for address 0006 16 , external memory data is read and modified, and the result is written in both the port latch o f the port p3 and the external memory. if the read enabled memory is not allocated at address 0006 16 , the read data is undefined. the undefined data is modifie d and written to the port latch of the port p3. the port latch data of po rt p3 becomes undefined. (2) overlap of an internal memory and an external memory when the internal and the external memory are overlapped in the memory expansion mode, the internal memory is valid in this overlapped area. when the cpu writes or rea ds to this area, the following is performed : l when reading data only the data in the internal memory is read into the cpu an d the data in the external memory is not read into the cpu. however, as the read signal and address are still v alid, the external memory data of the corresponding address is output to the external data bus. l when writing data data is written in both the internal and the external memory .
3800 group users manual 3-22 appendix 3.3 notes on use (2) write and read in prom mode, operation is the same as that of the m5m27c256ak, but programming conditions of prom programmer are not set automatically because there are no internal device id codes. accurately set the following conditions for data write/read. take care not to apply 21 v to vpp pin (is also used as the cnv ss pin), or the product may be permanently damaged. l programming voltage : 12.5 v l setting of programming adapter switch : refer to table 3.3.2 l setting of prom programmer address : refer to table 3.3.3 table 3.3.2 setting of programming adapter switch sw 1 cmos sw 2 cmos sw 3 off programming adapter pca4738s-64a pca4738l-64a pca4738f-64a microcomputer m38002e4ss m38004e8ss m38002e2sp m38002e4sp m38004e8sp (one-time blank) m38002e4dsp (one-time blank) m38002e4fs m38004e8fs m38002e2fp m38002e4fp m38004e8fp (one-time blank) m38002e4dfp (one-time blank) 3.3.6 notes on built-in prom (1) programming adapter to write or read data into/from the internal prom, use the dedicated programming adapter and general-purpose prom programmer as shown in table 3.3.1. table 3.3.1 programming adapter programming adapter pca4738s-64a pca4738l-64a pca4738f-64a
3800 group users manual 3-23 appendix 3.3 notes on use table 3.3.3 setting of prom programmer address prom programmer start address address : 6080 16 (note 1) address : 4080 16 (note 2) address : 0080 16 (note 3) microcomputer m38002e2sp m38002e2fp m38002e4ss m38002e4sp m38002e4fs m38002e4fp m38002e4dsp m38002e4dfp m38004e8ss m38004e8sp m38004e8fs m38004e8fp prom programmer completion address address : 7ffd 16 (note 1) address : 7ffd 16 (note 2) address : 7ffd 16 (note 3) note1 : addresses e080 16 to fffd 16 in the internal prom correspond to addresses 6080 16 to 7ffd 16 in the rom programmer. 2 : addresses c080 16 to fffd 16 in the internal prom correspond to addresses 4080 16 to 7ffd 16 in the rom programmer. 3 : addresses 8080 16 to fffd 16 in the internal prom correspond to addresses 0080 16 to 7ffd 16 in the rom programmer. (3) erasing contents of the windowed eprom are erased through an ultraviolet light source of the wavelength 2537- angstrom . at least 15 w-sec/cm are required to erase eprom contents. 2
3800 group user? manual 3-24 appendix 3.4 countermeasures against noise 3.4 countermeasures against noise countermeasures against noise are described below. the follo wing countermeasures are effective against noise in theory, however, it is necessary not only to take measures a s follows but to evaluate before actual use. 3.4.1 shortest wiring length the wiring on a printed circuit board can be as an antenna w hich feeds noise into the microcomputer. the shorter the total wiring length (by mm unit), the less t he possibility of noise insertion into a microcomputer. (1) wiring for the reset pin make the length of wiring which is connected to the reset pi n as short as possible. especially, connect a capacitor across the reset pin and the v ss pin with the shortest possible wiring (within 20mm). reason the reset works to initialize a microcomputer. the width of a pulse input into the reset pin is determined by the timing necessary conditions. if noise having a shorter pulse width than the standard is input to the rese t pin, the reset is released before the internal state of the microcomputer is completely initialized. this may cau se a program runaway. fig. 3.4.1 wiring for the reset pin (2) wiring for clock input/output pins l make the length of wiring which is connected to clock i/o p ins as short as possible. l make the length of wiring (within 20mm) across the grounding lead of a capacitor which is connected to an oscillatorand the v ss pin of a microcomputer as short as possible. l separate the v ss pattern only for oscillation from other v ss patterns. reason a microcomputer's operation synchronizes with a clock genera ted by the oscillator (circuit). if noise enters clock i/o pins, clock waveforms may be deformed. this may cause a malfunction or program runaway. also, if a potential difference is caused by the noise betwe en the v ss level of a microcomputer and the v ss level of an oscillator, the correct clock will not be input in the m icrocomputer. reset reset circuit noise v ss v ss reset circuit v ss reset v ss 3800 group 3800 group n.g. o.k.
3800 group users manual 3-25 appendix 3.4 countermeasures against noise fig. 3.4.2 wiring for clock i/o pins (3) wiring for the v pp pin of the one time prom version and the eprom version (in this microcomputer the v pp pin is also used as the cnv ss pin) connect an approximately 5 k w resistor to the v pp pin the shortest possible in series and also to the v ss pin. when not connecting the resistor, make the length of wiring between the v pp pin and the v ss pin the shortest possible. note:even when a circuit which inclued an approximately 5 k w resistor is used in the mask rom version, the maicrocomputer operates correctly. reason the v pp pin of the one time prom and the eprom version is the power source input pin for the built-in prom. when programming in the built-in prom, the impedance of the v pp pin is low to allow the electric current for wiring flow into the prom. be- cause of this, noise can enter easily. if noise enters the v pp pin, abnormal in struction codes or data are read from the built-in prom, which may cause a program runaway. 3.4.2 connection of a bypass capacitor across the vss line and the vcc line connect an approximately 0.1 m f bypass capacitor across the v ss line and the v cc line as follows: l connect a bypass capacitor across the v ss pin and the v cc pin at equal length . l connect a bypass capacitor across the v ss pin and the v cc pin with the shortest possible wiring. l use lines with a larger diameter than other signal lines for v ss line and v cc line. fig. 3.4.3 wiring for the v pp pin of the one time prom and the eprom version fig. 3.4.4 bypass capacitor across the v ss line and the v cc line aa aa aa aa aa aa aa aa aa aa aa aa v ss v cc aaa aaa aaa aaa aaa aaa a aa aa aa aa aa aa a v ss v cc chip aaa aaa aaa aaa aa aa aa aaa aaa aa aa aa a a x in x out v ss an example of v ss patterns on the underside of a printed circuit board oscillator wiring pattern example separate the v ss line for oscillation from other v ss lines noise x in x out v ss x in x out v ss n.g. o.k. cnv ss /v pp approximately 5k w 3800 group v ss make it the shortest possible
3800 group users manual 3-26 appendix 3.4 countermeasures against noise 3.4.3. consideration for oscillator take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. (1) keeping an oscillator away from large current signal lines install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. reason in the system using a microcomputer, there are signal lines for controlling motors, leds, and thermal heads or others. when a large current flows through those signal lines, strong noise occurs because of mutual inductance. (2) keeping an oscillator away from signal lines where potential levels change frequently install an oscillator and a connecting pattern of an osillator away from signal lines where potential levels change frequently. also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. reason signal lines where potential levels change frequently (such as the cntr pin line) may affect other lines at signal rising or falling edge. if such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway. 3.4.4 setup for i/o ports setup i/o ports using hardware and software as follows: l connect a resistor of 100 w or more to an i/o port inseries. l as for an input port, read data several times by a program for checking whether input levels are equal or not. l as for an output port, since the output data may reverse because of noise, rewrite data to its port latch at fixed periods. l rewirte data to direction registers and pull-up control registers (only the product having it) at fixed periods. fig.3.4.5 wiring for a large current signal line fig.3.4.6 wiring to a signal line where potential levels change frequently x in x out v ss m microcomputer mutual inductance large current gnd x in x out v ss cntr do not cross fig. 3.4.7 setup for i/o ports direction register port latch data bus i/o port pins noise noise n.g. o.k. when a direction register is set for input port again at fixed periods, a several-nanosecond short pulse may be output from this port. if this is undesirable, connect a capacitor to this port to remove the noise pulse.
3800 group users manual 3-27 appendix 3.4 countermeasures against noise 3.4.5 providing of watchdog timer function by software if a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. this is equal to or more effective than program runaway detection by a hardware watchdog timer. the following shows an example of a watchdog timer provided by software. in the following example, to reset a microcomputer to normal operation, the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine. this example assumes that interrupt processing is repeated multiple times in a single main routine processing. l assigns a single byte of ram to a software watchdog timer (swdt) and writes the initial value n in the swdt once at each execution of the main routine. the initial value n should satisfy the following condition: fig. 3.4.8 watchdog timer by software n+1 (counts of interrupt processing executed in each main routine) as the main routine execution cycle may change because of an interrupt processing or others, the initial value n should have a margin. l watches the operation of the interrupt processing routine by comparing the swdt contents with counts of interrupt processing count after the initial value n has been set. l detects that the interrupt processing routine has failed and determines to branch to the program initialization routine for recovery processing in the following cases: if the swdt contents do not change after interrupt processing l decrements the swdt contents by 1 at each interrupt processing. l determins that the main routine operates normally when the swdt contents are reset to the initial value n at almost fixed cycles (at the fixed interrupt processing count). l detects that the main routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: when the contents of the swdt reach 0 or less by continuative decrement without initializing to the initial value n . main routine (swdt) n cli main processing (swdt) interrupt processing routine errors n =n interrupt processing routine (swdt) (swdt)? interrupt processing (swdt) main routine errors > 0 0 rti return =n? 0?
3800 group users manual 3-28 appendix 3.5 list of registers 3.5 list of registers fig. 3.5.2 structure of port pi direction register (i = 0, 1, 2, 3, 4, 5, 6, 7) fig. 3.5.1 structure of port pi (i = 0, 1, 2, 3, 4, 5, 6, 7) port pi b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name port pi 0 port pi 1 port pi 2 port pi 3 port pi 4 port pi 5 port pi 6 port pi 7 in output mode write read l port latch in input mode write : port latch read : value of pins l ? ? ? ? ? ? ? ? port pi (pi) (i = 0, 1, 2, 3, 4, 5, 6, 7) [address : 00 16 , 02 16 , 04 16 , 06 16 , 08 16 , 0a 16 , 0c 16 , 0e 16 ] note : ( note ) port p7 register [address : 0e 16 ] port p7 is a 2-bit port (p7 0 , p7 1 ). accordingly, when bits 2 to 7 are read out, the contents are ?. port pi direction register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name port pi direction register 0 0 0 0 0 0 0 0 port pi direction register (pid) (i =0, 1, 2, 3, 4, 5, 6, 7) [address : 01 16 , 03 16 , 05 16 , 07 16 , 09 16 , 0b 16 , 0d 16 , 0f 16 ] 0 : port pi 0 input mode 1 : port pi 0 output mode 0 : port pi 1 input mode 1 : port pi 1 output mode 0 : port pi 2 input mode 1 : port pi 2 output mode 0 : port pi 3 input mode 1 : port pi 3 output mode 0 : port pi 4 input mode 1 : port pi 4 output mode 0 : port pi 5 input mode 1 : port pi 5 output mode 0 : port pi 6 input mode 1 : port pi 6 output mode 0 : port pi 7 input mode 1 : port pi 7 output mode 5 5 5 5 5 5 5 5 note : ( note ) port p7 direction register [address : 0f 16 ] port p7 is a 2-bit port (p7 0 , p7 1 ). accordingly, these bits do not have a direction register function. ( note ) ( note ) ( note ) ( note ) ( note )
3800 group users manual 3-29 appendix 3.5 list of registers fig. 3.5.3 structure of transmit/receive buffer register fig. 3.5.4 structure of serial i/o status register transmit/receive buffer register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 6 7 transmit/receive buffer register (tb/rb) [address : 18 16 ] a transmission data is written to or a receive data is read out from this buffer register. ? at writing : a data is written to the transmit buffer regi ster. ? at reading : a content of the receive buffer register is r ead out. ? ? ? ? ? 5 ? ? ? note : a content of the transmit buffer register cannot be read out . a data cannot be written to the receive buffer register. b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 1 serial i/o status reigster (siosts) [address : 19 16 ] name transmit buffer empty flag (tbe) 0 : (oe) (pe) (fe) = 0 1 : (oe) (pe) (fe) = 1 overrun error flag (oe) 0 : buffer full 1 : buffer empty nothing is allocated for this bit. it is a write disabled bi t. when this bit is read out, the value is 0. receive buffer full flag (rbf) transmit shift register shift completion flag (tsc) parity error flag (pe) framing error flag (fe) summing error flag (se) 0 : buffer empty 1 : buffer full 0 : transmit shift in progress 1 : transmit shift completed 0 : no error 1 : overrun error 0 : no error 1 : parity error 0 : no error 1 : framing error 5 5 5 5 5 5 5 5 serial i/o status register
3800 group users manual 3-30 appendix 3.5 list of registers b7 b6 b5 b4 b3 b2 b1 b0 serial i/o control register 0 0 0 0 0 : transmit buffer empty 1 : transmit shift operating completion 0 : f ( x i n ) 1 : f ( x i n ) / 4 serial i/o synchronous clock selection bit (scs) at selecting clock synchronous serial i/o 0 : brg output divided by 4 1 : external clock input at selecting uart 0 : brg output divided by 16 1 : external clock input divided by 16 transmit interrupt source selection bit (tic) s rdy output enable bit (srdy) 0 : i/o port (p47) 1 : s rdy output pin at reset b name function rw 0 1 2 3 0 0 0 : transmit disabled 1 : transmit enabled transmit enable bit (te) receive enable bit (re) 0 : receive disabled 1 : receive enabled 4 5 0 0 serial i/o enable bit (sioe) serial i/o mode selection bit (siom) 0 : uart 1 : clock synchronous serial i/o 0 : serial i/o disabled (p4 4 Cp4 7 : i/o port) 1 : serial i/o enabled (p4 4 Cp4 7 : serial i/o function pin) 6 7 brg count source selection bit (css) serial i/o control register (siocon) [address : 1a 16 ] fig. 3.5.5 structure of serial i/o control register fig. 3.5.6 structure of uart control register b7 b6 b5 b4 b3 b2 b1 b0 uart control register (uartcon) [address : 1b 16 ] uart control register 0 0 0 0 0 1 5 character length selection bit (chas) 0 : 8 bits 1 : 7 bits parity enable bit (pare) 0 : parity checking disabled 1 : parity checking enabled stop bit length selection bit (stps) 0 : 1 stop bit 1 : 2 stop bits p4 5 /txd p-channel output disable bit (poff) nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 1. parity selection bit (pars) 0 : even parity 1 : odd parity 1 5 1 5 at reset b name function rw 0 1 2 3 4 5 6 7 in output mode 1 : n-channel open-drain output 0 : cmos output
3800 group users manual 3-31 appendix 3.5 list of registers fig. 3.5.7 structure of baud rate generator fig. 3.5.8 structure of prescaler 12, prescaler x, prescaler y prescaler 12, prescaler x, prescaler y b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 prescaler 12 (pre12), prescaler x (prex), prescaler y (prey) [address : 20 16 , 24 16 , 26 16 ] the count value of each prescaler is set. the value set in this register is written to both the presca ler and the prescaler latch at the same time. when the prescaler is read out, the value (count value) of t he prescaler is read out. l l l b baud rate generator (brg) [ address : 1c 16 ] b7 b6 b5 b4 b3 b2 b1 b0 baud rate generator ? a count value of baud rate generator is set. ? ? ? ? ? ? ? function at reset w 0 1 2 3 4 5 6 7 r
3800 group users manual 3-32 appendix 3.5 list of registers fig. 3.5.9 structure of timer 1 fig. 3.5.10 structure of timer 2, timer x, timer y b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 1 0 0 0 0 0 0 0 timer 1 (t1) [address : 21 16 ] the count value of the timer 1 is set. the value set in this register is written to both the timer 1 and the timer 1 latch at the same time. when the timer 1 is read out, the value (count value) of the timer 1 is read out. l l l timer 1 timer 2, timer x, timer y b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 timer 2 (t2), timer x (tx), timer y (ty) [address : 22 16 , 25 16 , 27 16 ] the count value of each timer is set. the value set in this register is written to both the timer and the timer latch at the same time. when the timer is read out, the value (count value) of the timer is read out. l l l
3800 group users manual 3-33 appendix 3.5 list of registers operating mode of timer x/timer y timer mode pulse output mode event counter mode pulse width measurement mode table. 3.5.1 function of cntr 0 /cntr 1 edge switch bit fig. 3.5.11 structure of timer xy mode register function of cntr 0 /cntr 1 edge switch bit (bits 2 and 6) 0 1 0 1 0 1 0 1 ? generation of cntr 0 /cntr 1 interrupt request : falling edge (no effect on timer count) ? generation of cntr 0 /cntr 1 interrupt request : rising edge (no effect on timer count) ? start of pulse output : from h level ? generation of cntr 0 /cntr 1 interrupt request : falling edge ? start of pulse output : from l level ? generation of cntr 0 /cntr 1 interrupt request : rising edge ? timer x/timer y : count of rising edge ? generation of cntr 0 /cntr 1 interrupt request : falling edge ? timer x/timer y : count of falling edge ? generation of cntr 0 /cntr 1 interrupt request : rising edge ? timer x/timer y : measurement of h level width ? generation of cntr 0 /cntr 1 interrupt request : falling edge ? timer x/timer y : measurement of l level width ? generation of cntr 0 /cntr 1 interrupt request : rising edge a a aa aa function timer xy mode register b7 b6 b5 b4 b3 b2 b1 b0 b at reset r w 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 timer xy mode register (tm) name timer x operating mode bit cntr 0 active edge switch bit timer y operating mode bit cntr 1 active edge switch bit 0 0 : timer mode 0 1 : pulse output mode 1 0 : event counter mode 1 1 : pulse width measurement mode 0 0 : timer mode 0 1 : pulse output mode 1 0 : event counter mode 1 1 : pulse width measurement mode it depends on the operating mode of the timer x (refer to table 3.5.1). it depends on the operating mode of the timer y (refer to table 3.5.1). b5 b4 timer x count stop bit [address : 23 16 ] b1 b0 timer y count stop bit 0 : count start 1 : count stop 0 : count start 1 : count stop
3800 group users manual 3-34 appendix 3.5 list of registers fig. 3.5.12 structure of interrupt edge selection register fig. 3.5.13 structure of cpu mode register 5 5 5 5 3 2 0 1 cpu mode register (cpum) [ adress : 3b 16 ] nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 0. 0 0 0 0 0 cpu mode register processor mode bits 00 : single-chip mode 01 : memory expansion mode 10 : microprocessor mode 11 : not available stack page selection bit 0 : 0 page 1 : 1 page 0 0 5 5 [ an initial value of bit 1 is determined by a level of the c nv ss pin. [ at reset b name function rw 4 5 6 7 b7 b6 b5 b4 b3 b2 b1 b0 interrupt edge selection register (intedge) [address : 3a 16 ] interrupt edge selection register int 0 interrupt edge selection bit 0 : falling edge active 1 : rising edge active 0 int 1 interrupt edge selection bit 0 : falling edge active 1 : rising edge active int 3 interrupt edge selection bit 0 : falling edge active 1 : rising edge active nothing is allocated for these bits. these are write disable d bits. when these bits are read out, the values are 0. 0 int 4 interrupt edge selection bit 0 : falling edge active 1 : rising edge active int 5 interrupt edge selection bit 0 : falling edge active 1 : rising edge active 0 5 0 0 0 0 0 int 2 interrupt edge selection bit 0 : falling edge active 1 : rising edge active at reset b name function rw 0 1 2 3 4 5 6 7 5 b7 b6 b5 b4 b3 b2 b1 b0
3800 group users manual 3-35 appendix 3.5 list of registers fig. 3.5.14 structure of interrupt request register 1 fig. 3.5.15 structure of interrupt request register 2 [ 0 : no interrupt request 1 : interrupt request serial i/o receive interrupt request bit serial i/o transmit interrupt request bit interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw interrupt request reigster 1 (ireq1) [address : 3c 16 ] name [ ??is set by software, but not ?. timer y interrupt request bit 4 5 6 7 0 0 0 0 timer x interrupt request bit timer 1 interrupt request bit 0 : no interrupt request 1 : interrupt request timer 2 interrupt request bit 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request [ [ [ [ [ [ [ 0 0 0 0 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request int 0 interrupt request bit int 1 interrupt request bit 0 1 2 3 interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 0 0 0 0 interrupt request reigster 2 (ireq2) [address : 3d 16 ] name cntr 0 interrupt request bit cntr 1 interrupt request bit int 2 interrupt request bit 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request 0 : no interrupt request 1 : interrupt request int 3 interrupt request bit [ [ [ [ 5 6 0 0 : no interrupt request 1 : interrupt request nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are ?. int 5 interrupt request bit [ [ ??is set by software, but not ?. 4 0 0 : no interrupt request 1 : interrupt request int 4 interrupt request bit [ 0 7 0 5 5
3800 group users manual 3-36 appendix 3.5 list of registers fig. 3.5.16 structure of interrupt control register 1 fig. 3.5.17 structure of interrupt control register 2 timer y interrupt enable bit interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 0 0 0 0 interrupt control register 1 (icon1) [address : 3e 16 ] name int 0 interrupt enable bit int 1 interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 4 5 6 7 0 0 0 0 timer x interrupt enable bit timer 1 interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled timer 2 interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled serial i/o transmit interrupt enable bit serial i/o receive interrupt enable bit interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 0 0 0 0 interrupt control reigster 2 (icon2) [address : 3f 16 ] name cntr 0 interrupt enable bit cntr 1 interrupt enable bit int 2 interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled int 3 interrupt enable bit 5 6 0 0 : interrupt disabled 1 : interrupt enabled fix these bits to 0. int 5 interrupt enable bit 4 0 0 : interrupt disabled 1 : interrupt enabled int 4 interrupt enable bit 0 0 0 7 0
appendix 3.6 mask rom ordering method 3-37 3800 group users manual 3.6 mask rom ordering method gzz-sh04-34b<13b0> receipt 740 family mask rom confirmation form single-chip microcomputer m38002m2-xxxsp/fp mitsubishi electric mask rom number date: section head signature supervisor signature company name note : please fill in all items marked h . customer h issuance signature date issued submitted by tel () date: supervisor h 1. confirmation specify the name of the product being ordered and the type of eproms submitted. three eproms are required for each pattern. if at least two of the three sets of eproms submitted contain identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms. microcomputer name : 27256 27512 0000 16 000f 16 0010 16 607f 16 6080 16 7ffd 16 7ffe 16 7fff 16 m38002m2-xxxsp m38002m2-xxxfp checksum code for entire eprom (hexadecimal notation) in the address space of the microcomputer, the internal rom area is from address e080 16 to fffd 16 . the reset vector is stored in addresses fffc 16 and fffd 16 . (1) set the data in the unused area (the shaded area of the diagram) to ff 16 . (2) the ascii codes of the product name m38002m2C must be entered in addresses 0000 16 to 0008 16 . and set the data ff 16 in addresses 0009 16 to 000f 16 . the ascii codes and addresses are listed to the right in hexadecimal notation. address 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 m = 4d 16 3 = 33 16 8 = 38 16 0 = 30 16 0 = 30 16 2 = 32 16 m = 4d 16 2 = 32 16 address 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 C = 2d 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 (1/2) eprom address eprom address eprom type (indicate the type used) 0000 16 000f 16 0010 16 e07f 16 e080 16 fffd 16 fffe 16 ffff 16 product name ascii code : m38002m2C data rom 8062 bytes product name ascii code : m38002m2C data rom 8062 bytes
appendix 3.6 mask rom ordering method 3-38 3800 group users manual 740 family mask rom confirmation form single-chip microcomputer m38002m2-xxxsp/fp mitsubishi electric gzz-sh04-34b<13b0> mask rom number we recommend the use of the following pseudo-command to set the start address of the assembler source program. 27256 27512 eprom type the pseudo-command *= a $8000 .byte a m38002m2C *= a $0000 .byte a m38002m2C note : if the name of the product written to the eproms does not match the name of the mask confirmation form, the rom will not be processed. (2/2) h 2. mark specification mark specification must be submitted using the correct form for the package being ordered. fill out the appropriate mark specification form (64p4b for m38002m2-xxxsp, 64p6n for m38002m2-xxxfp) and attach it to the mask rom confirmation form. h 3. usage conditions please answer the following questions about usage for use in our product inspection : (1) how will you use the x in -x out oscillator? at what frequency? f(x in ) = (2) in which operation mode will you use your microcomputer? h 4. comments ceramic resonator external clock input single-chip mode microprocessor mode quartz crystal other ( ) memory expansion mode mhz
appendix 3.6 mask rom ordering method 3-39 3800 group users manual gzz-sh04-79b<16a0> receipt 740 family mask rom confirmation form single-chip microcomputer m38002m2dxxxsp/fp mitsubishi electric mask rom number date: section head signature supervisor signature company name note : please fill in all items marked h . customer h issuance signature date issued submitted by tel () date: supervisor h 1. confirmation specify the name of the product being ordered and the type of eproms submitted. three eproms are required for each pattern. if at least two of the three sets of eproms submitted contain identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms. microcomputer name : 27256 27512 0000 16 000f 16 0010 16 607f 16 6080 16 7ffd 16 7ffe 16 7fff 16 m38002m2dxxxsp m38002m2dxxxfp checksum code for entire eprom (hexadecimal notation) in the address space of the microcomputer, the internal rom area is from address e080 16 to fffd 16 . the reset vector is stored in addresses fffc 16 and fffd 16 . (1) set the data in the unused area (the shaded area of the diagram) to ff 16 . (2) the ascii codes of the product name m38002m2d must be entered in addresses 0000 16 to 0008 16 . and set the data ff 16 in addresses 0009 16 to 000f 16 . the ascii codes and addresses are listed to the right in hexadecimal notation. address 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 m = 4d 16 3 = 33 16 8 = 38 16 0 = 30 16 0 = 30 16 2 = 32 16 m = 4d 16 2 = 32 16 address 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 d = 44 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 (1/2) eprom address eprom address eprom type (indicate the type used) 0000 16 000f 16 0010 16 e07f 16 e080 16 fffd 16 fffe 16 ffff 16 product name ascii code : m38002m2d data rom 8062 bytes product name ascii code : m38002m2d data rom 8062 bytes
appendix 3.6 mask rom ordering method 3-40 3800 group users manual 740 family mask rom confirmation form single-chip microcomputer m38002m2dxxxsp/fp mitsubishi electric gzz-sh04-79b<16a0> mask rom number we recommend the use of the following pseudo-command to set the start address of the assembler source program. 27256 27512 eprom type the pseudo-command *= a $8000 .byte a m38002m2d *= a $0000 .byte a m38002m2d note : if the name of the product written to the eproms does not match the name of the mask confirmation form, the rom will not be processed. (2/2) h 2. mark specification mark specification must be submitted using the correct form for the package being ordered. fill out the appropriate mark specification form (64p4b for m38002m2dxxxsp, 64p6n for m38002m2dxxxfp) and attach it to the mask rom confirmation form. h 3. usage conditions please answer the following questions about usage for use in our product inspection : (1) how will you use the x in -x out oscillator? at what frequency? f(x in ) = (2) in which operation mode will you use your microcomputer? h 4. comments ceramic resonator external clock input single-chip mode microprocessor mode quartz crystal other ( ) memory expansion mode mhz
appendix 3.6 mask rom ordering method 3-41 3800 group users manual gzz-sh03-22b<9yb0> receipt 740 family mask rom confirmation form single-chip microcomputer m38002m4-xxxsp/fp mitsubishi electric mask rom number date: section head signature supervisor signature company name note : please fill in all items marked h . customer h issuance signature date issued submitted by tel () date: supervisor h 1. confirmation specify the name of the product being ordered and the type of eproms submitted. three eproms are required for each pattern. if at least two of the three sets of eproms submitted contain identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms. microcomputer name : 27256 27512 0000 16 000f 16 0010 16 407f 16 4080 16 7ffd 16 7ffe 16 7fff 16 m38002m4-xxxsp m38002m4-xxxfp checksum code for entire eprom (hexadecimal notation) in the address space of the microcomputer, the internal rom area is from address c080 16 to fffd 16 . the reset vector is stored in addresses fffc 16 and fffd 16 . (1) set the data in the unused area (the shaded area of the diagram) to ff 16 . (2) the ascii codes of the product name m38002m4C must be entered in addresses 0000 16 to 0008 16 . and set the data ff 16 in addresses 0009 16 to 000f 16 . the ascii codes and addresses are listed to the right in hexadecimal notation. address 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 m = 4d 16 3 = 33 16 8 = 38 16 0 = 30 16 0 = 30 16 2 = 32 16 m = 4d 16 4 = 34 16 address 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 C = 2d 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 (1/2) eprom address eprom address eprom type (indicate the type used) 0000 16 000f 16 0010 16 c07f 16 c080 16 fffd 16 fffe 16 ffff 16 product name ascii code : m38002m4C data rom 16254 bytes product name ascii code : m38002m4C data rom 16254 bytes
appendix 3.6 mask rom ordering method 3-42 3800 group users manual 740 family mask rom confirmation form single-chip microcomputer m38002m4-xxxsp/fp mitsubishi electric gzz-sh03-22b<9yb0> mask rom number we recommend the use of the following pseudo-command to set the start address of the assembler source program. 27256 27512 eprom type the pseudo-command *= a $8000 .byte a m38002m4C *= a $0000 .byte a m38002m4C note : if the name of the product written to the eproms does not match the name of the mask confirmation form, the rom will not be processed. (2/2) h 2. mark specification mark specification must be submitted using the correct form for the package being ordered. fill out the appropriate mark specification form (64p4b for m38002m4-xxxsp, 64p6n for m38002m4-xxxfp) and attach it to the mask rom confirmation form. h 3. usage conditions please answer the following questions about usage for use in our product inspection : (1) how will you use the x in -x out oscillator? at what frequency? f(x in ) = (2) in which operation mode will you use your microcomputer? h 4. comments ceramic resonator external clock input single-chip mode microprocessor mode quartz crystal other ( ) memory expansion mode mhz
appendix 3.6 mask rom ordering method 3-43 3800 group users manual gzz-sh05-12b<21a0> receipt 740 family mask rom confirmation form single-chip microcomputer m38002m4dxxxsp/fp mitsubishi electric mask rom number date: section head signature supervisor signature company name note : please fill in all items marked h . customer h issuance signature date issued submitted by tel () date: supervisor h 1. confirmation specify the name of the product being ordered and the type of eproms submitted. three eproms are required for each pattern. if at least two of the three sets of eproms submitted contain identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms. microcomputer name : 27256 27512 0000 16 000f 16 0010 16 407f 16 4080 16 7ffd 16 7ffe 16 7fff 16 m38002m4dxxxsp m38002m4dxxxfp checksum code for entire eprom (hexadecimal notation) in the address space of the microcomputer, the internal rom area is from address c080 16 to fffd 16 . the reset vector is stored in addresses fffc 16 and fffd 16 . (1) set the data in the unused area (the shaded area of the diagram) to ff 16 . (2) the ascii codes of the product name m38002m4d must be entered in addresses 0000 16 to 0008 16 . and set the data ff 16 in addresses 0009 16 to 000f 16 . the ascii codes and addresses are listed to the right in hexadecimal notation. address 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 m = 4d 16 3 = 33 16 8 = 38 16 0 = 30 16 0 = 30 16 2 = 32 16 m = 4d 16 4 = 34 16 address 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 d = 44 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 (1/2) eprom address eprom address eprom type (indicate the type used) 0000 16 000f 16 0010 16 c07f 16 c080 16 fffd 16 fffe 16 ffff 16 product name ascii code : m38002m4d data rom 16254 bytes product name ascii code : m38002m4d data rom 16254 bytes
appendix 3.6 mask rom ordering method 3-44 3800 group users manual 740 family mask rom confirmation form single-chip microcomputer m38002m4dxxxsp/fp mitsubishi electric gzz-sh05-12b<21a0> mask rom number we recommend the use of the following pseudo-command to set the start address of the assembler source program. 27256 27512 eprom type the pseudo-command *= a $8000 .byte a m38002m4d *= a $0000 .byte a m38002m4d note : if the name of the product written to the eproms does not match the name of the mask confirmation form, the rom will not be processed. (2/2) h 2. mark specification mark specification must be submitted using the correct form for the package being ordered. fill out the appropriate mark specification form (64p4b for m38002m4dxxxsp, 64p6n for m38002m4dxxxfp) and attach it to the mask rom confirmation form. h 3. usage conditions please answer the following questions about usage for use in our product inspection : (1) how will you use the x in -x out oscillator? at what frequency? f(x in ) = (2) in which operation mode will you use your microcomputer? h 4. comments ceramic resonator external clock input single-chip mode microprocessor mode quartz crystal other ( ) memory expansion mode mhz
appendix 3.6 mask rom ordering method 3-45 3800 group users manual gzz-sh04-62b<14b0> receipt 740 family mask rom confirmation form single-chip microcomputer m38003m6-xxxsp/fp/hp mitsubishi electric mask rom number date: section head signature supervisor signature company name note : please fill in all items marked h . customer h issuance signature date issued submitted by tel () date: supervisor h 1. confirmation specify the name of the product being ordered and the type of eproms submitted. three eproms are required for each pattern. if at least two of the three sets of eproms submitted contain identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms. microcomputer name : 27256 27512 0000 16 000f 16 0010 16 207f 16 2080 16 7ffd 16 7ffe 16 7fff 16 m38003m6-xxxsp checksum code for entire eprom (hexadecimal notation) in the address space of the microcomputer, the internal rom area is from address a080 16 to fffd 16 . the reset vector is stored in addresses fffc 16 and fffd 16 . (1) set the data in the unused area (the shaded area of the diagram) to ff 16 . (2) the ascii codes of the product name m38003m6C must be entered in addresses 0000 16 to 0008 16 . and set the data ff 16 in addresses 0009 16 to 000f 16 . the ascii codes and addresses are listed to the right in hexadecimal notation. address 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 m = 4d 16 3 = 33 16 8 = 38 16 0 = 30 16 0 = 30 16 3 = 33 16 m = 4d 16 6 = 36 16 address 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 C = 2d 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 (1/2) eprom address eprom address eprom type (indicate the type used) 0000 16 000f 16 0010 16 a07f 16 a080 16 fffd 16 fffe 16 ffff 16 product name ascii code : m38003m6C data rom 24446 bytes product name ascii code : m38003m6C data rom 24446 bytes m38003m6-xxxhp m38003m6-xxxfp
appendix 3.6 mask rom ordering method 3-46 3800 group users manual 740 family mask rom confirmation form single-chip microcomputer m38003m6-xxxsp/fp/hp mitsubishi electric gzz-sh04-62b<14b0> mask rom number we recommend the use of the following pseudo-command to set the start address of the assembler source program. 27256 27512 eprom type the pseudo-command *= a $8000 .byte a m38003m6C *= a $0000 .byte a m38003m6C note : if the name of the product written to the eproms does not match the name of the mask confirmation form, the rom will not be processed. (2/2) h 2. mark specification mark specification must be submitted using the correct form for the package being ordered. fill out the appropriate mark specification form (64p4b for m38003m6-xxxsp, 64p6n for m38003m6-xxxfp) and attach it to the mask rom confirmation form. m38003m6-xxxhp is specified to the standard mark. h 3. usage conditions please answer the following questions about usage for use in our product inspection : (1) how will you use the x in -x out oscillator? at what frequency? f(x in ) = (2) in which operation mode will you use your microcomputer? h 4. comments ceramic resonator external clock input single-chip mode microprocessor mode quartz crystal other ( ) memory expansion mode mhz
appendix 3.6 mask rom ordering method 3-47 3800 group users manual gzz-sh04-30b<13b0> receipt 740 family mask rom confirmation form single-chip microcomputer m38004m8-xxxsp/fp mitsubishi electric mask rom number date: section head signature supervisor signature company name note : please fill in all items marked h . customer h issuance signature date issued submitted by tel () date: supervisor h 1. confirmation specify the name of the product being ordered and the type of eproms submitted. three eproms are required for each pattern. if at least two of the three sets of eproms submitted contain identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms. microcomputer name : m38004m8-xxxsp m38004m8-xxxfp checksum code for entire eprom (hexadecimal notation) in the address space of the microcomputer, the internal rom area is from address 8080 16 to fffd 16 . the reset vector is stored in addresses fffc 16 and fffd 16 . (1) set the data in the unused area (the shaded area of the diagram) to ff 16 . (2) the ascii codes of the product name m38004m8C must be entered in addresses 0000 16 to 0008 16 . and set the data ff 16 in addresses 0009 16 to 000f 16 . the ascii codes and addresses are listed to the right in hexadecimal notation. address 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 m = 4d 16 3 = 33 16 8 = 38 16 0 = 30 16 0 = 30 16 4 = 34 16 m = 4d 16 8 = 38 16 address 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 C = 2d 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 (1/2) eprom type (indicate the type used) 27512 eprom address 0000 16 000f 16 0010 16 807f 16 8080 16 fffd 16 fffe 16 ffff 16 product name ascii code : m38004m8C data rom 32638 bytes
appendix 3.6 mask rom ordering method 3-48 3800 group users manual 27512 *= a $0000 .byte a m38004m8C 740 family mask rom confirmation form single-chip microcomputer m38004m8-xxxsp/fp mitsubishi electric gzz-sh04-30b<13b0> mask rom number we recommend the use of the following pseudo-command to set the start address of the assembier source program. eprom type the pseudo-command note : if the name of the product written to the eproms does not match the name of the mask confirmation form, the rom will not be processed. we recommend the use of the following pseudo-command to set the start address of the assembler source program. (2/2) h 2. mark specification mark specification must be submitted using the correct form for the package being ordered. fill out the appropriate mark specification form (64p4b for m38004m8-xxxsp, 64p6n for m38004m8-xxxfp) and attach it to the mask rom confirmation form. h 3. usage conditions please answer the following questions about usage for use in our product inspection : (1) how will you use the x in -x out oscillator? at what frequency? f(x in ) = (2) in which operation mode will you use your microcomputer? h 4. comments ceramic resonator external clock input single-chip mode microprocessor mode quartz crystal other ( ) memory expansion mode mhz
appendix 3.6 mask rom ordering method 3-49 3800 group users manual gzz-sh07-23b<33a0> receipt 740 family mask rom confirmation form single-chip microcomputer m38004m8dxxxsp/fp mitsubishi electric mask rom number date: section head signature supervisor signature company name note : please fill in all items marked h . customer h issuance signature date issued submitted by tel () date: supervisor h 1. confirmation specify the name of the product being ordered and the type of eproms submitted. three eproms are required for each pattern. if at least two of the three sets of eproms submitted contain identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms. microcomputer name : m38004m8dxxxsp m38004m8dxxxfp checksum code for entire eprom (hexadecimal notation) in the address space of the microcomputer, the internal rom area is from address 8080 16 to fffd 16 . the reset vector is stored in addresses fffc 16 and fffd 16 . (1) set the data in the unused area (the shaded area of the diagram) to ff 16 . (2) the ascii codes of the product name m38004m8d must be entered in addresses 0000 16 to 0008 16 . and set the data ff 16 in addresses 0009 16 to 000f 16 . the ascii codes and addresses are listed to the right in hexadecimal notation. address 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 m = 4d 16 3 = 33 16 8 = 38 16 0 = 30 16 0 = 30 16 4 = 34 16 m = 4d 16 8 = 38 16 address 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 d = 44 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 (1/2) eprom type (indicate the type used) 27512 eprom address 0000 16 000f 16 0010 16 807f 16 8080 16 fffd 16 fffe 16 ffff 16 product name ascii code : m38004m8d data rom 32638 bytes
appendix 3.6 mask rom ordering method 3-50 3800 group users manual 27512 *= a $0000 .byte a m38004m8d 740 family mask rom confirmation form single-chip microcomputer m38004m8dxxxsp/fp mitsubishi electric gzz-sh07-23b<33a0> mask rom number we recommend the use of the following pseudo-command to set the start address of the assembier source program. eprom type the pseudo-command note : if the name of the product written to the eproms does not match the name of the mask confirmation form, the rom will not be processed. we recommend the use of the following pseudo-command to set the start address of the assembler source program. (2/2) h 2. mark specification mark specification must be submitted using the correct form for the package being ordered. fill out the appropriate mark specification form (64p4b for m38004m8dxxxsp, 64p6n for m38004m8dxxxfp) and attach it to the mask rom confirmation form. h 3. usage conditions please answer the following questions about usage for use in our product inspection : (1) how will you use the x in -x out oscillator? at what frequency? f(x in ) = (2) in which operation mode will you use your microcomputer? h 4. comments ceramic resonator external clock input single-chip mode microprocessor mode quartz crystal other ( ) memory expansion mode mhz
appendix 3.7 mark specification form 3-51 3800 group users manual 3.7 mark specification form
appendix 3.7 mark specification form 3-52 3800 group users manual
appendix 3.8 package outline 3-53 3800 group users manual 3.8 package outline 2.5/1 2.5/1
appendix 3.8 package outline 3-54 3800 group users manual 2.5/1 1.5/1
appendix 3.8 package outline 3-55 3800 group users manual 1.5/1
appendix 3.9 machine instructions 3-56 3800 group users manual addressing mode symbol function details imp imm a bit, a zp bit, zp op n # op n # op n # op n # op n # op n # 3.9 machine instructions adds the carry, accumulator and memory con- tents. the results are entered into the accumulator. adds the contents of the memory in the ad- dress indicated by index register x, the contents of the memory specified by the ad- dressing mode and the carry. the results are entered into the memory at the address indi- cated by index register x. ands the accumulator and memory con- tents. the results are entered into the accumulator. ands the contents of the memory of the ad- dress indicated by index register x and the contents of the memory specified by the ad- dressing mode. the results are entered into the memory at the address indicated by index register x. shifts the contents of accumulator or contents of memory one bit to the left. the low order bit of the accumulator or memory is cleared and the high order bit is shifted into the carry flag. branches when the contents of the bit speci- fied in the accumulator or memory is 0. branches when the contents of the bit speci- fied in the accumulator or memory is 1. branches when the contents of carry flag is 0. branches when the contents of carry flag is 1. branches when the contents of zero flag is 1. ands the contents of accumulator and memory. the results are not entered any- where. branches when the contents of negative flag is 1. branches when the contents of zero flag is 0. branches when the contents of negative flag is 0. jumps to address specified by adding offset to the program counter. executes a software interrupt. adc (note 1) (note 5) and (note 1) asl bbc (note 4) bbs (note 4) bcc (note 4) bcs (note 4) beq (note 4) bit bmi (note 4) bne (note 4) bpl (note 4) bra brk 00 7 0 c ? ? 0 71 29 2 2 0a 2 1 03 + 2i 17 + 2i 07 + 2i 06 5 2 25 3 2 3 65 3 2 69 2 2 4 4 2 2 13 + 2i 5 5 3 3 24 when t = 0 a ? a + m + c when t = 1 m(x) ? m(x) + m + c when t = 0 a ? a m when t = 1 m(x) ? m(x) m ab or mb = 0? ab or mb = 1? c = 0? c = 1? z = 1? a m n = 1? z = 0? n = 0? pc ? pc offset b ? 1 m(s) ? pc h s ? s C 1 m(s) ? pc l s ? s C 1 m(s) ? ps s ? s C 1 pc l ? ad l pc h ? ad h v v v 2
3800 group users manual appendix 3.9 machine instructions addressing mode zp, x zp, y abs abs, x abs, y ind zp, ind ind, x ind, y rel sp 7 6 5 4 3 2 1 0 proc essor st atus register nvtbd i zc op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # 3-57 75 35 16 4 4 6 2 2 2 6d 2d 0e 2c 4 4 6 4 3 3 3 3 7d 3d 1e 5 5 7 3 3 3 79 39 5 5 3 3 61 21 6 6 2 2 90 b0 f0 30 d0 10 80 2 2 2 2 2 2 4 2 2 2 2 2 2 2 71 31 6 6 2 2 n n n ? ? ? ? ? m 7 ? ? ? ? ? v ? ? ? ? ? ? ? m 6 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 z z z ? ? ? ? ? z ? ? ? ? ? c ? c ? ? ? ? ? ? ? ? ? ? ?
appendix 3.9 machine instructions 3-58 3800 group users manual addressing mode symbol function details imp imm a bit, a zp bit, zp op n # op n # op n # op n # op n # op n # branches when the contents of overflow flag is 0. branches when the contents of overflow flag is 1. clears the contents of the bit specified in the accumulator or memory to 0. clears the contents of the carry flag to 0. clears the contents of decimal mode flag to 0. clears the contents of interrupt disable flag to 0. clears the contents of index x mode flag to 0. clears the contents of overflow flag to 0. compares the contents of accumulator and memory. compares the contents of the memory speci- fied by the addressing mode with the contents of the address indicated by index register x. forms a ones complement of the contents of memory, and stores it into memory. compares the contents of index register x and memory. compares the contents of index register y and memory. decrements the contents of the accumulator or memory by 1. decrements the contents of index register x by 1. decrements the contents of index register y by 1. divides the 16-bit data that is the contents of m (zz + x + 1) for high byte and the contents of m (zz + x) for low byte by the accumulator. stores the quotient in the accumulator and the 1s complement of the remainder on the stack. exclusive-ors the contents of accumulator and memory. the results are stored in the ac- cumulator. exclusive-ors the contents of the memory specified by the addressing mode and the contents of the memory at the address indi- cated by index register x. the results are stored into the memory at the address indi- cated by index register x. increments the contents of accumulator or memory by 1. increments the contents of index register x by 1. increments the contents of index register y by 1. bvc (note 4) bvs (note 4) clb clc cld cli clt clv cmp (note 3) com cpx cpy dec dex dey div eor (note 1) inc inx iny v = 0? v = 1? ab or mb ? 0 c ? 0 d ? 0 i ? 0 t ? 0 v ? 0 when t = 0 a C m when t = 1 m(x) C m m ? m x C m y C m a ? a C 1 or m ? m C 1 x ? x C 1 y ? y C 1 a ? (m(zz + x + 1), m(zz + x)) / a m(s) ? 1s complememt of remainder s ? s C 1 when t = 0 a ? a v C m when t = 1 m(x) ? m(x) v C m a ? a + 1 or m ? m + 1 x ? x + 1 y ? y + 1 18 d8 58 12 b8 ca 88 e8 c8 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 c9 e0 c0 49 2 2 2 2 2 2 2 2 1a 3a 2 2 1 1 1b + 2i c5 44 e4 c4 c6 45 e6 3 5 3 3 5 3 5 2 2 2 2 2 2 2 1f + 2i 21 52
3800 group users manual appendix 3.9 machine instructions addressing mode zp, x zp, y abs abs, x abs, y ind zp, ind ind, x ind, y rel sp 7 6 5 4 3 2 1 0 proc essor st atus register nvtbd i zc op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # 3-59 d5 d6 e2 55 f6 cd ec cc ce 4d ee 50 70 2 2 2 2 ? ? ? ? ? ? ? ? n n n n n n n ? n n n n ? ? ? ? ? ? ? 0 ? ? ? ? ? ? ? ? ? ? ? ? 4 6 16 4 6 4 4 4 6 4 6 3 3 3 3 3 3 dd de 5d fe 5 7 5 7 3 3 3 3 d9 59 5 5 3 3 c1 41 6 6 2 2 d1 51 6 6 2 2 ? ? ? ? ? ? 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? z z z z z z z ? z z z z ? ? ? 0 ? ? ? ? c ? c c ? ? ? ? ? ? ? ? 2 2 2 2 2
appendix 3.9 machine instructions 3-60 3800 group users manual addressing mode symbol function details imp imm a bit, a zp bit, zp op n # op n # op n # op n # op n # op n # jumps to the specified address. after storing contents of program counter in stack, and jumps to the specified address. load accumulator with contents of memory. load memory indicated by index register x with contents of memory specified by the ad- dressing mode. load memory with immediate value. load index register x with contents of memory. load index register y with contents of memory. shift the contents of accumulator or memory to the right by one bit. the low order bit of accumulator or memory is stored in carry, 7th bit is cleared. multiplies the accumulator with the contents of memory specified by the zero page x address- ing mode and stores the high byte of the result on the stack and the low byte in the accumula- tor. no operation. logical ors the contents of memory and ac- cumulator. the result is stored in the accumulator. logical ors the contents of memory indi- cated by index register x and contents of memory specified by the addressing mode. the result is stored in the memory specified by index register x. jmp jsr lda (note 2) ldm ldx ldy lsr mul nop ora (note 1) if addressing mode is abs pc l ? ad l pc h ? ad h if addressing mode is ind pc l ? m (ad h , ad l ) pc h ? m (ad h , ad l + 1) if addressing mode is zp, ind pc l ? m(00, ad l ) pc h ? m(00, ad l + 1) m(s) ? pc h s ? s C 1 m(s) ? pc l s ? s C 1 after executing the above, if addressing mode is abs, pc l ? ad l pc h ? ad h if addressing mode is sp, pc l ? ad l pc h ? ff if addressing mode is zp, ind, pc l ? m(00, ad l ) pc h ? m(00, ad l + 1) when t = 0 a ? m when t = 1 m(x) ? m m ? nn x ? m y ? m m(s) a ? a 5 m(zz + x) s ? s C 1 pc ? pc + 1 when t = 0 a ? a v m when t = 1 m(x) ? m(x) v m a9 a2 a0 09 4a 2 1 a5 3c a6 a4 46 05 3 4 3 3 5 3 2 3 2 2 2 2 ea 2 1 2 2 2 2 2 2 2 2 7 0 0 ? ? c
3800 group users manual appendix 3.9 machine instructions addressing mode zp, x zp, y abs abs, x abs, y ind zp, ind ind, x ind, y rel sp 7 6 5 4 3 2 1 0 proc essor st atus register nvtbd i zc op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # 3-61 b5 b4 56 62 15 4c 20 ad ae ac 4e 0d 6c a1 01 ? ? n ? n n 0 ? ? n ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? z ? z z z ? ? z ? ? ? ? ? ? c ? ? ? 4 4 6 15 4 2 2 2 2 2 b6 4 2 3 6 4 4 4 6 4 3 3 3 3 3 3 3 bd bc 5e 1d 5 5 7 5 b9 be 19 5 5 5 3 3 3 3 3 3 3 53b2 02 4 7 2 2 6 6 2 2 b1 11 6 6 2 2 22 5 2
appendix 3.9 machine instructions 3-62 3800 group users manual addressing mode symbol function details imp imm a bit, a zp bit, zp op n # op n # op n # op n # op n # op n # saves the contents of the accumulator in memory at the address indicated by the stack pointer and decrements the contents of stack pointer by 1. saves the contents of the processor status register in memory at the address indicated by the stack pointer and decrements the contents of the stack pointer by 1. increments the contents of the stack pointer by 1 and restores the accumulator from the memory at the address indicated by the stack pointer. increments the contents of stack pointer by 1 and restores the processor status register from the memory at the address indicated by the stack pointer. shifts the contents of the memory or accumu- lator to the left by one bit. the high order bit is shifted into the carry flag and the carry flag is shifted into the low order bit. shifts the contents of the memory or accumu- lator to the right by one bit. the low order bit is shifted into the carry flag and the carry flag is shifted into the high order bit. rotates the contents of memory to the right by 4 bits. returns from an interrupt routine to the main routine. returns from a subroutine to the main routine. subtracts the contents of memory and complement of carry flag from the contents of accumulator. the results are stored into the accumulator. subtracts contents of complement of carry flag and contents of the memory indicated by the addressing mode from the memory at the ad- dress indicated by index register x. the results are stored into the memory of the ad- dress indicated by index register x. sets the specified bit in the accumulator or memory to 1. sets the contents of the carry flag to 1. sets the contents of the decimal mode flag to 1. sets the contents of the interrupt disable flag to 1. sets the contents of the index x mode flag to 1. pha php pla plp rol ror rrf rti rts sbc (note 1) (note 5) seb sec sed sei set m(s) ? a s ? s C 1 m(s) ? ps s ? s C 1 s ? s + 1 a ? m(s) s ? s + 1 ps ? m(s) s ? s + 1 ps ? m(s) s ? s + 1 pc l ? m(s) s ? s + 1 pc h ? m(s) s ? s + 1 pc l ? m(s) s ? s + 1 pc h ? m(s) when t = 0 a ? a C m C c when t = 1 m(x) ? m(x) C m C c ab or mb ? 1 c ? 1 d ? 1 i ? 1 t ? 1 e9 2a 6a 26 66 82 e5 48 08 68 28 40 60 38 f8 78 32 7 0 ? ? c ? 7 0 ? ? 3 3 4 4 6 6 2 2 2 2 1 1 1 1 1 1 1 1 1 1 22 2 2 1 1 0b + 2i 5 5 8 3 2 2 2 2 0f + 2i 21 52 7 0 c ? ?
3800 group users manual appendix 3.9 machine instructions addressing mode zp, x zp, y abs abs, x abs, y ind zp, ind ind, x ind, y rel sp 7 6 5 4 3 2 1 0 proc essor st atus register nvtbd i zc op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # 3-63 36 76 f5 2e 6e ed ? ? n n n ? ? n ? ? ? ? ? ? ? ? ? ? ? ? v ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 ? ? ? ? ? ? ? ? ? ? ? ? ? 1 ? ? ? z z z ? ? z ? ? ? ? ? ? ? ? c c ? ? c ? 1 ? ? ? 6 6 4 2 2 2 6 6 4 3 3 3 3e 7e fd 7 7 5 3 3 3f95 3 e16 2f16 2 (value saved in stack) (value saved in stack)
appendix 3.9 machine instructions 3-64 3800 group users manual addressing mode symbol function details imp imm a bit, a zp bit, zp op n # op n # op n # op n # op n # op n # stores the contents of accumulator in memory. stops the oscillator. stores the contents of index register x in memory. stores the contents of index register y in memory. transfers the contents of the accumulator to index register x. transfers the contents of the accumulator to index register y. tests whether the contents of memory are 0 or not. transfers the contents of the stack pointer to index register x. transfers the contents of index register x to the accumulator. transfers the contents of index register x to the stack pointer. transfers the contents of index register y to the accumulator. stops the internal clock. sta stp stx sty tax tay tst tsx txa txs tya wit m ? a m ? x m ? y x ? a y ? a m = 0? x ? s a ? x s ? x a ? y 42 aa a8 ba 8a 9a 98 c2 85 86 84 64 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 4 4 4 3 2 2 2 2 notes 1 : the number of cycles n is increased by 3 when t is 1. 2 : the number of cycles n is increased by 2 when t is 1. 3 : the number of cycles n is increased by 1 when t is 1. 4 : the number of cycles n is increased by 2 when branching has occurred. 5 : n, v, and z flags are invalid in decimal operation mode.
3800 group users manual appendix 3.9 machine instructions addressing mode zp, x zp, y abs abs, x abs, y ind zp, ind ind, x ind, y rel sp 7 6 5 4 3 2 1 0 proc essor st atus register nvtbd i zc op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # 3-65 95 94 ? ? ? ? n n n n n ? n ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? z z z z z ? z ? ? ? ? ? ? ? ? ? ? ? ? ? addition subtraction logical or logical and logical exclusive or negation shows direction of data flow index register x index register y stack pointer program counter processor status register 8 high-order bits of program counter 8 low-order bits of program counter 8 high-order bits of address 8 low-order bits of address ff in hexadecimal notation immediate value memory specified by address designation of any ad- dressing mode memory of address indicated by contents of index register x memory of address indicated by contents of stack pointer contents of memory at address indicated by ad h and ad l , in ad h is 8 high-order bits and ad l is 8 low-or- der bits. contents of address indicated by zero page ad l 1 bit of accumulator 1 bit of memory opcode number of cycles number of bytes 5 5 2 2 96 5 2 8d 8e 8c 5 5 5 3 3 3 9d639963 81729172 implied addressing mode immediate addressing mode accumulator or accumulator addressing mode accumulator bit relative addressing mode zero page addressing mode zero page bit relative addressing mode zero page x addressing mode zero page y addressing mode absolute addressing mode absolute x addressing mode absolute y addressing mode indirect absolute addressing mode zero page indirect absolute addressing mode indirect x addressing mode indirect y addressing mode relative addressing mode special page addressing mode carry flag zero flag interrupt disable flag decimal mode flag break flag x-modified arithmetic mode flag overflow flag negative flag imp imm a bit, a zp bit, zp zp, x zp, y abs abs, x abs, y ind zp, ind ind, x ind, y rel sp c z i d b t v n symbol contents symbol contents + C v v C C ? x y s pc ps pc h pc l ad h ad l ff nn m m(x) m(s) m(ad h , ad l ) m(00, ad l ) ab mb op n # v
3800 group users manual appendix 3.10 list of instruction codes 3-66 3.10 list of instruction codes 3-byte instruction 2-byte instruction 1-byte instruction d 7 C d 4 d 3 C d 0 hexadecimal notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 a b c d e f 0001 1 ora ind, x ora ind, y and ind, x and ind, y eor ind, x eor ind, y adc ind, x adc ind, y sta ind, x sta ind, y lda ind, x lda ind, y cmp ind, x cmp ind, y sbc ind, x sbc ind, y 0010 2 jsr zp, ind clt jsr sp set stp mul zp, x rrf zp ldx imm jmp zp, ind wit div zp, x 0011 3 bbs 0, a bbc 0, a bbs 1, a bbc 1, a bbs 2, a bbc 2, a bbs 3, a bbc 3, a bbs 4, a bbc 4, a bbs 5, a bbc 5, a bbs 6, a bbc 6, a bbs 7, a bbc 7, a 0100 4 bit zp com zp tst zp sty zp sty zp, x ldy zp ldy zp, x cpy zp cpx zp 0101 5 ora zp ora zp, x and zp and zp, x eor zp eor zp, x adc zp adc zp, x sta zp sta zp, x lda zp lda zp, x cmp zp cmp zp, x sbc zp sbc zp, x 0110 6 asl zp asl zp, x rol zp rol zp, x lsr zp lsr zp, x ror zp ror zp, x stx zp stx zp, y ldx zp ldx zp, y dec zp dec zp, x inc zp inc zp, x 0111 7 bbs 0, zp bbc 0, zp bbs 1, zp bbc 1, zp bbs 2, zp bbc 2, zp bbs 3, zp bbc 3, zp bbs 4, zp bbc 4, zp bbs 5, zp bbc 5, zp bbs 6, zp bbc 6, zp bbs 7, zp bbc 7, zp 1000 8 php clc plp sec pha cli pla sei dey tya tay clv iny cld inx sed 1001 9 ora imm ora abs, y and imm and abs, y eor imm eor abs, y adc imm adc abs, y sta abs, y lda imm lda abs, y cmp imm cmp abs, y sbc imm sbc abs, y 1010 a asl a dec a rol a inc a lsr a ror a txa txs tax tsx dex nop 1011 b seb 0, a clb 0, a seb 1, a clb 1, a seb 2, a clb 2, a seb 3, a clb 3, a seb 4, a clb 4, a seb 5, a clb 5, a seb 6, a clb 6, a seb 7, a clb 7, a 1100 c bit abs ldm zp jmp abs jmp ind sty abs ldy abs ldy abs, x cpy abs cpx abs 1101 d ora abs ora abs, x and abs and abs, x eor abs eor abs, x adc abs adc abs, x sta abs sta abs, x lda abs lda abs, x cmp abs cmp abs, x sbc abs sbc abs, x 1110 e asl abs asl abs, x rol abs rol abs, x lsr abs lsr abs, x ror abs ror abs, x stx abs ldx abs ldx abs, y dec abs dec abs, x inc abs inc abs, x 1111 f seb 0, zp clb 0, zp seb 1, zp clb 1, zp seb 2, zp clb 2, zp seb 3, zp clb 3, zp seb 4, zp clb 4, zp seb 5, zp clb 5, zp seb 6, zp clb 6, zp seb 7, zp clb 7, zp 0000 0 brk bpl jsr abs bmi rti bvc rts bvs bra bcc ldy imm bcs cpy imm bne cpx imm beq
appendix 3.11 sfr memory map 3-67 3800 group users manual 3.11 sfr memory map 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 port p0 (p0) port p0 direction register (p0d) port p1 (p1) port p1 direction register (p1d) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p3 direction register (p3d) port p4 (p4) port p4 direction register (p4d) port p5 (p5) port p5 direction register (p5d) port p6 (p6) port p6 direction register (p6d) port p7 (p7) port p7 direction register (p7d) transmit/receive buffer register (tb/rb) serial i/o status register (siosts) serial i/o control register (siocon) uart control register (uartcon) baud rate generator (brg) 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 prescaler 12 (pre12) timer 1 (t1) timer 2 (t2) timer xy mode register (tm) prescaler x (prex) timer x (tx) prescaler y (prey) timer y (ty) interrupt edge selection register (intedge) cpu mode register (cpum) interrupt request register 1 (ireq1) interrupt request register 2 (ireq2) interrupt control register 1 (icon1) interrupt control register 2 (icon2)
appendix 3.12 pin configuration 3-68 3800 group users manual m38002m4-xxxfp m38003m6-xxxhp 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p3 3 /reset out p3 4 / f p3 5 /sync p3 7 /rd p3 6 /wr p3 2 /onw p6 4 p6 6 p6 7 p7 0 p7 1 v cc p3 0 p3 1 p6 3 p6 5 p6 2 p6 1 p6 0 p5 7 p5 6 p5 5 /cntr 1 p5 4 /cntr 0 p5 3 /int 5 p5 2 /int 4 p5 1 /int 3 p5 0 /int 2 p4 7 /s rdy p4 6 /s clk p4 3 /int 1 p4 4 /r x d p4 5 /t x d p2 4 /db 4 p2 3 /db 3 p2 2 /db 2 p2 0 /db 0 p2 1 /db 1 p2 5 /db 5 cnv ss p4 1 p4 0 x in x out v ss p2 7 /db 7 p2 6 /db 6 p4 2 /int 0 reset p0 0 /ad 0 p0 1 /ad 1 p0 2 /ad 2 p0 3 /ad 3 p0 4 /ad 4 p0 5 /ad 5 p0 6 /ad 6 p0 7 /ad 7 p1 0 /ad 8 p1 1 /ad 9 p1 2 /ad 10 p1 3 /ad 11 p1 4 /ad 12 p1 7 /ad 15 p1 6 /ad 14 p1 5 /ad 13 3.12 pin configuration pin configuration (top view) package type : 64p6n-a/64p6d-a 64-pin plastic-molded qfp
appendix 3.12 pin configuration 3-69 3800 group users manual pin configuration (top view) package type : 64p4b 64-pin shrink plastic-molded dip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p6 4 p6 6 p6 7 p7 0 p7 1 v cc p6 3 p6 5 p6 2 p6 1 p6 0 p5 7 p5 6 p5 5 /cntr 1 p5 4 /cntr 0 p5 3 /int 5 p5 2 /int 4 p5 1 /int 3 p5 0 /int 2 p4 7 /s rdy p4 6 /s clk p4 3 /int 1 p4 4 /r x d p4 5 /t x d cnv ss p4 1 p4 0 x in x out v ss p4 2 /int 0 reset p2 4 /db 4 p2 3 /db 3 p2 2 /db 2 p2 0 /db 0 p2 1 /db 1 p2 5 /db 5 p2 7 /db 7 p2 6 /db 6 p3 3 /reset out p3 4 / f p3 5 /sync p3 7 /rd p3 6 /wr p3 2 /onw p3 0 p3 1 p0 0 /ad 0 p0 1 /ad 1 p0 2 /ad 2 p0 3 /ad 3 p0 4 /ad 4 p0 5 /ad 5 p0 6 /ad 6 p0 7 /ad 7 p1 0 /ad 8 p1 1 /ad 9 p1 2 /ad 10 p1 3 /ad 11 p1 4 /ad 12 p1 7 /ad 15 p1 6 /ad 14 p1 5 /ad 13 m38002m4-xxxsp
mitsubishi semiconductors users manual 3800group mar. first edition 1996 editioned by committee of editing of mitsubishi semiconductor users manual published by mitsubishi electric corp., semiconductor marketing division this book, or parts thereof, may not be reproduced in any form without permission of mitsubishi electric corporation. ?1996 mitsubishi electric corporation
users manual 3800 group h-ee418-a ki-9603 printed in japan (rod) ? 1996 mitsubishi electric corporation new publication, effective mar. 1996. specifications subject to change without notice.

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