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| preliminary data sheet september 2000 3X38FTR 208-pin sqfp octal-fet (fast ethernet transceiver) for 10base-t/100base-tx/ fx overview the 3X38FTR 208-pin sqfp is an eight-channel, single-chip complete transceiver designed specifi- cally for dual-speed 10base-t, 100base-tx, and 100base-fx switches and repeaters. it supports simultaneous operation in three separate ieee * standard modes: 10base-t, 100base-tx, and 100base-fx. the 3x38 uses 0.25 m m low-power cmos to achieve extremely low power dissipation and operates from a single 3.3 v power supply. each channel implements the following: n 10base-t transceiver function of ieee 802.3. n 100base-tx transceiver function of ieee 802.3u. n 100base-fx transceiver function of ieee 802.3u. n autonegotiation of ieee 802.3u. n mii management of ieee 802.3u. the 3x38 supports operations over two pairs of unshielded twisted-pair (utp) cable (10base-t and 100base-tx) and over fiber-optic cable (100base- fx). it has been designed with a flexible system interface that allows configuration for optimum performance and effortless design. the individual per-port system interface can be configured as 10 mbits/s, or 100 mbits/s reduced mii (rmii), or 10 mbits/s, or 100 mbits/s serial mii (smii). features 10 mbits/s transceiver n compatible with ieee 802.3 10base-t standard for category 3 unshielded twisted-pair (utp) cable. n compatible with the reduced mii (rmii) specifica- tion of the rmii consortium version 1.2. n selectable 7-pin rmii or 2-pin serial mii (smii). n autopolarity detection and correction. n adjustable squelch level for extended line length capability (two levels). n on-chip filtering eliminates the need for external filters. n half- and full-duplex operations. 100 mbits/s tx transceiver n compatible with ieee 802.3u pcs (clause 23), pma (clause 24), autonegotiation (clause 28), and pmd (clause 25) specifications. n compatible with the reduced mii (rmii) specifica- tion of the rmii consortium version 1.2. n selectable 7-pin rmii, 2-pin smii (serial mii). n scrambler/descrambler bypass. n selectable carrier sense signal generation (crs) asserted during either transmission or reception in half duplex (crs asserted during reception only in full duplex). n full- or half-duplex operations. n on-chip filtering and adaptive equalization that eliminates the need for external filters. 100 mbits/s fx transceiver n pseudo-ecl compatible input/output for 100base- fx support (with fiber-optic signal detect). n compatible with ieee 802.3u 100base-fx stan- dard. n reuses existing twisted-pair i/o pins for compati- ble fiber-optic transceiver pseudo-ecl (pecl) data: no additional data pins required. reuses existing 3x38 pins for fiber-optic signal detect (fosd) inputs. * ieee is a registered trademark of the institute of electrical and electronics engineers, inc.
2 lucent technologies inc. 3X38FTR 208-pin sqfp preliminary data sheet octal-fet for 10base-t/100base-tx/fx september 2000 features (continued) n fiber mode automatically configures port: disables autonegotiation. disables 10base-t. enables 100base-fx far-end fault signaling. disables mlt-3 encoder/decoder. disables scrambler/descrambler. n fx mode enable is pin- or register-selectable on an individual per-port basis. general n low power dissipation (<0.4 w per port). n autonegotiation ( ieee 802.3u, clause 28): fast link pulse (flp) burst generator. arbitration function. n supports the station management protocol and frame format (clause 22): basic and extended registers. supports next page mode. accepts preamble suppression. maskable status interrupts. 12.5 mhz mdc clock rate. n supports the following management functions via pins if mii station management is unavailable: speed select. scrambler/descrambler bypass. full duplex. no link pulse mode. carrier sense select. autonegotiation. fx mode select. n single 50 mhz/125 mhz clock input in rmii and smii modes, respectively. n supports half- and full-duplex operations. n provides four led status signals: activity (transmit or receive). optional led blink mode (500 ms on, 500 ms off or 2.5 s on, 2.5 s off) or pulse stretch mode (40 ms80 ms). full duplex or collision, automatically configured. link integrity. speed indication. n internally generated power-on-reset configures 3x38 automatically on powerup. n serial led output stream for additional status moni- toring. n bicolor led mode. n led drivers on-chip (8 ma10 ma). drivers can be turned off when led is not used (power saving). n per-channel powerdown mode for 10 mbits/s and 100 mbits/s operation. n loopback for 10 mbits/s and 100 mbits/s operation. n internal pull-up or pull-down resistors to set default configuration during powerup. n 0.25 m m low-power cmos technology. n 208-pin sqfp package. n jtag boundary scan. n single 3.3 v power supply. lucent technologies inc. 3 preliminary data sheet 3X38FTR 208-pin sqfp september 2000 octal-fet for 10base-t/100base-tx/fx table of contents contents page overview....................................................................................................................... ............................................................................ 1 features....................................................................................................................... ............................................................................. 1 10 mbits/s transceiver ......................................................................................................... .................................................................. 1 100 mbits/s tx transceiver..................................................................................................... ............................................................... 1 100 mbits/s fx transceiver..................................................................................................... ............................................................... 1 general........................................................................................................................ .......................................................................... 2 description.................................................................................................................... ............................................................................ 5 rmii mode ...................................................................................................................... ....................................................................... 5 smii mode ...................................................................................................................... ....................................................................... 5 led control .................................................................................................................... ....................................................................... 5 clocking ....................................................................................................................... .......................................................................... 5 fx mode ........................................................................................................................ ........................................................................ 5 single-channel detail functions ................................................................................................ ........................................................... 7 block diagrams................................................................................................................. ..................................................................... 8 pin information ................................................................................................................ ....................................................................... 10 pin diagram for rmii mode ...................................................................................................... ........................................................... 10 pin diagram for smii mode ...................................................................................................... ........................................................... 11 pin maps....................................................................................................................... ....................................................................... 15 pin descriptions............................................................................................................... ....................................................................... 16 functional description ......................................................................................................... ................................................................... 27 reduced media independent interface (rmii)..................................................................................... ................................................ 27 rmii/smii interface............................................................................................................ .................................................................. 29 media independent interface (mii)internal ..................................................................................... .................................................. 31 100base-x module ............................................................................................................... ............................................................... 32 100base-tx transceiver......................................................................................................... ............................................................. 36 10base-t module ................................................................................................................ ................................................................ 37 operation modes ................................................................................................................ ................................................................. 37 led operational modes .......................................................................................................... ............................................................ 39 reset operation................................................................................................................ ................................................................... 43 mii station management ......................................................................................................... ............................................................... 44 basic operation ................................................................................................................ ................................................................... 44 unmanaged operations........................................................................................................... ............................................................ 45 register information ........................................................................................................... .................................................................... 46 register descriptions .......................................................................................................... ................................................................ 46 absolute maximum ratings ....................................................................................................... ............................................................. 56 clock timing ................................................................................................................... ........................................................................ 57 outline diagram................................................................................................................ ...................................................................... 63 208-pin sqfp ................................................................................................................... .................................................................. 63 tables page table 1. 3x38 signal in alphanumeric sequence according to pin number......................................................... ................................ 12 table 2. 3x38 rmii/smii pin map............................................................................................... ........................................................... 15 table 3. rmii/smii interface pins ............................................................................................. ............................................................. 16 table 4. mii management ....................................................................................................... ............................................................... 17 table 5. 10/100 mbits/s twisted-pair (tp) interface pins...................................................................... ................................................. 18 table 6. led and configuration pins........................................................................................... .......................................................... 18 table 7. table test mode pins ................................................................................................. .............................................................. 24 table 8. clock, reset, fosd, and special configuration pins ................................................................... ........................................... 25 table 9. power, ground, and no connects....................................................................................... ..................................................... 26 table 10. receive data/status encoding........................................................................................ ....................................................... 30 table 11. symbol code scrambler .............................................................................................. ......................................................... 33 table 12. led modes ........................................................................................................... ................................................................. 40 table 13. serial led pin descriptions ......................................................................................... .......................................................... 41 table 14. serial led port order ............................................................................................... ............................................................. 41 table 15. bicolor mode ........................................................................................................ .................................................................. 42 table 16. bicolor led mode descriptions ....................................................................................... ...................................................... 43 table 17. mii management frame format......................................................................................... .................................................... 44 table 18. mii management framesfield descriptions ............................................................................ ........................................... 44 table of contents (continued) tables (continued) page 3X38FTR 208-pin sqfp preliminary data sheet octal-fet for 10base-t/100base-tx/fx september 2000 4 lucent technologies inc. table 19. phy addresses ....................................................................................................... ...............................................................45 table 20. output pins ......................................................................................................... ....................................................................45 table 21. summary of management registers (mr) ................................................................................ .............................................46 table 22. mr0control register bit descriptions............................................................................... ..................................................46 table 23. mr1status register bit descriptions ................................................................................ ..................................................47 table 24. mr2, mr3phy identification registers (1 and 2) bit descriptions.................................................... .................................48 table 25. mr4autonegotiation advertisement register bit descriptions ......................................................... ..................................48 table 26. mr5autonegotiation link partner ability (base page) register bit descriptions...................................... ..........................49 table 27. mr5autonegotiation link partner (lp) ability register (next page) bit descriptions................................. ........................49 table 28. mr6autonegotiation expansion register bit descriptions............................................................. .....................................50 table 29. mr7next page transmit register bit descriptions .................................................................... .........................................50 table 30. mr20led and fifo configuration ..................................................................................... ................................................51 table 31. mr21rxer counter ................................................................................................... ........................................................51 table 32. mr28device-specific register 1 (status register) bit descriptions.................................................. .................................52 table 33. mr29device-specific register 2 (100 mbits/s control) bit descriptions .............................................. ..............................53 table 34. mr30device-specific register 3 (10 mbits/s control) bit descriptions ............................................... ...............................54 table 35. mr31device-specific register 4 (quick status) bit descriptions..................................................... ..................................55 table 36. absolute maximum ratings ............................................................................................ ........................................................56 table 37. operating conditions ................................................................................................ ..............................................................56 table 38. dc characteristics .................................................................................................. .................................................................56 table 39. system clock (rmii mode) ............................................................................................ .........................................................57 table 40. management clock .................................................................................................... .............................................................57 table 41. rmii receive timing................................................................................................. ..............................................................58 table 42. rmii transmit timing ................................................................................................ ..............................................................58 table 43. transmit timing..................................................................................................... ..................................................................59 table 44. smii timing......................................................................................................... ....................................................................59 table 45. receive timing ...................................................................................................... .................................................................60 table 46. reset and configuration timing ...................................................................................... .......................................................61 table 47. pmd characteristics ................................................................................................. ..............................................................62 figures page figure 1. 3x38 device overview ................................................................................................ ..............................................................6 figure 2. 3x38 single-channel detail functions ................................................................................ .....................................................7 figure 3. typical single-channel twisted-pair (tp) interface .................................................................. ................................................8 figure 4. typical single-channel fiber-optic (fx) interface ................................................................... .................................................9 figure 5. 3x38 pinout for rmii mode........................................................................................... ..........................................................10 figure 6. 3x38 pinout for smii mode ........................................................................................... ..........................................................11 figure 7. functional description .............................................................................................. ..............................................................27 figure 8. rmii receive timing from internal mii signals....................................................................... ................................................28 figure 9. smii connection diagram ............................................................................................. ..........................................................29 figure 10. receive sequence diagram ........................................................................................... ......................................................29 figure 11. transmit sequence diagram .......................................................................................... .......................................................30 figure 12. 100base-x data path ................................................................................................ ...........................................................32 figure 13. 10base-t module data path.......................................................................................... .......................................................37 figure 14. timing diagram..................................................................................................... ................................................................42 figure 15. hardware reset configuration....................................................................................... .......................................................43 figure 16. system clock ....................................................................................................... .................................................................57 figure 17. management clock ................................................................................................... ............................................................57 figure 18. rmii receive timing................................................................................................ .............................................................58 figure 19. rmii transmit timing ............................................................................................... .............................................................58 figure 20. transmit timing.................................................................................................... .................................................................59 figure 21. smii timing ........................................................................................................ ...................................................................59 figure 22. receive timing ..................................................................................................... ................................................................60 figure 23. reset and configuration timing..................................................................................... .......................................................61 figure 24. pmd characteristics ................................................................................................ .............................................................62 lucent technologies inc. 5 preliminary data sheet 3X38FTR 208-pin sqfp september 2000 octal-fet for 10base-t/100base-tx/fx description rmii mode the reduced media independent interface (rmii) is a low pin count interface specification promulgated by the rmii consortium. this specification reduces the total number of pins from 16 for the ieee 802.3u mii inter- face to seven for the rmii. architecturally, the rmii specification provides for an additional reconciliation sublayer on either side of the mii but, in the 3x38, has been implemented in the absence of the mii. the management interface (mdio/mdc) remains iden- tical to that defined in ieee 802.3u. the rmii specification has the following characteris- tics: n it supports 10 mbits/s and 100 mbits/s data rates. n a single 50 mhz clock reference is sourced from mac to phy or from an external shared source. n it provides independent 2-bit wide transmit and receive data paths. smii mode the serial media independent interface (smii) is a low pin count interface specification promulgated by cisco *. this specification reduces the total number of pins from 16 for the ieee 802.3u mii interface to two for the smii. architecturally, the smii specification pro- vides for an additional reconciliation sublayer on either side of the mii but, in the 3x38, has been implemented in the absence of the mii. the management interface (mdio/mdc) remains iden- tical to that defined in ieee 802.3u. the smii specification has the following characteristics: n it supports 10 mbits/s and 100 mbits/s data rates. n a single 125 mhz clock reference is sourced from mac to phy or from an external shared source. n it provides independent serial transmit and receive data paths. led control leds can be accessed in one of the following modes: n serial mode. in this mode, all of the leds are time- division multiplexed onto one pin, with a second pin acting as the clock and a third as a strobe. all leds and all channels share the same pins. n parallel mode. in this mode, each led and each channel has its own pin. there is a total of four led pins per channel for a total of 32 pins. n bicolor mode. in this mode, each channel has two outputs to control a bicolor led. one led can be used for each port, indicating link and activity. in all modes, the leds can be operated as follows: n led stretch. n led blink. n no stretch or blink. clocking the 3x38 operates with a 50 mhz clock input when in the rmii mode, and with a 125 mhz clock input when in the smii mode. fx mode each individual port of the 3x38 can be operated in 100base-fx mode by selecting it through the pin pro- gram option (fx_mode_en[7:0]), or through the reg- ister bit (register 29, bit 0). when operating in fx mode, the twisted-pair i/o pins are reused as the fiber-optic transceiver i/o data pins, and the fiber-optic signal detect (fosd) inputs are enabled. when a port is placed in fx mode, it will automatically configure the port for 100base-fx operation (and the register bit control will be ignored) such that: n the far-end fault signaling option will be enabled. n the mlt-3 encoding/decoding will be disabled. n scrambler/descrambler will be disabled. n autonegotiation will be disabled. n the signal detect inputs will be activated. n 10base-t will be disabled. * cisco is a registered trademark of cisco systems. 3X38FTR 208-pin sqfp preliminary data sheet octal-fet for 10base-t/100base-tx/fx september 2000 6 lucent technologies inc. description (continued) device overview 5-6878(f).c figure 1. 3x38 device overview 10 mbits/s transceiver autonegotiation pma pma tx pmd/ mux management pcs management pcs pll 25 mhz 125 mhz rmclk rmii/smii interface driver and filters driver and filters driver and filters tp magnetics interface fx port fx_mode_en tx pmd/ fx port rmii/smii interface 10 mbits/s transceiver autonegotiation mux driver and filters fx_mode_en port 0 port 7 port [16] 50 mhz/125 mhz rmii/smii interface lucent technologies inc. 7 preliminary data sheet 3X38FTR 208-pin sqfp september 2000 octal-fet for 10base-t/100base-tx/fx description (continued) single-channel detail functions 5-5136(f).kr2 figure 2. 3x38 single-channel detail functions tpin tpout autonegotiation and link monitor mtxd[3:0] 4b/5b encoder far-end fault gen. scrambler pdt sd pdr/ descrambler aligner 5b/4b decoder far-end fault detect 10 mbits/s transceiver 20 mhz mdc mdio mii tx state machine sd collision detect sd rx state machine rmii/ sync rxd txd rx_er rxd[1:0] crs_dv tx_en txd[1:0] management 25 mhz 125 mhz rmclk pmd tx pmd rx sd 100 mbits/s transceiver lc10 ls10 lc100 ls100 carrier cim detect rxerr_st car_stat smii rmii rmii/smii interface freq. 50 mh z /125 mh z management interface dcru synth. smii to mii 3X38FTR 208-pin sqfp preliminary data sheet octal-fet for 10base-t/100base-tx/fx september 2000 8 lucent technologies inc. description (continued) block diagrams single-channel twisted-pair interface 5-5433(f).sr1 figure 3. typical single-channel twisted-pair (tp) interface 3x38 rj-45 1 2 3 4 5 6 7 8 75 w 75 w 1:1 1:1 0.01 m f tpin+ tpinC tpout+ tpoutC 51.1 w 51.1 w v ddo 75 w 0.01 m f 75 w 50 w 50 w 0.01 m f 6 pf 1000 pf 2 kv lucent technologies inc. 9 preliminary data sheet 3X38FTR 208-pin sqfp september 2000 octal-fet for 10base-t/100base-tx/fx description (continued) single-channel fiber-optic interface * these terminations per fiber modules recommendation (as shown for siemens ? v23809-c8-c10). ? siemens is a registered trademark of siemens aktiegesellschaft. 5-5433(f).qr1 figure 4. typical single-channel fiber-optic (fx) interface 3x38 td tdn sd rd rdn 0.01 m f tpin+ tpinC tpout+ tpoutC 40 w 40 w v ddo 200 w * fosd 127 w 82.5 w * 127 w 82.5 w * v dd 0.01 m f 3.3 v fiber transceiver 3X38FTR 208-pin sqfp preliminary data sheet octal-fet for 10base-t/100base-tx/fx september 2000 10 lucent technologies inc. pin information pin diagram for rmii mode 5-8123(f) figure 5. 3x38 pinout for rmii mode 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 1 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 v dda 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 53 tpin+7/foin+7 tpinC7/foinC7 v dda tpin+6/foin+6 tpinC6/foinC6 v dda tpin+5/foin+5 tpinC5/foinC5 v dda tpin+4/foin+4 tpinC4/foinC4 v ss v dda tpin+3/foin+3 tpinC3/foinC3 v dda tpin+2/foin+2 tpinC2/foinC2 v dda tpin+1/foin+1 tpinC1/foinC1 v ss v dda tpin+0/foin+0 tpinC0/foinC0 v ss rextbs v dda v ddpll rmclk v ss v dda rext100 rext10 v ss tpoutC7/fooutC7 tpout+7/foout+7 tpoutC6/fooutC6 tpout+6/foout+6 tpoutC5/fooutC5 tpout+5/foout+5 tpoutC4/fooutC4 tpout+4/foout+4 tpoutC3/fooutC3 tpout+3/foout+3 tpoutC2/fooutC2 tpout+2/foout+2 tpoutC1/fooutC1 tpout+1/foout+1 tpoutC0/fooutC0 tpout+0/foout+0 rrxd1_1 rcrs_dv_1 rrxd0_1 rrxer_1 rtxd1_1 rtxen_1 rtxd0_1 v dd rrxd1_0 rcrs_dv_0 rrxd0_0 rrxer_0 v ss rtxd1_0 o_m rtxen_0 mask_stat_int rtxd0_0 v dd reset_not 3-state mdc mdio tmode4 tmode3 tmode2 tmode1 tmode0 iddq v dd tclk trst tms tdo v ss v ss nc v ss nc v ss nc nc nc v ss nc v ss nc v ss nc v ss nc v ss v ss actled_5/biactled_5/carin_en actled_4/biactled_4/auto_en actled_3/biactled_3/scram_desc_bypass actled_2/biactled_2/litf_en actled_1/biactled_1/blink_led_mode actled_0/biactled_0/stretch_led rrxd0_7 rrxd1_7 rcrs_dv_7 rrxer_7 rtxd1_7 rtxen_7 rcrs_dv_6 v dd rrxer_6 rrxd1_6 rrxd0_6 rtxd0_7 rtxd1_6 rtxen_6 rtxd0_6 rrxd1_5 rcrs_dv_5 rrxer_5 rrxd0_5 rtxd1_5 rtxd0_5 rcrs_dv_4 v dd rtxen_5 rrxd1_4 rtxd0_4 rrxer_4 rrxd0_4 rtxd1_4 rcrs_dv_3 rtxen_4 rrxd1_3 rrxd0_3 rtxd0_3 rtxd1_3 rrxer_3 rcrs_dv_2 v dd rtxen_3 rrxd1_2 rtxd0_2 rrxer_2 rrxd0_2 rtxd1_2 rtxen_2 actled_6/biactled_6 actled_7/biactled_7 speedled_0/phy_add[0] speedled_1/phy_add[1] speedled_2/phy_add[2] speedled_3/no_lp v dd speedled_4/led_mode0 speedled_5/led_mode1 speedled_6 speedled_7 fdupled_0/serclk/crs_sel fdupled_1/serdata/full_dup fdupled_2/serstrobe/isolate v ss v dd v ss v dda v dda pecp pecn atbon atbop v dda fosd0 fosd1 fosd2 fosd3 fosd4 fosd5 fosd6 fosd7 fdupled_3/reserved fdupled_4/rmii_mode v dd fdupled_5/speed fdupled_6 fdupled_7 linkled_0/blinkled0/fx_mode_en0 linkled_1/blinkled1/fx_mode_en1 linkled_2/blinkled2/fx_mode_en2 v dd linkled_3/blinkled3/fx_mode_en3 linkled_4/blinkled4/fx_mode_en4 linkled_5/blinkled5/fx_mode_en5 linkled_6/blinkled6/fx_mode_en6 linkled_7/blinkled7/fx_mode_en7 tdi v ss v ss v ss v ss 3X38FTR 208-pin sqfp rmii mode lucent technologies inc. 11 preliminary data sheet 3X38FTR 208-pin sqfp september 2000 octal-fet for 10base-t/100base-tx/fx pin information (continued) pin diagram for smii mode 5-8124(f).r1 figure 6. 3x38 pinout for smii mode 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 1 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 v dda 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 53 tpin+7/foin+7 tpinC7/foinC7 v dda tpin+6/foin+6 tpinC6/foinC6 v dda tpin+5/foin+5 tpinC5/foinC5 v dda tpin+4/foin+4 tpinC4/foinC4 v ss v dda tpin+3/foin+3 tpinC3/foinC3 v dda tpin+2/foin+2 tpinC2/foinC2 v dda tpin+1/foin+1 tpinC1/foinC1 v ss v dda tpin+0/foin+0 tpinC0/foinC0 v ss rextbs v dda v ddpll rmclk v ss v dda rext100 rext10 v ss tpoutC7/fooutC7 tpout+7/foout+7 tpoutC6/fooutC6 tpout+6/foout+6 tpoutC5/fooutC5 tpout+5/foout+5 tpoutC4/fooutC4 tpout+4/foout+4 tpoutC3/fooutC3 tpout+3/foout+3 tpoutC2/fooutC2 tpout+2/foout+2 tpoutC1/fooutC1 tpout+1/foout+1 tpoutC0/fooutC0 tpout+0/foout+0 nc stxd_1 nc nc nc nc srxd_1 v dd nc stxd_0 nc nc v ss nc o_m nc mask_stat_int srxd_0 v dd reset_not 3-state mdc mdio tmode4 tmode3 tmode2 tmode1 tmode0 iddq v dd tclk trst tms tdo v ss v ss nc v ss nc v ss nc nc nc v ss nc v ss nc v ss nc v ss nc v ss v ss actled_5/biactled_5/carin_en actled_4/biactled_4/auto_en actled_3/biactled_3/scram_desc_bypass actled_2/biactled_2/litf_en actled_1/biactled_1/blink_led_mode actled_0/biactled_0/stretch_led nc nc stxd_7 nc nc nc stxd_6 v dd nc nc nc srxd_7 nc nc srxd_6 nc stxd_5 ssync_7:4 nc nc srxd_5 stxd_4 v dd nc nc srxd_4 nc nc nc stxd_3 nc nc nc srxd_3 nc nc stxd_2 v dd nc nc srxd_2 ssync_3:0 nc nc nc actled_6/biactled_6 actled_7/biactled_7 speedled_0/phy_add[0] speedled_1/phy_add[1] speedled_2/phy_add[2] speedled_3/no_lp v dd speedled_4/led_mode0 speedled_5/led_mode1 speedled_6 speedled_7 fdupled_0/serclk/crs_sel fdupled_1/serdata/full_dup fdupled_2/serstrobe/isolate v ss v dd v ss v dda v dda pecp pecn atbon atbop v dda fosd0 fosd1 fosd2 fosd3 fosd4 fosd5 fosd6 fosd7 fdupled_3/reserved fdupled_4/rmii_mode v dd fdupled_5/speed fdupled_6 fdupled_7 linkled_0/blinkled0/fx_mode_en0 linkled_1/blinkled1/fx_mode_en1 linkled_2/blinkled2/fx_mode_en2 v dd linkled_3/blinkled3/fx_mode_en3 linkled_4/blinkled4/fx_mode_en4 linkled_5/blinkled5/fx_mode_en5 linkled_6/blinkled6/fx_mode_en6 linkled_7/blinkled7/fx_mode_en7 tdi v ss v ss v ss v ss 3X38FTR 208-pin sqfp smii mode 12 lucent technologies inc. 3X38FTR 208-pin sqfp preliminary data sheet octal-fet for 10base-t/100base-tx/fx september 2000 name rmii mode name smii mode name 1v ss v ss 2 actled_5 actled_5 3 actled_4 actled_4 4 actled_3 actled_3 5 actled_2 actled_2 6 actled_1 actled_1 7 actled_0 actled_0 8 rrxd0_7 nc 9 rrxd1_7 nc 10 rcrs_dv_7 stxd_7 11 rrxer_7 nc 12 rtxd1_7 nc 13 rtxen_7 nc 14 rcrs_dv_6 stxd_6 15 v dd v dd 16 rrxer_6 nc 17 rrxd1_6 nc 18 rrxd0_6 nc 19 rtxd0_7 srxd_7 20 rtxd1_6 nc 21 rtxen_6 nc 22 rtxd0_6 srxd_6 23 rrxd1_5 nc 24 rcrs_dv_5 stxd_5 25 rrxer_5 ssync_7:4 26 rrxd0_5 nc 27 rtxd1_5 nc 28 rtxd0_5 srxd_5 29 rcrs_dv_4 stxd_4 30 v dd v dd 31 rtxen_5 nc 32 rrxd1_4 nc 33 rtxd0_4 srxd_4 34 rrxer_4 nc 35 rrxd0_4 nc 36 rtxd1_4 nc 37 rcrs_dv_3 stxd_3 38 rtxen_4 nc 39 rrxd1_3 nc 40 rrxd0_3 nc 41 rtxd0_3 srxd_3 42 rtxd1_3 nc 43 rrxer_3 nc 44 rcrs_dv_2 stxd_2 45 v dd v dd 46 rtxen_3 nc 47 rrxd1_2 nc 48 rtxd0_2 srxd_2 49 rrxer_2 ssync_3:0 50 rrxd0_2 nc 51 rtxd1_2 nc 52 rtxen_2 nc 53 rrxd1_1 nc 54 rcrs_dv_1 stxd_1 55 rrxd0_1 nc 56 rrxer_1 nc 57 rtxd1_1 nc 58 rtxen_1 nc 59 rtxd0_1 srxd_1 60 v dd v dd 61 rrxd1_0 nc 62 rcrs_dv_0 stxd_0 63 rrxd0_0 nc 64 rrxer_0 nc 65 v ss v ss 66 rtxd1_0 nc 67 o_m o_m 68 rtxen_0 nc 69 mask_stat_int mask_stat_int 70 rtxd0_0 srxd_0 71 v dd v dd 72 reset_not reset_not 73 3-state 3-state 74 mdc mdc 75 mdio mdio 76 tmode4 tmode4 77 tmode3 tmode3 78 tmode2 tmode2 79 tmode1 tmode1 80 tmode0 tmode0 81 iddq iddq 82 v dd v dd 83 tclk tclk 84 trst trst 85 tms tms 86 tdo tdo name rmii mode name smii mode name pin information (continued) table 1. 3x38 signal in alphanumeric sequence according to pin number lucent technologies inc. 13 preliminary data sheet 3X38FTR 208-pin sqfp september 2000 octal-fet for 10base-t/100base-tx/fx 87 v ss v ss 88 v ss v ss 89 nc nc 90 v ss v ss 91 nc nc 92 v ss v ss 93 nc nc 94 nc nc 95 nc nc 96 v ss v ss 97 nc nc 98 v ss v ss 99 nc nc 100 v ss v ss 101 nc nc 102 v ss v ss 103 nc nc 104 v ss v ss 105 tpout+0 tpout+0 106 tpoutC0 tpoutC0 107 tpout+1 tpout+1 108 tpoutC1 tpoutC1 109 tpout+2 tpout+2 110 tpoutC2 tpoutC2 111 tpout+3 tpout+3 112 tpoutC3 tpoutC3 113 tpout+4 tpout+4 114 tpoutC4 tpoutC4 115 tpout+5 tpout+5 116 tpoutC5 tpoutC5 117 tpout+6 tpout+6 118 tpoutC6 tpoutC6 119 tpout+7 tpout+7 120 tpoutC7 tpoutC7 121 v ss v ss 122 rext10 rext10 123 rext100 rext100 124 v dda v dda 125 v ss v ss 126 rmclk rmclk 127 v ddpll v ddpll 128 v dda v dda 129 rextbs rextbs name rmii mode name smii mode name 130 v ss v ss 131 tpinC0 tpinC0 132 tpin+0 tpin+0 133 v dda v dda 134 v ss v ss 135 tpinC1 tpinC1 136 tpin+1 tpin+1 137 v dda v dda 138 tpinC2 tpinC2 139 tpin+2 tpin+2 140 v dda v dda 141 tpinC3 tpinC3 142 tpin+3 tpin+3 143 v dda v dda 144 v ss v ss 145 tpinC4 tpinC4 146 tpin+4 tpin+4 147 v dda v dda 148 tpinC5 tpinC5 149 tpin+5 tpin+5 150 v dda v dda 151 tpinC6 tpinC6 152 tpin+6 tpin+6 153 v dda v dda 154 tpinC7 tpinC7 155 tpin+7 tpin+7 156 v dda v dda 157 v ss v ss 158 v ss v ss 159 v ss v ss 160 v ss v ss 161 tdi tdi 162 linkled_7 linkled_7 163 linkled_6 linkled_6 164 linkled_5 linkled_5 165 linkled_4 linkled_4 166 linkled_3 linkled_3 167 v dd v dd 168 linkled_2 linkled_2 169 linkled_1 linkled_1 170 linkled_0 linkled_0 171 fdupled_7 fdupled_7 172 fdupled_6 fdupled_6 name rmii mode name smii mode name pin information (continued) table 1. 3x38 signal in alphanumeric sequence according to pin number (continued) 14 lucent technologies inc. 3X38FTR 208-pin sqfp preliminary data sheet octal-fet for 10base-t/100base-tx/fx september 2000 173 fdupled_5 fdupled_5 174 v dd v dd 175 fdupled_4 fdupled_4 176 fdupled_3 fdupled_3 177 fosd7 fosd7 178 fosd6 fosd6 179 fosd5 fosd5 180 fosd4 fosd4 181 fosd3 fosd3 182 fosd2 fosd2 183 fosd1 fosd1 184 fosd0 fosd0 185 v dda v dda 186 atbop atbop 187 atbon atbon 188 pecn pecn 189 pecp pecp 190 v dda v dda name rmii mode name smii mode name 191 v dda v dda 192 v ss v ss 193 v dd v dd 194 v ss v ss 195 fdupled_2 fdupled_2 196 fdupled_1 fdupled_1 197 fdupled_0 fdupled_0 198 speedled_7 speedled_7 199 speedled_6 speedled_6 200 speedled_5 speedled_5 201 speedled_4 speedled_4 202 v dd v dd 203 speedled_3 speedled_3 204 speedled_2 speedled_2 205 speedled_1 speedled_1 206 speedled_0 speedled_0 207 actled_7 actled_7 208 actled_6 actled_6 name rmii mode name smii mode name pin information (continued) table 1. 3x38 signal in alphanumeric sequence according to pin number (continued) lucent technologies inc. 15 preliminary data sheet 3X38FTR 208-pin sqfp september 2000 octal-fet for 10base-t/100base-tx/fx pin information (continued) pin maps table 2. 3x38 rmii/smii pin map pin number rmii mode pins i/o smii mode pins i/o 70 rtxd0_0 i srxd_0 o 68 rtxen_0 i nc 66 rtxd1_0 i nc 64 rrxer_0 o nc 63 rrxd0_0 o nc 62 rcrs_dv_0 o stxd_0 i 61 rrxd1_0 o nc 59 rtxd0_1 i srxd_1 o 58 rtxen_1 i nc 57 rtxd1_1 i nc 56 rrxer_1 o nc 55 rrxd0_1 o nc 54 rcrs_dv_1 o stxd_1 i 53 rrxd1_1 o nc 52 rtxen_2 i nc 51 rtxd1_2 i nc 50 rrxd0_2 o nc 49 rrxer_2 o ssync_3:0 i 48 rtxd0_2 i srxd_2 o 47 rrxd1_2 o nc 44 rcrs_dv_2 o stxd_2 i 46 rtxen_3 i nc 43 rrxer_3 o nc 42 rtxd1_3 i nc 41 rtxd0_3 i srxd_3 o 40 rrxd0_3 o nc 39 rrxd1_3 o nc 37 rcrs_dv_3 o stxd_3 i 38 rtxen_4 i nc 36 rtxd1_4 i nc 35 rrxd0_4 o nc 34 rrxer_4 o nc 33 rtxd0_4 i srxd_4 o 32 rrxd1_4 o nc 29 rcrs_dv_4 o stxd_4 i 31 rtxen_5 i nc 28 rtxd0_5 i srxd_5 o 3X38FTR 208-pin sqfp preliminary data sheet octal-fet for 10base-t/100base-tx/fx september 2000 16 lucent technologies inc. pin descriptions table 3. rmii/smii interface pins 27 rtxd1_5 i nc 26 rrxd0_5 o nc 25 rrxer_5 o ssync_7:4 i 24 rcrs_dv_5 o stxd_5 i 23 rrxd1_5 o nc 22 rtxd0_6 i srxd_6 o 21 rtxen_6 i nc 20 rtxd1_6 i nc 18 rrxd0_6 o nc 17 rrxd1_6 o nc 16 rrxer_6 o nc 14 rcrs_dv_6 o stxd_6 i 19 rtxd0_7 i srxd_7 o 13 rtxen_7 i nc 12 rtxd1_7 i nc 11 rrxer_7 o nc 10 rcrs_dv_7 o stxd_7 i 9 rrxd1_7 o nc 8 rrxd0_7 o nc 175 fdupled_4/rmii_mode [tie low] i fdupled_4/smii_mode [tie high] i 126 rmclk 50 mhz clock in i rmclk 125 mhz clock in i pins signal type description 19, 22, 28, 33, 41, 48, 59, 70 rtxd0_[7:0]/ srxd_[7:0] i rmii transmit data 0 . transmit data bit zero, transitions synchro- nously with rmclk. o smii receive data and control . receive data and control transi- tions synchronously with rmclk. 12, 20, 27, 36, 42, 51, 57, 66 rtxd1_[7:0] i rmii transmit data 1 . transmit data bit one, transitions synchro- nously with rmclk. 13, 21, 31, 38, 46, 52, 58, 68 rtxen_[7:0] i rmii transmit enable . transmit enable indicates that the mac is presenting dibits on rtxd[1:0] for transmission. 8, 18, 26, 35, 40, 50, 55, 63 rrxd0_[7:0] o rmii receive data 0 . receive data bit zero, transitions synchro- nously with rmclk. 9, 17, 23, 32, 39, 47, 53, 61 rrxd1_[7:0] o rmii receive data 1 . receive data bit one, transitions synchro- nously with rmclk. pin number rmii mode pins i/o smii mode pins i/o pin information (continued) table 2. 3x38 rmii/smii pin map (continued) lucent technologies inc. 17 preliminary data sheet 3X38FTR 208-pin sqfp september 2000 octal-fet for 10base-t/100base-tx/fx table 4. mii management 10, 14, 24, 29, 37, 44, 54, 62 rcrs_dv_[7:0]/ stxd_[7:0] o rmii carrier sense and receive data valid . the crs_dv will be asserted when valid data is being received. this signal is asserted asynchronously. i smii transmit data and control . this signal transitions synchro- nously with the rmclk. 11, 16, 34, 43, 56, 64 rrxer_[7, 6, 4, 3, 1, 0] o rmii receive error . receive error is asserted for one or more clock periods to indicate that a coding error or other error was detected in the frame presently being transferred. 49 rrxer_2/ ssync_3:0 o rmii receive error . receive error is asserted for one or more clock periods to indicate that a coding error or other error was detected in the frame presently being transferred. i smii sync . synchronization input to the 3x38 that segments the boundaries between each receive data and control 10-bit seg- ments. this input generates a sync pulse every 10 clock cycles. 25 rrxer_5/ ssync_7:4 o rmii receive error . receive error is asserted for one or more clock periods to indicate that a coding error or other error was detected in the frame presently being transferred. i smii sync . synchronization input to the 3x38 that segments the boundaries between each receive data and control 10-bit seg- ments. there is a sync pulse once every 10 clock cycles. pins signal type description 74 mdc i management data clock . this is the timing reference for the transfer of data on the mdio signal. this signal may be asynchro- nous to rmclk. the maximum clock rate is 12.5 mhz. when running mdc above 6.25 mhz, mdc must be synchronous with rmclk and have a setup time of 15 ns and a hold time of 5 ns with respect to rmclk. 75 mdio i/o management data input/output . this i/o is used to transfer con- trol and status information between the 3x38 and the station man- agement. control information is driven by the station management synchronous with mdc. status information is driven by the 3x38 synchronous with mdc. this pin requires an external 1.5 k w pull-up resistor. 69 mask_stat_int o maskable status interrupt . this pin will go low whenever there is a change in status as defined in table 35 (register 31). this is an open-drain output and requires a 10 k w pull-up resistor. pins signal type description pin descriptions (continued) table 3. rmii/smii interface pins (continued) 3X38FTR 208-pin sqfp preliminary data sheet octal-fet for 10base-t/100base-tx/fx september 2000 18 lucent technologies inc. pin descriptions (continued) table 5. 10/100 mbits/s twisted-pair (tp) interface pins table 6. led and configuration pins pin signal type description 155, 152, 149, 146, 142, 139, 136, 132 tpin+/ foin+[7:0] i receive data. positive differential received 125 mbaud mlt3, or 10 mbaud manchester data from magnetics. fiber-optic data input. positive differential received 125 mbaud pseudo-ecl data from fiber transceiver. 154, 151, 148, 145, 141, 138, 135, 131 tpinC/ foinC[7:0] i receive data. negative differential received 125 mbaud mlt3 or 10 mbaud manchester data from magnetics. fiber-optic data input. negative differential received 125 mbaud pseudo-ecl data from fiber transceiver. 119, 117, 115, 113, 111, 109, 107, 105 tpout+/ foout+[7:0] o transmit data. positive differential transmit 125 mbaud mlt3 or 10 mbaud manchester data to magnetics. fiber-optic data output. positive differential transmit 125 mbaud pseudo-ecl compatible data to fiber transceiver. 120, 118, 116, 114, 112, 110, 108, 106 tpoutC/ fooutC[7:0] o transmit data. negative differential transmit 125 mbaud mlt3 or 10 mbaud manchester data to magnetics. fiber-optic data output. negative differential transmit 125 mbaud pseudo-ecl compatible data to fiber transceiver. 177, 178, 179, 180, 181, 182, 183, 184 fosd[7:0] i fiber-optic signal detect. pseudo-ecl input signal which indicates whether or not the fiber-optic receive pairs (foin) are receiving valid signal levels. these inputs are ignored when not in fiber mode and should be grounded. pin signal type description 2 actled_5/ biactled_5/ carin_en o activity led[5]. this pin indicates transmit or receive activity on port 5. 10 ma active-high output. o bicolor activity led[5]. when the 3x38 is placed in the bicolor led mode by pulling both of the led_mode[1:0] pins high at powerup or reset, this output will go high whenever there is either transmit or receive activity. this output works in conjunction with the link led out- puts to drive a single bicolor led package, when in bicolor led mode. 10 ma active-high output. i carrier integrity enable. at powerup or reset, if this pin is pulled high through a 10 k w resistor, it will enable the carrier integrity function of register 29, bit 3, if station management is unavailable. this pin has an internal 50 k w pull-down resistor for normal operation (carin_en is disabled). this input and register bits [29.3] are ored together. lucent technologies inc. 19 preliminary data sheet 3X38FTR 208-pin sqfp september 2000 octal-fet for 10base-t/100base-tx/fx 3actled_4/ biactled_4/ auto_en o activity led[4]. this pin indicates transmit or receive activity on port 4. 10 ma active-high output. o bicolor activity led[4] . when the 3x38 is placed in the bicolor led mode by pulling both of the led_mode[1:0] pins high at powerup or reset, this output will go high whenever there is either transmit or receive activity. this output works in conjunction with the link led out- puts to drive a single bicolor led package, when in bicolor led mode. 10 ma active-high output. i autonegotiation enable . at powerup or reset, when this pin is high through a 10 k w resistor, autonegotiation is enabled. pulsing this pin will cause autonegotiation to restart. this input has the same function as register 0, bit 12. this input and the register bit are anded together. this pin has an internal 50 k w pull-down resistor; default is autonegotia- tion off. 4actled_3/ biactled_3/ scram_desc_byp ass o activity led[3]. this pin indicates transmit or receive activity on port 3. 10 ma active-high output. o bicolor activity led[3] . when the 3x38 is placed in the bicolor led mode by pulling both of the led_mode[1:0] pins high at powerup or reset, this output will go high whenever there is either transmit or receive activity. this output works in conjunction with the link led out- puts to drive a single bicolor led package, when in bicolor led mode. 10 ma active-high output. i scrambler/descrambler bypass. at powerup or reset, this pin may be used to enable the scram_desc_bypass function by pulling this pin high through a 10 k w resistor, if station management is unavailable. this is the same function as register 29, bit 4. this pin has an internal 50 k w pull-down resistor for normal operation (scrambler/descrambler on). this input and the register bit [29.4] are ored together during powerup and reset. 5actled_2/ biactled_2/ litf_en o activity led[2]. this pin indicates transmit or receive activity on port 2. 10 ma active-high output. o bicolor activity led[2] . when the 3x38 is placed in the bicolor led mode by pulling both of the led_mode[1:0] pins high at powerup or reset, this output will go high whenever there is either transmit or receive activity. this output works in conjunction with the link led out- puts to drive a single bicolor led package, when in bicolor led mode. 10 ma active-high output. i enhanced link integrity test function. when this input is pulled high at powerup or reset through a 10 k w resistor, the 3x38 will detect and change speed from 10 mbits/s to 100 mbits/s, when an instantaneous speed change occurs. this pin is ored with register 30, bit 6. this pin has an internal 50 k w pull-up resistor; default is litf_en enabled. pin signal type description pin descriptions (continued) table 6. led and configuration pins (continued) 3X38FTR 208-pin sqfp preliminary data sheet octal-fet for 10base-t/100base-tx/fx september 2000 20 lucent technologies inc. 6 actled_1/ biactled_1/ blink_led_mode o activity led[1]. this pin indicates transmit or receive activity on port 1. 10 ma active-high output. o bicolor activity led[1] . when the 3x38 is placed in the bicolor led mode by pulling both of the led_mode[1:0] pins high at powerup or reset, this output will go high whenever there is either transmit or receive activity. this output works in conjunction with the link led out- puts to drive a single bicolor led package, when in bicolor led mode. 10 ma active-high output. i blink led mode. at powerup or reset, when pulled high through a 10 k w resistor (and the stretch_led pin is low), the activity led output will blink high for 40 ms and low for 40 ms whenever there is activity. this signal is ored with register 29, bit 11. this pin has an internal 50 k w pull-down resistor; default is blink mode disabled. 7 actled_0/ biactled_0/ stretch_led o activity led[0]. this pin indicates transmit or receive activity on port 0. 10 ma active-high output. o bicolor activity led[0] . when the 3x38 is placed in the bicolor led mode by pulling both of the led_mode[1:0] pins high at powerup or reset, this output will go high whenever there is either transmit or receive activity. this output works in conjunction with the link led out- puts to drive a single bicolor led package, when in bicolor led mode. 10 ma active-high output. i stretch led mode. at powerup or reset, when pulled high through a 10 k w resistor, this pin enables stretching. when high, the activity led output is stretched to 42 ms minimum and 84 ms maximum, unless blink_led_mode is high, in which case it blinks 40 ms high and 40 ms low. this pin is ored with register 29, bit 7. this pin has an inter- nal 50 k w pull-up resistor. default is stretch led mode enabled. 207, 208 actled_[7:6]/ biactled[7:6] o activity led[7:6]. this pin indicates transmit or receive activity on port 7 or 6. 10 ma active-high output. o bicolor activity led[7:6] . when the 3x38 is placed in the bicolor led mode by pulling both of the led_mode[1:0] pins high at powerup or reset, this output will go high whenever there is either transmit or receive activity. this output works in conjunction with the link led out- puts to drive a single bicolor led package, when in bicolor led mode. 10 ma active-high output. 206 speedled_0/ phy_add[0] o speed led[0]. this pin indicates the operating speed of port 0 on the 3x38. a high on this pin indicates 100 mbits/s operation. a low indicates 10 mbits/s operation. 10 ma active-high output. i phy address 0 . at powerup or reset, this pin may be used to set the phy address bit 0. at powerup or reset, if this pin is pulled high through a 10 k w resistor, it will set phyadd[0] to a 1. if this pin is pulled low through a 10 k w resis- tor, it will set phyadd[0] to a 0. this pin has an internal 50 k w pull- down resistor. pin signal type description pin descriptions (continued) table 6. led and configuration pins (continued) lucent technologies inc. 21 preliminary data sheet 3X38FTR 208-pin sqfp september 2000 octal-fet for 10base-t/100base-tx/fx 205 speedled_1/ phy_add[1] o speed led[1]. this pin indicates the operating speed of port 1 on the 3x38. a high on this pin indicates 100 mbits/s operation. a low indicates 10 mbits/s operation. 10 ma active-high output. i phy address 1 . at powerup or reset, this pin may be used to set the phy address bit 1. if this pin is pulled high through a 10 k w resistor, it will set phyadd[0] to a 1. if this pin is pulled low through a 10 k w resistor, it will set phy- add[1] to a 0. this pin has an internal 50 k w pull-down resistor. 204 speedled_2/ phy_add[2] o speed led[2]. this pin indicates the operating speed of port 2 on the 3x38. a high on this pin indicates 100 mbits/s operation. a low indicates 10 mbits/s operation. 10 ma active-high output. i phy address 2 . at powerup or reset, this pin may be used to set the phy address bit 2. if this pin is pulled high through a 10 k w resistor, it will set phyadd[0] to a 1. if this pin is pulled low through a 10 k w resistor, it will set phy- add[2] to a 0. this pin has an internal 50 k w pull-down resistor. 203 speedled_3/ no_lp o speed led[3]. this pin indicates the operating speed of port 3 on the 3x38. a high on this pin indicates 100 mbits/s operation. a low indicates 10 mbits/s operation. 10 ma active-high output. i no link pulse mode . at powerup or rest, pulling this signal high through a 10 k w resistor, will allow 10 mbits/s operation with link pulses disabled. if the 3x38 is configured for 100 mbits/s operation, this signal is ignored. this is the same function as register 30, bit 0. the input and the register bit are ored together. this pin has an internal 50 k w pull- down resistor, default is normal link pulse mode. 200, 201 speedled_[5:4]/ led_mode[1:0] o speed led[5:4]. these pins indicate the operating speed of ports [5:4] on the 3x38. a high on this pin indicates 100 mbits/s operation. a low indicates 10 mbits/s operation. 10 ma active-high output. i led mode [1:0] . at powerup or reset, the led mode configuration pins[1:0] are used to select the led mode of operation by pulling them high or low through a 10 k w resistor as shown below. led modes pin 1 pin 0 mode outputs 0 0 parallel speedled_[7:0], fdupled[7:0], linkled[7:0], actled[7:0] 0 1 reserved reserved 1 0 serial serclk, serdata, serstrobe 1 1 bicolor actled[7:0], linkled[7:0] when in serial led mode, all eight channels led functions will be mul- tiplexed onto one serial led output stream. when in bicolor led mode, each of the eight channels will have two led outputs each, to drive a bicolor led. these pins have internal 50 k w pull-down resistors. 198, 199 speedled_[7:6] o speed led[7:6]. these pins indicate the operating speed of ports [7:6] on the 3x38. a high on this pin indicates 100 mbits/s operation. a low indicates 10 mbits/s operation. 10 ma active-high output. pin signal type description pin descriptions (continued) table 6. led and configuration pins (continued) 3X38FTR 208-pin sqfp preliminary data sheet octal-fet for 10base-t/100base-tx/fx september 2000 22 lucent technologies inc. 197 fdupled_0/ serclk/ crs_sel o full-duplex led[0]. this led output can operate as the full-duplex led indicator, or as a collision led indicator, or as a serial led output. this output is only valid when the link is up. when the link is operating in full-duplex mode, this led output is the full-duplex led (logic high out- put). when the link is operating in half-duplex mode, this led output becomes the collision led output (logic high output). 10 ma active-high output. o serial led clock . this is approximately a 1.56 mhz clock output used to clock out the serial led data, when the serial led mode is enabled by pulling the serial_led_mode[1] pin high and the serial_led_mode[0] pin low through a 10 k w resistor at powerup or reset. i carrier sense select. at powerup, this pin may be used to select the mode of crs (carrier sense) operation. when this pin is pulled high through a 10 k w resistor, crs (carrier sense) will be asserted on receive activity only. this is the same function as register 29, bit 10. this pin has an internal 50 k w pull-down resistor for normal mode oper- ation (default: crs asserted on transmit or receive activity). this input and the register bit [29.10] are ored together during powerup and reset. 196 fdupled_1/ serdata/ full_dup o full-duplex led[1]. this led output can operate as the full-duplex led indicator, or as a collision led indicator, or as a serial led output. this output is only valid when the link is up. when the link is operating in full-duplex mode, this led output is the full-duplex led (logic high out- put). when the link is operating in half-duplex mode, this led output becomes the collision led output (logic high output). 10 ma active-high output. o serial led data . a single serial led data stream output that contains led status information from all eight 3x38 ports. the serial led mode is enabled by pulling the serial_led_mode_1 pin high through a 10 k w resistor, and the serial_mode_0 pin low at powerup or reset. i full duplex. at powerup, this pin may be used to select full-duplex operation for all eight channels by pulling it high through a 10 k w resis- tor, if station management is unavailable. this is the same function as register 0, bit 8. this pin has an internal 50 k w pull-up resistor to default to full duplex for normal operation. this input and the register bit[0:8] are ored together during powerup and reset. this pin is ignored when autonegotiation is enabled. this pin has an internal 50 k w pull-up to default to full duplex. pin signal type description pin descriptions (continued) table 6. led and configuration pins (continued) lucent technologies inc. 23 preliminary data sheet 3X38FTR 208-pin sqfp september 2000 octal-fet for 10base-t/100base-tx/fx 195 fdupled_2/ serstrobe/ isolate o full-duplex led[2]. this led output can operate as the full-duplex led indicator, or as a collision led indicator, or as a serial led output. this output is only valid when the link is up. when the link is operating in full-duplex mode, this led output is the full-duplex led (logic high out- put). when the link is operating in half-duplex mode, this led output becomes the collision led output (logic high output). 10 ma active-high output. o serial led strobe . this is a synchronizing strobe for the serial led data output stream that goes high at the start of each serial stream, once every 32 clocks when in serial led mode. i isolate mode. as an input, this pin can be used at powerup or reset to select the isolate operation mode. if this pin is pulled high through a 10 k w resistor, the 3x38 will powerup or reset to the isolate mode. (rmii and smii outputs to high-impedance state.) this pin is internally pulled through a 50 k w resistor. the default state is for the 3x38 to powerup or reset in a nonisolate mode. this pin and reg- ister bit [0.10] are ored together during powerup and reset. 173 fdupled_5/ speed o full-duplex led[5]. this led output can operate as the full-duplex led indicator, or as a collision led indicator, or as a serial led output. this output is only valid when the link is up. when the link is operating in full-duplex mode, this led output is the full-duplex led (logic high out- put). when the link is operating in half-duplex mode, this led output becomes the collision led output (logic high output). 10 ma active-high output. i speed . at powerup or reset, this signal can be used to select the oper- ating speed and is the same function as register 0, bit 13. if this signal is pulled high with a 10 k w , it will enable 100 mbits/s operation. if this sig- nal is pulled low with a 10 k w , it will enable 10 mbits/s operation. this signal is ignored when autonegotiation is enabled. this signal and the register bit are anded. this pin has an internal 50 k w pull-up, to default to 100tx mode, when autonegoatiation is not enabled. 171, 172 fdupled[7:6] o full-duplex led[7:6]. this led output can operate as the full-duplex led indicator, or as a collision led indicator, or as a serial led output. this output is only valid when the link is up. when the link is operating in full-duplex mode, this led output is the full-duplex led (logic high out- put). when the link is operating in half-duplex mode, this led output becomes the collision led output (logic high output). 10 ma active-high output. 176 fdupled_3/ reserved o full-duplex led[3]. this led output can operate as the full-duplex led indicator, or as a collision led indicator, or as a serial led output. this output is only valid when the link is up. when the link is operating in full-duplex mode, this led output is the full-duplex led (logic high out- put). when the link is operating in half-duplex mode, this led output becomes the collision led output (logic high output). 10 ma active-high output. i reserved . do not pull this pin high at powerup or reset. pin signal type description pin descriptions (continued) table 6. led and configuration pins (continued) 3X38FTR 208-pin sqfp preliminary data sheet octal-fet for 10base-t/100base-tx/fx september 2000 24 lucent technologies inc. table 7. table test mode pins 175 fdupled_4/ rmii_mode o full-duplex led[4]. this led output can operate as the full-duplex led indicator, or as a collision led indicator, or as a serial led output. this output is only valid when the link is up. when the link is operating in full-duplex mode, this led output is the full-duplex led (logic high out- put). when the link is operating in half-duplex mode, this led output becomes the collision led output (logic high output). 10 ma active-high output. i rmii mode . when pulled high through a 10 k w resistor at powerup or reset, this will place the 3x38 in the smii mode of operation. when pulled low, the 3x38 will operate in rmii mode. this pin has an internal 50 k w pull-down. 162, 163, 164, 165, 166, 168, 169, 170 linkled_[7:0]/ bilinkled[7:0]/ fx_mode_en[7:0] o link led[7:0]. this pin indicates good link status on port [7:0]. 10 ma active-high output. o bicolor led[7:0] . when the 3x38 is placed in the bicolor led mode by writting a one to bit 10 of register 20. this bit will go high whenever the link is up and there is no transmit or receive activity. this output works in conjunction with the activity led when in bicolor mode. this is a 10 ma active-high output. i fx mode enable . at powerup or reset, when pulled high through a 10 k w resistor, this pin will enable the fx mode (10base-t and 100base-tx disabled). when pulled low, it will enable 10base-t and 100base-tx modes (100base-fx mode disabled). these pins are ored with register 29, bit 0 [29.0]. these pins have internal 50 k w pull-down resistors. pin signal type description 186, 187 atbop at b o n o reserved. leave these pins unconnected. 189, 188 pecp pecn o reserved. place a 1 k w resistor from these pins to ground. these resistors control the slew rate of the rmii and smii outputs. 81 iddq i iddq mode. reserved for manufacturing test. for normal use, tie low. 161 tdi i test data input. serial data input to the jtag tap controller. sam- pled on the rising edge of tck. when not in jtag mode, tie low. 86 tdo o test data output. serial data output from the jtag tap controller. updated on the falling edge of tck. when not in use, leave uncon- nected. 85 tms i test mode select. when pulled high through a 10 k w resistor, this pin selects the jtag test mode. when not in use, tie low. 83 tclk i test clock. jtag clock input used to synchronize jtag control and data tranfers. when unused, tie low. 84 trst i test reset . asynchronous active-low reset input to jtag tap con- troller. for normal use, tie low. pin signal type description pin descriptions (continued) table 6. led and configuration pins (continued) lucent technologies inc. 25 preliminary data sheet 3X38FTR 208-pin sqfp september 2000 octal-fet for 10base-t/100base-tx/fx table 8. clock, reset, fosd, and special configuration pins 76, 77, 78, 79, 80 tmode[4:0] i test mode select . reserved for manufacturing testing. these pins should be tied low for normal operation. 73 3-state i 3-state. when this pin is high, all digital outputs will be 3-stated. for normal operation, pull this pin low. pin signal type description 126 rmclk i rmii/smii clock input . cmos input level system clock input. 50 mhz in rmii mode, 125 mhz in smii mode. 50 ppm, 40% 60% duty cycle. 72 reset_not i full chip reset not . reset must be asserted low for at least 1 ms. the 3x38 will come out of reset after 2 ms. rmclk must remain running during reset. 129 rextbs i external bias resistor . connect this pin to a 24.9 k w 1% resis- tor to ground. the parasitic load capacitance must be less than 15 pf. 123 rext100 i external bias resistor 100 . connect this pin to a 21.5 k w 1% resistor to ground. this sets the 100 mbits/s tp driver output level. 122 rext10 i external bias resistor 10 . connect this pin to a 21.5 k w 1% resistor to ground. this sets the 10 mbits/s tp driver output level. 67 o_m i reserved . tie this pin high through 10 k w resistor. pin signal type description pin descriptions (continued) table 7. table test mode pins (continued) 3X38FTR 208-pin sqfp preliminary data sheet octal-fet for 10base-t/100base-tx/fx september 2000 26 lucent technologies inc. pin descriptions (continued) table 9. power, ground, and no connects pin signal type description 124, 127, 128, 133, 137, 140, 143, 147, 150, 153, 156, 185, 190, 191 v dda pwr analog power 3.3 v 5%. 127 v ddpll pwr phase-locked loop power 3.3 v 5%. 15, 30, 45, 60, 71, 82, 167, 174, 193, 202 v dd pwr digital power 3.3 v 5%. magnetics center taps v ddo pwr tp driver output power 3.3 v 5%. connected to cen- tral tap of tp driver output transformer and 51 w termi- nating resistor. 1, 65, 87, 88, 90, 92, 96, 98, 100, 102, 104, 121, 125, 130, 134, 144, 157, 158, 159, 160, 192, 194 v ss gnd ground. 89, 91, 93, 94, 95, 97, 99, 101, 103 nc nc no connects listed here are for rmii mode only. may be different in smii mode. lucent technologies inc. 27 preliminary data sheet 3X38FTR 208-pin sqfp september 2000 octal-fet for 10base-t/100base-tx/fx functional description the 3x38 integrates eight 100base-x physical sublay- ers (phy), 100base-tx physical medium dependent (pmd) transceivers, and eight complete 10base-t modules into a single chip for both 10 mbits/s and 100 mbits/s ethernet operation. it also supports 100base-fx operation through external fiber-optic transceivers. this device provides a reduced media independent interface (rmii) or serial media indepen- dant interface (smii) to communicate between the physical signaling and the medium access control (mac) layers for both 100base-x and 10base-t opera- tions. additionally, it provides a shared mii port for inter- facing to repeater devices. the device is capable of operating in either full-duplex mode or half-duplex mode in either 10 mbits/s or 100 mbits/s operation. operational modes can be selected by hardware con- figuration pins or software settings of management reg- isters, or can be determined by the on-chip autonegotiation logic. the 10base-t section of the device consists of the 10 mbits/s transceiver module with filters and a manchester endec module. the 100base-x section of the device implements the following functional blocks: n 100base-x physical coding sublayer (pcs) n 100base-x physical medium attachment (pma) n twisted-pair transceiver (pmd) the 100base-x and 10base-t sections share the fol- lowing functional blocks: n clock synthesizer module (csm) n mii registers n ieee 802.3u autonegotiation additionally, there is an interface module that converts the internal mii signals of the phy to rmii signal pins. each of these functional blocks is described below. reduced media independent interface (rmii) this interface reduces the interconnect circuits between a mac and phy. in switch applications, this protocol helps to reduce the pin count on the switch asic significantly. a regular 16-pin mii reduces to a 6-pin (7 with an optional rxer pin) rmii. the intercon- nect circuits are the following: 1. rmclk: a 50 mhz clock. 2. rtxen. 3. rtxd[1:0]. 4. rrxd[1:0]. 5. rcrs_dv. 6. rrxer: mandator y for the phy, but optional for the switch. transmit data path the phy uses the 50 mhz rmclk as its reference so that txc (at the internal mii) and rmclk maintain a phase relationship. this helps to avoid elasticity buffers on the transmit side. on the rising edge of rmclk, 2-bit data is provided on the rmii rtxd[1:0] when rtxen is high. txd[1:0] are ignored when rtxen is deasserted. 5-7505(f).a figure 7. functional description txen txd[3:0] txer txclk col crs rxdv rxd[3:0] rxer rxclk txen txd[3:0] txer txclk col crs rxdv rxd[3:0] rxer rxclk mii mac i/f to rmii mac i/f mac rmii phy rmii phy i/f to mii phy i/f rtxen rtxd[1:0] rcrs_dv rrxd[1:0] rrxer rrefclk 50 mhz 28 lucent technologies inc. 3X38FTR 208-pin sqfp preliminary data sheet octal-fet for 10base-t/100base-tx/fx september 2000 functional description (continued) tx 10 mbits/s mode the rmclk frequency is 10 times the data rate in this mode; therefore, the value on rtxd[1:0] will be valid such that rtxd[1:0] may be sampled every tenth cycle, regardless of the starting cycle within the group. tx 100 mbits/s mode there will be valid data on rtxd[1:0] for each rmclk period when rtxen is asserted. receive data path rxc (at the internal mii) is derived from the incoming data and, hence, does not maintain a phase relation- ship with rmclk. therefore, an elasticity buffer is required on the receive path. the 3x38 provides a 32-bit fifo (default) to synchronize the receive data to the system clock. the start of packet latency can be reduced from 16 bits to 8 bits by writing a 1 to register 20, bit 11. crs_dv is asserted asynchronously. pre- amble is output onto the rmii once the internal signal rrx_dv is asserted (on the rising edge of the rmclk). crs_dv is deasserted asynchronously with the fall of rrx_dv, but rcrs_dv keeps toggling as long as data is being flushed out of the elasticity buffer. the crs_dv signal behavior can be modified by regis- ter 20, bit 12. when this bit is set to 0, crs causes crs_dv to be asserted. when this bit is set to a 1, only rx_dv causes rx_dv to be asserted; this ensures that false carrier events do not propagate through the mac connected to the 3x38. rx 10 mbits/s mode after the assertion of rcrs_dv, the receive data sig- nals, rrxd[1:0], will be 00 until the 10base-t phy has recovered the clock and decoded the receive data. since rmclk is 10 times the data rate in this mode, the value on rrxd[1:0] will be valid such that it can be sampled every tenth cycle, regardless of the starting cycle within the group. rx 100 mbits/s mode after the assertion of rcrs_dv, the receive data sig- nals, rrxd[1:0] will be 00 until the start-of-stream (ssd) delimiter has been detected. collision detection the rmii does not have a collision signal, so all colli- sions are detected internal to the mac. this is an and function of rtxen and rcrs derived from rcrs_dv. rcrs_dv cannot be directly anded with rtxen because rcrs_dv may toggle at the end of a frame to provide separation between rcrs and rrxdv. receiver error the rrx_er signal is asserted for one or more rmclk periods to indicate that an error was detected within the current receive frame. 5-7506(f).a figure 8. rmii receive timing from internal mii signals rmclk rcrs rrx_dv rcrs_dv rrxd[1:0] 00 01 01 00 crs lucent technologies inc. 29 preliminary data sheet 3X38FTR 208-pin sqfp september 2000 octal-fet for 10base-t/100base-tx/fx functional description (continued) loopback during normal operation, rtxd[1:0] and rtxen will not be looped back to rcrs_dv and rrxd[1:0]. rmii/smii interface rmii isolate mode the 3x38 also implements an rmii isolate mode that is controlled by bit 10 of each one of the eight control reg- isters (register 0h). at reset, the 3x38 will initialize this bit to 0. setting the bit to a 1 will put the port into rmii isolate mode. when in isolate mode, the specified port on the 3x38 does not respond to packet data present at the rtxd[1:0] and rtxen inputs, and presents a high impedance on the rcrs_dv, rrxer, and rrxd[1:0] outputs. the 3x38 will continue to respond to all man- agement transactions while the port is in isolate mode. serial media independent interface (smii) the smii allows a further reduction in the number of signals that are required to interface a phy to a mac. there are two global signals, rmclk and ssync, and two per-port signals, srxd and stxd. all signals are synchronous to the 125 mhz clock. 5-7507(f).b figure 9. smii connection diagram 5-7507(f) figure 10. receive sequence diagram stxd0 srxd0 stxd[16] srxd[16] stad7 srxd7 125 mhz reference clock multi-mac port 0 port [16] 3x38 ssync[4:7] clock ssync[3:0] port 7 crs rx_dv rxd0 rxd1 rxd2 rxd3 rxd4 rxd5 rxd6 rxd7 1234567891011 smii_clk sync rxd 30 lucent technologies inc. 3X38FTR 208-pin sqfp preliminary data sheet octal-fet for 10base-t/100base-tx/fx september 2000 functional description (continued) receive path receive data and control information are signaled in ten bit segments. these ten bit boundaries are delim- ited by the sync signal. the connected mac should generate these sync pulses every ten clocks. in 100 mbits/s mode, each segment represents a new byte of data. in 10 mbits/s mode, each segment is repeated ten times, so every ten segments represents a new byte of data. the receive sequence contains all of the information found on the standard mii receive path. out-of-band signaling during an interframe gap, bit rxd5 indicates the valid- ity of the upper nibble of the last byte of data of the pre- vious frame. bit rxd0 indicates an error detected by the phy in the previous frame. both of these bits will be valid in the segment immediately following a frame, and will remain valid until the first data segment of the next frame. transmit data path transmit data and control information are signaled in ten bit segments similar to the receive path. these ten bit boundaries are delimited by the sync signal. the connected mac should generate these sync pulses every ten clocks. in 100 mbits/s mode, each new seg- ment represents a new byte of data. in 10 mbits/s mode, each segment is repeated ten times; therefore, every ten segments represents a new byte of data. the phy can sample one of every ten segments. collision detection the phy does not directly indicate that a collision has occurred. it is left up to the mac to detect the assertion of both crs and txen. table 10. receive data/status encoding 5-7508(f).r1 figure 11. transmit sequence diagram crs rx_dv rxd0 rxd1 rxd2 rxd3 rxd4 rxd5 rxd6 rxd7 x 0 rcvr error in the previous frame speed: 0 = 10 mbits/s 1 = 100 mbits/s duplex: 0 = half 1 = full link: 0 = no link 1 = good link jabber: 0 = ok 1 = detected upper nibble 0 = invalid 1 = valid false carrier: 0 = ok 1 = detected 1 x 1 one data byte (two mii nibbles) txer txen txd0 txd1 txd2 txd3 txd4 txd5 txd6 txd7 1234567891011 smii_clk sync txd lucent technologies inc. 31 preliminary data sheet 3X38FTR 208-pin sqfp september 2000 octal-fet for 10base-t/100base-tx/fx functional description (continued) media independent interface (mii)internal the 3x38 implements ieee 802.3u clause 22 compli- ant mii interface which connects to the mii-rmii mod- ule. this module converts the 4-bit mii receive data to 2-bit rmii receive data. similarly, it converts the 2-bit rmii transmit data (received from the mac) to 4-bit mii transmit data. the following describes the internal mii functions. transmit data interface each internal mii transmit data interface comprises seven signals: txd[3:0] are the nibble size data path, txen signals the presence of data on txd, txer indi- cates substitution of data with the halt symbol, and txclk carries the transmit clock that synchronizes all the transmit signals. txclk is usually supplied by the on-chip clock synthesizer. receive data interface each internal mii receive data interface also comprises seven signals: rxd[3:0] are the nibble size data path, rxdv signals the presence of data on rxd, rxer indicates the validity of data, and rxclk carries the receive clock. depending upon the operation mode, rxclk signal is generated by the clock recovery mod- ule of either the 100base-x or 10base-t receiver. status interface two internal mii status signals, col and crs, are gen- erated in each of the eight channels to indicate collision status and carrier sense status. col is asserted asyn- chronously whenever the respective channel of 3x38 is transmitting and receiving at the same time in a half- duplex operation mode. crs is asserted asynchro- nously whenever there is activity on either the transmit- ter or the receiver. when crs_sel is asserted, crs is asserted only when there is activity on the receiver. operation modes each channel of the 3x38 supports two operation modes and an isolate mode as described below. 100 mbits/s mode . for 100 mbits/s operation, the internal mii operates in nibble mode with a clock rate of 25 mhz. in normal operation, the internal mii data at rxd[7:0] and txd[7:0] are 4 bits wide. 10 mbits/s mode . for 10 mbits/s nibble mode opera- tion, the txclk and rxclk operate at 2.5 mhz. the data paths are 4 bits wide using txd[7:0] and rxd[7:0] signal lines. mii isolate mode . the 3x38 implements an mii isolate mode that is controlled by bit 10 of each one of the four control registers (register 0h). at reset, 3x38 will initial- ize this bit to the logic level transition of the isolate pin. setting the bit to a 1 will also put the port in mii iso- late mode. when in isolate mode, the specified port on the 3x38 does not respond to packet data present at txd[3:0], txen, and txer inputs and presents a logic zero on the txclk, rxclk, rxdv, rxer, rxd[3:0], col, and crs outputs. the 3x38 will continue to respond to all management transactions while the phy is in iso- late mode. serial management interface (smi) the serial management interface is used to obtain sta- tus and to configure the phy. this mechanism corre- sponds to the mii specifications for 100base-x (clause 22) and supports registers 0 through 6. additional ven- dor-specific registers are implemented within the range of 16 to 31. all the registers are described in the regis- ter information section on page 46. management register access the management interface consists of two pins, man- agement data clock (mdc) and management data input/output (mdio). the 3x38 is designed to support an mdc frequency specified up to 12.5 mhz. the mdio line is bidirectional and may be shared by up to 32 devices. the mdio pin requires a 1.5 k w pull-up resistor which, during idle and turnaround periods, will pull mdio to a logic one state. each mii management data frame is 64 bits long. the first 32 bits are preamble consisting of 32 continuous logic one bits on mdio and 32 corre- sponding cycles on mdc. following preamble is the start-of-frame field indicated by a <01> pattern. the next field signals the operation code (op). <10> indi- cates read from mii management register operation, and <01> indicates write to mii management register operation. the next two fields are phy device address and mii management register address. both of them are 5 bits wide, and the most significant bit is trans- ferred first. during read operation, a 2-bit turnaround (ta) time spacing between the register address field and data field is provided for the mdio to avoid contention. fol- lowing the turnaround time, a 16-bit data stream is read from or written into the mii management registers of the 3x38. 32 lucent technologies inc. 3X38FTR 208-pin sqfp preliminary data sheet octal-fet for 10base-t/100base-tx/fx september 2000 functional description (continued) the 3x38 supports a preamble suppression mode as indicated by a 1 in bit 6 of the basic mode status regis- ter (bmsr, address 01h). if the station management entity (i.e., mac or other management controller) determines that all phys in the system support pream- ble suppression by reading a 1 in this bit, then the sta- tion management entity need not generate preamble for each management transaction. the 3x38 requires a single initialization sequence of 32 bits of preamble fol- lowing powerup/hardware reset. this requirement is generally met by the mandatory pull-up resistor on mdio or the management access made to determine whether preamble suppression is supported. while the 3x38 will respond to management accesses without preamble, a minimum of one idle bit between man- agement transactions is required as specified in ieee 802.3u. interrupt the 3x38 implements interrupt capability that can be used to notify the management station of certain events. interrupt requested by any of the eight phys is combined in this pin. it generates an active-high inter- rupt pulse on the mask_stat_int output pin when- ever one of the interrupt status registers (register address 31) becomes set while its corresponding inter- rupt mask register is unmasked. reading the interrupt status register (register 31) shows the source of the interrupt and clears the interrupt output signal. 100base-x module the 3x38 implements 100base-x compliant pcs and pma and 100base-tx compliant tp-pmd as illustrated in figure 12. bypass options for each of the major functional blocks within the 100base-x pcs provide flexibility for various applications. 100 mbits/s phy loopback is included for diagnostic purposes. 5-7519(f).a.r1 figure 12. 100base-x data path mii-to-rmii conversion rxen rxdv crs rxd[3:0] rxclk descrambler serial-to-parallel clock recovery equalizer 4b/5b ryp_scr byp_4b5b byp_align rx state machine rxd[1:0] crs_dv fosd tpin 100base-x receiver rmii-to-mii conversion txen txd[1:0] tx state machine col txclk txen txer parallel-to-serial 4b/5b decode scrambler byp_4b5b byp_scr byp_align mlt-3 state machine 10/100 tx driver tpout 100base-x transmitter txd[3:0] decode 100m phy loopback lucent technologies inc. 33 preliminary data sheet 3X38FTR 208-pin sqfp september 2000 octal-fet for 10base-t/100base-tx/fx functional description (continued) 100base-x transmitter the 100base-x transmitter consists of functional blocks which convert synchronous 4-bit nibble data, as pro- vided by the internal mii, to a 125 mbits/s serial data stream. this data stream may be routed either to the on-chip twisted-pair pmd for 100base-tx signaling, or to an external fiber-optic pmd for 100base-fx applica- tions. the 3x38 implements the 100base-x transmit state machine as specified in the ieee 802.3u stan- dard, clause 24 and comprises the following functional blocks in its data path: n symbol encoder n scrambler block n parallel/serial converter and nrz/nrzi encoder block symbol encoder the symbol encoder converts 4-bit (4b) nibble data generated by the rmii-mii module into 5-bit (5b) sym- bols for transmission. this conversion is required to allow control symbols to be combined with data sym- bols. refer to the table below for 4b to 5b symbol map- ping. following onset of the txen signal, the 4b/5b symbol encoder replaces the first two nibbles of the preamble from the mac frame with a /j/k code-group pair (11000 10001) start-of-stream delimiter (ssd). the symbol encoder then replaces subsequent 4b codes with corresponding 5b symbols. following negation of the txen signal, the encoder substitutes the first two idle symbols with a /t/r code-group pair (01101 00111) end-of-stream delimiter (esd) and then contin- uously injects idle symbols into the transmit data stream until the next transmit packet is detected. table 11. symbol code scrambler symbol name 5b code [4:0] 4b code [3:0] interpretation 0 11110 0000 data 0 1 01001 0001 data 1 2 10100 0010 data 2 3 10101 0011 data 3 4 01010 0100 data 4 5 01011 0101 data 5 6 01110 0110 data 6 7 01111 0111 data 7 8 10010 1000 data 8 9 10011 1001 data 9 a 10110 1010 data a b 10111 1011 data b c 11010 1100 data c d 11011 1101 data d e 11100 1110 data e f 11101 1111 data f i 11111 undefined idle: interstream fill code j 11000 0101 first start-of-stream delimiter k 10001 0101 second start-of-stream delimiter t 01101 undefined first end-of-stream delimiter r 00111 undefined second end-of-stream delimiter h 00100 undefined halt: transfer error v 00000 undefined invalid code v 00001 undefined invalid code v 00010 undefined invalid code v 00011 undefined invalid code v 00101 undefined invalid code 34 lucent technologies inc. 3X38FTR 208-pin sqfp preliminary data sheet octal-fet for 10base-t/100base-tx/fx september 2000 v 00110 undefined invalid code v 01000 undefined invalid code v 01100 undefined invalid code v 10000 undefined invalid code v 11001 undefined invalid code symbol name 5b code [4:0] 4b code [3:0] interpretation for 100base-tx applications, the scrambler is required to control the radiated emissions at the media connec- tor and on the twisted-pair cable. the 3x38 implements a data scrambler as defined by the tp-pmd stream cipher function. the scrambler uses an 11-bit ciphering linear feedback shift register (lfsr) with the following recursive linear function: x[n] = x[n C 11] + x[n C 9] (modulo 2) the output of the lfsr is combined with data from the encoder via an exclusive-or logic function. by scram- bling the data, the total energy launched onto the cable is randomly distributed over a wide frequency range. parallel-to-serial and nrz-to-nrzi conversion after the transmit data stream is scrambled, data is loaded into a shift register and clocked out with a 125 mhz clock into a serial bit stream. the serialized data is further converted from nrz-to-nrzi format, which produces a transition on every logic one and no transition on logic zero. collision detect during 100 mbits/s half-duplex operation, collision con- dition is detected if the transmitter and receiver become active simultaneously. collision detection is indicated by the col signal of the internal mii. when the fdup led input configuration is pulled low, the fudup led outputs are redefined to be col led outputs. for full- duplex applications, the col signal is never asserted. 100base-x receiver the 100base-x receiver consists of functional blocks required to recover and condition the 125 mbits/s receive data stream. the 3x38 implements the 100base-x receive state machine diagram as given in ansi */ ieee standard 802.3u, clause 24. the 125 mbits/s receive data stream may originate from the on-chip, twisted-pair transceiver in a 100base-tx application. alternatively, the receive data stream may be generated by an external optical receiver as in a 100base-fx application. the receiver block consists of the following functional blocks: n equalizer n clock recovery module n nrzi/nrz and serial/parallel decoder n descrambler n symbol alignment block n symbol decoder n collision detect block n carrier sense block n stream decoder block clock recovery the clock recovery module accepts 125 mbits/s scram- bled nrzi data stream from either the on-chip 100base-tx receiver or from an external 100base-fx transceiver. the 3x38 uses an onboard digital phase- locked loop (pll) to extract clock information of the incoming nrzi data, which is then used to retime the data stream and set data boundaries. after power-on or reset, the pll locks to a free-running 25 mhz clock derived from the external clock source. when initial lock is achieved, the pll switches to lock to the data stream, extracts a 125 mhz clock from the data, and uses it for bit framing of the recovered data. nrzi-to-nrz and serial-to-parallel conversion the recovered data is converted from nrzi to nrz. the data is not necessarily aligned to 4b/5b code- groups boundary. xored by the deciphering lfsr and descrambled. * ansi is a registered trademark of the american national standards institute. functional description (continued) table 11. symbol code scrambler (continued) lucent technologies inc. 35 preliminary data sheet 3X38FTR 208-pin sqfp september 2000 octal-fet for 10base-t/100base-tx/fx functional description (continued) data descrambling the descrambler acquires synchronization with the data stream by recognizing idle bursts of 40 or more bits and locking its deciphering linear feedback shift register (lfsr) to the state of the scrambling lfsr. upon achieving synchronization, the incoming data is xored by the deciphering lfsr and descrambled. in order to maintain synchronization, the descrambler continuously monitors the validity of the unscrambled data that it generates. to ensure this, a link state moni- tor and a hold timer are used to constantly monitor the synchronization status. upon synchronization of the descrambler, the hold timer starts a 722 m s countdown. upon detection of sufficient idle symbols within the 722 m s period, the hold timer will reset and begin a new countdown. this monitoring operation will continue indefinitely given a properly operating network connec- tion with good signal integrity. if the link state monitor does not recognize sufficient unscrambled idle sym- bols within the 722 m s period, the descrambler will be forced out of the current state of synchronization and reset in order to reacquire synchronization. symbol alignment the symbol alignment circuit in the 3x38 determines code word alignment by recognizing the /j/k delimiter pair. this circuit operates on unaligned data from the descrambler. once the /j/k symbol pair (11000 10001) is detected, subsequent data is aligned on a fixed boundary. symbol decoding the symbol decoder functions as a look-up table that translates incoming 5b symbols into 4b nibbles. the symbol decoder first detects the /j/k symbol pair pre- ceded by idle symbols and replaces the symbol with mac preamble. all subsequent 5b symbols are con- verted to the corresponding 4b nibbles for the duration of the entire packet. this conversion ceases upon the detection of the /t/r symbol pair denoting the end-of- stream delimiter (esd). the translated data is pre- sented on the rxd[3:0] signal lines with rxd[0] repre- senting the least significant bit of the translated nibble. valid data signal the valid data signal (rxdv) indicates that recovered and decoded nibbles are being presented on the rxd[3:0] outputs synchronous to rxclk. rxdv is asserted when the first nibble of translated /j/k is ready for transfer over the internal mii. it remains active until either the /t/r delimiter is recognized, link test indicates failure, or no signal is detected. on any of these conditions, rxdv is deasserted. receiver errors the rxer signal is used to communicate receiver error conditions. while the receiver is in a state of hold- ing rxdv asserted, the rxer will be asserted for each code word that does not map to a valid code-group. 100base-x link monitor the 100base-x link monitor function allows the receiver to ensure that reliable data is being received. without reliable data reception, the link monitor will halt both transmit and receive operations until such time that a valid link is detected. the 3x38 performs the link integrity test as outlined in ieee 100base-x (clause 24) link monitor state dia- gram. the link status is multiplexed with 10 mbits/s link status to form the reportable link status bit in serial management register 1 and driven to the lnkled pins. when persistent signal energy is detected on the net- work, the logic moves into a link-ready state after approximately 500 m s and waits for an enable from the autonegotiation module. when received, the link-up state is entered and the transmit and receive logic blocks become active. should autonegotiation be dis- abled, the link integrity logic moves immediately to the link-up state after entering the link-ready state. carrier sense carrier sense (crs) for 100 mbits/s operation is asserted upon the detection of two noncontiguous zeros occurring within any 10-bit boundary of the receive data stream. the carrier sense function is independent of symbol alignment. in default mode, crs is asserted during either packet transmission or reception. when crs_sel is pulled high at powerup or reset, or when register 29, bit 10 is written to a 1, crs is asserted only during packet reception. when the idle symbol pair is detected in the receive data stream, crs is deasserted. in repeater mode, crs is only asserted due to receive activity. crs is intended to encapsulate rxdv. 36 lucent technologies inc. 3X38FTR 208-pin sqfp preliminary data sheet octal-fet for 10base-t/100base-tx/fx september 2000 functional description (continued) bad ssd detection a bad start-of-stream delimiter (bad ssd) is an error condition that occurs in the 100base-x receiver if car- rier is detected (crs asserted) and a valid /j/k set of code-groups (ssd) is not received. if this condition is detected, then the 3x38 will assert rxer and present rxd[3:0] = 1110 to the internal mii for the cycles that correspond to received 5b code- groups until at least two idle code-groups are detected. in addition, the false carrier counter will be incremented by one. once at least two idle code groups are detected, rxer and crs become deas- serted. far-end fault indication autonegotiation provides a mechanism for transferring information from the local station to the link partner that a remote fault has occurred for 100base-tx. since autonegotiation is not currently specified for operation over fiber, the far-end fault indication function (fefi) provides this capability for 100base-fx applications. a remote fault is an error in the link that one station can detect while the other cannot. an example of this is a disconnected wire at a stations transmitter. this station will be receiving valid data and detect that the link is good via the link integrity monitor, but will not be able to detect that its transmission is not propagating to the other station. a 100base-fx station that detects such a remote fault may modify its transmitted idle stream from all ones to a group of 84 ones followed by a single 0. this is referred to as the fefi idle pattern. the fefi function is controlled by bit 1 of register 29. it is initialized to 1 (enabled) if the fosel pin is at logic high level during powerup or reset. if the fefi function is enabled, the 3x38 will halt all current operations and transmit the fefi idle pattern when fosd signal is deasserted following a good link indication from the link integrity monitor. if three or more fefi idle patterns are detected by the 3x38, then bit 4 of the basic mode status register (address 01) is set to one until read by management. additionally, upon detection of far-end fault, all receive and transmit mii activity is disabled/ ignored. carrier integrity monitor the carrier integrity monitor (cim) function protects the repeater from transient conditions that would otherwise cause spurious transmission due to a faulty link. this function is required for repeater applications and is not specified for switch applications. the cim function is controlled by bit 3 of register 29. it is initialized to 1 (enabled) during powerup or reset. if the cim determines that the link is unstable, the 3x38 will not propagate the received data or control signaling to the mii and will ignore data transmitted via the mii. the 3x38 will continue to monitor the receive stream for valid carrier events. the false carrier counter incre- ments each time the link is unstable (bad ssd). two back-to-back false carrier events will isolate the phy, incrementing the associated isolate counter. register 21 provides counters of carrier integrity events when register 20, bit 11 is written to a 1 (the fifo is in 32-bit mode). 100base-tx transceiver 3x38 implements a tp-pmd compliant transceiver for 100base-tx operation. the differential transmit driver is shared by the 10base-t and 100base-tx sub- systems. this arrangement results in one device that uses the same external magnetics for both the 10base-t and the 100base-tx transmission with sim- ple rc component connections. the individually wave- shaped 10base-t and 100base-tx transmit signals are multiplexed in the transmit output driver section. transmit drivers the 3x38 100base-tx transmit driver implements mlt- 3 translation and wave-shaping functions. the rise/fall time of the output signal is closely controlled to conform to the target range specified in the ansi tp-pmd stan- dard. twisted-pair receiver for 100base-tx operation, the incoming signal is detected by the on-chip, twisted-pair receiver that com- prises the differential line receiver, an adaptive equal- izer, and baseline wander compensation circuits. the 3x38 uses an adaptive equalizer which changes equalizer frequency response in accordance with cable length. the cable length is estimated based on the incoming signal behavior. the equalizer tunes itself automatically for any cable length to compensate for the amplitude and phase distortions incurred from the cable. lucent technologies inc. 37 preliminary data sheet 3X38FTR 208-pin sqfp september 2000 octal-fet for 10base-t/100base-tx/fx functional description (continued) 10base-t module the 10base-t transceiver module is ieee 802.3 com- pliant. it includes the receiver, transmitter, collision, heartbeat, loopback, jabber, waveshaper, and link integrity functions, as defined in the standard. figure 13 provides an overview for the 10base-t module. the 3x38 10base-t module is comprised of the follow- ing functional blocks: n manchester encoder and decoder n collision detector n link test function n transmit driver and receiver n serial and parallel interface n jabber and sqe test functions n polarity detection and correction 5-7521(f).b figure 13. 10base-t module data path operation modes the 3x38 10base-t module is capable of operating in either half-duplex mode or full-duplex mode. in half-duplex mode, the 3x38 functions as an ieee 802.3 compliant transceiver with fully integrated filtering. the col signal is asserted during collisions or jabber events, and the crs signal is asserted during transmit and receive. in full- duplex mode, the 3x38 can simultaneously transmit and receive data. manchester encoder/decoder: data encoding and transmission begins when the transmit enable input (txen) goes high and continues as long as the transceiver is in good link state. transmission ends when the transmit enable input goes low. the last transition occurs at the center of the bit cell if the last bit is a 1, or at the boundary of the bit cell if the last bit is 0. decoding is accomplished by a differential input receiver circuit and a phase-locked loop that separates the manchester-encoded data stream into clock signals and nrz data. the decoder detects the end of a frame when no more midbit transitions are detected. within one and a half bit times after the last bit, carrier sense is deas- serted. tpin receive filter smart squelch clock recovery 10base-t receive pcs rxclk crs rxd[3:0] rxdv col mii-to-rmii converter rcrs_dv rrxd[1:0] 10/100 tx driver wave shaper 10base-t transmit pcs txen txer txd[3:0] txclk mii-to-rmii converter rtxen rtxclk rtxd[1:0] tpout 38 lucent technologies inc. 3X38FTR 208-pin sqfp preliminary data sheet octal-fet for 10base-t/100base-tx/fx september 2000 functional description (continued) transmit driver and receiver: the 3x38 integrates all the required signal conditioning functions in its 10base-t block such that external filters are not required. only an isolation transformer and impedance matching resistors are needed for the 10base-t trans- mit and receive interface. the internal transmit filtering ensures that all the harmonics in the transmit signal are attenuated properly. smart squelch: the smart squelch circuit is responsi- ble for determining when valid data is present on the differential receive. the 3x38 implements an intelligent receive squelch on the tpi differential inputs to ensure that impulse noise on the receive inputs will not be mistaken for a valid signal. the squelch circuitry employs a combination of amplitude and timing mea- surements (as specified in the ieee 802.3 10base-t standard) to determine the validity of data on the twisted-pair inputs. the signal at the start of the packet is checked by the analog squelch circuit, and any pulses not exceeding the squelch level (either positive or negative, depend- ing upon polarity) will be rejected. once this first squelch level is overcome correctly, the opposite squelch level must then be exceeded within 150 ns. finally, the signal must exceed the original squelch level within an additional 150 ns to ensure that the input waveform will not be rejected. only after all of these conditions have been satisfied will a control signal be generated to indicate to the remainder of the circuitry that valid data is present. valid data is considered to be present until the squelch level has not been generated for a time longer than 200 ns, indicating end of packet. once good data has been detected, the squelch levels are reduced to mini- mize the effect of noise, causing premature end-of- packet detection. the receive squelch threshold level can be lowered for use in longer cable applications. this is achieved by setting bit 4 of register 30. carrier sense: carrier sense (crs) is asserted due to receive activity once valid data is detected via the smart squelch function. for 10 mbits/s half-duplex operation, crs is asserted during either packet transmission or reception. for 10 mbits/s full-duplex operation, the crs is asserted only due to receive activity. in repeater mode, crs is only asserted due to receive activity. crs is deasserted following an end of packet. collision detection: the rmii does not have a colli- sion pin. collision is detected internal to the mac, which is generated by an and function of txen and crs derived from crs_dv. crs_dv cannot be directly anded with txen because crs_dv may tog- gle at the end of a frame to provide separation between crs and rxdv. the internal mii will still generate the col signal, but this information is not passed to the mac via the rmii. link test function: a link pulse is used to check the integrity of the connection with the remote end. if valid link pulses are not received, the link detector disables the 10base-t twisted-pair transmitter, receiver, and col- lision detection functions. the link pulse generator produces pulses as defined in the ieee 802.3 10base-t standard. each link pulse is nominally 100 ns in duration and is transmitted every 16 ms, in the absence of transmit data. automatic link polarity detection: the 3x38's 10base-t transceiver module incorporates an auto- matic link polarity detection circuit. the inverted polar- ity is determined when seven consecutive link pulses of inverted polarity or three consecutive packets are received with inverted end-of-packet pulses. if the input polarity is reversed, the error condition will be automat- ically corrected and reported in bit 6 of register 28. the automatic link polarity detection function can be disabled by setting bit 3 of register 30. clock synthesizer the 3x38 implements a clock synthesizer that gener- ates all the reference clocks needed from a single external frequency source. the clock source must be a cmos signal at 50 mhz or 125 mhz 100 ppm. autonegotiation the autonegotiation function provides a mechanism for exchanging configuration information between two ends of a link segment and automatically selecting the highest-performance mode of operation supported by both devices. fast link pulse (flp) bursts provide the signaling used to communicate autonegotiation abilities between two devices at each end of a link segment. for further detail regarding autonegotiation, refer to clause 28 of the ieee 802.3u specification. the 3x38 sup- ports four different ethernet protocols, so the inclusion of autonegotiation ensures that the highest-perfor- mance protocol will be selected based on the ability of the link partner. lucent technologies inc. 39 preliminary data sheet 3X38FTR 208-pin sqfp september 2000 octal-fet for 10base-t/100base-tx/fx functional description (continued) the autonegotiation function within the 3x38 can be controlled either by internal register access or by the use of configuration pins. at powerup and at device reset, the configuration pins are sampled. if disabled, autonegotiation will not occur until software enables bit 12 in register 0. if autonegotiation is enabled, the nego- tiation process will commence immediately. when autonegotiation is enabled, the 3x38 transmits the abilities programmed into the autonegotiation advertisement register at address 04h via flp bursts. any combination of 10 mbits/s, 100 mbits/s, half- duplex, and full-duplex modes may be selected. auto- negotiation controls the exchange of configuration information. upon successful autonegotiation, the abili- ties reported by the link partner are stored in the auto- negotiation link partner ability register at address 5. the contents of the autonegotiation link partner ability register are used to automatically configure to the highest-performance protocol between the local and far-end nodes. software can determine which mode has been configured by autonegotiation by comparing the contents of register 04h and 05h and then selecting the technology whose bit is set in both registers of high- est priority relative to the following list: 1. 100base-tx full duplex (highest priority) 2. 100base-tx half duplex 3. 10base-t full duplex 4. 10base-t half duplex (lowest priority) the basic mode control register at address 00 provides control of enabling, disabling, and restarting of the autonegotiation function. when autonegotiation is dis- abled, the speed selection bit (bit 13) controls switching between 10 mbits/s or 100 mbits/s operation, while the duplex mode bit (bit 8) controls switching between full- duplex operation and half-duplex operation. the speed selection and duplex mode bits have no effect on the mode of operation when the autonegotiation enable bit (bit 12) is set. the basic mode status register at address 01h indi- cates the set of available abilities for technology types (bits 15 to 11), autonegotiation ability (bit 3), and extended register capability (bit 0). these bits are hard- wired to indicate the full functionality of the 3x38. the bmsr also provides status on: 1. whether autonegotiation is complete (bit 5). 2. whether the link partner is advertising that a remote fault has occurred (bit 4). 3. whether a valid link has been established (bit 2). the autonegotiation advertisement register at address 04h indicates the autonegotiation abilities to be adver- tised by the 3x38. all available abilities are transmitted by default, but any ability can be suppressed by writing to this register or configuring external pins. the autonegotiation link partner ability register at address 05h indicates the abilities of the link partner as indicated by autonegotiation communication. the con- tents of this register are considered valid when the autonegotiation complete bit (bit 5, register address 01h) is set. the 3x38 contains an enhanced autonegotiation func- tion that can detect instantaneous speed changes from 10 mbits/s to 100 mbits/s. this function can be acti- vated by the litf_en input pin, or by setting register 30, bit 6 high. register 31 provides enhanced autone- gotiation status information for debugging purposes. led operational modes the 3x38 provides three basic led output modes of operation: parallel mode, serial mode, and bicolor led mode. the parallel mode provides four led output sig- nals for each of the eight channels (32 signals total): activity, link, speed, and full duplex. the serial mode multiplexes all eight channels led status information onto one single serial output stream. the single data stream, serdata, is accompanied with a serial clock, serclk, and a serial led strobe, serstrobe (three signals total). the bicolor led mode provides two led output sig- nals, biactled [7:0] and bilinkled [7:0], for each of the eight channels (16 signals total). these two outputs are intended to drive a bicolor led, packaged in one single led package. this reduces the total number of led packages to one per channel. 40 lucent technologies inc. 3X38FTR 208-pin sqfp preliminary data sheet octal-fet for 10base-t/100base-tx/fx september 2000 functional description (continued) the led mode of operation is selected at powerup or reset by the led_mode [1:0] configuration pins as shown below. table 12. led modes pin 1 pin 0 mode outputs 0 0 parallel speedled_[7:0], fdupled[7:0], linkled[7:0], actled[7:0] 0 1 reserved reserved 1 0 serial serclk, serdata, serstrobe 1 1 bicolor actled[7:0], linkled[7:0] additional led output control can be obtained by using the management registers. each led can be forced either high or low via register 20 on a per-channel basis. any register 20 bit that is set overrides the led value, no matter what mode the device is in. in bicolor mode, the activity and link leds can be set to flash at a 320 ms rate by setting register 20, bit 9 for activity and bit 8 for link, on a per-channel basis. when flash is activated, the led will continuously flash at the 320 ms rate regardless of the link state or data activity state. the activity led output can operate in three different modes: pulse stretching, pulse blinking, or no stretch- ing or blinking. with no stretching or blinking, the activ- ity led will light for as long as there is transmit and/or receive activity only. when pulse stretching is enabled by pulling the stretch_led pin high at powerup or reset, or by setting register 29, bit 7 high, the activity led will light approximately 42 ms to 84 ms, when transmit or receive activity is detected. if the blink func- tion is enabled by pulling the blink_led pin high at powerup or reset, or by setting register 29, bit 11 high, the activity led will blink 500 ms on 500 ms off every time transmit or receive activity is detected. if both blink and stretch are enabled, the activity led will blink 2.5 s on 2.5 s off, every time a packet is received. all led outputs are 10 ma active-high outputs, no external buffers are required. parallel led mode when operating in the parallel led mode, each chan- nel has four led outputs: activity, link, speed, and full duplex/collision. the activity led can be stretched or can blink on transmit or receive activity as described above. each of these four leds can be forced on or off by using register 20. serial led mode when the serial led mode is selected, the led status information from all eight channels is multiplexed into one serial led data stream. the activity led function can still be stretched or blink as described above and each led output can still be forced high or low as described above. the 3x38 contains a serial led mode. this mode is selected by holding the input led mode pin 1 high and the led mode pin 0 low. this mode is a 3-pin serial led mode. lucent technologies inc. 41 preliminary data sheet 3X38FTR 208-pin sqfp september 2000 octal-fet for 10base-t/100base-tx/fx functional description (continued) table 13. serial led pin descriptions serial stream order every serledstrobe indicates a serial led stream follows. each serial led stream consists of the following components. table 14. serial led port order chnl4:0 is the current phy channel count (0 = channel 0 (a), 1 = channel 1, . . . , 00101 = channel 5 (f)). all other signals are discussed above. note that data always goes high when strobe goes high; thus, if a user wishes to implement a 2-pin interface using just clock and data, this high pulse can be used for synchronization. the chnl4:0 will cycle through each of the phy addresses from 0 to 7 before starting over. since the led strobe occurs once every 32 clocks, there will be 17 clocks between each data burst. thus, the data burst looks some- thing like (for phy channel 0, then channel 1) figure 14. signal type description serledclk output this is roughly a 1 mhz output clock (25 mhz/16 mhz). all other serial led signals change 80 ns200 ns after the falling edge of this clock. this clock is generated from ledclk. serleddata output this is a serial stream, clocked by serled clock. the serial stream contents are discussed below. serledstrobe output this is a strobe, which goes high at the start of each serial stream. a strobe occurs once every 32 clocks. clock #C10123456 strobe10000000 data 1 chnl(4) chnl(3) chnl(2) chnl(1) chnl(0) act link clock # 7 8 9 10 11 12 13 strobe0000000 data speed fulldup coll jabber aps rs xs 3X38FTR 208-pin sqfp preliminary data sheet octal-fet for 10base-t/100base-tx/fx september 2000 42 lucent technologies inc. functional description (continued) 5-7897(f).r1 figure 14. timing diagram bicolor led mode when bicolor led mode is selected, the 3x38 provides two led output signals per channel. these signals are the activity led outputs (biactled) and the link led outputs (bilinkled). these two signals work together to drive a single bicolor led per channel; this is a single led package with two leds connected in parallel with opposite polarities. typically, the biactled is connected to the anode of a green led with the cathode connected to the bilinkled output. a yellow led is connected to the same outputs in the opposite polarity. the truth table is pro- vided below. table 15. bicolor mode activity pulse stretching and blinking can be used as described above, as well as forcing the leds on, off, or flash- ing. to enable the bicolor led forced mode, register 20, bit 10 must be written to a 1, and then register 20, bits 9 and 8 will be activated. when register 20, bit 9 is written to a 1 the biactled (yellow) will flash 320 ms on, 320 ms off. when register 20, bit 8 is written to a 1, the bilinkled (green) will flash 320 ms on, 320 ms off. other register 20 bits can be used to force these leds on or off. see register 20 description for details. biactled bilinkled bicolor led state indicates 00offno link 0 1 green link up 1 0 yellow activity 1 1 off undefined clk data strobe clk data strobe clk data strobe clk data strobe 01234567890 ccccc a ls fc 1 43210c1pdl 1 1234567890 bpss ar x 0 2345678901 0 123456789 ccccc a ls fc 1 43210c1pdl lucent technologies inc. 43 preliminary data sheet 3X38FTR 208-pin sqfp september 2000 octal-fet for 10base-t/100base-tx/fx functional description (continued) table 16. bicolor led mode descriptions reset operation the 3x38 can be reset either by hardware or software. a hardware reset is accomplished by applying a negative pulse, with a duration of at least 1 ms to the reset_not pin of the 3x38 during normal operation. the device does not internally generate a hardware reset during powerup, an external reset pulse will have to be applied. the 3x38 will come out of reset after 2 ms. a software reset is activated by setting the reset bit in the basic mode control register (bit 15, register 00h). this bit is self-clearing and, when set, will return a value of 1 until the software reset operation has completed. hardware reset operation samples the pins and initializes all registers to their default values. this process includes re-evaluation of all hardware-configurable registers. a hardware reset affects all eight phys in the device. a software reset can reset an individual phy, and it does not latch the external pins but does reset the registers to their respective default values. logic levels on several i/o pins are detected during a hardware reset to determine the initial functionality of 3x38. some of these pins are used as output ports after reset operation. care must be taken to ensure that the configuration setup will not interfere with normal operation. dedicated con- figuration pins can be tied to vcc or ground directly. configuration pins multiplexed with logic level output functions should be either weakly pulled up or weakly pulled down through resistors. configuration pins multiplexed with led outputs should be set up with one of the following circuits shown in figure 15. note: if a resistor value other then 1.5 k w is used for the led current limit resistor the configuration pull-up should also be this value. 5-6783(f).d figure 15. hardware reset configuration r20b10 r20b9 r20b8 state 1 x x bicolor mode 0 1 0 continuously flash yellow (320 ms on, 320 ms off) 0 0 1 continuously flash green (320 ms on, 320 ms off) 01 1na i/o pin i/o pin logic 1 configuration logic 0 configuration v dd r1 r2 r2 3X38FTR 208-pin sqfp preliminary data sheet octal-fet for 10base-t/100base-tx/fx september 2000 44 lucent technologies inc. mii station management basic operation the primary function of station management is to transfer control and status information about the 3x38 to a man- agement entity. this function is accomplished by the mdc clock input, which has a maximum frequency of 12.5 mhz, along with the mdio signal. the mii management interface uses mdc and mdio to physically transport information between the phy and the station management entity. a specific set of registers and their contents (described in table 18) defines the nature of the information trans- ferred across the mdio interface. frames transmitted on the mii management interface will have the frame struc- ture shown in table 17. the order of bit transmission is from left to right. note that reading and writing the management register must be completed without interruption. the port addresses are set by the phyadd pins (see table 19 for more detail). table 17. mii management frame format table 18. mii management framesfield descriptions read/write (r/w) pre st op phy_add regad ta data idle r 1. . .1 01 10 aaaaa rrrrr z0 dddddddddddddddd z w 1. . .1 01 01 aaaaa rrrrr 10 dddddddddddddddd z field descriptions pre preamble . the 3x38 will accept frames with no preamble. this is indicated by a 1 in register 1, bit 6. st start of frame. the start of frame is indicated by a 01 pattern. op operation code . the operation code for a read transaction is 10. the operation code for a write transaction is a 01. phy_add phy address . the phy address is 5 bits, allowing for 32 unique addresses. the first phy address bit transmitted and received is the msb of the address. a station management entity that is attached to multiple phy entities must have prior knowledge of the appropriate phy address for each entity. regad register address. the register address is 5 bits, allowing for 32 unique registers within each phy. the first register address bit transmitted and received is the msb of the address. ta turnaround . the turnaround time is a 2-bit time spacing between the register address field, and the data field of a frame, to avoid drive contention on mdio during a read transaction. during a write to the 3x38, these bits are driven to 10 by the station. during a read, the mdio is not driven during the first bit time and is driven to a 0 by the 3x38 during the second bit time. data data . the data field is 16 bits. the first bit transmitted and received will be bit 15 of the register being addressed. idle idle condition. the idle condition on mdio is a high-impedance state. all three state drivers will be disabled, and the phys pull-up resistor will pull the mdio line to a logic 1. lucent technologies inc. 45 preliminary data sheet 3X38FTR 208-pin sqfp september 2000 octal-fet for 10base-t/100base-tx/fx mii station management (continued) phy_add[2:0] these signals set the management addresses and are decoded as follows. table 19. phy addresses unmanaged operations the 3x38 allows the user to set some of the station management functions during powerup or reset by strapping outputs high or low through weak resistors (10 k w ). table 20 shows the functions and their associated output pins. for detailed information on the functions of these output pins, refer to the section on management registers described earlier in this data sheet. also, information on how these output pins should be strapped is discussed in the pin descriptions section (table 3 through table 7). table 20. output pins phy_add[2:0] port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7 000 01234567 001 8 9 10 11 12 13 14 15 010 16 17 18 19 20 21 22 23 011 24 25 26 27 28 29 30 31 100 678910111213 101 12 13 14 15 16 17 18 19 110 18 19 20 21 22 23 24 25 111 00000000 function (register/bit) pin internal pull-up/pull-down phy_add[2:0] speedled_[2:0] 50 k w down no_lp speedled_3 50 k w down speed fdupled_5 50 k w up carin_en actled_5 50 k w down scram_desc_bypass actled_3 50 k w down stretch_led actled_0 50 k w up full_dup fdupled_1 50 k w up crs_sel fdupled_0 50 k w down isolate_mode fdupled_2 50 k w down fx_mode_en[7:0] linkled[7:0] 50 k w down reserved fdupled_3 50 k w down auto_en actled_4 50 k w down lift_en actled_2 50 k w up blink_led_mode actled_1 50 k w down led_mode[1:0] speedled[5:4] 50 k w down rmii_mode fdupled_4 50 k w down 3X38FTR 208-pin sqfp preliminary data sheet octal-fet for 10base-t/100base-tx/fx september 2000 46 lucent technologies inc. register information register descriptions the mii management 16-bit register set implemented is as follows. the phy address pins control the management pins. table 21. summary of management registers (mr) table 22. mr0control register bit descriptions register address symbol name default (hex code) 0 mr0 control 3000h 1 mr1 status 7849h 2 mr2 phy identifier 1 0180h 3 mr3 phy identifier 2 bb80h 4 mr4 autonegotiation advertisement 01e1h 5 mr5 autonegotiation link partner ability (base page, next page) 0000 6 mr6 autonegotiation expansion 0000 7 mr7 next page transmit 0000 819 mr8mr19 reserved 20 mr20 21 mr21 rxer counter 0000 2227 mr22mr27 reserved 28 mr28 device specific 1 (status) 29 mr29 device specific 2 (100 mbits/s control) 2080 30 mr30 device specific 3 (10 mbits/s control) 0000 31 mr31 quick status register bit * type ? description 0.15 (sw_reset) r/w reset. setting this bit to a 1 will reset the 3x38. all registers will be set to their default state. this bit is self-clearing. the default is 0. 0.14 (loopback) r/w loopback. when this bit is set to 1, no data transmission will take place on the media. any receive data will be ignored. the loopback signal path will contain all circuitry up to, but not including, the pmd. the autonegotiation must be turned off, and then loopback can be initiated. transmit data can start 2 ms after loopback is initiated. the default value is a 0. 0.13 (speed100) r/w speed selection. the value of this bit reflects the current speed of operation (1 = 100 mbits/s; 0 = 10 mbits/s). this bit will only affect operating speed when the auto- negotiation enable bit (register 0, bit 12) is disabled (0). this bit is ignored when autonegotiation is enabled (register 0, bit 12). this bit is anded with the speed pin signal (v13). 0.12 (nway_ena) r/w autonegotiation enable. the autonegotiation process will be enabled by setting this bit to a 1. the default state is a 1. this bit is anded with the auto_en pin dur- ing powerup and reset. 0.11 (pwrdn) r/w powerdown. the 3x38 may be placed in a low-power state by setting this bit to a 1; both the 10 mbits/s transceiver and the 100 mbits/s transceiver will be powered down. while in the powerdown state, the 3x38 will respond to management trans- actions. the default state is a 0. * the format for the bit descriptions is as follows: the first number is the register number, the second number is the bit posit ion in the register. ? r = read, w = write, na = not applicable. lucent technologies inc. 47 preliminary data sheet 3X38FTR 208-pin sqfp september 2000 octal-fet for 10base-t/100base-tx/fx * the format for the bit descriptions is as follows: the first number is the register number, the second number is the bit posit ion in the register. ? r = read, w = write, na = not applicable. table 23. mr1status register bit descriptions 0.10 (isolate) r/w isolate. when this bit is set to a 1, the mii outputs will be brought to the high- impedance state. the default state is a 0. 0.9 (redonway) r/w restart autonegotiation. normally, the autonegotiation process is started at pow- erup. the process may be restarted by setting this bit to a 1. the default state is a 0. the nwaydone bit (register 1, bit 5) is reset when this bit goes to a 1. this bit is self-cleared when autonegotiation restarts. 0.8 (full_dup) r/w duplex mode. this bit reflects the mode of operation (1 = full duplex; 0 = half duplex). this bit is ignored when the autonegotiation enable bit (register 0, bit 12) is enabled. the default state is a 0. this bit is ored with the full_dup pin (w6). 0.7 (coltst) r/w collision test. when this bit is set to a 1, the 3x38 will assert the internal col signal in response to rtx_en. this bit has no external effect on the rmii or smii pins. 0.6:0 (reserved) na reserved. all bits will read 0. bit * type ? description 1.15 (t4able) r 100base-t4 ability. this bit will always be a 0. 0: not able. 1: able. 1.14 (txfuldup) r 100base-tx full-duplex ability. this bit will always be a 1. 0: not able. 1: able. 1.13 (txhafdup) r 100base-tx half-duplex ability. this bit will always be a 1. 0: not able. 1: able. 1.12 (enfuldup) r 10base-t full-duplex ability. this bit will always be a 1. 0: not able. 1: able. 1.11 (enhafdup) r 10base-t half-duplex ability. this bit will always be a 1. 0: not able. 1: able. 1.10:7 (reserved) r reserved. all bits will read as a 0. 1.6 (no_pa_ok) r suppress preamble. when this bit is set to a 1, it indicates that the 3x38 accepts management frames with the preamble suppressed. 1.5 (nwaydone) r autonegotiation complete. when this bit is a 1, it indicates the autonegotiation process has been completed. the contents of registers mr4, mr5, mr6, and mr7 are now valid. the default value is a 0. this bit is reset when autonegotia- tion is started. 1.4 (rem_flt) r remote fault. when this bit is a 1, it indicates a remote fault has been detected. this bit will remain set until cleared by reading the register. the default is a 0. 1.3 (nwayable) r autonegotiation ability. when this bit is a 1, it indicates the ability to perform autonegotiation. the value of this bit is always a 1. bit * type ? description register information (continued) table 22. mr0control register bit descriptions (continued) * the format for the bit descriptions is as follows: the first number is the register number, the second number is the bit posit ion in the register. ? r = read, w = write, na = not applicable. 3X38FTR 208-pin sqfp preliminary data sheet octal-fet for 10base-t/100base-tx/fx september 2000 48 lucent technologies inc. * the format for the bit descriptions is as follows: the first number is the register number, the second number is the bit posit ion in the register. ? r = read. table 24. mr2, mr3phy identification registers (1 and 2) bit descriptions * the format for the bit descriptions is as follows: the first number is the register number, the second number is the bit posit ion in the register. ? r = read. table 25. mr4autonegotiation advertisement register bit descriptions * the format for the bit descriptions is as follows: the first number is the register number, the second number is the bit posit ion in the register. ? r = read, w = write. 1.2 (lstat_ok) r link status. when this bit is a 1, it indicates a valid link has been established. this bit has a latching function: a link failure will cause the bit to clear and stay cleared until it has been read via the management interface. 1.1 (jabber) r jabber detect. this bit will be a 1 whenever a jabber condition is detected. it will remain set until it is read, and the jabber condition no longer exists. 1.0 (ext_able) r extended capability. this bit indicates that the 3x38 supports the extended register set (mr2 and beyond). it will always read a 1. bit * type ? description 2.15:0 (oui[3:18]) r organizationally unique identifier. the third through the twenty-fourth bit of the oui assigned to the phy manufacturer by the ieee are to be placed in bits 2.15:0 and 3.15:10. the value of bits 15:0 is 0180h. 3.15:10 (oui[19:24]) r organizationally unique identifier. the remaining 6 bits of the oui. the value for bits 15:10 is 1dh. 3.9:4 (model[5:0]) r model number. 6-bit model number of the device. the model number is 38h. 3.3:0 (version[3:0]) r revision number. the value of the present revision number is 3h. bit * type ? description 4.15 (next_page) r/w next page. the next page function is activated by setting this bit to a 1. this will allow the exchange of additional data. data is carried by optional next pages of information. 4.14 (ack) r/w acknowledge. this bit is the acknowledge bit from the link code word. 4.13 (rem_fault) r/w remote fault. when set to 1, the 3x38 indicates to the link partner a remote fault condition. 4.12:11 (reserved) na reserved. these bits will read zero. 4.10 (pause) r/w pause. when set to a 1, it indicates that the 3x38 wishes to exchange flow con- trol information with its link partner. 4.9 (100baset4) r/w 100base-t4. this bit should always be set to 0. 4.8 (100baset_fd) r/w 100base-tx full duplex. if written to 1, autonegotiation will advertise that the 3x38 is capable of 100base-tx full-duplex operation. 4.7 (100basetx) r/w 100base-tx. if written to 1, autonegotiation will advertise that the 3x38 is capa- ble of 100base-tx operation. 4.6 (10baset_fd) r/w 10base-t full duplex. if written to 1, autonegotiation will advertise that the 3x38 is capable of 10base-t full-duplex operation. 4.5 (10baset) r/w 10base-t. if written to 1, autonegotiation will advertise that the 3x38 is capable of 10base-t operation. 4.4:0 (select) r/w selector field . reset with the value 00001 for ieee 802.3. bit * type ? description register information (continued) table 23. mr1status register bit descriptions (continued) lucent technologies inc. 49 preliminary data sheet 3X38FTR 208-pin sqfp september 2000 octal-fet for 10base-t/100base-tx/fx register information (continued) table 26. mr5autonegotiation link partner ability (base page) register bit descriptions * the format for the bit descriptions is as follows: the first number is the register number, the second number is the bit posit ion in the register. ? r = read. table 27. mr5autonegotiation link partner (lp) ability register (next page) bit descriptions * the format for the pin descriptions is as follows: the first number is the register number, the second number is the bit posit ion in the register. ? r = read. bit * type ? description 5.15 (lp_next_page) r link partner next page. when this bit is set to 1, it indicates that the link partner wishes to engage in next page exchange. 5.14 (lp_ack) r link partner acknowledge. when this bit is set to 1, it indicates that the link partner has successfully received at least three consecutive and consis- tent flp bursts. 5.13 (lp_rem_fault) r remote fault. when this bit is set to 1, it indicates that the link partner has a fault. 5.12:5 (lp_tech_ability) r technology ability field. this field contains the technology ability of the link partner. these bits are similar to the bits defined for the mr4 register (see table 25). 5.4:0 (lp_select) r selector field. this field contains the type of message sent by the link part- ner. for ieee 802.3 compliant link partners, this field should read 00001. bit * type ? description 5.15 (lp_next_page) r next page . when this bit is set to a logic 0, it indicates that this is the last page to be transmitted. a logic 1 indicates that additional pages will follow. 5.14 (lp_ack) r acknowledge. when this bit is set to a logic 1, it indicates that the link partner has successfully received its partners link code word. 5.13 (lp_mes_page) r message page. this bit is used by the next _page function to differenti- ate a message page (logic 1) from an unformatted page (logic 0). 5.12 (lp_ack2) r acknowledge 2. this bit is used by the next_page function to indicate that a device has the ability to comply with the message (logic 1) or not (logic 0). 5.11 (lp_toggle) r toggle . this bit is used by the arbitration function to ensure synchroniza- tion with the link partner during next page exchange. logic 0 indicates that the previous value of the transmitted link code word was logic 1. logic 1 indicates that the previous value of the transmitted link code word was logic 0. 5.10:0 (mcf) r message/unformatted code field . with these 11 bits, there are 2048 possible messages. message code field definitions are described in annex 28c of the ieee 802.3u standard. 3X38FTR 208-pin sqfp preliminary data sheet octal-fet for 10base-t/100base-tx/fx september 2000 50 lucent technologies inc. register information (continued) table 28. mr6autonegotiation expansion register bit descriptions * the format for the bit descriptions is as follows: the first number is the register number, the second number is the bit posit ion in the register. ? r = read, lh = latched high. table 29. mr7next page transmit register bit descriptions * the format for the bit descriptions is as follows: the first number is the register number, the second number is the bit posit ion in the register. ? r = read, w = write. bit * type ? description 6.15:5 (reserved) r reserved . 6.4 (par_det_fault) r/lh parallel detection fault. when this bit is set to 1, it indicates that a fault has been detected in the parallel detection function. this fault is due to more than one technology detecting concurrent link conditions. this bit can only be cleared by reading this register. 6.3 (lp_next_page_able) r link partner next page able. when this bit is set to 1, it indicates that the link partner supports the next page function. 6.2 (next_page_able) r next page able. this bit is set to 1, indicating that this device supports the next_page function. 6.1 (page_rec) r/lh page received . when this bit is set to 1, it indicates that a next_page has been received. 6.0 (lp_nway_able) r link partner autonegotiation able. when this bit is set to 1, it indicates that the link partner is autonegotiation able. bit * type ? description 7.15 (next_page) r/w next page. this bit indicates whether or not this is the last next page to be transmit- ted. when this bit is 0, it indicates that this is the last page. when this bit is 1, it indicates there is an additional next page. 7.14 (ack) r acknowledge. this bit is the acknowledge bit from the link code word. 7.13 (message) r/w message page. this bit is used to differentiate a message page from an unformat- ted page. when this bit is 0, it indicates an unformatted page. when this bit is 1, it indicates a formatted page. 7.12 (ack2) r/w acknowledge 2. this bit is used by the next page function to indicate that a device has the ability to comply with the message. it is set as follows: n when this bit is 0, it indicates the device cannot comply with the message. n when this bit is 1, it indicates the device will comply with the message. 7.11 (toggle) r toggle. this bit is used by the arbitration function to ensure synchronization with the link partner during next page exchange. this bit will always take the opposite value of the toggle bit in the previously exchanged link code word: n if the bit is a logic 0, the previous value of the transmitted link code word was a logic 1. n if the bit is a 1, the previous value of the transmitted link code word was a 0. the initial value of the toggle bit in the first next page transmitted is the inverse of the value of bit 11 in the base link code word, and may assume a value of 1 or 0. 7.10:0 (mcf) r/w message/unformatted code field. with these 11 bits, there are 2048 possible messages. message code field definitions are described in annex 28c of the ieee 802.3u standard. lucent technologies inc. 51 preliminary data sheet 3X38FTR 208-pin sqfp september 2000 octal-fet for 10base-t/100base-tx/fx register information (continued) table 30. mr20led and fifo configuration * the format for the bit descriptions is as follows: the first number is the register number, the second number is the bit posit ion in the register. ? r = read, w = write. table 31. mr21rxer counter bit * signal type ? description 20.15:13 reserved r reserved. 20.12 enh_crs_dv r/w enhanced crs_dv . this bit, when written to a 1, changes the behavior of crs_dv in 100 mbits/s mode so that crs_dv only goes high if rxdv (receive data valid) is high. when this bit is a 0 (default), rcrs_dv will go high on crs assertion. default = 0. 20.11 fifo_dep r/w fifo depth . 0 = normal rmii fifo depth (32-bit) 1 = reduced rmii fifo depth (16-bit) (for better latency). default = 0. 20.10 auto_mode r/w automatic mode . disable bicolor automatic mode, when written to a 1. when the bicolor automatic mode is disabled the forced bicolor led mode is entered, such that register 20, bits 9 and 8 are now acti- vated. when in automatic mode (default), the link led will go low whenever activity led is high. default = 0. this bit is only valid in bicolor led mode. 20.9 actled_flash r/w activity led flash . force activity led to flash at 320 ms high/low time, when written to a 1. default = 0. this bit is only valid in bicolor led mode, and automatic mode is disabled. 20.8 linkled_flash r/w link led flash . force link led to flash at 320 ms high/low time, when written to a 1. default = 0. this bit is only valid in bicolor led mode, and automatic mode is disabled. 20.7 fdupled_on r/w fdupled on . force fdupled on, when written to a 1. default = 0. 20.6 fdupled_off r/w fduled off . force fdupled off, when written to a 1 (fdupled on overrides this). default = 0. 20.5 actled_on r/w force act on . force activity led on, when written to a 1. default = 0. 20.4 actled_off r/w force act off . force activity led off, when written to a 1 (act on overrides this). default = 0. 20.3 speedled_on r/w force speed on . force speed led on, when written to a 1. default = 0. 20.2 speedled_off r/w force speed off . force speed led off, when written to a 1 (speed on overrides this). default = 0. 20.1 linkled_on r/w force linkled on . force link led on, when written to a 1. default = 0. 20.0 linkled_off r/w force linkled off . force link led on, when written to a 1 (linkled on overrides this). default = 0. bit * signal type ? description 21.0 count_mode w counter mode . this bit, when 0, puts this register in 16-bit counter mode. when 1, it puts this register in 8-bit counter mode. this bit is reset to a 0 and cannot be read. 21.15:0 count_16 r counter value 16-bit mode . when in 16-bit counter mode, these maintain a count of rxers (receive errors). it is reset on a read oper- ation. * the format for the bit descriptions is as follows: the first number is the register number, the second number is the bit posit ion in the register. ? r = read, w = write, na = not applicable. 3X38FTR 208-pin sqfp preliminary data sheet octal-fet for 10base-t/100base-tx/fx september 2000 52 lucent technologies inc. * the format for the bit descriptions is as follows: the first number is the register number, the second number is the bit posit ion in the register. ? r = read, w = write. table 32. mr28device-specific register 1 (status register) bit descriptions * the format for the bit descriptions is as follows: the first number is the register number, the second number is the bit posit ion in the register. ? r = read, lh = latched high. 21.7:0 count_8 r counter value 8-bit mode . when in 8-bit counter mode, these main- tain a count of rxers (receive errors). it is reset on a read operation. 21.11:8 false_carrier r false carrier count . when in 8-bit mode, these contain a count of false carrier events (802.3 section 27.3.1.5.1). it is reset on a read operation. 21.15:12 disconn r disconnect count . when in 8-bit mode, these contain a count of dis- connect events (link unstable 6, 802.3 section 27.3.1.5.1). it is reset on a read operation. bit * type ? description 28.15:9 (unused) r unused. read as 0. 28.8 (bad_frm) r/lh bad frame. if this bit is a 1, it indicates a packet has been received without an sfd. this bit is only valid in 10 mbits/s mode. this bit is latching high and will only clear after it has been read or the device has been reset. 28.7 (code) r/lh code violation. when this bit is a 1, it indicates a manchester code violation has occurred. the error code will be output on the rrxd lines. refer to table 1 for a detailed description of the rrxd pin error codes. this bit is only valid in 10 mbits/s mode. this bit is latching high and will only clear after it has been read or the device has been reset. 28.6 (aps) r autopolarity status. when register 30, bit 3 is a 0 and this bit is a 1, it indicates the 3x38 has detected and corrected a polarity reversal on the twisted pair. if the apf_en bit (register 30, bit 3) is a 0, the reversal will be corrected inside the 3x38. this bit is not valid in 100 mbits/s operation. 28.5 (discon) r/lh disconnect. if this bit is a 1, it indicates a disconnect. this bit will latch high until read. this bit is only valid in 100 mbits/s mode. 28.4 (unlocked) r/lh unlocked. indicates that the tx scrambler lost lock. this bit will latch high until read. this bit is only valid in 100 mbits/s mode. 28.3 (rxerr_st) r/lh rx error status. indicates a false carrier. this bit will latch high until read. this bit is only valid in 100 mbits/s mode. 28.2 (frc_jam) r/lh force jam. this bit will latch high until read. this bit is only valid in 100 mbits/s mode. 28.1 (lnk100up) r link up 100. this bit, when set to a 1, indicates a 100 mbits/s transceiver is up and operational. 28.0 (lnk10up) r link up 10. this bit, when set to a 1, indicates a 10 mbits/s transceiver is up and operational. bit * signal type ? description register information (continued) table 31. mr21rxer counter (continued) lucent technologies inc. 53 preliminary data sheet 3X38FTR 208-pin sqfp september 2000 octal-fet for 10base-t/100base-tx/fx register information (continued) table 33. mr29device-specific register 2 (100 mbits/s control) bit descriptions * the format for the bit descriptions is as follows: the first number is the register number, the second number is the bit posit ion in the register. ? r = read, w = write. bit * type ? description 29.15 (localrst) r/w management reset. this is the local management reset bit. writing a logic 1 to this bit will cause the lower 16 registers and registers 28 and 29 to be reset to their default values. this bit is self-clearing. 29.14 (rst1) r/w generic reset 1. this register is used for manufacture test only. 29.13 (rst2) r/w generic reset 2. this register is used for manufacture test only. 29.12 (100_off) r/w 100 mbits/s transmitter off. when this bit is set to 0, it forces tpip low and tpinC high. this bit defaults to 1. 29.11 (led_blink) r/w led blinking. this register, when 1, enables led blinking. this is ored with the blink_led_mode pin (t2). default is 0. 29.10 (crs_sel) r/w carrier sense select. rcrs_dv will be asserted on receive only when this bit is set to a 1. if this bit is set to logic 0, rcrs_dv will by asserted on receive or transmit. this bit is ored with the crs_sel pin. 29.9 (link_err) r/w link error indication. when this bit is a 1, a link error code will be reported on rrxd[1:0] of the 3x38 when rrx_er is asserted on the mii. if it is 0, it will dis- able this function. 29.8 (pkt_err) r/w packet error indication enable. when this bit is a 1, a packet error code, which indicates that the scrambler is not locked, will be reported on receive data out- puts of the 3x38 when rrx_er is asserted on the rmii. when this bit is 0, it will disable this function. 29.7 (pulse_str) r/w pulse stretching. when this bit is set to 1, the activity led and collision led output signals will be stretched between approximately 42 ms84 ms. if this bit is 0, it will disable this feature. default state is 0. 29.6 (edb) r/w encoder/decoder bypass. this mode is no longer supported; keep this bit set to 0 (default). 29.5 (sab) r/w symbol aligner bypass. when this bit is set to 1, the aligner function will be disabled. 29.4 (sdb) r/w scrambler/descrambler bypass. when this bit is set to 1, the scrambling/ descrambling functions will be disabled. this bit is ored with the scrambler/ descrambler bypass pin (u1). 29.3 (carin_en) r/w carrier integrity enable. when this bit is set to a 1, carrier integrity is enabled. this bit is ored with the carin_en pin (u3). 29.2 (jam_col) r/w jam enable. this mode is no longer supported, keep this bit set to 0 (default). 29.1 (fef-en) r/w far-end fault enable . this bit is used to enable the far-end fault detection and transmission capability. this capability may only be used if autonegotiation is disabled. this capability is to be used only with media which does not support autonegotiation. setting this bit to 1 enables far-end fault detection, and logic 0 will disable the function. default state is 0. 29.0 (fx) r/w fiber-optic mode. when this bit is a 1, the 3x38 is in fiber-optic mode (10base- t and 100base-tx disabled). when low, it will enable 10base-t and 100base- tx mode. this bit is ored with fx_mode_en pins. this bit defaults to 1. 3X38FTR 208-pin sqfp preliminary data sheet octal-fet for 10base-t/100base-tx/fx september 2000 54 lucent technologies inc. register information (continued) table 34. mr30device-specific register 3 (10 mbits/s control) bit descriptions * the format for the bit descriptions is as follows: the first number is the register number, the second number is the bit posit ion in the register. ? r = read, w = write. bit * type ? description 30.15 (test10tx) r/w 10base-t transmitter test . when high and 10base-t is powered up, a con- tinuous 10 mhz signal (1111) will be transmitted. this is only meant for test- ing. default 0. 30.14 (rxpllen) r/w 10base-t low power mode disable . when high, all 10base-t logic will be powered up when the link is up. otherwise, portions of the logic will be pow- ered down when no data is being received to conserve power. default is 0. 30.13 (jab_dis) r/w jabber disable. when this bit is 1, disables the jabber function of the 10base-t receive. default is 0. 30.12:7 (unused) r/w unused. read as 0. 30.6 (litf_enh) r/w enhanced link integrity test function. when high, and function is enabled, it will detect and change speed from 10 mbits/s to 100 mbits/s when an instan- taneous speed change occurs. this is ored with the litf_enh input (pin t3). default is 0. 30.5 (hbt_en) r/w heartbeat enable. when this bit is a 1, the heartbeat function will be enabled. valid in 10 mbits/s mode only. 30.4 (ell_en) r/w extended line length enable. when this bit is a 1, the receive squelch lev- els are reduced from a nominal 435 mv to 350 mv, allowing reception of sig- nals with a lower amplitude. valid in 10 mbits/s mode only. 30.3 (apf_en) r/w autopolarity function disable. when this bit is a 0 and the 3x38 is in 10 mbits/s mode, the autopolarity function will determine if the tp link is wired with a polarity reversal. default is 0. if there is a polarity reversal, the 3x38 will assert the aps bit (register 28, bit 6) and correct the polarity reversal. if this bit is a 1 and the device is in 10 mbits/s mode, the reversal will not be corrected. 30.2 (reserved) r/w reserved . 30.1 (serial _sel) r/w serial select. when this bit is set to a 1, 10 mbits/s serial mode will be selected. when the 3x38 is in 100 mbits/s mode, this bit will be ignored. 30.0 (ena_no_lp) r/w no link pulse mode. setting this bit to a 1 will allow 10 mbits/s operation with link pulses disabled. if the 3x38 is configured for 100 mbits/s operation, setting this bit will not affect operation. lucent technologies inc. 55 preliminary data sheet 3X38FTR 208-pin sqfp september 2000 octal-fet for 10base-t/100base-tx/fx register information (continued) table 35. mr31device-specific register 4 (quick status) bit descriptions * the format for the bit descriptions is as follows: the first number is the register number, the second number is the bit posit ion in the register. ? r = read, w = write. register/bit * type ? description 31.15 (error) r receiver error. when this bit is a 1, it indicates that a receive error has been detected. this bit is valid in 100 mbits/s only. this bit will remain set until cleared by reading the register. default is a 0. 31.14 (rxerr_st)/ (link_stat_change) r false carrier. when bit [31.7] is set to 0 and this bit is a 1, it indicates that the carrier detect state machine has found a false carrier. this bit is valid in 100 mbits/s only. this bit will remain set until cleared by reading the register. default is 0. link status change. when bit [31.7] is set to a 1, this bit is redefined to become the link_stat_change bit and goes high whenever there is a change in link status (bit [31.11] changes state). 31.13 (rem_flt) r remote fault. when this bit is a 1, it indicates a remote fault has been detected. this bit will remain set until cleared by reading the register. default is a 0. 31.12 (unlocked)/ (jabber) r unlocked/jabber. if this bit is set when operating in 100 mbits/s mode, it indicates that the tx descrambler has lost lock. if this bit is set when operating in 10 mbits/s mode, it indicates a jabber condition has been detected. this bit will remain set until cleared by reading the register. 31.11 (lstat_ok) r link status. when this bit is a 1, it indicates a valid link has been established. this bit has a latching low function: a link failure will cause the bit to clear and stay cleared until it has been read via the management interface. 31.10 (pause) r link partner pause. when this bit is set to a 1, it indicates that the 3x38 wishes to exchange flow control information. 31.9 (speed100) r link speed. when this bit is set to a 1, it indicates that the link has negotiated to 100 mbits/s. when this bit is a 0, it indicates that the link is operating at 10 mbits/s. 31.8 (full_dup) r duplex mode. when this bit is set to a 1, it indicates that the link has negotiated to full-duplex mode. when this bit is a 0, it indicates that the link has negotiated to half- duplex mode. 31.7 (int_conf) r/w interrupt configuration. when this bit is set to a 0, it defines bit [31.14] to be the rxerr_st bit and the interrupt pin (mask_stat_int) (pin 69) goes low whenever any of bits [31.15:12] go high, or bit [31.11] goes low. when this bit is set high, it rede- fines bit [31.14] to become the link_stat_change bit, and the interrupt pin (mask_stat_int) goes low only when the link status changes (bit [31.14] goes high). this bit defaults to 0. 31.6 (int_mask) r/w interrupt mask. when set high, no interrupt is generated by this channel under any condition. when set low, interrupts are generated according to bit [31.7]. 31.5:3 (low_auto_state) r lowest autonegotiation state. these 3 bits report the state of the lowest autonego- tiation state reached since the last register read, in the priority order defined below: 000: autonegotiation enable. 001: transmit disable or ability detect. 010: link status check. 011: acknowledge detect. 100: complete acknowledge. 101: flp link good check. 110: next page wait. 111: flp link good. 31.2:0 (hi_auto_state) r highest autonegotiation state. these 3 bits report the state of the highest autone- gotiation state reached since the last register read, as defined above for bit [31.5:3]. 3X38FTR 208-pin sqfp preliminary data sheet octal-fet for 10base-t/100base-tx/fx september 2000 56 lucent technologies inc. absolute maximum ratings (t a = 25 c) stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. table 36. absolute maximum ratings table 37. operating conditions * typical power dissipations are specified at 3.3 v and 25 c. this is the power dissipated by the 3x38. ? during autonegotiation, we use a patent-pending technique of turning off a majority of the circuitry, and only powerup the ne cessary link detect circuitry. thus, our autonegotiation power is very low. table 38. dc characteristics parameter symbol min max unit ambient operating temperature t a 070 c storage temperature t stg C40 125 c power dissipation p d 3.5w voltage on any pin with respect to ground C0.5 v dd + 0.3 v maximum supply voltage 3.8 v parameter symbol min typ* max unit operating supply voltage 3.135 3.3 3.465 v power dissipation: powerdown all ports autonegotiating ? all ports 10base-t link tx/rx 0% 10base-t tx/rx 100% 100base-t tx p d p d p d p d 0.2 0.4 0.25 2.7 3.2 w w w w w parameter symbol conditions min max unit ttl input high voltage v ih v dd = 3.3 v, v ss = 0.0 v 2.0 v ttl input low voltage v il v dd = 3.3 v, v ss = 0.0 v 0.8 v ttl output high voltage v oh v dd = 3.3 v, v ss = 0.0 v 2.4 v ttl output low voltage v ol v dd = 3.3 v, v ss = 0.0 v 0.4 v led output current i led 10ma rmii output current i mii 10ma pecl input high voltage v ih v dd C 1.16 v dd C 0.88 v pecl input low voltage v il v dd C 1.81 v dd C 1.47 v pecl output high voltage v oh v dd C 0.8 v pecl output low voltage v ol v dd C 1.60 v oscillator input x in C50 50 ppm input capacitance mii c in 8pf lucent technologies inc. 57 preliminary data sheet 3X38FTR 208-pin sqfp september 2000 octal-fet for 10base-t/100base-tx/fx clock timing table 39. system clock (rmii mode) 5-6784(f).b figure 16. system clock table 40. management clock * if the mdc period is less than 160 ns, then there are additional constraints with respect to rmclk (see mdc pin description). 5-6786(f) figure 17. management clock symbol parameter min max unit t1 clock high pulse width 8 12 ns t2 clock low pulse width 8 12 ns t3 clock period 19.999 20.001 ns symbol parameter min max unit t1 mdc high pulse width 40 ns t2 mdc low pulse width 40 ns t3 mdc period* 80 ns t4 mdio(i) setup to mdc rising edge 10 ns t5 mdio(o) hold time from mdc rising edge 10 ns t6 mdio(o) valid from mdc rising edge 0 40 ns rmclk t2 t1 t3 mdc t2 t1 mdio(i) mdio(o) t4 t5 t6 t3 3X38FTR 208-pin sqfp preliminary data sheet octal-fet for 10base-t/100base-tx/fx september 2000 58 lucent technologies inc. clock timing (continued) table 41. rmii receive timing 5-6787(f).b.r1 figure 18. rmii receive timing table 42. rmii transmit timing 5-6788(f).b.r1 figure 19. rmii transmit timing symbol parameter min typ max unit t1 rxer, crs_dv, rxd[1:0] prop delay with 25 pf load 210ns symbol parameter min max unit t1 txen, txd[1:0] setup to ref_clk rise 4 ns t2 txer, txen, txd[3:0] hold after txclk rise 2ns rmclk t1 rxer, crs_dv, rxd[1:0] t2 t1 rmclk txen, txd[1:0] lucent technologies inc. 59 preliminary data sheet 3X38FTR 208-pin sqfp september 2000 octal-fet for 10base-t/100base-tx/fx clock timing (continued) table 43. transmit timing 5-6789(f).a.r2 figure 20. transmit timing table 44. smii timing 5-7508(f).ar2 figure 21. smii timing symbol parameter min max unit t1 transmit latency (100 mbits/s) 6 14 bt transmit latency (10 mbits/s) 4 10 bt t2 sampled txen inactive to end of frame (100 mbits/s) 20bt sampled txen inactive to end of frame (10 mbits/s) 7bt symbol parameter min max unit t1 rmclk period ( 50 ppm) 8 8 ns t2 output delay 2.0 5 ns t3 setup 1.5 ns t4 input hold 1 ns rmclk txen tptx preamble t1 t2 txer txen txd0 txd1 txd2 txd3 txd4 txd5 txd6 txd7 1234 56789 1011 rmclk sync tx crs rxdv rxd0 rxd1 rxd2 rxd3 rxd4 rxd5 rxd6 rxd7 rx t2 t3 t4 t1 3X38FTR 208-pin sqfp preliminary data sheet octal-fet for 10base-t/100base-tx/fx september 2000 60 lucent technologies inc. clock timing (continued) table 45. receive timing 5-6790(f).a.r1 figure 22. receive timing symbol parameter min max unit t1 receive frame to crs_dv high (100 mbits/s) 18 bt receive frame to crs_dv high (10 mbits/s) 32 bt t2 end of receive frame to crs_dv low (100 mbits/s) 13 24 bt end of receive frame to crs_dv low (10 mbits/s) 9bt rmclk crs_dv tprx t1 t2 data lucent technologies inc. 61 preliminary data sheet 3X38FTR 208-pin sqfp september 2000 octal-fet for 10base-t/100base-tx/fx clock timing (continued) table 46. reset and configuration timing 5-6791(f).a figure 23. reset and configuration timing symbol parameter min max unit t1 power on to reset high 0.5 s t2 reset pulse width 1 ms t3 configuration pin setup 10 ns t4 configuration pin hold 20 ns v cc rstz config t3 t4 t2 t1 3X38FTR 208-pin sqfp preliminary data sheet octal-fet for 10base-t/100base-tx/fx september 2000 62 lucent technologies inc. clock timing (continued) table 47. pmd characteristics 5-6792(f).a figure 24. pmd characteristics symbol parameter min max unit t1 tptx+/tptxC rise time 3 5 ns t2 tptx+/tptxC fall time 3 5 ns t3 tp skew 0.5 ns t3 t2 t1 tptx+ tptxC lucent technologies inc. 63 preliminary data sheet 3X38FTR 208-pin sqfp september 2000 octal-fet for 10base-t/100base-tx/fx outline diagram 208-pin sqfp dimensions are in millimeters. 5-52196(f).r14 156 105 30.60 0.20 157 208 1 52 53 104 28.00 0.20 28.00 0.20 30.60 0.20 pin #1 identifier zone 4.10 max 0.08 3.40 0.20 seating plane 0.25 min 0.50 typ detail b detail a 0.50/0.75 gage plane seating plane 1.30 ref 0.25 detail a detail b 0.17/0.27 0.10 m 0.090/0.200 lucent technologies inc. reserves the right to make changes to the product(s) or information contained herein without notice. n o liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. copyright ? 2000 lucent technologies inc. all rights reserved september 2000 ds00-364lan (replaces ds00-245lan) for additional information, contact your microelectronics group account manager or the following: internet: http://www.lucent.com/micro , or for fpga information, http://www.lucent.com/orca e-mail: docmaster@micro.lucent.com n. america: microelectronics group, lucent technologies inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18109-3286 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia pacific: microelectronics group, lucent technologies singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singap ore 118256 tel. (65) 778 8833 , fax (65) 777 7495 china: microelectronics group, lucent technologies (china) co., ltd., a-f2, 23/f, zao fong universe building, 1800 zhong shan xi road, shanghai 200233 p. r. china tel. (86) 21 6440 0468 , ext. 325 , fax (86) 21 6440 0652 japan: microelectronics group, lucent technologies japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 europe: data requests: microelectronics group dataline: tel. (44) 7000 582 368 , fax (44) 1189 328 148 technical inquiries: germany: (49) 89 95086 0 (munich), united kingdom: (44) 1344 865 900 (ascot), france: (33) 1 40 83 68 00 (paris), sweden: (46) 8 594 607 00 (stockholm), finland: (358) 9 3507670 (helsinki), italy: (39) 02 6608131 (milan), spain: (34) 1 807 1441 (madrid) |
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