1 ps7085b 06/12/97 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74fct322501t pi74fct322q501t fast cmos 36-bit registered transceiver with 3-state outputs inputs outputs xoeab xleab xclkab ax bx lxxx z hhxl l hhxh h hl - ll hl - hh hlhx b (2) hllx b (3) truth table (1,4) notes: 1. a-to-b data flow is shown. b-to-a data flow is similar but uses xoeba, xleba, and xclkba. 2. output level before the indicated steady-state input conditions were established. 3. output level before the indicated steady-state input conditions were established, provided that xclkab was low before xleab went low. 4. h = high voltage level l = low voltage level z = high impedance - = low-to-high transition product features common features ?v cc = 5v 10% ? hysteresis on all inputs ? bus hold retains last active bus state during 3-state ? internal resistors eliminates the need for external pullup resistors ? packages available: ? 100-pin tqfp (f100) pi74fct322501t features ? balanced output drivers: 24ma pi74fct322q501t features ? balanced output drivers: 12ma ? output impedance 35 w (typical) product description pericom semiconductor?s pi74fct series of logic circuits are produced in the company?s advanced 0.6 micron cmos technology, achieving industry leading speed grades. the pi74fct322501t and pi74fct322q501t are 36-bit registered bus transceivers designed with d-type latches and flip-flops to allow data flow in transparent, latched, and clocked modes. the output enable (xoeab and xoeba), latch enable (xleab and xleba) and clock (xclkab and xclkba) inputs control the data flow in each direction. when xleab is high, the device operates in transparent mode for a-to-b data flow. when xleab is low, the a data is latched if xclkab is held at a high or low logic level. when xleab is low, the a bus data is stored in the latch/flip-flop on the transition of xclkab. data flow from b port to a port is similar to that of a port to b port but uses xoeba, xleba and xclkba. internal 50k w pullup and pulldown resistors are provided for the two output enable inputs. xoeab should be tied to gnd through a pulldown resistor. its minimum value is determined by the current- sourcing capability of the driver. the output enables are complementary (xoeab is active high and xoeba is active low). the pi74fct322501t and pi74fct322q501t have ?bus hold? which retains the input's last state whenever the input goes to high- impedance preventing ?floating? inputs and eliminating the need for pullup/down resistors. the pi74fct322501t and pi74fct322q501t are designed with current limiting resistors at its outputs to control the output edge rate resulting in lower ground bounce and undershoot. the pi74fct322q501t also features an additional internal series resistor which further minimizes noise. this virtually eliminates the need for any external terminating resistors for most low noise bus interface applications. this noise suppression benefit is designated by the letter ?q? (for quiet) in the part number .
2 ps7085b 06/12/97 pi74fct322501/322q501t 36-bit registered transceiver 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 logic block diagram 1leab 1clkab 1oeba 1leba 1clkba 1oeab d 1a1 1b1 to 17 other channels 50k 50k vcc le d le clk clk 2leab 2clkab 2oeba 2leba 2clkba 2oeab d 2a1 2b1 to 17 other channels 50k 50k vcc le d le clk clk
pi74fct322501/322q501t 36-bit registered transceiver 3 ps7085b 06/12/97 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 product pin configuration product pin description pin name description xoeab a-to-b output enable inputs (active high) xoeba b-to-a output enable inputs (active low) xleab a-to-b latch enable inputs xleba b-to-a latch enable inputs xclkab a-to-b clock inputs xclkba b-to-a clock inputs xax a-to-b data inputs or b-to-a 3-state outputs xbx b-to-a data inputs or a-to-b 3-state outputs gnd ground v cc power 2b10 2b9 gnd 2b8 2b7 2b6 2b5 gnd 2b4 2b3 2b2 2b1 vcc 1b1 1b2 1b3 1b4 gnd 1b5 1b6 1b7 1b8 gnd 1b9 1b10 2a11 2a12 2a13 gnd 2a14 2a15 2a16 2a17 2a18 2oeba 2leba 2clkba vcc 2clkab 2leab 2oeab 2b18 2b17 2b16 2b15 2b14 gnd 2b13 2b12 2b11 2a10 2a9 gnd 2a8 2a7 2a6 2a5 gnd 2a4 2a3 2a2 2a1 vcc 1a1 1a2 1a3 1a4 gnd 1a5 1a6 1a7 1a8 gnd 1a9 1a10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 1a11 1a12 1a13 gnd 1a14 1a15 1a16 1a17 1a18 1oeba 1leba 1clkba vcc 1clkab 1leab 1oeab 1b18 1b17 1b16 1b15 1b14 gnd 1b13 1b12 1b11 46 47 48 49 50 26 27 28 29 30
4 ps7085b 06/12/97 pi74fct322501/322q501t 36-bit registered transceiver 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 dc electrical characteristics (over the operating range, t a = ?40c to +85c, v cc = 5.0v 10%) parameters description test conditions (1) min. typ (2) max. units v ih input high voltage guaranteed logic high level 2.0 v v il input low voltage guaranteed logic low level 0.8 v i ih input high current standard input, v cc = max. v in = v cc 1a i ih input high current standard i/o, v cc = max. v in = v cc 1a i ih input high current bus hold input (4) , v cc = max. v in = v cc 100 a i ih input high current bus hold i/o (4) , v cc = max. v in = v cc 100 a i il input low current standard input, v cc = min. v in = gnd ?1 a i il input low current standard i/o, v cc = min. v in = gnd ?1 a i il input low current bus hold input (4) , v cc = min. v in = gnd 100 a i il input low current bus hold i/o (4) , v cc = min. v in = gnd 100 a i bhh bus hold bus hold input (4) , v cc = min. v in = 2.0v ?50 a i bhl sustain current v in = 0.8v +50 i bhho bus hold bus hold input (4) , v cc = max. v in = 1.5v tbd ma i bhlo overdrive current i ozh high-impedance v cc = max. v out = 2.7v 1 a i ozl output current v cc = max. v out = 0.5v ?1 a (3-state outputs) v ik clamp diode voltage v cc = min., i in = ?18 ma ?0.7 ?1.2 v i os short circuit current v cc = max. (3) , v out = gnd ?80 ?140 ?200 ma i o output drive current v cc = max. (3) , v out = 2.5v ?50 ?180 ma v h input hysteresis 100 mv maximum ratings (above which the useful life may be impaired. for user guidelines, not tested.) storage temperature ................................................................. ?55c to +125c ambient temperature with power applied ................................ ?40c to +85c supply voltage to ground potential (inputs & vcc only) .......... ?0.5v to +7.0v supply voltage to ground potential (outputs & d/o only) ....... ?0.5v to +7.0v dc input voltage ......................................................................... ?0.5v to +7.0v dc output current ................................................................................... 120 ma power dissipation ......................................................................................... 1.2w note: stresses greater than those listed under maxi- mum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reli- ability. notes: 1. for max. or min. conditions, use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at vcc = 5.0v, +25c ambient and maximum loading. 3. not more than one output should be shorted at one time. duration of the test should not exceed one second. 4. pins with bus hold are identified in the pin description.
pi74fct322501/322q501t 36-bit registered transceiver 5 ps7085b 06/12/97 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74fct322501t output drive characteristics (over the operating range) parameters description test conditions (1) min. typ (2) max. units v oh output high voltage v cc = min., v in = v ih or v il i oh = ?24.0 ma 2.4 3.3 ? v v ol output low voltage v cc = min., v in = v ih or v il i ol = 24 ma ? 0.3 0.55 v i odl output low current v cc = 5v, v in = v ih or v il , v out = 1.5v (3) 60 115 150 ma i odh output high current v cc = 5v, v in = v ih or v il , v out = 1.5v (3) ?60 ?115 ?150 ma pi74fct322q501t output drive characteristics (over the operating range) parameters description test conditions (1) min. typ (2) max. units v oh output high voltage v cc = min., v in = v ih or v il i oh = ?12.0 ma 2.4 3.3 ? v v ol output low voltage v cc = min., v in = v ih or v il i ol = 12 ma ? 0.3 0.55 v i odl output low current v cc = 5v, v in = v ih or v il , v out = 1.5v (3) ? tbd ? ma i odh output high current v cc = 5v, v in = v ih or v il , v out = 1.5v (3) ? tbd ? ma notes: 1. for max. or min. conditions, use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at vcc = 5.0v, +25c ambient and maximum loading. 3. not more than one output should be shorted at one time. duration of the test should not exceed one second. 4. this parameter is determined by device characterization but is not production tested. capacitance (t a = 25c, f = 1 mhz) parameters (4) description test conditions typ. max. units c in input capacitance v in = 0v 4.5 6 pf c out output capacitance v out = 0v 5.5 8 pf power supply characteristics parameters description test conditions (1) min. typ (2) max. units i cc quiescent power v cc = max. v in = gnd or v cc 0.2 20 a supply current d i cc supply current per v cc = max. v in = 3.4v (3) 1.0 6.0 ma input @ ttl high i ccd supply current per v cc = max., outputs open v in = v cc 150 240 a/ input per mhz (4) oeab = oeba = v cc or gnd v in = gnd mhz one bit toggling 50% duty cycle notes: 1. for max. or min. conditions, use appropriate value specified under electrical characteristics for the applicable device. 2. typical values are at vcc = 5.0v, +25c ambient. 3. per ttl driven input (v in = 3.4v); all other inputs at vcc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations.
6 ps7085b 06/12/97 pi74fct322501/322q501t 36-bit registered transceiver 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 notes: 1. see test circuit and wave forms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. this parameter is guaranteed but not production tested. 4. skew between any two outputs, of the same package, switching in the same direction. this parameter is guaranteed by design. 322501/q501at 322501/q501ct 322501/q501dt 322501/q501et com. com. com. com. parameters description conditions (1) min max min max min max min max unit t plh propagation delay c l = 50 pf 1.5 5.1 1.5 4.6 1.5 4.1 1.5 3.8 ns t phl a x to b x or a x to b x r l = 500 w t plh propagation delay 1.5 5.6 1.5 5.3 1.5 4.6 1.5 4.2 ns t phl x leba to a x , x leab to b x t plh propagation delay 1.5 5.6 1.5 5.3 1.5 4.6 1.5 4.2 ns t phl x clkba to a x , clkab to b x t pzh output enable time 1.5 6.0 1.5 5.6 1.5 5.2 1.5 4.8 ns t pzl x oeba to a x , x oeab to b x t phz output disable time (3) 1.5 5.6 1.5 5.2 1.5 5.2 1.5 5.2 ns t plz x oeba to a x , x oeab to b x t su setup time high or low 3.0 ? 3.0 ? 3.0 ? 2.4 ? ns ax to xclkab, bx to xclkba t h hold time high or low 0 ? 0 ? 0 ? 0 ? ns ax to xclkab, bx to xclkba t su setup time clock high 3.0 ? 3.0 ? 3.0 ? 2.0 ? ns high or low ax to xleab, clock low 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns bx to xleba t h hold time high or low 1.5 ? 1.5 ? 1.5 ? 0.5 ? ns ax to xleab, bx to xleba t w xleab or xleba pulse width 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns high (3) t w xclkab or xclkba pulse 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns width high or low (3) t sk ( o ) output skew (4) ? 0.5 ? 0.5 ? 0.5 ? 0.5 ns pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com pi74fct322501/322q501t switching characteristics over operating range
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