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amendment this document contains information on a product under development at advanced micro devices. the information is intended to help you evaluate this product. amd reserves the right to change or discontinue work on this product without notice. publication# 21032 rev: a amendment/ 1 issue date: december 1997 lan ? sc400 microcontroller register set reference manual including changes for the lansc410 microcontroller this document amends the lan?sc400 microcontroller register set reference manual , order #21032a, including additional information for the lansc410 microcontroller. it consists of three parts: n documentation defects and corrections lists documentation defects found in the original publication. n changes for the lansc410 microcontroller on page 25 gives an overview of differences between the lansc400 microcontroller and the lansc410 microcontroller, and lists all the registers and bits not supported on the lansc410 microcontroller. n the index beginning on page 35 includes all of the registers listed in this document, with index offsets listed sep- arately by subsystem. documentation defects and corrections table 1 lists defects that have been found in the lan?sc400 microcontroller register set reference manual, order #21032a. defects are listed in page or- der. each entry lists the following: n page number n item to be corrected n original text n corrected text n comments explaining the change table entries that correct text in a diagram do not con- tain the entire diagram. if a default value is changed, the original and changed default values are shown for the whole register. if other text is changed, the entry de- scribes the affected part of the diagram and lists the original and changed text. each item description includes the register name, so changes affecting a particular register can be found by consulting the index in this document. unchanged portions of a paragraph are replaced by an ellipsis (...) in entries where this might make the change easier to find. the whole paragraph is included if it is useful for understanding why the change was made. table 1. corrections to the lan?sc400 microcontroller register set reference manual page item original text change to comment title page lan?sc400 microcontroller register set reference manual lan?sc400 and lansc410 microcontrollers register set reference manual add lansc410 microcontroller to book title. chapter 2: pc/at-compatible direct-mapped registers 2-36 programmable interval timer #1 channel 0 count register, address 0040h; last paragraph when set up for either bcd or 16-bit binary count operation, the maximum count for channel 0 is achieved by writing the internal counting element associated with this register to 0000h/d. see direct- mapped register 43h for more detail. when set up for either bcd or 16-bit binary count operation, the maximum count for channel 0 is achieved by writing the internal counting element associated with this register to 0. see direct-mapped register 43h for more detail. same change for all three pages. notation 0000h/d is misleading. zero value written can be binary (hex) or bcd (decimal). 2-37 programmable interval timer #1 channel 1 count register, address 0041h; last paragraph 2-38 programmable interval timer #1 channel 2 count register, address 0042h; last paragraph
2 lan?sc400 microcontroller register set reference manual amendment amendment 2-49 pc/at keyboard mouse interface status register, address 0064h; bit 5 description when csc index c0h[0] is set, this bit is a pc/2 mouse-compatible mouse output buffer full flay... when csc index c0h[0] is set, this bit is a ps/2 mouse-compatible mouse output buffer full flag... two corrections: ps/2 mouse and flag. 2-52 rtc/cmos ram index register, address 0070h; diagram (bit 7 column) reserved C nmi_gate 0 w the nmi_gate function has not moved to csc index 9dh[2] in the lansc400 or lansc410 microcontrollers. rtc/cmos ram index register, address 0070h; bit 7 description 7 reserved reserved during read/modify/ write operations, software must preserve this bit. 7 nmi_gate master nmi mask 1 = nmi events are gated off from reaching the core 0 = nmi events will propagate to the cpu core rtc/cmos ram index register, address 0070h; programming notes programming notes bit 7 of this register is the master nmi gate control in a typical pc/at compatible system. for various reason, this bit has been made to reside at csc index 9dh[2]... (entire paragraph) programming notes 2-92 master software drq(n) request register, address 00d2h; default bit values in diagram 0 0 0 0 0 0 0 0 x x x x x x x x x = non- deterministic. master software drq(n) request register, address 00d2h; bits 1C0 description 0 0 = mask/unmask dma channel 4 mask per the reqdma bit 0 1 = mask/unmask dma channel 5 mask per the reqdma bit 1 0 = mask/unmask dma channel 6 mask per the reqdma bit 1 1 = mask/unmask dma channel 7 mask per the reqdma bit 0 0 = set/reset dma channel 4 internal dma request per the reqdma bit 0 1 = set/reset dma channel 5 internal dma request per the reqdma bit 1 0 = set/reset dma channel 6 internal dma request per the reqdma bit 1 1 = set/reset dma channel 7 internal dma request per the reqdma bit this field selects the dma request channel to assert or deassert, depending on the state of bit 2. 2-93 master dma mask register channels 4C7, address 00d4h; default bit values in diagram 0 0 0 0 0 0 0 0 x x x x x x x x x = non- deterministic. 2-94 master dma mode register channels 4C7, address 00d6h; default bit values in diagram 0 0 0 0 0 0 0 0 x x x x x x x x x = non- deterministic. 2-95 master dma clear byte pointer register, address 00d8h; default bit values in diagram 0 0 0 0 0 0 0 0 x x x x x x x x x = non- deterministic. table 1. corrections to the lan?sc400 microcontroller register set reference manual (continued) page item original text change to comment
lan?sc400 microcontroller register set reference manual amendment 3 amendment 2-96 master dma controller reset register, address 00dah; default bit values in diagram 0 0 0 0 0 0 0 0 x x x x x x x x x = non- deterministic. 2-97 master dma controller temporary register, address 00dah; default bit values in diagram 0 0 0 0 0 0 0 0 x x x x x x x x x = non- deterministic. 2-98 master dma reset mask register, address 00dch; default bit values in diagram 0 0 0 0 0 0 0 0 x x x x x x x x x = non- deterministic. 2-103 2-104 parallel port 2 status register, address 0279h; default bit values in diagram ? ? ? ? ? x x x x = non- deterministic. ? = depends on input state. parallel port 2 status register, address 0279h; programming notes programming notes (entire note) programming notes on power-up, the parallel port defaults to pc/at-compatible mode. upon switching to epp mode the bit defaults change to ?????xx0b clarify behavior. 2-105 parallel port 2 status register (epp mode), address 0279h; default bit values in diagram ? ? ? ? ? x x 0 x = non- deterministic. ? = depends on input state. parallel port 2 status register (epp mode), address 0279h; programming notes programming notes programming notes on power-up, the parallel port defaults to pc/at-compatible mode. upon switching to epp mode the bit defaults change to ?????xx0b clarify behavior. table 1. corrections to the lan?sc400 microcontroller register set reference manual (continued) page item original text change to comment
4 lan?sc400 microcontroller register set reference manual amendment amendment 2-111 com2 baud clock divisor latch lsb, address 02f8h; default bit values in diagram 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 divisor must be nonzero. com2 baud clock divisor latch lsb, address 02f8h; programming notes programming notes programming notes in order to determine the uart baud rate that will result from a particular setting of the baud rate divisor latch, the 16x baud clock is divided by 16 to give a normalized baud rate. because the standard 16x baud clock runs at 1.8432 mhz, the normalized baud rate is 115200. this rate is then divided by the value of the 16-bit baud clock divisor latch register. it is invalid to program a baud rate divisor of 0. the baud rate divisor latch, being a 16-bit value, provides for up to 64kC1 different baud rates (0 is not a valid baud rate). however, only a few of the available rates are ever used in common practice. see the following table for the commonly used baud rates along with the baud rate divisor required to achieve them: baud divisor latch value 110 0417h 150 0300h 300 0180h 600 00c0h 1200 0060h 2400 0030h 4800 0018h 9600 000ch 19200 0006h 38400 0003h 57600 0002h 115200 0001h add text to programming notes on both pages. 2-112 com2 baud clock divisor latch msb, address 02f9h; programming notes 2-114 com2 interrupt id register, address 02fah; bits 7C6 description 0 0 = no significance 0 1 = no significance 1 0 = 16450-compatible mode is enabled 1 1 = 16550-compatible mode is enabled 0 0 = 16450-compatible mode is enabled (default) 0 1 = no significance 1 0 = no significance 1 1 = 16550-compatible mode is enabled default of 0 0 indicates 16450- compatible mode. 2-121 com2 modem status register, address 02feh; default bit values in diagram x x x x 0 0 0 0 ? ? ? ? 0 0 0 0 ? = depends on input state table 1. corrections to the lan?sc400 microcontroller register set reference manual (continued) page item original text change to comment
lan?sc400 microcontroller register set reference manual amendment 5 amendment 2-124 2-125 parallel port 1 status register, address 0379h; default bit values in diagram ? ? ? ? ? x x x x = non- deterministic. ? = depends on input state. parallel port 1 status register, address 0379h; programming notes programming notes (entire note) programming notes on power-up, the parallel port defaults to pc/at-compatible mode. upon switching to epp mode the bit defaults change to ?????xx0b clarify behavior. 2-126 parallel port 1 status register (epp mode), address 0379h; default bit values in diagram ? ? ? ? ? x x 0 x = non- deterministic. ? = depends on input state. parallel port 1 status register (epp mode), address 0379h; programming notes programming notes programming notes on power-up, the parallel port defaults to pc/at-compatible mode. upon switching to epp mode the bit defaults change to ?????xx0b clarify behavior. table 1. corrections to the lan?sc400 microcontroller register set reference manual (continued) page item original text change to comment
6 lan?sc400 microcontroller register set reference manual amendment amendment 2-144 com1 baud clock divisor latch lsb, address 03f8h; default bit values in diagram 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 divisor must be nonzero com1 baud clock divisor latch lsb, address 03f8h; programming notes programming notes programming notes in order to determine the uart baud rate that will result from a particular setting of the baud rate divisor latch, the 16x baud clock is divided by 16 to give a normalized baud rate. because the standard 16x baud clock runs at 1.8432 mhz, the normalized baud rate is 115200. this rate is then divided by the value of the 16-bit baud clock divisor latch register. it is invalid to program a baud rate divisor of 0. the baud rate divisor latch, being a 16-bit value, provides for up to 64kC1 different baud rates (0 is not a valid baud rate). however, only a few of the available rates are ever used in common practice. see the following table for the commonly used baud rates along with the baud rate divisor required to achieve them: baud divisor latch value 110 0417h 150 0300h 300 0180h 600 00c0h 1200 0060h 2400 0030h 4800 0018h 9600 000ch 19200 0006h 38400 0003h 57600 0002h 115200 0001h add text to programming notes on both pages. 2-145 com1 baud clock divisor latch msb, address 03f9h; programming notes 2-147 com1 interrupt id register, address 03fah; default value for bit 0 in diagram 0 0 = no significance 0 1 = no significance 1 0 = 16450-compatible mode is enabled 1 1 = 16550-compatible mode is enabled 0 0 = 16450-compatible mode is enabled (default) 0 1 = no significance 1 0 = no significance 1 1 = 16550-compatible mode is enabled default of 0 0 indicates 16450- compatible mode. 2-150 com1 modem control register, address 03fch; bit 3 description enable com2 interrupts enable com1 interrupts correction. 2-153 com1 modem status register, address 03feh; default bit values in diagram x x x x 0 0 0 0 ? ? ? ? 0 0 0 0 ? = depends on input state. table 1. corrections to the lan?sc400 microcontroller register set reference manual (continued) page item original text change to comment
lan?sc400 microcontroller register set reference manual amendment 7 amendment chapter 3: chip setup and control (csc) indexed registers 3-15 dram control register, index 04h; programming notes programming notes programming notes the cas precharge delay (controlled by tcp, bit 3) always has at least one added state (t) during cpu write-back and copy-back cycles. this is required due to the amount of time it takes for cpu data to be valid during subsequent cycles of a burst. furthermore, if the dram width for the bank receiving the write- back or copy-back is 16 bits, the added wait state occurs only between dwords. add note text. 3-16 dram refresh control register, index 05h; bits 1 C0 description when the 32-khz clock is used.... thus, selecting the divide by 1 option results in a refresh interval of 15.6 ms. for the divide by 2, 4, and 8 selections, the refresh intervals are 31.2 ms, 62.5 ms, and 125 ms respectively. when the 32-khz clock is used... thus, selecting the divide by 1 option results in a refresh interval of 15.6 m s. for the divide by 2, 4, and 8 selections, the refresh intervals are 31.2 m s, 62.5 m s, and 125 m s respectively. change all times to microseconds ( m s). 3-20 non-cacheable window 0 address/ attributes/smm register, index 11h; default bit values in diagram 0 0 0 0 0 0 0 0 x 0 0 0 0 0 0 0 x = non- deterministic. 3-23 cache and vl miscellaneous register, index 14h; bit 4 vl_reset description vesa local bus reset 0 = vl_reset deasserted 1 = vl_reset asserted vesa local bus reset 0 = vl_rst signal deasserted 1 = v l_rst signal asserted vesa local bus reset signal name is vl_rst . 3-26 linear romcs0 / shadow register, index 21h; default bit values in diagram x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 7 default is zero. note: bit 6 and bits 4C1 are reserved in the lansc410 microcontroller. 3-31 r omcs0 configuration register b, index 24h; bits 4C3 description 00 = 0 wait states 00 = reservednot valid zero wait states not supported for fast rom. r omcs0 configuration register b, index 24h; bits 2C0 description 000 = 0 wait states 000 = reservednot valid zero wait states not supported for fast rom. 3-33 r omcs1 configuration register a, index 25h; bits 2C1 description these two bits can be read back to determine the romcs1 data bus width which is set via pin strapping options, and latched at power-on reset. these two bits can be read back to determine the romcs1 data bus width. delete reference to pin strapping (which applies to romcs0 only). table 1. corrections to the lan?sc400 microcontroller register set reference manual (continued) page item original text change to comment
8 lan?sc400 microcontroller register set reference manual amendment amendment 3-34 r omcs1 configuration register b, index 26h; bits 4C3 description 00 = 0 wait states 00 = reservednot valid zero wait states not supported for fast rom. r omcs1 configuration register b, index 26h; bits 2C0 description 000 = 0 wait states 000 = reservednot valid zero wait states not supported for fast rom. 3-36 r omcs2 configuration register a, index 27h; bits 2C1 description these two bits can be read back to determine the romcs2 data bus width which is set via pin strapping options, and latched at power-on reset. these two bits can be read back to determine the romcs2 data bus width. delete reference to pin strapping (which applies to romcs0 only). 3-37 r omcs2 configuration register b, index 28h; bits 4C3 description 00 = 0 wait states 00 = reservednot valid zero wait states not supported for fast rom. r omcs2 configuration register b, index 28h; bits 2C0 description 000 = 0 wait states 000 = reservednot valid zero wait states not supported for fast rom. 3-44 pin mux register a, index 38h; diagram, (bit 5 column) reserved 0 r/w reserved x correction. pin mux register a, index 38h; bit 5 description reserved reserved during read/modify/write operations, software must preserve this bit. correct omission. pin mux register a, index 38h; bits 2C1 descriptions select gpio... or isa pirqx 0 = ... 1 = isa signal is available... select gpio... or pirqx 0 = ... 1 = pirqx signal... isa pirq is misleading. the pirq pins can be assigned to other interrupts. pin mux register a, index 38h; programming notes programming notes programming notes bit 0 of this register must be set in order to use most isa i/o peripherals. this is because it enables the aen signal which, although listed in the dma signal group, is generated by the dma controller for consumption by all other isa i/o devices which are not part of the current dma transfer. these i/o devices should ignore i/o cycles on the bus if aen is active because it means that fly-by dma is occurring, not an i/o cycle. clarify. bit 0 is not just for isa dma devices. table 1. corrections to the lan?sc400 microcontroller register set reference manual (continued) page item original text change to comment
lan?sc400 microcontroller register set reference manual amendment 9 amendment 3-53 pmu present and last mode register, index 41h; bit 6 description set this bit to immediately time out the current mode timer. this bit does not need to be cleared and is not read back. software should not invoke this feature for at least 15 microseconds after a wake-up from suspend mode. software can read the last mode from bits 5C3 of this register and delay 15 microseconds if the last mode was suspend mode before setting this bit. set this bit to force an immediate time-out of the current mode timer, causing the pmu to drop to the next lower speed. this bit does not need to be cleared and is not read back. this function is designed for debugging power management software. software should not invoke this feature for at least one 32-khz clock cycle (30.5 m s) after a wake-up from suspend mode. software can read the last mode from bits 5C3 of this register and delay 30.5 m s if the last mode was suspend mode before setting this bit. expand description. increase delay. forced time-out might be missed (bit not latched) if used too soon after wake-up from suspend mode. 3-57 wake-up pause/high- speed clock timers register, index 45h; bits 2C0 description timer value to count down after a wake up is sensed and the plls are started up (if necessary) and the gpio_csx signals are switched to high-speed (or low-speed) mode levels (for those gpio_csx signals that are programmed to change based on pmu mode) to allow the power supplies to stabilize before the lansc400 microcontroller starts driving its outputs or using its inputs. read returns the last value written. selects the required delay from the time a wake-up is sensed and the plls are started up to allow the power supplies to stabilize before the microcontroller begins driving its outputs or using its inputs. read returns the last value written. rewrite. remove reference to programmed gpio_csx signals. all chip functions are delayed. 3-59 wake-up source enable register a, index 52h; diagram, (bit 3 column) reserved 0 r/w reserved x correction. wake-up source enable register a, index 52h; bit 3 description reserved reserved during read/modify/write operations, software must preserve this bit. correct omission. 3-61 wake-up source enable register c, index 54h; diagram (bits 7C6 columns) pdrq1_wake pdrq0_wake 00 r/w r/w reserved reserved xx dma requests do not support wake-ups. wake-up source enable register c, index 54h; bit 7 description pdrq1_wake programmable dma request 1 (pdrq1) wake-up control 0 = do not wake up system 1 = wake up system reserved reserved dma requests do not support wake-ups. wake-up source enable register c, index 54h; bit 6 description pdrq0_wake programmable dma request 0 (pdrq0) wake-up control 0 = do not wake up system 1 = wake up system reserved reserved dma requests do not support wake-ups. table 1. corrections to the lan?sc400 microcontroller register set reference manual (continued) page item original text change to comment
10 lan?sc400 microcontroller register set reference manual amendment amendment 3-63 wake-up source status register a, index 56h; diagram, (bit 3 column) reserved 0 r/w reserved x correction. wake-up source status register a, index 56h; bit 3 description reserved reserved during read/modify/write operations, software must preserve this bit. correct omission. 3-65 wake-up source status register c, index 58h; diagram (bits 7C6 columns) pdrq1_woke pdrq0_woke 00 r/w r/w reserved reserved xx dma requests do not support wake-ups. wake-up source status register c, index 58h; bit 7 description pdrq1_woke programmable dma request 1 (pdrq1) wake-up status write to 0b to clear. 0 = did not wake up system 1 = awakened system reserved reserved dma requests do not support wake-ups. wake-up source status register c, index 58h; bit 6 description pdrq0_woke programmable dma request 0 (pdrq0) wake-up status write to 0b to clear. 0 = did not wake up system 1 = awakened system reserved reserved dma requests do not support wake-ups. 3-73 activity source enable register c, index 64h; diagram (bit 6 column) drq_is_act 0 r/w reserved x dma requests do not support activities. activity source enable register c, index 64h; space below diagram \ remove stray backslash character. activity source enable register c, index 64h; bit 6 description drq_is_act dma request will be activity 0 = not an activity 1 = will be activity reserved reserved dma requests do not support activities. 3-74 activity source enable register d, index 65h; diagram (bit 7) intreg_was_act intreg_is_act correction. activity source enable register d, index 65h; bit 7 description intreg_was_act intreg_is_act correction. table 1. corrections to the lan?sc400 microcontroller register set reference manual (continued) page item original text change to comment
lan?sc400 microcontroller register set reference manual amendment 11 amendment 3-77 activity source status register c, index 68h; diagram (bit 6 column) drq_was_act 0 r/w reserved x dma requests do not support activities. activity source status register c, index 68h; bit 6 description drq_was_act dma request activity status write to 0b to clear. 0 = not detected as activity 1 = detected as activity reserved reserved dma requests do not support activities. 3-81 activity classification register c, index 6ch; diagram (bit 6 column) drq_sec_act 0 r/w reserved x dma requests do not support activities. activity classification register c, index 6ch; bit 6 description drq_sec_act dma request activity status 0 = primary activity 1 = secondary activity reserved reserved dma requests do not support activities. 3-85 battery/ac pin configuration register b, index 71h; bit 0 description, last paragraph ...to enter suspend mode.8 ...to enter suspend mode. remove stray character. 3-86 battery/ac pin state register, index 72h; bits 4C0 default values in diagram x x x 0 0 0 0 0 x x x ? ? ? ? ? x = non- deterministic. ? = depends on input state. 3-87 cpu clock speed register, index 80h; bit 0 description 1 = clock tripled (99 mhz) the lansc400 microcontroller and lansc410 microcontroller may require special packaging to safely support clock-tripled mode. selection of clock-tripled mode results in much higher heat generation by the device. selecting clock-tripled mode for an lansc400 microcontroller device which uses a package that is not specifically approved by amd for use at clock- tripled speed may result in erratic system operation, loss of data, or damage to the lansc400 microcontroller device. 1 = clock tripled (100 mhz) selection of clock-tripled mode results in much higher heat generation by the device. lansc400 and lansc410 microcontroller devices that use the 292-pin bga (ball grid array) package type can safely support clock-tripled mode under amd- approved operating conditions. amd may make the lansc400 and lansc410 microcontroller devices available in other package types that are not approved by amd for use at clock-tripled speed. selecting clock- tripled mode for such devices may result in erratic system operation, loss of data, or damage to the microcontroller device. correction. rewrite. table 1. corrections to the lan?sc400 microcontroller register set reference manual (continued) page item original text change to comment
12 lan?sc400 microcontroller register set reference manual amendment amendment 3-88 cpu clock auto slowdown register, index 81h; bit 4 description the pmu modes or states provide a way to trade off performance for processing power in discrete steps. the auto slowdown feature allows the (average power/average performance) to be fine tuned when the pmu is operating in the highest available pmu mode. this can be either be hyper - speed mode or high - speed mode, depending on whether or not hyper - speed mode is disabled. enabling this feature causes the cpu clock to switch between the fast speed and slow speed operating frequencies as defined by the fast_period and slow_period bit fields. the pmu modes or states provide a way to trade off performance for processing power in discrete steps. the auto slowdown feature allows the (average power/average performance) to be fine tuned by allowing the pmu to toggle between high-speed and low- speed pmu modes with a duty cycle which is user configurable via the fast_period and slow_period bit fields in this register. the auto slowdown feature must not be enabled if hyper-speed mode is enabled, or unexpected system operation may occur. auto slowdown is not supported in hyper-speed mode. cpu clock auto slowdown register, index 81h; bits 3 C2 description when auto slowdown is enabled, these bits define how long the cpu clock runs at the slow clock frequency before switching up to run at the fast clock frequency. when the hyper - speed pmu mode is enabled, the slow clock frequency will be the high - speed mode clock frequency. when the hyper - speed pmu mode is disabled, the slow clock will equal the low - speed mode clock frequency. see the fast_period field for further explanation. when auto slowdown is enabled, these bits define how long the cpu clock runs at the clock frequency that is currently configured for low-speed pmu mode before switching up to run at the clock frequency that is currently configured for high-speed pmu mode. see the fast_period field for further explanation. auto slowdown is not supported in hyper-speed mode. cpu clock auto slowdown register, index 81h; bits 1C0 description when auto slowdown is enabled, these bits define how long the cpu clock runs at the fast clock frequency before switching down to run at the slow clock frequency. when the hyper - speed pmu mode is enabled, the fast clock frequency will be the hyper - speed mode clock frequency. when the hyper - speed pmu mode is disabled, the fast clock will equal the high - speed mode clock frequency. see the slow_period field for further explanation. when auto slowdown is enabled, these bits define how long the cpu clock runs at the clock frequency that is currently configured for high- speed pmu mode before switching down to run at the clock frequency that is currently configured for low- speed pmu mode. see the slow_period field for further explanation. auto slowdown is not supported in hyper-speed mode. 3-90 clock control register, index 82h; default bit values in diagram 0 0 1 0 0 0 0 1 x 0 1 0 0 0 0 1 x = non- deterministic. clock control register, index 82h; diagram (bit 7 r/w status) r/w bit 7 r/w status is undefined. 3-91 clk_io pin output clock select register, index 83h; bits 3C0 description cli_io pin select ... 0 0 0 0 = uart clock (18.432 mhz) clk_io pin select ... 0 0 0 0 = uart clock (1.8431 mhz) correct pin name and uart clock frequency. 3-94 miscellaneous smi/ nmi enable register, index 90h; bit 2 description rising edge on sus_res pin xmi enable falling edge on sus_res pin xmi enable correction. table 1. corrections to the lan?sc400 microcontroller register set reference manual (continued) page item original text change to comment
lan?sc400 microcontroller register set reference manual amendment 13 amendment 3-94 miscellaneous smi/ nmi enable register, index 90h; programming notes programming notes bits 6C2: if, when an xmi is enabled... to xmi on a falling edge, the smi will occur immediately... 1. disable the smi at its master control. ... 4. re-enable the smi at its master source... programming notes bits 6C2: if, when an xmi is enabled... to xmi on a falling edge, the xmi will occur immediately... 1. disable the xmi at its master control. ... 4. re-enable the xmi at its master control... replace smi with xmi (three places) and replace master source with master control (one place). 3-97 battery low and acin smi/nmi enable register, index 93h; diagram and description (all bits) acn_rise_was_xmi acn_fall_was_xmi bl2_rise_was_xmi bl2_fall_was_xmi bl1_rise_was_xmi bl1_fall_was_xmi bl0_rise_was_xmi bl0_fall_was_xmi acn_rise_will_xmi acn_fall_will_xmi bl2_rise_will_xmi bl2_fall_will_xmi bl1_rise_will_xmi bl1_fall_will_xmi bl0_rise_will_xmi bl0_fall_will_xmi change was to will in all bit names. this is an enable register, not a status register. battery low and acin smi/nmi enable register, index 93h; description (all bits) 0 = did not cause smi/nmi 1 = caused smi/nmi 0 = do not cause smi/nmi 1 = cause smi/nmi change state definitions for all bits. this is an enable register, not a status register. 3-103 battery low and acin smi/nmi status register, index 97h; programming notes, step 4 (last paragraph) re-enable the xmi at its master control (csc index 9dh[2] for nmis... re-enable the xmi at its master control (port 70h[7] for nmis... the nmi_gate function has not moved to csc index 9dh[2] in the lansc400 or lansc410 microcontrollers. 3-104 smi/nmi select register, index 98h; bit 3 description ...each of these can have individual enables. see the keyboard index registers for more detail. ...each of these can be individually enabled. see the pc card and keyboard smi/nmi enable register, csc index 91h, for more detail. clarify. table 1. corrections to the lan?sc400 microcontroller register set reference manual (continued) page item original text change to comment
14 lan?sc400 microcontroller register set reference manual amendment amendment 3-105 i/o access smi enable register a, index 99h; descriptions for bits 4C0 1 = cause an smi due to.... 1 = cause an smi due to.... requires special handling; see programming notes section. for all five bits, add reference to programming notes. i/o access smi enable register a, index 99h; programming notes programming notes programming notes special handling for smi to emulate i/o accesses: if the system requires the use of emulating and/or restarting i/o accesses, then the software must select the 80486 cache policy as write through via csc index 14h, bit 0. do not use the i/o trap address in smbase offset 0ff06h to determine which i/o address to emulate. instead, to determine the i/o address to emulate, the software should examine the saved values of the eip and cs at smbase offsets 0fff0h and 0ffach, respectively. the software then examines the instruction that caused the smi by decrementing the eip value, determining the opcode, and using the dx and ax registers in the smm save state or opcode operands to determine the correct i/o address. the i/o restart (writing 0ffh to smbase offset 0ff00h) will work correctly with the write through policy. the lansc400 microcontroller only supports i/o trapping with the write through cache policy and requires special handling. table 1. corrections to the lan?sc400 microcontroller register set reference manual (continued) page item original text change to comment
lan?sc400 microcontroller register set reference manual amendment 15 amendment 3-106 i/o access smi enable register b, index 9ah; descriptions for bits 6 C0 1 = cause an smi due to.... 1 = cause an smi due to.... requires special handling; see programming notes section. for all seven bits, add reference to programming notes. i/o access smi enable register b, index 9ah; programming notes programming notes programming notes special handling for smi to emulate i/o accesses: if the system requires the use of emulating and/or restarting i/o accesses, then the software must select the 80486 cache policy as write through via csc index 14h, bit 0. do not use the i/o trap address in smbase offset 0ff06h to determine which i/o address to emulate. instead, to determine the i/o address to emulate, the software should examine the saved values of the eip and cs at smbase offsets 0fff0h and 0ffach, respectively. the software then examines the instruction that caused the smi by decrementing the eip value, determining the opcode, and using the dx and ax registers in the smm save state or opcode operands to determine the correct i/o address. the i/o restart (writing 0ffh to smbase offset 0ff00h) will work correctly with the write through policy. the lansc400 microcontroller only supports i/o trapping with the write through cache policy and requires special handling. 3-109 xmi control register, index 9dh; diagram, bits 7C3 and bit 2 functions reserved nmi_gate reserved add bit 2 to reserved field bits 7C3. delete bit 2 description. the nmi_gate function is performed by direct-mapped port 70h[7] in the lansc400 and lansc410 microcontrollers. xmi control register, index 9dh; bits 7C3 description 7C3 reserved... 7C2 reserved... xmi control register, index 9dh; bit 2 description 2 nmi_gate master nmi enable ... (entire description) 3-116 gpio read-back/write register aCd, index a6h, a7h, a8h, a9h; default bit values in diagram x x x x x x x x ? ? ? ? ? ? ? ? ? = depends on input state. 3-122 gpio_pmub mode change register, index abh; bit 4 description drive gpio_pmub signal with programmed value in hyper- speed mode drive gpio_pmub signal with programmed value in high-speed mode correction. table 1. corrections to the lan?sc400 microcontroller register set reference manual (continued) page item original text change to comment
16 lan?sc400 microcontroller register set reference manual amendment amendment 3-124 gpio_pmuc mode change register, index ach; bit 4 description drive gpio_pmuc signal with programmed value in hyper- speed mode drive gpio_pmuc signal with programmed value in high-speed mode correction. 3-126 gpio_pmud mode change register, index adh; bit 4 description drive gpio_pmud signal with programmed value in hyper- speed mode drive gpio_pmud signal with programmed value in high-speed mode correction. 3-130 gpio_xmi to gpio_cs map register, index b0h; bits 3C0 description, step 1 of procedure 1. disable xmis to the cpu core... for nmis, this is done via csc index 9dh[2]. 1. disable xmis to the cpu core... for nmis, this is done via port 70h[7]. the nmi_gate function has not moved to csc index 9dh[2] in the lansc400 or lansc410 microcontrollers. 3-135 gp_csa i/o address decode and mask register, index b5h; diagram (bits 1C0 r/w status) r/w field is r/w. 3-137 gp_csb i/o address decode and mask register, index b7h; diagram (bits 1C0) csb_sa0_mask csb_addr[9C8] correction. bit 2 name was repeated in bits 1C0 field. 3-147 keyboard configuration register a, index c0h; bit 2 description ... 1 = disabled ... 1 = disabled this bit may not be set if xt mode is enabled via csc register c1h[4]. addition. 3-150 keyboard configuration register b, index c1h; bit 1 description, fourth line ... transmit date, this bit... ... transmit data, this bit... correction. 3-164 internal i/o device disable/echo z-bus configuration register, index d0h; bit 5 description ... during echo_zbus cycles, aen is also asserted so that isa i/o devices will not decode the echo_zbus cycles. ... during echoed cycles, aen is also asserted so that isa i/o devices will not decode the echoed cycles. use more meaningful references to internal i/o cycles. 3-165 internal i/o device disable/echo z-bus configuration register, index d0h; bit 2 description dma 0 slave controller disable dma 0 master controller disable correction. internal i/o device disable/echo z-bus configuration register, index d0h; bit 1 description 1 = internal pc card controller... ...if the last value written to port 3e0h was greater than 80h, the write to 3e1h will generate an external bus cycle. 1 = internal pc card controller... ...if the last value written to port 3e0h was equal to or greater than 80h, the write to 3e1h will generate an external bus cycle. correction. table 1. corrections to the lan?sc400 microcontroller register set reference manual (continued) page item original text change to comment
lan?sc400 microcontroller register set reference manual amendment 17 amendment 3-168 parallel port configuration register, index d2h; bits 1 C0 description 0 0 = set/reset dma channel 4 dma request per the reqdma bit 0 1 = set/reset dma channel 5 dma request per the reqdma bit 1 0 = set/reset dma channel 6 dma request per the reqdma bit 11= set/reset dma channel 7 dma request per the reqdma bit 0 0 = unidirectional mode (pc/at compatible) 0 1 = epp mode 1 0 = bidirectional mode (ps/2 compatible) 11= reserved correction. 3-169 uart fifo control shadow register, index d3h; diagram (bits 7C6 r/w status) r bits 7C6 r/w status is r. uart fifo control shadow register, index d3h; diagram (bits 5C4 and bit 3 function) reserved reserved reserved combine fields for bits 5C3. uart fifo control shadow register, index d3h; diagram (bit 3 r/w status) r bit 3 r/w status is undefined. uart fifo control shadow register, index d3h; bits 5C4 and bit 3 descriptions (entire description text) 5C3 reserved reserved during read/modify/ write operations, software must preserve these bits. combine descriptions for bits 5C3 and correct. 3-174 interrupt configuration register e, index d8h; diagram, (bits 2C0 column) reserved 0 0 0 r/w reserved x x x correction. interrupt configuration register e, index d8h; bits 2C0 description reserved reserved during read/modify/write operations, software must preserve this bit. correct omission. 3-184 suspend pin state register a, index e3h; diagram, (bit 4 column) reserved 0 r/w reserved x correction. suspend pin state register a, index e3h; bit 4 description reserved reserved during read/modify/write operations, software must preserve this bit. correct omission. table 1. corrections to the lan?sc400 microcontroller register set reference manual (continued) page item original text change to comment
18 lan?sc400 microcontroller register set reference manual amendment amendment 3-189 irda control register, index eah; bit 0 description 0 = uart mode 1 = irda mode when uart mode is selected, the irda interface and all associated control and status bits have no meaning except this bit. when irda mode is selected and is operated in slow-speed irda mode by clearing this bit, use all of the normal 16550 uart control and status bits to transmit and receive data over the irda interface. 0 = uart mode. when uart mode is selected, the irda interface and all associated control and status bits have no meaning except this bit. serial data transfer is via the sin and sout pins. 1 = irda mode. when irda mode is selected, the irda interface is enabled, and data transfer will occur over the dedicated sirout and sirin pins. note: software can switch between uart and irda modes at any time. rewrite. irda control register, index eah; programming notes the use of either low- or high- speed irda requires that the on- board uart be enabled by setting csc index d1h[0]. the use of either slow- or high- speed irda requires that the on- board uart be enabled by setting csc index d1h[0]. if csc index eah[3] = 0b, the interrupt status bits in this register are undefined. thus, they cannot be used for polled status unless the high-speed irda interrupt is enabled. to use these bits in a polled-only fashion, simply set csc index d8h[6C5] = 00b while csc index eah[3] = 1b. rewrite. 3-192 irda crc status register, index ech; default bit values in diagram x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 7 default is zero. table 1. corrections to the lan?sc400 microcontroller register set reference manual (continued) page item original text change to comment
lan?sc400 microcontroller register set reference manual amendment 19 amendment 3-194 irda frame length register a, index eeh; bits 7 C0 description bits 7C0 of the 11-bit irda data frame length register. see csc index efh for bits 10C8. the 11-bit value... (entire description) bits 7C0 of the 12-bit irda data frame length register. see csc index efh for bits 11C8. the 12-bit value written across these two registers controls the length of a transmitted irda data frame. this 12-bit internal register should be programmed with the total number of frame bytes (address, control, and information fields) plus two for the 2-byte crc/fcs field. the programmed value must not include the two required bof bytes or the sto flag byte. for example, consider a frame to be transmitted that contains the following bytes, which must be written into the frame's (dram- based) dma transmit buffer prior to starting the transmit process. assuming that the dma memory address will increment after each transfer (see the direct-mapped dma mode registers), the frame will appear in the buffer as follows: (lower addresses) bof/sta = 2 bytes addr = 1 byte control = 1 byte information = 19 bytes crc/fcs = 2 bytes eof/sto = 1 byte (higher addresses) total number of bytes in the transmit buffer = 26 subtracting three (for the two required bof bytes plus the one required sto byte) from the total results in 23d (17h). thus, the value of 17h should be programmed into the 12-bit frame length register via csc index eehCefh. modify for frame length of 12 bits rather than 11. expand description. table 1. corrections to the lan?sc400 microcontroller register set reference manual (continued) page item original text change to comment
20 lan?sc400 microcontroller register set reference manual amendment amendment 3-195 irda frame length register b, index efh; bit names in diagram bits 7C3: reserved bits 2C0: frame_len[10C8] bits 7C4: reserved bits 3C0: frame_len[11C8] modify for frame length of 12 bits rather than 11. irda frame length register b, index efh; bit default values in diagram x x x x x 0 0 0 x x x x 0 0 0 0 irda frame length register b, index efh; bit name text bits 7C3: reserved bits 2C0: frame_len[10C8] bits 7C4: reserved bits 3C0: frame_len[11C8] irda frame length register b, index efh; bit descriptions irda data frame length... bits 10C8 bits 10C8 of the 11-bit irda data frame length register. see csc index efh for bits 7C0. the 11-bit value... the number programmed in this 11-bit register will be data size plus 3... the length of each of these frames must conform to frame_len10Cframe_len0. irda data frame length... bits 11C8 bits 1 1C8 of the 12-bit irda data frame length register. see csc index eeh for bits 7C0. the 12-bit value... the number programmed in this 12-bit register will be data size plus three... the length of each of these frames must conform to frame_len11Cframe_len0. modify for frame length of 12 bits rather than 11. also index value referred to should be eeh, not efh. 3-201 lansc400 microcontroller revision id register, index ffh; default bit values in diagram 0 0 0 0 0 0 0 0 default values depend on the microcontroller version. lansc400 microcontroller revision id register, index ffh; programming notes programming notes the value read back depends on the current major.minor versions of a specific lansc400 microcontroller. programming notes the value read back depends on the current major.minor versions of a specific lansc400 microcontroller. contact your amd representative for current version information. addition. table 1. corrections to the lan?sc400 microcontroller register set reference manual (continued) page item original text change to comment
lan?sc400 microcontroller register set reference manual amendment 21 amendment chapter 4: rtc and cmos ram indexed registers 4-3 rtc/cmos ram index register, address 0070h; diagram (bit 7 column) reserved C nmi_gate 0 w the nmi_gate function has not moved to csc index 9dh[2] in the lansc400 or lansc410 microcontrollers. rtc/cmos ram index register, address 0070h; bit 7 description 7 reserved reserved 7 nmi_gate master nmi enable 1 = nmi events are gated off from reaching the core 0 = nmi events will propagate to the cpu core rtc/cmos ram index register, address 0070h; programming notes programming notes bit 7 of this register is the master nmi gate control in a typical pc/at compatible system. for various reason, this bit has been made to reside at csc index 9dh[2]... (entire paragraph) programming notes 4-15 general purpose cmos ram, indexes 0eC7fh move section to end of chapter. 4-16 register a, index 0ah; bit 7 description this bit is provided for use by software that needs to modify the time, calendar or alarm registers in the real time clock. when this bit reads back 1b, these internal registers are unavailable for access by software since internal rtc logic is using them. when this bit reads back 0b, software will have a guaranteed minimum window of 244 m s in which modifications to these registers are allowed... the time, calendar, and alarm information in ram is fully available to the program when the uip bit is 0, it is not in transition... this bit is provided for use by software that needs to either read or write the time, calendar, or alarm registers in the real time clock. when this bit reads back 1b, these internal registers are unavailable for access by software because internal rtc logic is using them. when this bit reads back 0b, software will have a guaranteed minimum window of 244 m s in which reads or writes to these registers are guaranteed to be valid... the time, calendar, and alarm information in ram is fully available to the program when the uip bit is 0 because an update cycle is not in progress... rewrite to clarify meaning. the terms modify and modifications are misleading. both reads and writes are affected. register a, index 0ah; bits 6C4 description 0 1 0 = ... 1 1 x = ... all other values = programming dv2-dv0 to any value except 010b or 11xb turns the oscillator off. 0 1 0 = ... 1 1 x = ... all other values = programming dv2Cdv0 to any value except 010b or 11xb disables the input clock from the oscillator circuit. clarify. table 1. corrections to the lan?sc400 microcontroller register set reference manual (continued) page item original text change to comment
22 lan?sc400 microcontroller register set reference manual amendment amendment note: the following chapters in the register set manual apply only to the lansc400 microcontroller. chapter 5: graphics controller indexed registers 5-4 cga/mda index register, address 03x4h; diagram, r/w designation w r/w register is read/ write. 5-5 cga/mda data port, address 03x5h; diagram, r/w designation w r/w register is read/ write. 5-7 cursor end register, index 0ah; bits 7C5 in diagram cur_end[4C0] reserved bit name designators are reversed in the diagram. cursor end register, index 0ah; bits 4C0 in diagram reserved cur_end[4C0] 5-18 non-display lines register, index 34h; bits 1C0 description these bits allow 2 or 4 additional non-display lines to be added... these bits allow 1, 2, or 4 additional non-display lines to be added... correction. 5-20 overflow register, index 36h; bit 1 description vertical display enable end bit 8 this is the eighth bit of the vertical display enable end register. see graphics index 37h for more detail. vertical display end bit 8 this is the eighth bit of the vertical display end register. see graphics index 37h for more detail. correction. delete enable (two places). 5-21 vertical display end register, index 37h; bits 7C0 description determines the number of the last character line to be output from the frame buffer... value = (number of horizontal displayed character lines from memory) - 1. determines the number of the last character line to be output from the frame buffer... value = (number of vertical displayed character lines from memory) C 1. correction. formula is for vertical lines. 5-22 vertical border end register, index 38h; bits 7C0 description determines the last character line to be output to the panel at the bottom of the display. value = (number of horizontal displayed character lines) - 1... determines the last character line to be output to the panel at the bottom of the display. value = (number of vertical displayed character lines) C 1... correction. formula is for vertical lines. 5-36 pixel clock control register, index 4ch; bits 4C3 description divides the base dot clock (as controlled by bits 2C0 above)... divides the base dot clock (as controlled by bits 2C0)... correction. table 1. corrections to the lan?sc400 microcontroller register set reference manual (continued) page item original text change to comment
lan?sc400 microcontroller register set reference manual amendment 23 amendment chapter 6: pc card controller indexed registers 6-8 interface status register, index 01h/ 41h; default bit values in diagram 0 0 x x x x x x 0 0 ? ? ? ? ? ? x = non- deterministic. ? = depends on input state. interface status register, index 01h/ 41h; descriptions for bits 5, 4, and 1C0 rdy_x pin wp_x pin bvd2_x pin (2 places) bvd1_x pin (2 places) rdy_x pin wp_x pin bvd2_x pin bvd1_x pin these pins are active high. 6-11 interrupt and general control register, index 03h/43h; bits 3C0 description, irq6 0 1 1 0 = irq6 enabled 0 1 1 0 = irq6 enabled added for pc card based floppy disk drives that support pc/at- compatible irqs and dma. an irq6 driven from the pcmcia controller will not cause any pmu events (activity). clarification. 6-15 address window enable register, index 06h/46h; programming notes text (all text before table in programming notes section.) when the lansc400 microcontroller is operating in enhanced mode (see csc index f1h[0], the five memory windows that belong to pc card socket b have the same meaning and controls as they do on a standard 82356 controller. when operating in standard mode, pc card controller socket b memory windows 1C5 are redefined to be mms windows cCf. in this mode, the mms windows cCf base addresses and offsets are configured using the same pc card controller registers that would have been used if the windows were configured to be pc card windows. however, the destination devices (and other attributes that apply only to mms windows) are now controlled by csc index 30h and 31h. rewrite of programming notes text. address window enable register, index 06h/46h; programming notes table, center column mms window mms window correction. none none mms 0 mms c mms 1 mms d mms 2 mms e mms 3 mms f 6-56 command timing 0 register, index 3bh; default value for bits 3C1 in diagram 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 correction. table 1. corrections to the lan?sc400 microcontroller register set reference manual (continued) page item original text change to comment
24 lan?sc400 microcontroller register set reference manual amendment amendment 6-59 command timing 1 register, index 3eh; default value for b its 3C0 in diagram 0 0 0 0 2 2 2 2 0 0 0 0 0 0 1 0 correction. 6-62 command timing 2 register, index 7bh; default value for bits 3C0 in diagram 0 0 0 0 3 3 3 3 0 0 0 0 0 0 1 1 correction. table 1. corrections to the lan?sc400 microcontroller register set reference manual (continued) page item original text change to comment
lan?sc400 microcontroller register set reference manual amendment 25 amendment changes for the lansc410 microcontroller this section gives an overview of differences between the lansc400 microcontroller and the lansc410 mi- crocontroller. thelansc410 microcontroller is identical to the lansc400 microcontroller, except that the following on-chip peripheral functions are not supported in the lansc410 microcontroller: n pc card controller n lcd graphics controller these functions are highlighted in grey in the block di- agram shown in figure 1 on the following page. table 2 on page 27 lists all affected register bit fields and describes how those fields differ in the lansc410 microcontroller from the function described in the lan?sc400 microcontroller register set reference manual , order #21032a). in general, register bits or bit field values that apply to the pc card controller or lcd graphics controller are reserved in the lansc410 microcontroller. the state of reserved bits must be preserved by software during read/modify/write operations. two pc card controller register bits are shared by mms windows cCf, which is supported by the lansc410 microcontroller. before mms windows cCf can be configured, software must set csc index bit d0h[1] = 1 and bit f1h[0] = 0.
26 lan?sc400 microcontroller register set reference manual amendment amendment figure 1. block diagramlansc400 and lansc410 microcontrollers serial port infrared graphics or vl-bus controller socket a ctrl gpios or parallel port or pc card socket b 32-khz crystal clock i/o gpios gpios columns or xt keyboard dram control addr addr gpios gpios internal bus sa bus data rom control data bus gpios or keyboard rows dram control or keyboard rows isa control or keyboard rows isa control isa control or gpios gpios am486 cpu dual dma controllers 8237 power management unit clock generation real-time clock boundary scan at port logic timer 8254 dual interrupt controllers 8259 pc card controller epp parallel port uart 16550 infrared port memory management unit address decoder data steering lcd graphics controller vl-bus controller system arbiter memory controller keyboard interface: matrix/xt/scp isa bus controller lansc400 or lansc410 microcontroller not supported in the lansc410 microcontroller.
lan?sc400 microcontroller register set reference manual amendment 27 amendment register set differences the following table lists changes to the register de- scriptions found in the lan?sc400 microcontroller register set reference manual , order #21032a, that are required for the lansc410 microcontroller. be- cause the pc card controller and lcd graphics con- troller are not supported on the lansc410 microcontroller, most register bit fields that control those functions are reserved. a few register bits are shared between unsupported and supported functions. these shared bit functions are also explained in the ta- ble. note: the state of reserved register bits must be preserved by software during read/modify/write operations. page numbers in the following table refer to the lan?sc400 microcontroller register set reference manual , order #21032a. table 2. register set manual differences for lansc410 microcontroller register i/o address bits comment page direct-mapped registers mda/hga index register 03b4h 7C0 reserved on the lansc410 microcontroller 2-130 mda/hga data register 03b5 7C0 reserved on the lansc410 microcontroller 2-131 mda/hga mode control register 03b8h 7C0 reserved on the lansc410 microcontroller 2-132 mda/hga status register 03bah 7C0 reserved on the lansc410 microcontroller 2-133 hga configuration register 03bfh 7C0 reserved on the lansc410 microcontroller 2-134 cga index register 03d4h 7C0 reserved on the lansc410 microcontroller 2-135 cga data port 03d5h 7C0 reserved on the lansc410 microcontroller 2-136 cga mode control register 03d8h 7C0 reserved on the lansc410 microcontroller 2-137 cga color select register 03d9h 7C0 reserved on the lansc410 microcontroller 2-138 cga status register 03dah 7C0 reserved on the lansc410 microcontroller 2-139 primary 82365-compatible pc card controller index register 03e0h 7C0 reserved on the lansc410 microcontroller 2-140 primary 82365-compatible pc card controller data port 03e1h 7C0 reserved on the lansc410 microcontroller 2-141 chip setup and control (csc) index registers cache and vl miscellaneous register 22h/23h index 14h 7 reserved on the lansc410 microcontroller 3-23 pin strap status register 22h/23h index 20h 2 1 = reserved on the lansc410 microcontroller 3-25 linear romcs0 /shadow register 22h/23h index 21h 6 1 = reserved on the lansc410 microcontroller 3-26 mms window cCf attributes register 22h/23h index 30h 7C0 on the lansc410 microcontroller, the pc card functions referred to on these pages are not valid. however, the enable and mode bits referred to are shared by mms windows and must be configured as described (csc index d0h[1] = 1 and f1h[0] = 0) to enable the configuration of mms windows cCf. 3-38 mms window cCf device select register 22h/23h index 31h 7C0 3-39 pin mux register b 22h/23h index 39h 6, 5 1 = reserved on the lansc410 microcontroller 3-45 1, 0 0 1 = reserved on the lansc410 microcontroller pin mux register c 22h/23h index 3ah 0 1 = reserved on the lansc410 microcontroller 3-46
28 lan?sc400 microcontroller register set reference manual amendment amendment pmu force mode register 22h/23h index 40h 5 reserved on the lansc410 microcontroller 3-51 wake-up source enable register d 22h/23h index 55h 7C0 reserved on the lansc410 microcontroller 3-62 wake-up source status register d 22h/23h index 59h 7C0 reserved on the lansc410 microcontroller 3-66 activity source enable register a 22h/23h index 62h 3C2 reserved on the lansc410 microcontroller 3-71 activity source enable register d 22h/23h index 65h 6C1 reserved on the lansc410 microcontroller 3-74 activity source status register a 22h/23h index 66h 3C2 reserved on the lansc410 microcontroller 3-75 activity source status register d 22h/23h index 69h 6C1 reserved on the lansc410 microcontroller 3-78 activity classification register a 22h/23h index 6ah 3C2 reserved on the lansc410 microcontroller 3-79 activity classification register d 22h/23h index 6dh 6C1 reserved on the lansc410 microcontroller 3-82 clk_io pin output clock select register 22h/23h index 83h 3C0 0 0 1 0 = reserved on the lansc410 microcontroller 3-91 pc card and keyboard smi/ nmi enable register 22h/23h index 91h 3C0 reserved on the lansc410 microcontroller 3-95 pc card and keyboard smi/ nmi status register 22h/23h index 95h 3C0 reserved on the lansc410 microcontroller 3-100 smi/nmi select register 22h/23h index 98h 5 reserved on the lansc410 microcontroller 3-104 i/o access smi enable register a 22h/23h index 99h 3 reserved on the lansc410 microcontroller 3-105 i/o access smi enable register b 22h/23h index 9ah 4, 3 reserved on the lansc410 microcontroller 3-106 i/o access smi status register a 22h/23h index 9bh 3 reserved on the lansc410 microcontroller 3-107 i/o access smi status register b 22h/23h index 9ch 4, 3 reserved on the lansc410 microcontroller 3-108 internal i/o device disable/ echo z-bus configuration register 22h/23h index d0h 1 this bits pc card function is invalid on the lansc410 microcontroller. however, this bit is shared by mms windows and must be set (= 1) to enable mms windows cCf setup. 3-165 dma resource channel map register b 22h/23h index dch 3C0 reserved on the lansc410 microcontroller 3-178 internal graphics control register a 22h/23h index ddh 7C0 reserved on the lansc410 microcontroller 3-179 internal graphics control register b 22h/23h index deh 7C0 reserved on the lansc410 microcontroller 3-180 suspend pin state register a 22h/23h index e3h 7, 6 reserved on the lansc410 microcontroller 3-184 table 2. register set manual differences for lansc410 microcontroller (continued) register i/o address bits comment page
lan?sc400 microcontroller register set reference manual amendment 29 amendment suspend mode pin state override register 22h/23h index e5h 7, 6 reserved on the lansc410 microcontroller 3-186 pc card extended features register 22h/23h index f0h 7C0 reserved on the lansc410 microcontroller 3-196 pc card mode and dma control register 22h/23h index f1h 7C1 reserved on the lansc410 microcontroller 3-198 0 this bits pc card function is invalid on the lansc410 microcontroller. however, this bit is shared by mms windows and must be cleared (= 0) to enable mms windows cCf setup. pc card socket a/b input pull-up control register 22h/23h index f2h 7C0 reserved on the lansc410 microcontroller 3-200 rtc index registers (no changes) graphics index registers cursor start register 3x4h/3x5h index 0ah 7C0 reserved on the lansc410 microcontroller 5-6 cursor end register 3x4h/3x5h index 0bh 7C0 reserved on the lansc410 microcontroller 5-7 start address high register 3x4h/3x5h index 0ch 7C0 reserved on the lansc410 microcontroller 5-8 start address low register 3x4h/3x5h index 0dh 7C0 reserved on the lansc410 microcontroller 5-9 cursor address high register 3x4h/3x5h index 0eh 7C0 reserved on the lansc410 microcontroller 5-10 cursor address low register 3x4h/3x5h index 0fh 7C0 reserved on the lansc410 microcontroller 5-11 light pen high register (read only) 3x4h/3x5h index 10h 7C0 reserved on the lansc410 microcontroller 5-12 light pen low register (read only) 3x4h/3x5h index 11h 7C0 reserved on the lansc410 microcontroller 5-13 horizontal total register 3x4h/3x5h index 30h 7C0 reserved on the lansc410 microcontroller 5-14 horizontal display end register 3x4h/3x5h index 31h 7C0 reserved on the lansc410 microcontroller 5-15 horizontal line pulse start register 3x4/3x5 index 32h 7C0 reserved on the lansc410 microcontroller 5-16 horizontal border end register 3x4h/3x5h index 33h 7C0 reserved on the lansc410 microcontroller 5-17 non-display lines register 3x4h/3x5h index 34h 7C0 reserved on the lansc410 microcontroller 5-18 vertical adjust register 3x4h/3x5h index 35h 7C0 reserved on the lansc410 microcontroller 5-19 overflow register 3x4h/3x5h index 36h 7C0 reserved on the lansc410 microcontroller 5-20 vertical display end register 3x4h/3x5h index 37h 7C0 reserved on the lansc410 microcontroller 5-21 table 2. register set manual differences for lansc410 microcontroller (continued) register i/o address bits comment page
30 lan?sc400 microcontroller register set reference manual amendment amendment vertical border end register 3x4h/3x5h index 38h 7C0 reserved on the lansc410 microcontroller 5-22 frame sync delay register 3x4h/3x5h index 39h 7C0 reserved on the lansc410 microcontroller 5-23 dual scan row adjust register 3x4h/3x5h index 3bh 7C0 reserved on the lansc410 microcontroller 5-24 dual scan offset address high register 3x4h/3x5h index 3ch 7C0 reserved on the lansc410 microcontroller 5-25 dual scan offset address low register 3x4h/3x5h index 3dh 7C0 reserved on the lansc410 microcontroller 5-26 offset register 3x4h/3x5h index 3eh 7C0 reserved on the lansc410 microcontroller 5-27 underline location register 3x4h/3x5h index 3fh 7C0 reserved on the lansc410 microcontroller 5-28 maximum scan line register 3x4h/3x5h index 40h 7C0 reserved on the lansc410 microcontroller 5-29 lcd panel ac modulation clock control register 3x4h/3x5h index 41h 7C0 reserved on the lansc410 microcontroller 5-30 font table register 3x4h/3x5h index 42h 7C0 reserved on the lansc410 microcontroller 5-31 graphics controller grayscale mode register 3x4h/3x5h index 43h 7C0 reserved on the lansc410 microcontroller 5-32 graphics controller grayscale remapping registers 3x4h/3x5h index 44C4bh 7C0 reserved on the lansc410 microcontroller 5-34 pixel clock control register 3x4h/3x5h index 4ch 7C0 reserved on the lansc410 microcontroller 5-36 frame buffer base address register 3x4h/3x5h index 4dh 7C0 reserved on the lansc410 microcontroller 5-37 font buffer base address high byte register 3x4h/3x5h index 4eh 7C0 reserved on the lansc410 microcontroller 5-38 frame/font buffer base address register low 3x4h/3x5h index 4fh 7C0 reserved on the lansc410 microcontroller 5-39 pmu control register 1 3x4h/3x5h index 50h 7C0 reserved on the lansc410 microcontroller 5-40 pmu control register 2 3x4h/3x5h index 51h 7C0 reserved on the lansc410 microcontroller 5-41 extended feature control register 3x4h/3x5h index 52h 7C0 reserved on the lansc410 microcontroller 5-42 pc card controller indexed registers identification and revision register 3e0h/3e1h index 00, 40h 7C0 reserved on the lansc410 microcontroller 6-7 interface status register 3e0h/3e1h index 01, 41h 7C0 reserved on the lansc410 microcontroller 6-8 power and resetdrv control register 3e0h/3e1h index 02, 42h 7C0 reserved on the lansc410 microcontroller 6-9 table 2. register set manual differences for lansc410 microcontroller (continued) register i/o address bits comment page
lan?sc400 microcontroller register set reference manual amendment 31 amendment interrupt and general control register 3e0h/3e1h index 03, 43h 7C0 reserved on the lansc410 microcontroller 6-11 card status change register 3e0h/3e1h index 04, 44h 7C0 reserved on the lansc410 microcontroller 6-12 card status change interrupt configuration register 3e0h/3e1h index 05, 45h 7C0 reserved on the lansc410 microcontroller 6-13 address window enable register 3e0h/3e1h index 06, 46h 7C0 reserved on the lansc410 microcontroller 6-15 i/o window control register 3e0h/3e1h index 07, 47h 7C0 reserved on the lansc410 microcontroller 6-16 i/o window 0 start address low register 3e0h/3e1h index 08h, 48h 7C0 reserved on the lansc410 microcontroller 6-17 i/o window 0 start address high register 3e0h/3e1h index 09h, 49h 7C0 reserved on the lansc410 microcontroller 6-18 i/o window 0 stop address low register 3e0h/3e1h index 0ah, 4ah 7C0 reserved on the lansc410 microcontroller 6-19 i/o window 0 stop address high register 3e0h/3e1h index 0bh, 4bh 7C0 reserved on the lansc410 microcontroller 6-20 i/o window 1 start address low register 3e0h/3e1h index 0ch, 4ch 7C0 reserved on the lansc410 microcontroller 6-21 i/o window 1 start address high register 3e0h/3e1h index 0dh, 4dh 7C0 reserved on the lansc410 microcontroller 6-22 i/o window 1 stop address low register 3e0h/3e1h index 0eh, 4eh 7C0 reserved on the lansc410 microcontroller 6-23 i/o window 1 stop address high register 3e0h/3e1h index 0fh, 4fh 7C0 reserved on the lansc410 microcontroller 6-24 memory window 0 start address low register 3e0h/3e1h index 10h, 50h 7C0 reserved on the lansc410 microcontroller 6-25 memory window 0 start address high register 3e0h/3e1h index 11h, 51h 7C0 reserved on the lansc410 microcontroller 6-26 memory window 0 stop address low register 3e0h/3e1h index 12h, 52h 7C0 reserved on the lansc410 microcontroller 6-27 memory window 0 stop address high register 3e0h/3e1h index 13h, 53h 7C0 reserved on the lansc410 microcontroller 6-28 memory window 0 address offset low register 3e0h/3e1h index 14h, 54h 7C0 reserved on the lansc410 microcontroller 6-29 memory window 0 address offset high register 3e0h/3e1h index 15h, 55h 7C0 reserved on the lansc410 microcontroller 6-30 memory window 1 start address low register 3e0h/3e1h index 18h, 58h 7C0 reserved on the lansc410 microcontroller 6-31 memory window 1 start address high register 3e0h/3e1h index 19h, 59h 7C0 reserved on the lansc410 microcontroller 6-32 memory window 1 stop address low register 3e0h/3e1h index 1ah, 5ah 7C0 reserved on the lansc410 microcontroller 6-33 memory window 1 stop address high register 3e0h/3e1h index 1bh, 5bh 7C0 reserved on the lansc410 microcontroller 6-34 table 2. register set manual differences for lansc410 microcontroller (continued) register i/o address bits comment page
32 lan?sc400 microcontroller register set reference manual amendment amendment memory window 1 address offset low register 3e0h/3e1h index 1ch, 5ch 7C0 reserved on the lansc410 microcontroller 6-35 memory window 1 address offset high register 3e0h/3e1h index 1dh, 5dh 7C0 reserved on the lansc410 microcontroller 6-36 memory window 2 start address low register 3e0h/3e1h index 20h, 60h 7C0 reserved on the lansc410 microcontroller 6-37 memory window 2 start address high register 3e0h/3e1h index 21h, 61h 7C0 reserved on the lansc410 microcontroller 6-38 memory window 2 stop address low register 3e0h/3e1h index 22h, 62h 7C0 reserved on the lansc410 microcontroller 6-39 memory window 2 stop address high register 3e0h/3e1h index 23h, 63h 7C0 reserved on the lansc410 microcontroller 6-40 memory window 2 address offset low register 3e0h/3e1h index 24h, 64h 7C0 reserved on the lansc410 microcontroller 6-41 memory window 2 address offset high register 3e0h/3e1h index 25h, 65h 7C0 reserved on the lansc410 microcontroller 6-42 memory window 3 start address low register 3e0h/3e1h index 28h, 68h 7C0 reserved on the lansc410 microcontroller 6-43 memory window 3 start address high register 3e0h/3e1h index 29h, 69h 7C0 reserved on the lansc410 microcontroller 6-44 memory window 3 stop address low register 3e0h/3e1h index 2ah, 6ah 7C0 reserved on the lansc410 microcontroller 6-45 memory window 3 stop address high register 3e0h/3e1h index 2bh, 6bh 7C0 reserved on the lansc410 microcontroller 6-46 memory window 3 address offset low register 3e0h/3e1h index 2ch, 6ch 7C0 reserved on the lansc410 microcontroller 6-47 memory window 3 address offset high register 3e0h/3e1h index 2dh, 6dh 7C0 reserved on the lansc410 microcontroller 6-48 memory window 4 start address low register 3e0h/3e1h index 30h, 70h 7C0 reserved on the lansc410 microcontroller 6-49 memory window 4 start address high register 3e0h/3e1h index 31h, 71h 7C0 reserved on the lansc410 microcontroller 6-50 memory window 4 stop address low register 3e0h/3e1h index 32h, 72h 7C0 reserved on the lansc410 microcontroller 6-51 memory window 4 stop address high register 3e0h/3e1h index 33h, 73h 7C0 reserved on the lansc410 microcontroller 6-52 memory window 4 address offset low register 3e0h/3e1h index 34h, 74h 7C0 reserved on the lansc410 microcontroller 6-53 memory window 4 address offset high register 3e0h/3e1h index 35h, 75h 7C0 reserved on the lansc410 microcontroller 6-54 setup timing 0 register 3e0h/3e1h index 3ah 7C0 reserved on the lansc410 microcontroller 6-55 command timing 0 register 3e0h/3e1h index 3bh 7C0 reserved on the lansc410 microcontroller 6-56 recovery timing 0 register 3e0h/3e1h index 3ch 7C0 reserved on the lansc410 microcontroller 6-57 table 2. register set manual differences for lansc410 microcontroller (continued) register i/o address bits comment page
lan?sc400 microcontroller register set reference manual amendment 33 amendment setup timing 1 register 3e0h/3e1h index 3dh 7C0 reserved on the lansc410 microcontroller 6-58 command timing 1 register 3e0h/3e1h index 3eh 7C0 reserved on the lansc410 microcontroller 6-59 recovery timing 1 register 3e0h/3e1h index 3fh 7C0 reserved on the lansc410 microcontroller 6-60 setup timing 2 register 3e0h/3e1h index 7ah 7C0 reserved on the lansc410 microcontroller 6-61 command timing 2 register 3e0h/3e1h index 7bh 7C0 reserved on the lansc410 microcontroller 6-62 recovery timing 2 register 3e0h/3e1h index 7ch 7C0 reserved on the lansc410 microcontroller 6-63 setup timing 3 register 3e0h/3e1h index 7dh 7C0 reserved on the lansc410 microcontroller 6-64 command timing 3 register 3e0h/3e1h index 7eh 7C0 reserved on the lansc410 microcontroller 6-65 recovery timing 3 register 3e0h/3e1h index 7fh 7C0 reserved on the lansc410 microcontroller 6-66 table 2. register set manual differences for lansc410 microcontroller (continued) register i/o address bits comment page
34 lan?sc400 microcontroller register set reference manual amendment amendment
lan?sc400 microcontroller register set reference manual amendment 35 amendment index a activity classification register a, 28 activity classification register c, 11 activity classification register d, 28 activity source enable register a, 28 activity source enable register c, 10 activity source enable register d, 10, 28 activity source status register a, 28 activity source status register c, 11 activity source status register d, 28 address window enable register, 23, 31 b battery low and acin smi/nmi enable register, 13 battery low and acin smi/nmi status register, 13 battery/ac pin configuration register b, 11 battery/ac pin state register, 11 block diagram, 26 c cache and vl miscellaneous register, 7, 27 card status change interrupt configuration register, 31 card status change register, 31 cga color select register, 27 cga data port, 27 cga index register, 27 cga mode control register, 27 cga status register, 27 cga/mda data port, 22 cga/mda index register, 22 chip setup and control (csc) indexed registers, 7, 27 clk_io pin output clock select register, 12, 28 clock control register, 12 com1 baud clock divisor latch lsb, 6 com1 baud clock divisor latch msb, 6 com1 interrupt id register, 6 com1 modem control register, 6 com1 modem status register, 6 com2 baud clock divisor latch lsb, 4 com2 baud clock divisor latch msb, 4 com2 interrupt id register, 4 com2 modem status register, 4 command timing 0 register, 23, 32 command timing 1 register, 24, 33 command timing 2 register, 24, 33 command timing 3 register, 33 cpu clock auto slowdown register, 12 cpu clock speed register, 11 csc index 04h, 7 csc index 05h, 7 csc index 11h, 7 csc index 14h, 7, 27 csc index 20h, 27 csc index 21h, 7, 27 csc index 24h, 7 csc index 25h, 7 csc index 26h, 8 csc index 27h, 8 csc index 28h, 8 csc index 30h, 27 csc index 31h, 27 csc index 38h, 8 csc index 39h, 27 csc index 3ah, 27 csc index 40h, 28 csc index 41h, 9 csc index 45h, 9 csc index 52h, 9 csc index 54h, 9 csc index 55h, 28 csc index 56h, 10 csc index 58h, 10 csc index 59h, 28 csc index 62h, 28 csc index 64h, 10 csc index 65h, 10, 28 csc index 66h, 28 csc index 68h, 11 csc index 69h, 28 csc index 6ah, 28 csc index 6ch, 11 csc index 6dh, 28 csc index 71h, 11 csc index 72h, 11 csc index 80h, 11 csc index 81h, 12 csc index 82h, 12 csc index 83h, 12, 28 csc index 90h, 12, 13 csc index 91h, 28 csc index 93h, 13 csc index 95h, 28 csc index 97h, 13 csc index 98h, 13, 28 csc index 99h, 14, 28 csc index 9ah, 15, 28 csc index 9bh, 28 csc index 9ch, 28 csc index 9dh, 15 csc index a6h, 15 csc index a7h, 15 csc index a8h, 15 csc index a9h, 15 csc index abh, 15 csc index ach, 16 csc index adh, 16 csc index b5h, 16 csc index b7h, 16 csc index boh, 16
36 lan?sc400 microcontroller register set reference manual amendment amendment csc index c0h, 16 csc index c1h, 16 csc index d0h, 16, 28 csc index d2h, 17 csc index d3h, 17 csc index d8h, 17 csc index dch, 28 csc index ddh, 28 csc index deh, 28 csc index e3h, 17, 28 csc index e5h, 29 csc index eah, 18 csc index ech, 18 csc index eeh, 19 csc index efh, 20 csc index f0h, 29 csc index f1h, 29 csc index f2h, 29 csc index ffh, 20 cursor address high register, 29 cursor address low register, 29 cursor end register, 22, 29 cursor start register, 29 d direct-mapped register 0040h, 1 direct-mapped register 0041h, 1 direct-mapped register 0042h, 1 direct-mapped register 0064h, 2 direct-mapped register 0070h, 2, 21 direct-mapped register 00d2h, 2 direct-mapped register 00d4h, 2 direct-mapped register 00d6h, 2 direct-mapped register 00d8h, 2 direct-mapped register 00dah, 3 direct-mapped register 00dch, 3 direct-mapped register 0279h, 3 direct-mapped register 02f8h, 4 direct-mapped register 02f9h, 4 direct-mapped register 02fah, 4 direct-mapped register 02feh, 4 direct-mapped register 0379h, 5 direct-mapped register 03b4h, 27 direct-mapped register 03b5ah, 27 direct-mapped register 03b8h, 27 direct-mapped register 03bah, 27 direct-mapped register 03bfh, 27 direct-mapped register 03d4h, 27 direct-mapped register 03d5h, 27 direct-mapped register 03d8h, 27 direct-mapped register 03d9h, 27 direct-mapped register 03dah, 27 direct-mapped register 03e0h, 27 direct-mapped register 03e1h, 27 direct-mapped register 03f8h, 6 direct-mapped register 03f9h, 6 direct-mapped register 03fah, 6 direct-mapped register 03fch, 6 direct-mapped register 03feh, 6 direct-mapped register 03x4h, 22 direct-mapped register 03x5h, 22 direct-mapped registers, 1, 27 dma resource channel map register b, 28 dram control register, 7 dram refresh control register, 7 dual scan offset address high register, 30 dual scan offset address low register, 30 dual scan row adjust register, 30 e lansc400 microcontroller revision id register, 20 extended feature control register, 30 f font buffer base address high byte register, 30 font table register, 30 frame buffer base address register, 30 frame sync delay register, 30 frame/font buffer base address register low, 30 g general purpose cmos ram, 21 gp_csa i/o address decode and mask register, 16 gp_csb address decode and mask register, 16 gpio read-back/write register aCd, 15 gpio_pmub mode change register, 15 gpio_pmuc mode change register, 16 gpio_pmud mode change register, 16 gpio_xmi to gpio_cs map, 16 graphics controller, 25 graphics controller grayscale mode register, 30 graphics controller grayscale remapping registers, 30 graphics controller indexed registers, 22, 29 graphics index 0ah, 22, 29 graphics index 0bh, 29 graphics index 0ch, 29 graphics index 0dh, 29 graphics index 0eh, 29 graphics index 0fh, 29 graphics index 10h, 29 graphics index 11h, 29 graphics index 30h, 29 graphics index 31h, 29 graphics index 32h, 29 graphics index 33h, 29 graphics index 34h, 22, 29 graphics index 35h, 29 graphics index 36h, 22, 29 graphics index 37h, 22, 29 graphics index 38h, 22, 30 graphics index 39h, 30 graphics index 3bh, 30 graphics index 3ch, 30 graphics index 3dh, 30
lan?sc400 microcontroller register set reference manual amendment 37 amendment graphics index 3eh, 30 graphics index 3fh, 30 graphics index 40h, 30 graphics index 41h, 30 graphics index 42h, 30 graphics index 43h, 30 graphics index 44C4bh, 30 graphics index 4ch, 22, 30 graphics index 4dh, 30 graphics index 4eh, 30 graphics index 4fh, 30 graphics index 50h, 30 graphics index 51h, 30 graphics index 52h, 30 h hga configuration register, 27 horizontal border end register, 29 horizontal display end register, 29 horizontal line pulse start register, 29 horizontal total register, 29 i i/o access smi enable register a, 14, 28 i/o access smi enable register b, 15, 28 i/o access smi status register a, 28 i/o access smi status register b, 28 i/o window 0 start address high register, 31 i/o window 0 start address low register, 31 i/o window 0 stop address high register, 31 i/o window 0 stop address low register, 31 i/o window 1 start address high register, 31 i/o window 1 start address low register, 31 i/o window 1 stop address high register, 31 i/o window 1 stop address low register, 31 i/o window control register, 31 identification and revision register, 30 interface status register, 23, 30 internal graphics control register a, 28 internal graphics control register b, 28 internal i/o device disable/echo z-bus configuration register, 28 internal i/o device disable/internal cycle echo config- uration register, 16 interrupt and general control register, 23, 31 interrupt configuration register e, 17 irda control register, 18 irda crc status register, 18 irda frame length register a, 19 irda frame length register b, 20 k keyboard configuration register a, 16 keyboard configuration register b, 16 l lcd graphics controller. see graphics controller lcd panel ac modulation clock register, 30 light pen high register, 29 light pen low register, 29 linear romcs0 /shadow register, 7, 27 m master dma clear byte pointer register, 2 master dma controller reset register, 3 master dma controller temporary register, 3 master dma mask register channels 4C7, 2 master dma mode register channels 4C7, 2 master dma reset mask register, 3 master software drq(n) request register, 2 maximum scan line register, 30 mda/hga data register, 27 mda/hga index register, 27 mda/hga mode control register, 27 mda/hga status register, 27 memory window 0 address offset high register, 31 memory window 0 address offset low register, 31 memory window 0 start address high register, 31 memory window 0 start address low register, 31 memory window 0 stop address high register, 31 memory window 0 stop address low register, 31 memory window 1 address offset high register, 32 memory window 1 address offset low register, 32 memory window 1 start address high register, 31 memory window 1 start address low register, 31 memory window 1 stop address high register, 31 memory window 1 stop address low register, 31 memory window 2 address offset high register, 32 memory window 2 address offset low register, 32 memory window 2 start address high register, 32 memory window 2 start address low register, 32 memory window 2 stop address high register, 32 memory window 2 stop address low register, 32 memory window 3 address offset high register, 32 memory window 3 address offset low register, 32 memory window 3 start address high register, 32 memory window 3 start address low register, 32 memory window 3 stop address high register, 32 memory window 3 stop address low register, 32 memory window 4 address offset high register, 32 memory window 4 address offset low register, 32 memory window 4 start address high register, 32 memory window 4 start address low register, 32 memory window 4 stop address high register, 32 memory window 4 stop address low register, 32 miscellaneous smi/nmi enable register, 12, 13 mms window cCf attributes register, 27 mms window cCf device select register, 27 mms window cCf setup, 27, 28, 29
38 lan?sc400 microcontroller register set reference manual amendment amendment n non-cacheable window 0 address/attributes/smm register, 7 non-display lines register, 22, 29 o offset register, 30 overflow register, 22, 29 p parallel port 1 status register, 5 parallel port 2 status register, 3 parallel port configuration register, 17 pc card and keyboard smi/nmi enable register, 28 pc card and keyboard smi/nmi status register, 28 pc card controller, 25 pc card controller data port, 27 pc card controller index register, 27 pc card controller indexed registers, 23, 30 pc card extended features register, 29 pc card index 00h/40h, 30 pc card index 01h/41h, 23, 30 pc card index 02h/42h, 30 pc card index 03h/43h, 23, 31 pc card index 04h/44h, 31 pc card index 05h/45h, 31 pc card index 06h/46h, 23, 31 pc card index 07h/47h, 31 pc card index 08h/48h, 31 pc card index 09h/49h, 31 pc card index 0ah/4ah, 31 pc card index 0bh/4bh, 31 pc card index 0ch/4ch, 31 pc card index 0dh/4dh, 31 pc card index 0eh/4eh, 31 pc card index 0fh/4fh, 31 pc card index 10h/50h, 31 pc card index 11h/51h, 31 pc card index 12h/52h, 31 pc card index 13h/53h, 31 pc card index 14h/54h, 31 pc card index 15h/55h, 31 pc card index 18h/58h, 31 pc card index 19h/59h, 31 pc card index 1ah/5ah, 31 pc card index 1bh/5bh, 31 pc card index 1ch/5ch, 32 pc card index 1dh/5dh, 32 pc card index 20h/60h, 32 pc card index 21h/61h, 32 pc card index 22h/62h, 32 pc card index 23h/63h, 32 pc card index 24h/64h, 32 pc card index 25h/65h, 32 pc card index 28h/68h, 32 pc card index 29h/69h, 32 pc card index 2ah/6ah, 32 pc card index 2bh/6bh, 32 pc card index 2ch/6ch, 32 pc card index 2dh/6dh, 32 pc card index 30h/70h, 32 pc card index 31h/71h, 32 pc card index 32h/72h, 32 pc card index 33h/73h, 32 pc card index 34h/74h, 32 pc card index 35h/75h, 32 pc card index 3ah, 32 pc card index 3bh, 23, 32 pc card index 3ch, 32 pc card index 3dh, 33 pc card index 3eh, 24, 33 pc card index 3fh, 33 pc card index 7ah, 33 pc card index 7bh, 24, 33 pc card index 7ch, 33 pc card index 7dh, 33 pc card index 7eh, 33 pc card index 7fh, 33 pc card mode and dma control register, 29 pc card socket a/b input pull-up control register, 29 pc/at keyboard mouse interface status register, 2 pin mux register a, 8 pin mux register b, 27 pin mux register c, 27 pin strap status register, 27 pixel clock control register, 22, 30 pmu control register 1, 30 pmu control register 2, 30 pmu force mode register, 28 pmu present and last mode register, 9 power and resetdrv control register, 30 primary 82365-compatible pc card controller data port, 27 primary 82365-compatible pc card controller index register, 27 programmable interval timer #1 channel 0 count register, 1 programmable interval timer #1 channel 1 count register, 1 programmable interval timer #1 channel 2 count register, 1 r recovery timing 0 register, 32 recovery timing 1 register, 33 recovery timing 2 register, 33 recovery timing 3 register, 33 register a, 21 romcs0 configuration register b, 7 romcs1 configuration register a, 7 romcs1 configuration register b, 8 romcs2 configuration register a, 8 romcs2 configuration register b, 8 rtc and cmos ram indexed registers, 21
lan?sc400 microcontroller register set reference manual amendment 39 amendment rtc index 0ah, 21 rtc index 0e-7fh, 21 rtc index registers, 29 rtc register a, 21 rtc/cmos ram index register, 2, 21 s setup timing 0 register, 32 setup timing 1 register, 33 setup timing 2 register, 33 setup timing 3 register, 33 smi/nmi select register, 13, 28 start address high register, 29 start address low register, 29 suspend mode pin state override register, 29 suspend pin state register a, 17, 28 u uart fifo control shadow register, 17 underline location register, 30 v vertical adjust register, 29 vertical border end register, 22, 30 vertical display end register, 22, 29 vl_rst signal, 7 w wake-up pause/high-speed clock timers register, 9 wake-up source enable register a, 9 wake-up source enable register c, 9 wake-up source enable register d, 28 wake-up source status register a, 10 wake-up source status register c, 10 wake-up source status register d, 28 x xmi control register, 15 ? 1997 advanced micro devices, inc. all rights reserved. trademarks amd, the amd logo, and combinations thereof are trademarks of advanced micro devices, inc. lan is a trademark of advanced micro devices, inc. microsoft and windows are registered trademarks of microsoft corp. product names used in this publication are for identification purposes and may be trademarks of their respective companies.
40 lan?sc400 microcontroller register set reference manual amendment amendment

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