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| the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. mos integrated circuit m m m m pd98412 1.5g atm switch lsi document no. s14237ej2v0ds00 (2nd edition) date published april 2000 n cp(k) printed in japan data sheet 1999 description the m pd98412 (neascot-x15) is an lsi integrating atm switch functions on a single chip. it has utopia level2 interfaces and can switch 30 30 circuits by connecting multiple phy devices. this lsi employs a shared buffer non-blocking type switch and realizes a switch capacity of 1.5g bps by using an externally connected sram for buffering cells. for a detailed description of the functions of the controller, refer to the following users manual: m m m m pd98412 users manual: s14169e features ? conforms to atm forum uni version 3.1 & traffic management 4.0 ? realizes all switch functions with a single chip ? non-blocking type with switch capacity of 1.5g bps ? utopia level2 interface allowing you to select bit widths (4 ports 8 bits, 2 ports 8 bits + 1 port 16 bits, 2 ports 16 bits) ? various polling modes for utopia level2 interface ? can switch 30 logical ports ? multi-speed (622m bps, 155m bps, 52m bps, 25m bps, etc.) ? microprocessor connecting port can be set for signaling processing and oam cell processing ? supports 16k/32k/64k uni-cast vp/vc and 1k/2k/4k multi-cast vp/vc ? shared buffer architecture using standard sram ? cell buffer capacity: 12.8k/25.6k/51.2k cells ? supports four qos classes (cbr, vbr, abr, ubr) ? abr traffic control (binary mode) ? supports epd (early packet discard) and ppd (partial packet discard) ? +3.3-v single power source (directly connectable with +5-v ttl level signals) ? test function: supports jtag (ieee 1149.1) remark active low pins are indicated as _b (symbol_b after pin names) in this document. ordering information part number package m pd98412n7-h6 576-pin tape bga (40 40) the mark shows major revised points.
data sheet s14237ej2v0ds00 2 m m m m pd98412 example of system configuration (application) the m pd98412 can be used to realize an atm layer cell switching function by connecting it to a microprocessor, sram for use as a cell buffer, and a header translation table (htt)/sram for storing control information as shown below. logical inport logical outport #0 phy #28 phy #29 phy phy #0 phy #28 phy #29 16-bit 50 mhz 8-bit 33 mhz 32-bit + parity 92-bit 8-bit 33 mhz utopia level 2 16-bit 50 mhz utopia level 2 utopia level 2 utopia level 2 micro- processer htt & control memory cell buffer (memory ) htt: header translation table physical inport #0 physical outport #0 #1 #1 #2 #2 #3 #3 pd98412 neascot/x15 m data sheet s14237ej2v0ds00 3 m m m m pd98412 block diagram utopia receive port 0 utopia receive port 1 utopia receive port 2 utopia receive port 3 utopia transmit port 0 utopia transmit port 1 utopia transmit port 2 utopia transmit port 3 input port interface output interface microprocessor interface output arbiter output header selector input header selector microprocessor htt & control memory test htt & control memory interface test interface queue controller input payload separator output payload selector cell buffer memory cell buffer interface data sheet s14237ej2v0ds00 4 m m m m pd98412 pin configuration (1) 8-bit 12-phy polling mode/15-phy polling mode jdi jdo jck jtag utopia interface 3 utopia interface 1 utopia interface 2 utopia interface 0 jms jrst_b rxdata3 [7:0] txdata3 [7:0] uclk3 rxenb3_b txenb3_b rxsoc3 txsoc3 rxclav3 txclav3 rxaddr3 [3:0] rxdata1 [7:0] uclk1 rxenb1_b rxsoc1 rxclav1 rxaddr1 [3:0] txaddr3 [3:0] txdata1 [7:0] txenb1_b txsoc1 txclav1 txaddr1 [3:0] txdata2 [7:0] txenb2_b txsoc2 txclav2 txaddr2 [3:0] txdata0 [7:0] txenb0_b txsoc0 txclav0 txaddr0 [3:0] uclk2 rxdata2 [7:0] rxenb2_b rxsoc2 rxclav2 rxaddr2 [3:0] uclk0 rxdata0 [7:0] rxenb0_b rxsoc0 rxclav0 rxaddr0 [3:0] rdy_b int hclk cbcs_b [1:0] cbwe_b cboe_b cba [17:0] cbd [91:0] reset_b swclk htd [31:0] htp [3:0] htoe_b htwe_b htcs_b [1:0] hta [17:0] ad [31:0] uwe_b r/w_b mcs_b iocs_b cell buffer interface control htt & control memory interface microprocessor interface 8 8 8 8 4 4 4 4 8 8 8 8 4 4 4 4 2 32 18 32 42 18 92 neascot-x15 pd98412 m data sheet s14237ej2v0ds00 5 m m m m pd98412 (2) 16-bit multiplexed status polling mode jdi jdo jck jtag utopia interface 1 utopia interface 0 jms jrst_b rxdata1 [15:0] uclk1 rxenb1_b rxsoc1 rxclav1 rxaddr1 [4:0] txdata1 [15:0] txenb1_b txsoc1 txclav1 txaddr1 [4:0] txdata0 [15:0] txenb0_b txsoc0 txclav0 txaddr0 [4:0] uclk0 rxdata0 [15:0] rxenb0_b rxsoc0 rxclav0 rxaddr0 [4:0] rdy_b int hclk cbcs_b [1:0] cbwe_b cboe_b cba [17:0] cbd [91:0] reset_b swclk htd [31:0] htp [3:0] htoe_b htwe_b htcs_b [1:0] hta [17:0] ad [31:0] uwe_b r/w_b mcs_b iocs_b cell buffer interface control htt & control memory interface microprocessor interface 16 16 5 5 16 16 5 5 2 32 18 32 42 18 92 neascot-x15 pd98412 m data sheet s14237ej2v0ds00 6 m m m m pd98412 (3) 16-bit 2-group weighted polling mode jdi jdo jck rxclav1a rxaddr1a [3:0] rxenb1a_b rxdata1 [15:0] uclk1 rxsoc1 rxclav1b rxaddr1b [3:0] rxenb1b_b txaddr1a [3:0] txclav1a txenb1a_b txaddr1b [3:0] txclav1b txenb1b_b txsoc1 txdata1 [15:0] txclav0a txaddr0a [3:0] txenb0a_b txdata0 [15:0] txsoc0 txclav0b txaddr0b [3:0] txenb0b_b rxaddr0a [3:0] rxclav0a rxenb0a_b rxsoc0 uclk0 rxdata0 [15:0] rxaddr0b [3:0] rxclav0b rxenb0b_b jtag jms jrst_b rdy_b int hclk cbcs_b [1:0] cbwe_b cboe_b cba [17:0] cbd [91:0] reset_b swclk htd [31:0] htp [3:0] htoe_b htwe_b htcs_b [1:0] hta [17:0] ad [31:0] uwe_b r/w_b mcs_b iocs_b cell buffer interface control htt & control memory interface microprocessor interface 2 32 18 32 42 18 92 neascot-x15 pd98412 m 16 4 4 4 4 16 16 16 4 4 4 group b utopia interace 1 group a group b group a group a utopia interace 0 group b group a group b 4 data sheet s14237ej2v0ds00 7 m m m m pd98412 (4) 16-bit 1-group weighted polling mode jdi jdo jck jtag utopia interface 1 utopia interface 0 jms jrst_b rxdata1 [15:0] uclk1 rxenb1_b rxsoc1 rxclav1 [3:0] rxaddr1 [4:0] txdata1 [15:0] txenb1_b txsoc1 txclav1 [3:0] txaddr1 [4:0] txdata0 [15:0] txenb0_b txsoc0 txclav0 [3:0] txaddr0 [4:0] uclk0 rxdata0 [15:0] rxenb0_b rxsoc0 rxclav0 [3:0] rxaddr0 [4:0] rdy_b int hclk cbcs_b [1:0] cbwe_b cboe_b cba [17:0] cbd [91:0] reset_b swclk htd [31:0] htp [3:0] htoe_b htwe_b htcs_b [1:0] hta [17:0] ad [31:0] uwe_b r/w_b mcs_b iocs_b cell buffer interface control htt & control memory interface microprocessor interface 16 16 5 5 16 16 5 5 2 32 18 32 42 18 92 neascot-x15 pd98412 m data sheet s14237ej2v0ds00 8 m m m m pd98412 pin configuration (bottom view) ? 576-pin tape bga (40 40) m m m m pd98412n7-h6 59 171 198 275 300 371 394 459 480 539 30 144 250 348 438 520 558 88 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 ak aj ah ag af ae ad ac ab aa y w v u t r p n m l k j h g f e d c b a 117 116 225 224 325 324 417 416 501 576 500 1 index area note note the index area is shown in top view. data sheet s14237ej2v0ds00 9 m m m m pd98412 pin name 1. power 4. jtag v dd : supply voltage jdi : jtag data input gnd : ground jdo : jtag data output jck : jtag data clock 2. memory interface jms : jtag mode select hta17 - hta0 : htt memory address jrst_b : jtag reset htd31 - htd0 : htt memory data bus htp3 - htp0 : htt memory data bus parity 5. other htcs1_b, htcs0_b : htt memory chip select swclk : system clock htwe_b : htt memory write enable reset_b : hardware reset htoe_b : htt memory output enable ic : internal connected cba17 - cba0 : cell buffer memory address cg : connect ground cbd91 - cbd0 : cell buffer memory data bus pu : pull-up cbcs1_b, cbcs0_b: cell buffer memory chip select cbwe_b : cell buffer memory write enable cboe_b : cell buffer memory output enable 3. cpu interface iocs_b : i/o chip select mcs_b : memory chip select rdy_b : i/o ready, memory ready int : interrupt request hclk : host clock ad31 - ad00 : address and data r/w_b : read/write uwe_b : upper word enable data sheet s14237ej2v0ds00 10 m m m m pd98412 6. utopia (1) 8-bit 12-phy polling mode/15-phy polling mode uclk0 : utopia clock rxaddr33-rxaddr30 : receive address rxaddr03-rxaddr00 : receive address rxdata307-rxdata300 : receive data bus rxdata007-rxdata000 : receive data bus rxsoc3 : receive start of cell rxsoc0 : receive start of cell rxenb3_b : receive enable data rxenb0_b : receive enable data transfers transfers rxclav3 : receive cell buffer rxclav0 : receive cell buffer available available txaddr33-txaddr30 : transmit address txaddr03-txaddr00 : transmit address txdata307-txdata300 : transmit data bus txdata007-txdata000 : transmit data bus txsoc3 : transmit start of cell txsoc0 : transmit start of cell txenb3_b : transmit enable data txenb0_b : transmit enable data transfers transfers txclav3 : transmit cell buffer txclav0 : transmit cell buffer available available uclk1 : utopia clock (2) 16-bit multiplexed status polling mode rxaddr13-rxaddr10 : receive address uclk0 : utopia clock rxdata107-rxdata100 : receive data bus rxaddr04-rxaddr00 : receive address rxsoc1 : receive start of cell rxdata015-rxdata000 : receive data bus rxenb1_b : receive enable data rxsoc0 : receive start of cell transfers rxenb0_b : receive enable data rxclav1 : receive cell buffer transfers available rxclav0[3]-rxclav0[0] : receive cell buffer txaddr13-txaddr10 : transmit address available txdata107-txdata100 : transmit data bus txaddr04-txaddr00 : transmit address txsoc1 : transmit start of cell txdata015-txdata000 : transmit data bus txenb1_b : transmit enable data txsoc0 : transmit start of cell transfers txenb0_b : transmit enable data txclav1 : transmit cell buffer transfers available txclav0[3]-txclav0[0] : transmit cell buffer uclk2 : utopia clock available rxaddr23-rxaddr20 : receive address uclk1 : utopia clock rxdata207-rxdata200 : receive data bus rxaddr14-rxaddr10 : receive address rxsoc2 : receive start of cell rxdata115-rxdata100 : receive data bus rxenb2_b : receive enable data rxsoc1 : receive start of cell transfers rxenb1_b : receive enable data rxclav2 : receive cell buffer transfers available rxclav1[3]-rxclav1[0] : receive cell buffer txaddr23-txaddr20 : transmit address available txdata207-txdata200 : transmit data bus txaddr14-txaddr10 : transmit address txsoc2 : transmit start of cell txdata115-txdata100 : transmit data bus txenb2_b : transmit enable data txsoc1 : transmit start of cell transfers txenb1_b : transmit enable data txclav2 : transmit cell buffer txclav1[3]-txclav1[0] : transmit cell buffer available available uclk3 : utopia clock data sheet s14237ej2v0ds00 11 m m m m pd98412 (3) 16-bit 2-group weighted polling mode (4) 16-bit 1-group weighted polling mode uclk0 : utopia clock uclk0 : utopia clock rxaddr0a3-rxaddr0a0 : receive address rxaddr04-rxaddr00 : receive address rxaddr0b3-rxaddr0b0 : receive address rxdata015-rxdata000 : receive data bus rxdata015-rxdata000 : receive data bus rxsoc0 : receive start of cell rxsoc0 : receive start of cell rxenb0_b : receive enable data rxenb0a_b, rxenb0b_b : receive enable data transfers transfers rxclav0 : receive cell buffer rxclav0a, rxclav0b : receive cell buffer available available txaddr04-txaddr00 : transmit address txaddr0a3-txaddr0a0 : transmit address txdata015-txdata000 : transmit data bus txaddr0b3-txaddr0b0 : transmit address txsoc0 : transmit start of cell txdata015-txdata000 : transmit data bus txenb0_b : transmit enable data txsoc0 : transmit start of cell transfers txenb0a_b, txenb0b_b : transmit enable data txclav0 : transmit cell buffer transfers available txclav0a, txclav0b : transmit cell buffer uclk1 : utopia clock available rxaddr14-rxaddr10 : receive address uclk1 : utopia clock rxdata115-rxdata100 : receive data bus rxaddr1a3-rxaddr1a0 : receive address rxsoc1 : receive start of cell rxaddr1b3-rxaddr1b0 : receive address rxenb1_b : receive enable data rxdata115-rxdata100 : receive data bus transfers rxsoc1 : receive start of cell rxclav1 : receive cell buffer rxenb1a_b, rxenb1b_b : receive enable data available transfers txaddr14-txaddr10 : transmit address rxclav1a, rxclav1b : receive cell buffer txdata115-txdata100 : transmit data bus available txsoc1 : transmit start of cell txaddr1a3-txaddr1a0 : transmit address txenb1_b : transmit enable data txaddr1b3-txaddr1b0 : transmit address transfers txdata115-txdata100 : transmit data bus txclav1 : transmit cell buffer txsoc1 : transmit start of cell available txenb1a_b, txenb1b_b : transmit enable data transfers txclav1a, txclav1b : transmit cell buffer available data sheet s14237ej2v0ds00 12 m m m m pd98412 pin layout (1/15) pin no. address 12-phy polling mode/ 15-phy polling mode multiplexed status polling mode 2-group weighted polling mode 1-group weighted polling mode i/o 1 a01 ad30 ??? i/o 2b01 gnd ??? 3 c01 ad24 ??? i/o 4 d01 ad20 ??? i/o 5 e01 ad16 ??? i/o 6f01 gnd ??? 7 g01 ad10 ??? i/o 8 h01 ad06 ??? i/o 9j01 gnd ??? 10 k01 ad01 ??? i/o 11 l01 hta17 ??? o 12 m01 hta13 ??? o 13 n01 hta09 ??? o 14 p01 gnd ??? 15 r01 hta06 ??? o 16 t01 hta02 ??? o 17 u01 htcs0_b ??? o 18 v01 htd31 ??? i/o 19 w01 htd29 ??? i/o 20 y01 v dd ??? 21 aa01 htd24 ??? i/o 22 ab01 htd21 ??? i/o 23 ac01 htd17 ??? i/o 24 ad01 htp1 ??? i/o 25 ae01 v dd ??? 26 af01 gnd ??? 27 ag01 htd06 ??? i/o 28 ah01 htd05 ??? i/o 29 aj01 htd01 ??? i/o 30 ak01 pu ??? i 31 ak02 v dd ??? 32 ak03 gnd ??? 33 ak04 jck ??? i 34 ak05 rxdata307 rxdata115 rxdata115 rxdata115 i 35 ak06 v dd ??? 36 ak07 rxdata301 rxdata109 rxdata109 rxdata109 i 37 ak08 gnd ??? 38 ak09 rxclav3 rxclav1[2] rxclav1b cg i 39 ak10 v dd ??? 40 ak11 txaddr33 ic txaddr1b3 ic o data sheet s14237ej2v0ds00 13 m m m m pd98412 (2/15) pin no. address 12-phy polling mode/ 15-phy polling mode multiplexed status polling mode 2-group weighted polling mode 1-group weighted polling mode i/o 41 ak12 cg txclav1[3] cg cg i 42 ak13 txdata307 txdata115 txdata115 txdata115 o 43 ak14 v dd ??? 44 ak15 txdata304 txdata112 txdata112 txdata112 o 45 ak16 txdata300 txdata108 txdata108 txdata108 o 46 ak17 rxdata104 rxdata104 rxdata104 rxdata104 i 47 ak18 rxdata100 rxdata100 rxdata100 rxdata100 i 48 ak19 uclk1 uclk1 uclk1 uclk1 i 49 ak20 rxclav1 rxclav1[0] rxclav1a rxclav1 i 50 ak21 rxaddr12 rxaddr12 rxaddr1a2 rxaddr12 o 51 ak22 txaddr12 txaddr12 txaddr1a2 txaddr12 o 52 ak23 txclav1 txclav1[0] txclav1a txclav1 i 53 ak24 txdata107 txdata107 txdata107 txdata107 o 54 ak25 txdata103 txdata103 txdata103 txdata103 o 55 ak26 cbd87 ??? i/o 56 ak27 cbd84 ??? i/o 57 ak28 v dd ??? 58 ak29 gnd ??? 59 ak30 cbd77 ??? i/o 60 aj30 gnd ??? 61 ah30 v dd ??? 62 ag30 cbd68 ??? i/o 63 af30 cbd64 ??? i/o 64 ae30 v dd ??? 65 ad30 cbd58 ??? i/o 66 ac30 cbd54 ??? i/o 67 ab30 v dd ??? 68 aa30 cbd49 ??? i/o 69 y30 cbd47 ??? i/o 70 w30 cbcs1_b ??? o 71 v30 cba17 ??? o 72 u30 v dd ??? 73 t30 cba14 ??? o 74 r30 cba10 ??? o 75 p30 cba06 ??? o 76 n30 cba02 ??? o 77 m30 cba00 ??? o 78 l30 v dd ??? 79 k30 cbd39 ??? i/o 80 j30 cbd35 ??? i/o data sheet s14237ej2v0ds00 14 m m m m pd98412 (3/15) pin no. address 12-phy polling mode/ 15-phy polling mode multiplexed status polling mode 2-group weighted polling mode 1-group weighted polling mode i/o 81 h30 v dd ??? 82 g30 cbd29 ??? i/o 83 f30 cbd25 ??? i/o 84 e30 gnd ??? 85 d30 cbd18 ??? i/o 86 c30 v dd ??? 87 b30 v dd ??? 88 a30 cbd11 ??? i/o 89 a29 v dd ??? 90 a28 cbd05 ??? i/o 91 a27 cbd01 ??? i/o 92 a26 rxdata005 rxdata005 rxdata005 rxdata005 i 93 a25 rxdata003 rxdata003 rxdata003 rxdata003 i 94 a24 v dd ??? 95 a23 rxclav0 rxclav0[0] rxclav0a rxclav0 i 96 a22 v dd ??? 97 a21 txaddr03 txaddr03 txaddr03 txaddr03 o 98 a20 txaddr01 txaddr01 txaddr01 txaddr01 o 99 a19 txsoc0 txsoc0 txsoc0 txsoc0 o 100 a18 txdata005 txdata005 txdata005 txdata005 o 101 a17 gnd ??? 102 a16 txdata001 txdata001 txdata001 txdata001 o 103 a15 rxdata205 rxdata013 rxdata013 rxdata013 i 104 a14 rxdata201 rxdata009 rxdata009 rxdata009 i 105 a13 rxenb2_b ic rxenb0b_b ic o 106 a12 rxclav2 rxclav0[2] rxclav0b cg i 107 a11 rxaddr21 ic rxaddr0b1 ic o 108 a10 txaddr22 ic txaddr0b2 ic o 109 a09 txclav2 txclav0[2] txclav0b cg i 110 a08 gnd ??? 111 a07 txdata203 txdata011 txdata011 txdata011 o 112 a06 v dd ??? 113 a05 gnd ??? 114 a04 r/w_b ??? i 115 a03 uwe_b ??? i 116 a02 cg ??? i 117 b02 ad29 ??? i/o 118 c02 ad27 ??? i/o 119 d02 v dd ??? 120 e02 ad19 ??? i/o data sheet s14237ej2v0ds00 15 m m m m pd98412 (4/15) pin no. address 12-phy polling mode/ 15-phy polling mode multiplexed status polling mode 2-group weighted polling mode 1-group weighted polling mode i/o 121 f02 ad15 ??? i/o 122 g02 ad11 ??? i/o 123 h02 ad09 ??? i/o 124 j02 ad05 ??? i/o 125 k02 ad04 ??? i/o 126 l02 ad00 ??? i/o 127 m02 hta14 ??? o 128 n02 hta10 ??? o 129 p02 v dd ??? 130 r02 hta05 ??? o 131 t02 hta01 ??? o 132 u02 htwe_b ??? o 133 v02 htd30 ??? i/o 134 w02 htd26 ??? i/o 135 y02 htd25 ??? i/o 136 aa02 htd22 ??? i/o 137 ab02 htd20 ??? i/o 138 ac02 htd16 ??? i/o 139 ad02 htd13 ??? i/o 140 ae02 htd10 ??? i/o 141 af02 htd07 ??? i/o 142 ag02 htd02 ??? i/o 143 ah02 gnd ??? 144 aj02 gnd ??? 145 aj03 cbd91 ??? i/o 146 aj04 jdo ??? o 147 aj05 v dd ??? 148 aj06 rxdata306 rxdata114 rxdata114 rxdata114 i 149 aj07 rxdata302 rxdata110 rxdata110 rxdata110 i 150 aj08 rxdata300 rxdata108 rxdata108 rxdata108 i 151 aj09 rxenb3_b ic rxenb1b_b ic o 152 aj10 v dd ??? 153 aj11 rxaddr30 rxaddr14 rxaddr1b0 rxaddr14 o 154 aj12 txaddr30 txaddr14 txaddr1b0 txaddr14 o 155 aj13 txenb3_b ic txenb1b_b ic o 156 aj14 gnd ??? 157 aj15 txdata303 txdata111 txdata111 txdata111 o 158 aj16 rxdata107 rxdata107 rxdata107 rxdata107 i 159 aj17 rxdata103 rxdata103 rxdata103 rxdata103 i 160 aj18 v dd ??? data sheet s14237ej2v0ds00 16 m m m m pd98412 (5/15) pin no. address 12-phy polling mode/ 15-phy polling mode multiplexed status polling mode 2-group weighted polling mode 1-group weighted polling mode i/o 161 aj19 v dd ??? 162 aj20 gnd ??? 163 aj21 txaddr13 txaddr13 txaddr1a3 txaddr13 o 164 aj22 txaddr10 txaddr10 txaddr1a0 txaddr10 o 165 aj23 txenb1_b txenb1_b txenb1a_b txenb1_b o 166 aj24 txdata104 txdata104 txdata104 txdata104 o 167 aj25 txdata101 txdata101 txdata101 txdata101 o 168 aj26 cbd85 ??? i/o 169 aj27 v dd ??? 170 aj28 cbd80 ??? i/o 171 aj29 cbd76 ??? i/o 172 ah29 cbd74 ??? i/o 173 ag29 gnd ??? 174 af29 cbd67 ??? i/o 175 ae29 cbd63 ??? i/o 176 ad29 cbd59 ??? i/o 177 ac29 cbd57 ??? i/o 178 ab29 cbd53 ??? i/o 179 aa29 cbd52 ??? i/o 180 y29 cbd48 ??? i/o 181 w29 cbd44 ??? i/o 182 v29 cboe_b ??? o 183 u29 gnd ??? 184 t29 cba13 ??? o 185 r29 cba09 ??? o 186 p29 cba05 ??? o 187 n29 cba01 ??? o 188 m29 cbd41 ??? i/o 189 l29 cbd40 ??? i/o 190 k29 cbd36 ??? i/o 191 j29 cbd34 ??? i/o 192 h29 cbd30 ??? i/o 193 g29 cbd26 ??? i/o 194 f29 cbd23 ??? i/o 195 e29 cbd19 ??? i/o 196 d29 gnd ??? 197 c29 cbd14 ??? i/o 198 b29 cbd10 ??? i/o 199 b28 cbd08 ??? i/o 200 b27 cbd02 ??? i/o data sheet s14237ej2v0ds00 17 m m m m pd98412 (6/15) pin no. address 12-phy polling mode/ 15-phy polling mode multiplexed status polling mode 2-group weighted polling mode 1-group weighted polling mode i/o 201 b26 cbd00 ??? i/o 202 b25 rxdata004 rxdata004 rxdata004 rxdata004 i 203 b24 rxdata000 rxdata000 rxdata000 rxdata000 i 204 b23 rxenb0_b rxenb0_b rxenb0a_b rxenb0_b o 205 b22 rxaddr03 rxaddr03 rxaddr0a3 rxaddr03 o 206 b21 rxaddr02 rxaddr02 rxaddr0a2 rxaddr02 o 207 b20 txaddr02 txaddr02 txaddr0a2 txaddr02 o 208 b19 txclav0 txclav0[0] txclav0a txclav0 i 209 b18 txdata006 txdata006 txdata006 txdata006 o 210 b17 txdata002 txdata002 txdata002 txdata002 o 211 b16 txdata000 txdata000 txdata000 txdata000 o 212 b15 rxdata204 rxdata012 rxdata012 rxdata012 i 213 b14 rxdata200 rxdata008 rxdata008 rxdata008 i 214 b13 rxsoc2 rxllav0[3] cg cg i 215 b12 gnd ??? 216 b11 txaddr23 ic txaddr0b3 ic o 217 b10 cg txclav0[3] cg cg i 218 b09 txenb2_b ic txenb0b_b ic o 219 b08 txdata204 txdata012 txdata012 txdata012 o 220 b07 txdata200 txdata008 txdata008 txdata008 o 221 b06 iocs_b ??? i 222 b05 cg ??? i 223 b04 cg ??? i 224 b03 ic ??? o 225 c03 ad28 ??? i/o 226 d03 ad26 ??? i/o 227 e03 ad22 ??? i/o 228 f03 ad18 ??? i/o 229 g03 ad14 ??? i/o 230 h03 v dd ??? 231 j03 ad08 ??? i/o 232 k03 v dd ??? 233 l03 gnd ??? 234 m03 hta15 ??? o 235 n03 hta11 ??? o 236 p03 hta07 ??? o 237 r03 hta03 ??? o 238 t03 hta00 ??? o 239 u03 htoe_b ??? o 240 v03 v dd ??? data sheet s14237ej2v0ds00 18 m m m m pd98412 (7/15) pin no. address 12-phy polling mode/ 15-phy polling mode multiplexed status polling mode 2-group weighted polling mode 1-group weighted polling mode i/o 241 w03 gnd ??? 242 y03 htd23 ??? i/o 243 aa03 v dd ??? 244 ab03 gnd ??? 245 ac03 htd14 ??? i/o 246 ad03 htd11 ??? i/o 247 ae03 htp0 ??? i/o 248 af03 htd03 ??? i/o 249 ag03 htd00 ??? i/o 250 ah03 ic ??? o 251 ah04 cbd90 ??? i/o 252 ah05 jdi ??? i 253 ah06 jms ??? i 254 ah07 rxdata305 rxdata113 rxdata113 rxdata113 i 255 ah08 gnd ??? 256 ah09 gnd ??? 257 ah10 rxsoc3 rxclav1[3] cg cg i 258 ah11 rxaddr31 ic rxaddr1b1 ic o 259 ah12 txaddr31 ic txaddr1b1 ic o 260 ah13 txsoc3 ic ic ic o 261 ah14 txdata305 txdata113 txdata113 txdata113 o 262 ah15 txdata301 txdata109 txdata109 txdata109 o 263 ah16 rxdata106 rxdata106 rxdata106 rxdata106 i 264 ah17 rxdata102 rxdata102 rxdata102 rxdata102 i 265 ah18 gnd ??? 266 ah19 rxaddr13 rxaddr13 rxaddr1a3 rxaddr13 o 267 ah20 rxaddr10 rxaddr10 rxaddr1a0 rxaddr10 o 268 ah21 txaddr11 txaddr11 txaddr1a1 txaddr11 o 269 ah22 txsoc1 txsoc1 txsoc1 txsoc1 o 270 ah23 txdata105 txdata105 txdata105 txdata105 o 271 ah24 txdata102 txdata102 txdata102 txdata102 o 272 ah25 cbd86 ??? i/o 273 ah26 cbd81 ??? i/o 274 ah27 cbd79 ??? i/o 275 ah28 cbd75 ??? i/o 276 ag28 cbd73 ??? i/o 277 af28 cbd69 ??? i/o 278 ae28 cbd66 ??? i/o 279 ad28 cbd62 ??? i/o 280 ac28 gnd ??? data sheet s14237ej2v0ds00 19 m m m m pd98412 (8/15) pin no. address 12-phy polling mode/ 15-phy polling mode multiplexed status polling mode 2-group weighted polling mode 1-group weighted polling mode i/o 281 ab28 cbd56 ??? i/o 282 aa28 gnd ??? 283 y28 v dd ??? 284 w28 cbd45 ??? i/o 285 v28 cbwe_b ??? o 286 u28 cba15 ??? o 287 t28 cba11 ??? o 288 r28 cba08 ??? o 289 p28 cba04 ??? o 290 n28 v dd ??? 291 m28 gnd ??? 292 l28 cbd37 ??? i/o 293 k28 v dd ??? 294 j28 cbd31 ??? i/o 295 h28 cbd27 ??? i/o 296 g28 cbd24 ??? i/o 297 f28 cbd20 ??? i/o 298 e28 cbd15 ??? i/o 299 d28 cbd13 ??? i/o 300 c28 cbd09 ??? i/o 301 c27 cbd07 ??? i/o 302 c26 cbd03 ??? i/o 303 c25 rxdata007 rxdata007 rxdata007 rxdata007 i 304 c24 gnd ??? 305 c23 gnd ??? 306 c22 rxsoc0 rxsoc0 rxsoc0 rxsoc0 i 307 c21 gnd ??? 308 c20 v dd ??? 309 c19 cg txclav0[1] cg cg i 310 c18 txdata007 txdata007 txdata007 txdata007 o 311 c17 txdata003 txdata003 txdata003 txdata003 o 312 c16 rxdata206 rxdata014 rxdata014 rxdata014 i 313 c15 gnd ??? 314 c14 gnd ??? 315 c13 v dd ??? 316 c12 rxaddr20 rxaddr04 rxaddr0b0 rxaddr04 o 317 c11 txaddr20 txaddr04 txaddr0b0 txaddr04 o 318 c10 txsoc2 ic ic ic o 319 c09 txdata205 txdata013 txdata013 txdata013 o 320 c08 txdata201 txdata009 txdata009 txdata009 o data sheet s14237ej2v0ds00 20 m m m m pd98412 (9/15) pin no. address 12-phy polling mode/ 15-phy polling mode multiplexed status polling mode 2-group weighted polling mode 1-group weighted polling mode i/o 321 c07 cg ??? i 322 c06 rdy_b ??? o 323 c05 gnd ??? 324 c04 v dd ??? 325 d04 v dd ??? 326 e04 ad25 ??? i/o 327 f04 gnd ??? 328 g04 ad17 ??? i/o 329 h04 v dd ??? 330 j04 gnd ??? 331 k04 ad07 ??? i/o 332 l04 v dd ??? 333 m04 hta16 ??? o 334 n04 hta12 ??? o 335 p04 hta08 ??? o 336 r04 hta04 ??? o 337 t04 v dd ??? 338 u04 htp3 ??? i/o 339 v04 gnd ??? 340 w04 htp2 ??? i/o 341 y04 gnd ??? 342 aa04 v dd ??? 343 ab04 htd15 ??? i/o 344 ac04 htd12 ??? i/o 345 ad04 htd08 ??? i/o 346 ae04 htd04 ??? i/o 347 af04 reset_b ??? i 348 ag04 ic ??? o 349 ag05 cbd89 ??? i/o 350 ag06 ic ??? 351 ag07 jrst_b ??? i 352 ag08 gnd ??? 353 ag09 v dd ??? 354 ag10 uclk3 cg cg cg i 355 ag11 rxaddr32 ic rxaddr1b2 ic o 356 ag12 txaddr32 ic txaddr1b2 ic o 357 ag13 txclav3 txclav1[2] txclav1b cg i 358 ag14 txdata306 txdata114 txdata114 txdata114 o 359 ag15 txdata302 txdata110 txdata110 txdata110 o 360 ag16 v dd ??? data sheet s14237ej2v0ds00 21 m m m m pd98412 (10/15) pin no. address 12-phy polling mode/ 15-phy polling mode multiplexed status polling mode 2-group weighted polling mode 1-group weighted polling mode i/o 361 ag17 rxdata101 rxdata101 rxdata101 rxdata101 i 362 ag18 rxenb1_b rxenb1_b rxenb1a_b rxenb1_b o 363 ag19 rxaddr11 rxaddr11 rxaddr1a1 rxaddr11 o 364 ag20 gnd ??? 365 ag21 gnd ??? 366 ag22 txdata106 txdata106 txdata106 txdata106 o 367 ag23 gnd ??? 368 ag24 gnd ??? 369 ag25 cbd82 ??? i/o 370 ag26 gnd ??? 371 ag27 v dd ??? 372 af27 cbd72 ??? i/o 373 ae27 cbd70 ??? i/o 374 ad27 cbd65 ??? i/o 375 ac27 gnd ??? 376 ab27 v dd ??? 377 aa27 cbd55 ??? i/o 378 y27 gnd ??? 379 w27 cbd46 ??? i/o 380 v27 cbcs0_b ??? o 381 u27 cba16 ??? o 382 t27 cba12 ??? o 383 r27 v dd ??? 384 p27 cba03 ??? o 385 n27 gnd ??? 386 m27 cbd38 ??? i/o 387 l27 gnd ??? 388 k27 gnd ??? 389 j27 cbd28 ??? i/o 390 h27 gnd ??? 391 g27 cbd21 ??? i/o 392 f27 cbd16 ??? i/o 393 e27 v dd ??? 394 d27 gnd ??? 395 d26 cbd06 ??? i/o 396 d25 gnd ??? 397 d24 rxdata006 rxdata006 rxdata006 rxdata006 i 398 d23 v dd ??? 399 d22 uclk0 uclk0 uclk0 uclk0 i 400 d21 cg rxclav0[1] cg cg i data sheet s14237ej2v0ds00 22 m m m m pd98412 (11/15) pin no. address 12-phy polling mode/ 15-phy polling mode multiplexed status polling mode 2-group weighted polling mode 1-group weighted polling mode i/o 401 d20 gnd ??? 402 d19 txaddr00 txaddr00 txaddr0a0 txaddr00 o 403 d18 txenb0_b txenb0_b txenb0a_b txenb0_b o 404 d17 txdata004 txdata004 txdata004 txdata004 o 405 d16 rxdata207 rxdata015 rxdata015 rxdata015 i 406 d15 v dd ??? 407 d14 uclk2 cg cg cg i 408 d13 rxaddr23 ic rxaddr0b3 ic o 409 d12 txaddr21 ic txaddr0b1 ic o 410 d11 gnd ??? 411 d10 txdata206 txdata014 txdata014 txdata014 o 412 d09 txdata202 txdata010 txdata010 txdata010 o 413 d08 gnd ??? 414 d07 int ??? o 415 d06 cg ??? i 416 d05 ad31 ??? i/o 417 e05 v dd ??? 418 f05 v dd ??? 419 g05 ad21 ??? i/o 420 h05 v dd ??? 421 j05 ad12 ??? i/o 422 k05 v dd ??? 423 l05 ad02 ??? i/o 424 m05 v dd ??? 425 n05 gnd ??? 426 p05 v dd ??? 427 r05 v dd ??? 428 t05 htcs1_b ??? o 429 u05 v dd ??? 430 v05 htd28 ??? i/o 431 w05 v dd ??? 432 y05 htd19 ??? i/o 433 aa05 v dd ??? 434 ab05 gnd ??? 435 ac05 v dd ??? 436 ad05 v dd ??? 437 ae05 swclk ??? i 438 af05 v dd ??? 439 af06 cbd88 ??? i/o 440 af07 gnd ??? data sheet s14237ej2v0ds00 23 m m m m pd98412 (12/15) pin no. address 12-phy polling mode/ 15-phy polling mode multiplexed status polling mode 2-group weighted polling mode 1-group weighted polling mode i/o 441 af08 v dd ??? 442 af09 rxdata303 rxdata111 rxdata111 rxdata111 i 443 af10 v dd ??? 444 af11 gnd ??? 445 af12 v dd ??? 446 af13 v dd ??? 447 af14 v dd ??? 448 af15 v dd ??? 449 af16 rxdata105 rxdata105 rxdata105 rxdata105 i 450 af17 v dd ??? 451 af18 rxsoc1 rxsoc1 rxsoc1 rxsoc1 i 452 af19 v dd ??? 453 af20 v dd ??? 454 af21 v dd ??? 455 af22 v dd ??? 456 af23 v dd ??? 457 af24 cbd83 ??? i/o 458 af25 v dd ??? 459 af26 v dd ??? 460 ae26 gnd ??? 461 ad26 v dd ??? 462 ac26 v dd ??? 463 ab26 cbd60 ??? i/o 464 aa26 v dd ??? 465 y26 cbd50 ??? i/o 466 w26 v dd ??? 467 v26 v dd ??? 468 u26 v dd ??? 469 t26 v dd ??? 470 r26 cba07 ??? o 471 p26 v dd ??? 472 n26 cbd43 ??? i/o 473 m26 v dd ??? 474 l26 cbd33 ??? i/o 475 k26 v dd ??? 476 j26 v dd ??? 477 h26 v dd ??? 478 g26 cbd17 ??? i/o 479 f26 gnd ??? 480 e26 v dd ??? data sheet s14237ej2v0ds00 24 m m m m pd98412 (13/15) pin no. address 12-phy polling mode/ 15-phy polling mode multiplexed status polling mode 2-group weighted polling mode 1-group weighted polling mode i/o 481 e25 v dd ??? 482 e24 v dd ??? 483 e23 v dd ??? 484 e22 rxdata001 rxdata001 rxdata001 rxdata001 i 485 e21 v dd ??? 486 e20 rxaddr00 rxaddr00 rxaddr0a0 rxaddr00 o 487 e19 v dd ??? 488 e18 v dd ??? 489 e17 v dd ??? 490 e16 v dd ??? 491 e15 rxdata202 rxdata010 rxdata010 rxdata010 i 492 e14 v dd ??? 493 e13 rxaddr22 ic rxaddr0b2 ic o 494 e12 v dd ??? 495 e11 v dd ??? 496 e10 v dd ??? 497 e09 hclk ??? i 498 e08 v dd ??? 499 e07 v dd ??? 500 e06 ic ??? 501 f06 gnd ??? 502 g06 ad23 ??? i/o 503 h06 gnd ??? 504 j06 ad13 ??? i/o 505 k06 gnd ??? 506 l06 ad03 ??? i/o 507 m06 gnd ??? 508 n06 v dd ??? 509 p06 gnd ??? 510 r06 gnd ??? 511 t06 gnd ??? 512 u06 gnd ??? 513 v06 htd27 ??? i/o 514 w06 gnd ??? 515 y06 htd18 ??? i/o 516 aa06 gnd ??? 517 ab06 htd09 ??? i/o 518 ac06 gnd ??? 519 ad06 v dd ??? 520 ae06 gnd ??? data sheet s14237ej2v0ds00 25 m m m m pd98412 (14/15) pin no. address 12-phy polling mode/ 15-phy polling mode multiplexed status polling mode 2-group weighted polling mode 1-group weighted polling mode i/o 521 ae07 v dd ??? 522 ae08 gnd ??? 523 ae09 rxdata304 rxdata112 rxdata112 rxdata112 i 524 ae10 gnd ??? 525 ae11 rxaddr33 ic rxaddr1b3 ic o 526 ae12 gnd ??? 527 ae13 gnd ??? 528 ae14 gnd ??? 529 ae15 gnd ??? 530 ae16 gnd ??? 531 ae17 gnd ??? 532 ae18 cg rxclav1[1] cg cg i 533 ae19 gnd ??? 534 ae20 cg txclav1[1] cg cg i 535 ae21 gnd ??? 536 ae22 txdata100 txdata100 txdata100 txdata100 o 537 ae23 gnd ??? 538 ae24 cbd78 ??? i/o 539 ae25 gnd ??? 540 ad25 cbd71 ??? i/o 541 ac25 gnd ??? 542 ab25 cbd61 ??? i/o 543 aa25 gnd ??? 544 y25 cbd51 ??? i/o 545 w25 gnd ??? 546 v25 gnd ??? 547 u25 gnd ??? 548 t25 gnd ??? 549 r25 gnd ??? 550 p25 gnd ??? 551 n25 cbd42 ??? i/o 552 m25 gnd ??? 553 l25 cbd32 ??? i/o 554 k25 gnd ??? 555 j25 cbd22 ??? i/o 556 h25 gnd ??? 557 g25 cbd12 ??? i/o 558 f25 gnd ??? 559 f24 cbd04 ??? i/o 560 f23 gnd ??? data sheet s14237ej2v0ds00 26 m m m m pd98412 (15/15) pin no. address 12-phy polling mode/ 15-phy polling mode multiplexed status polling mode 2-group weighted polling mode 1-group weighted polling mode i/o 561 f22 rxdata002 rxdata002 rxdata002 rxdata002 i 562 f21 gnd ??? 563 f20 rxaddr01 rxaddr01 rxaddr0a1 rxaddr01 o 564 f19 gnd ??? 565 f18 gnd ??? 566 f17 gnd ??? 567 f16 gnd ??? 568 f15 rxdata203 rxdata011 rxdata011 rxdata011 i 569 f14 gnd ??? 570 f13 v dd ??? 571 f12 gnd ??? 572 f11 txdata207 txdata015 txdata015 txdata015 o 573 f10 gnd ??? 574 f09 mcs_b ??? i 575 f08 gnd ??? 576 f07 gnd ??? data sheet s14237ej2v0ds00 27 m m m m pd98412 contents 1. pin functions ............................................................................................................ ............... 28 1.1 power supply ............................................................................................................. ........... 28 1.2 utopia interface ......................................................................................................... ......... 29 1.3 memory interface signals ................................................................................................. ... 41 1.4 microprocessor interface signals ....................................................................................... 42 1.5 jtag ..................................................................................................................... ................. 43 1.6 others ................................................................................................................... ................. 43 1.7 recommended connections of unused pins.................................................................... 44 1.8 pin status at reset ...................................................................................................... ......... 45 2. electrical specifications ................................................................................................ .46 3. package drawing .......................................................................................................... ........ 60 4. recommended soldering conditions........................................................................... 61 data sheet s14237ej2v0ds00 28 m m m m pd98412 1. pin functions although the m pd98412 is a device operating at 3.3 v, it can be directly connected to a phy device, cpu, and memory with a 5-v ttl interface. 1.1 power supply table 1-1. power supply pin name pin no. i/o function v dd 20, 25, 31, 35, 39, 43, 57, 61, 64, 67, 72, 78, 81, 86, 87, 89, 94, 96, 112, 119, 129, 147, 152, 160, 161, 169, 230, 232, 240, 243, 283, 290, 293, 308, 315, 324, 325, 329, 332, 337, 342, 353, 360, 371, 376, 383, 393, 398, 406, 417, 418, 420, 422, 424, 426, 427, 429, 431, 433, 435, 436, 438, 441, 443, 445 - 448, 450, 452 - 456, 458, 459, 461, 462, 464, 466 - 469, 471, 473, 475 - 477, 480 - 483, 485, 487 - 490, 492, 494 - 496, 498, 499, 508, 519, 521, 570 these pins supply a power of +3.3 v 5%. gnd 2, 6, 9, 14, 26, 32, 37, 58, 60, 84, 101, 110, 113, 143, 144, 156, 162, 173, 183, 196, 215, 233, 241, 244, 255, 256, 265, 280, 282, 291, 304, 305, 307, 313, 314, 323, 327, 330, 339, 341, 352, 364, 365, 367, 368, 370, 375, 378, 385, 387, 388, 390, 394, 396, 401, 410, 413, 425, 434, 440, 444, 460, 479, 501, 503, 505, 507, 509 - 512, 514, 516, 518, 520, 522, 524, 526 - 531, 533, 535, 537, 539, 541, 543, 545 - 550, 552, 554, 556, 558, 560, 562, 564 - 567, 569, 571, 573, 575, 576 these are ground pins. data sheet s14237ej2v0ds00 29 m m m m pd98412 1.2 utopia interface the m pd98412 employs a utopia level2 (cell level transfer) interface between phy layer and atm layer. symbol, pim number, and function are varied depending on the polling mode. (1) 8-bit 12-phy polling mode/15-phy polling mode table 1-2. receive interface signals (1/2) symbol pin no. i/o function rxaddr03 - rxaddr00 205, 206, 563, 486 o multi-phy select address of receive interface 0. rxaddr03 is the msb. rxdata007 - rxdata000 303, 397, 92, 202, 93, 561, 484, 203 i cell data input of receive interface 0. cell data is input from a phy layer device in byte units. the m pd98412 reads the data at the rising edge of uclk0. rxdata007 is the msb. rxsoc0 306 i cell transfer start signal of receive interface 0. this signal is input from a phy layer device in synchronization with the first byte of cell data. rxenb0_b 204 o transfer enable signal of receive interface 0. this signal informs a phy layer device that the m pd98412 is ready for reception in the next clock cycle. rxclav0 95 i cell transfer enable signal of receive interface 0. this pin inputs a signal that indicates that no more cells will be supplied to the m pd98412 after the current cell has been transferred. uclk0 399 i utopia clock input of receive interface 0. data is transferred/received at the rising edge of this clock. rxaddr13 - rxaddr10 266, 50, 363, 267 o multi-phy select address of receive interface 1. rxaddr13 is the msb. rxdata107 - rxdata100 158, 263, 449, 46, 159, 264, 361, 47 i cell data input of receive interface 1. cell data is input from a phy layer device in byte units. the m pd98412 reads the data at the rising edge of uclk1. rxdata107 is the msb. rxsoc1 451 i cell transfer start signal of receive interface 1. this signal is input from a phy layer device in synchronization with the first byte of cell data. rxenb1_b 362 o transfer enable signal of receive interface 1. this signal informs a phy layer device that the m pd98412 is ready for reception in the next clock cycle. rxclav1 49 i cell transfer enable signal of receive interface 1. this pin inputs a signal that indicates that no more cells will be supplied to the m pd98412 after the current cell has been transferred. uclk1 48 i utopia clock input of receive interface 1. data is transferred/received at the rising edge of this clock. data sheet s14237ej2v0ds00 30 m m m m pd98412 table 1-2. receive interface signals (2/2) symbol pin no. i/o function rxaddr23 - rxaddr20 408, 493, 107, 316 o multi-phy select address of receive interface 2. rxaddr23 is the msb. rxdata207 - rxdata200 405, 312, 103, 212, 568, 491, 104, 213 i cell data input of receive interface 2. cell data is input from a phy layer device in byte units. the m pd98412 reads the data at the rising edge of uclk2. rxdata207 is the msb. rxsoc2 214 i cell transfer start signal of receive interface 2. this signal is input from a phy layer device in synchronization with the first byte of cell data. rxenb2_b 105 o transfer enable signal of receive interface 2. this signal informs a phy layer device that the m pd98412 is ready for reception in the next clock cycle. rxclav2 106 i cell transfer enable signal of receive interface 2. this pin inputs a signal that indicates that no more cells will be supplied to the m pd98412 after the current cell has been transferred. uclk2 407 i utopia clock input of receive interface 2. data is transferred/received at the rising edge of this clock. rxaddr33 - rxaddr30 525, 355, 258, 153 o multi-phy select address of receive interface 3. rxaddr33 is the msb. rxdata307 - rxdata300 34, 148, 254, 523, 442, 149, 36, 150 i cell data input of receive interface 3. cell data is input from a phy layer device in byte units. the m pd98412 reads the data at the rising edge of uclk3. rxdata307 is the msb. rxsoc3 257 i cell transfer start signal of receive interface 3. this signal is input from a phy layer device in synchronization with the first byte of cell data. rxenb3_b 151 o transfer enable signal of receive interface 3. this signal informs a phy layer device that the m pd98412 is ready for reception in the next clock cycle. rxclav3 38 i cell transfer enable signal of receive interface 3. this pin inputs a signal that indicates that no more cells will be supplied to the m pd98412 after the current cell has been transferred. uclk3 354 i utopia clock input of receive interface 3. data is transferred/received at the rising edge of this clock. data sheet s14237ej2v0ds00 31 m m m m pd98412 table 1-3. transmit interface signals (1/2) symbol pin no. i/o function txaddr03 - txaddr00 97, 207, 98, 402 o multi-phy select address of transmit interface 0. txaddr03 is the msb. txdata007 - txdata000 310, 209, 100, 404, 311, 210, 102, 211 o cell data output of transmit interface 0. cell data is output to a phy layer device in byte units. the m pd98412 outputs the data at the rising edge of uclk0. txdata007 is the msb. (3-state buffer) txsoc0 99 o cell transfer start signal of transmit interface 0. this signal is output to a phy layer device in synchronization with the first byte of cell data. (3-state buffer) txenb0_b 403 o transfer enable signal of transmit interface 0. this signal informs a phy layer device that the m pd98412 outputs data in the current clock cycle. txclav0 208 i cell transfer enable signal of transmit interface 0. this pin inputs a signal that indicates that the m pd98412 is ready to receive the next cell after transfer of the current cell is completed. txaddr13 - txaddr10 163, 51, 268, 164 o multi-phy select address of transmit interface 1. txaddr13 is the msb. txdata107 - txdata100 53, 366, 270, 166, 54, 271, 167, 536 o cell data output of transmit interface 1. the m pd98412 outputs the data at the rising edge of uclk1. txdata107 is the msb. (3-state buffer) txsoc1 269 o cell transfer start signal of transmit interface 1. this signal is output to a phy layer device in synchronization with the first byte of cell data. (3-state buffer) txenb1_b 165 o transfer enable signal of transmit interface 1. this signal informs a phy layer device that the m pd98412 outputs data in the current clock cycle. txclav1 52 i cell transfer enable signal of transmit interface 1. this pin inputs a signal that indicates that the m pd98412 is ready to receive the next cell after transfer of the current cell is completed. data sheet s14237ej2v0ds00 32 m m m m pd98412 table 1-3. transmit interface signals (2/2) symbol pin no. i/o function txaddr23 - txaddr20 216, 108, 409, 317 o multi-phy select address of transmit interface 2. txaddr23 is the msb. txdata207 - txdata200 572, 411, 319, 219, 111, 412, 320, 220 o cell data output of transmit interface 2. the m pd98412 outputs the data at the rising edge of uclk2. txdata207 is the msb. (3-state buffer) txsoc2 318 o cell transfer start signal of transmit interface 2. this signal is output to a phy layer device in synchronization with the first byte of cell data. (3-state buffer) txenb2_b 218 o transfer enable signal of transmit interface 2. this signal informs a phy layer device that the m pd98412 outputs data in the current clock cycle. txclav2 109 i cell transfer enable signal of transmit interface 2. this pin inputs a signal that indicates that the m pd98412 is ready to receive the next cell after transfer of the current cell is completed. txaddr33 - txaddr30 40, 356, 259, 154 o multi-phy select address of transmit interface 3. txaddr33 is the msb. txdata307 - txdata300 42, 358, 261, 44, 157, 359, 262, 45 o cell data output of transmit interface 3. the m pd98412 outputs the data at the rising edge. txdata307 is the msb. (3-state buffer) txsoc3 260 o cell transfer start signal of transmit interface 3. this signal is output to a phy layer device in synchronization with the first byte of cell data. (3-state buffer) txenb3_b 155 o transfer enable signal of transmit interface 3. this signal informs a phy layer device that the m pd98412 outputs data in the current clock cycle. txclav3 357 i cell transfer enable signal of transmit interface 3. this pin inputs a signal that indicates that the m pd98412 is ready to receive the next cell after transfer of the current cell is completed. data sheet s14237ej2v0ds00 33 m m m m pd98412 (2) 16-bit multiplexed status polling mode table 1-4. receive interface signals symbol pin no. i/o function rxaddr04 - rxaddr00 316, 205, 206, 563, 486 o multi-phy select address of receive interface 0. rxaddr04 is the msb. rxdata015 - rxdata000 405, 312, 103, 212, 568, 491, 104, 213, 303, 397, 92, 202, 93, 561, 484, 203 i cell data input of receive interface 0. cell data is input from a phy layer device in 16-bit units. the m pd98412 reads the data at the rising edge of uclk0. rxdata015 is the msb. rxsoc0 306 i cell transfer start signal of receive interface 0. this signal is input from a phy layer device in synchronization with the first byte of cell data. rxenb0_b 204 o transfer enable signal of receive interface 0. this signal informs a phy layer device that the m pd98412 is ready for reception in the next clock cycle. rxclav0[0] - rxclav0[3] 95, 400, 106, 214 i cell transfer enable signal of receive interface 0. this pin inputs a signal that indicates that no more cells will be supplied to the m pd98412. pins to be connected (rxclav0[0]- [3]) differ depending on phy address of the connected phy device. uclk0 399 i utopia clock input of receive interface 0. data is transferred/received at the rising edge of this clock. rxaddr14 - rxaddr10 153, 266, 50, 363, 267 o multi-phy select address of receive interface 1. rxaddr14 is the msb. rxdata115 - rxdata100 34, 148, 254, 523, 442, 149, 36, 150, 158, 263, 449, 46, 159, 264, 361, 47 i cell data input of receive interface 1. cell data is input from a phy layer device in 16-bit units. the m pd98412 reads the data at the rising edge of uclk1. rxdata115 is the msb. rxsoc1 451 i cell transfer start signal of receive interface 1. this signal is input from a phy layer device in synchronization with the first byte of cell data. rxenb1_b 362 o transfer enable signal of receive interface 1. this signal informs a phy layer device that the m pd98412 is ready for reception in the next clock cycle. rxclav1[0] - rxclav1[3] 49, 532, 38, 257 i cell transfer enable signal of receive interface 1. this pin inputs a signal that indicates that no more cells will be supplied to the m pd98412 after the current cell has been transferred. pins to be connected (rxclav1[0]-[3]) differ depending on phy address of the connected phy device. uclk1 48 i utopia clock input of receive interface 1. data is transferred/received at the rising edge of this clock. data sheet s14237ej2v0ds00 34 m m m m pd98412 table 1-5. transmit interface signals symbol pin no. i/o function txaddr04 - txaddr00 317, 97, 207, 98, 402 o multi-phy select address of transmit interface 0. txaddr04 is the msb. txdata015 - txdata000 572, 411, 319, 219, 111, 412, 320, 220, 310, 209, 100, 404, 311, 210, 102, 211 o cell data output of transmit interface 0. cell data is output to a phy layer device in 16-bit units. the m pd98412 outputs the data at the rising edge of uclk0. txdata015 is the msb. (3-state buffer) txsoc0 99 o cell transfer start signal of transmit interface 0. this signal is output to a phy layer device in synchronization with the first byte of cell data. (3-state buffer) txenb0_b 403 o transfer enable signal of transmit interface 0. this signal informs a phy layer device that the m pd98412 outputs data in the current clock cycle. txclav0[0] - txclav0[3] 208, 309, 109, 217 i cell transfer enable signal of transmit interface 0. this pin inputs a signal that indicates that the m pd98412 is ready to receive the next cell after transfer of the current cell is completed. pins to be connected (txclav0[0]-[3]) differ depending on phy address of the connected phy device. txaddr14 - txaddr10 154, 163, 51, 268, 164 o multi-phy select address of transmit interface 1. txaddr14 is the msb. txdata115 - txdata100 42, 358, 261, 44, 157, 359, 262, 45, 53, 366, 270, 166, 54, 271, 167, 536 o cell data output of transmit interface 1. the m pd98412 outputs the data at the rising edge of uclk1. txdata115 is the msb. (3-state buffer) txsoc1 269 o cell transfer start signal of transmit interface 1. this signal is output to a phy layer device in synchronization with the first byte of cell data. (3-state buffer) txenb1_b 165 o transfer enable signal of transmit interface 1. this signal informs a phy layer device that the m pd98412 outputs data in the current clock cycle. txclav1[0] - txclav1[3] 52, 534, 357, 41 i cell transfer enable signal of transmit interface 1. this pin inputs a signal that indicates that the m pd98412 is ready to receive the next cell after transfer of the current cell is completed. pins to be connected (txclav1[0]-[3]) differ depending on phy address of the connected phy device. data sheet s14237ej2v0ds00 35 m m m m pd98412 (3) 16-bit 2-group weighted polling mode table 1-6. receive interface signals (1/2) symbol pin no. i/o function rxaddr0a3 - rxaddr0a0 205, 206, 563, 486 o multi-phy select address of receive interface 0, group a. rxaddr0a3 is the msb. rxaddr0b3 - rxaddr0b0 408, 493, 107, 316 o multi-phy select address of receive interface 0, group b. rxaddr0b3 is the msb. rxenb0a_b 204 o transfer enable signal of receive interface 0, group a. this signal informs a phy layer device that the m pd98412 is ready for reception in the next clock cycle. rxenb0b_b 105 o transfer enable signal of receive interface 0, group b. this signal informs a phy layer device that the m pd98412 is ready for reception in the next clock cycle. rxclav0a 95 i cell transfer enable signal of receive interface 0, group a. this pin inputs a signal that indicates that no more cells will be supplied to the m pd98412 after the current cell has been transferred. rxclav0b 106 i cell transfer enable signal of receive interface 0, group b. this pin inputs a signal that indicates that no more cells will be supplied to the m pd98412 after the current cell has been transferred. rxdata015 - rxdata000 405, 312, 103, 212, 568, 491, 104, 213, 303, 397, 92, 202, 93, 561, 484, 203 i cell data input of receive interface 0. cell data is input from a phy layer device in 16-bit units. the m pd98412 reads the data at the rising edge of uclk0. rxdata015 is the msb. rxsoc0 306 i cell transfer start signal of receive interface 0. this signal is input from a phy layer device in synchronization with the first byte of cell data. uclk0 399 i utopia clock input of receive interface 0. data is transferred/received at the rising edge of this clock. data sheet s14237ej2v0ds00 36 m m m m pd98412 table 1-6. receive interface signals (2/2) symbol pin no. i/o function rxaddr1a3 - rxaddr1a0 266, 50, 363, 267 o multi-phy select address of receive interface 1, group a. rxaddr1a3 is the msb. rxaddr1b3 - rxaddr1b0 525, 355, 258, 153 o multi-phy select address of receive interface 1, group b. rxaddr1b3 is the msb. rxenb1a_b 362 o transfer enable signal of receive interface 1, group a. this signal informs a phy layer device that the m pd98412 is ready for reception in the next clock cycle. rxenb1b_b 151 o transfer enable signal of receive interface 1, group b. this signal informs a phy layer device that the m pd98412 is ready for reception in the next clock cycle. rxclav1a 49 i cell transfer enable signal of receive interface 1, group a. this pin inputs a signal that indicates that no more cells will be supplied to the m pd98412 after the current cell has been transferred. rxclav1b 38 i cell transfer enable signal of receive interface 1, group b. this pin inputs a signal that indicates that no more cells will be supplied to the m pd98412 after the current cell has been transferred. rxdata115 - rxdata100 34, 148, 254, 523, 442, 149, 36, 150, 158, 263, 449, 46, 159, 264, 361, 47 i cell data input of receive interface 1. cell data is input from a phy layer device in 16-bit units. the m pd98412 reads the data at the rising edge of uclk1. rxdata115 is the msb. rxsoc1 451 i cell transfer start signal of receive interface 1. this signal is input from a phy layer device in synchronization with the first byte of cell data. uclk1 48 i utopia clock input of receive interface 1. data is transferred/received at the rising edge of this clock. data sheet s14237ej2v0ds00 37 m m m m pd98412 table 1-7. transmit interface signals (1/2) symbol pin no. i/o function txaddr0a3 - txaddr0a0 97, 207, 98, 402 o multi-phy select address of transmit interface 0, group a. txaddr0a3 is the msb. txaddr0b3 - txaddr0b0 216, 108, 409, 317 o multi-phy select address of transmit interface 0, group b. txaddr0b3 is the msb. txenb0a_b 403 o transfer enable signal of transmit interface 0, group a. this signal informs a phy layer device that the m pd98412 outputs data in the current clock cycle. txenb0b_b 218 o transfer enable signal of transmit interface 0, group b. this signal informs a phy layer device that the m pd98412 outputs data in the current clock cycle. txclav0a 208 i cell transfer enable signal of transmit interface 0, group a. this pin inputs a signal that indicates that the m pd98412 is ready to receive the next cell after transfer of the current cell is completed. txclav0b 109 i cell transfer enable signal of transmit interface 0, group b. this pin inputs a signal that indicates that the m pd98412 is ready to receive the next cell after transfer of the current cell is completed. txdata015 - txdata000 572, 411, 319, 219, 111, 412, 320, 220, 310, 209, 100, 404, 311, 210, 102, 211 o cell data output of transmit interface 0. cell data is output to a phy layer device in 16-bit units. the m pd98412 outputs the data at the rising edge of uclk0. txdata015 is the msb. (3-state buffer) txsoc0 99 o cell transfer start signal of transmit interface 0. this signal is output to a phy layer device in synchronization with the first byte of cell data. (3-state buffer) data sheet s14237ej2v0ds00 38 m m m m pd98412 table 1-7. transmit interface signals (2/2) symbol pin no. i/o function txaddr1a3 - txaddr1a0 163, 51, 268, 164 o multi-phy select address of transmit interface 1, group a. txaddr1a3 is the msb. txaddr1b3 - txaddr1b0 40, 356, 259, 154 o multi-phy select address of transmit interface 1, group b. txaddr1b3 is the msb. txenb1a_b 165 o transfer enable signal of transmit interface 1, group a. this signal informs a phy layer device that the m pd98412 outputs data in the current clock cycle. txenb1b_b 155 o transfer enable signal of transmit interface 1, group b. this signal informs a phy layer device that the m pd98412 outputs data in the current clock cycle. txclav1a 52 i cell transfer enable signal of transmit interface 1, group a. this pin inputs a signal that indicates that the m pd98412 is ready to receive the next cell after transfer of the current cell is completed. txclav1b 357 i cell transfer enable signal of transmit interface 1, group b. this pin inputs a signal that indicates that the m pd98412 is ready to receive the next cell after transfer of the current cell is completed. txdata115 - txdata100 42, 358, 261, 44, 157, 359, 262, 45, 53, 366, 270, 166, 54, 271, 167, 536 o cell data output of transmit interface 1. cell data is output to a phy layer device in 16-bit units. the m pd98412 outputs the data at the rising edge of uclk1. txdata115 is the msb. (3-state buffer) txsoc1 269 o cell transfer start signal of transmit interface 1. this signal is output to a phy layer device in synchronization with the first byte of cell data. (3-state buffer) data sheet s14237ej2v0ds00 39 m m m m pd98412 (4) 16-bit 1-group weighted polling mode table 1-8. receive interface signals symbol pin no. i/o function rxaddr04 - rxaddr00 316, 205, 206, 563, 486 o multi-phy select address of receive interface 0. rxaddr04 is the msb. rxdata015 - rxdata000 405, 312, 103, 212, 568, 491, 104, 213, 303, 397, 92, 202, 93, 561, 484, 203 i cell data input of receive interface 0. cell data is input from a phy layer device in 16-bit units. the m pd98412 reads the data at the rising edge of uclk0. rxdata015 is the msb. rxsoc0 306 i cell transfer start signal of receive interface 0. this signal is input from a phy layer device in synchronization with the first byte of cell data. rxenb0_b 204 o transfer enable signal of receive interface 0. this signal informs a phy layer device that the m pd98412 is ready for reception in the next clock cycle. rxclav0 95 i cell transfer enable signal of receive interface 0. this pin inputs a signal that indicates that no more cells will be supplied to the m pd98412 after the current cell has been transferred. uclk0 399 i utopia clock input of receive interface 0. data is transferred/received at the rising edge of this clock. rxaddr14 - rxaddr10 153, 266, 50, 363, 267 o multi-phy select address of receive interface 1. rxaddr14 is the msb. rxdata115 - rxdata100 34, 148, 254, 523, 442, 149, 36, 150, 158, 263, 449, 46, 159, 264, 361, 47 i cell data input of receive interface 1. cell data is input from a phy layer device in 16-bit units. the m pd98412 reads the data at the rising edge of uclk1. rxdata115 is the msb. rxsoc1 451 i cell transfer start signal of receive interface 1. this signal is input from a phy layer device in synchronization with the first byte of cell data. rxenb1_b 362 o transfer enable signal of receive interface 1. this signal informs a phy layer device that the m pd98412 is ready for reception in the next clock cycle. rxclav1 49 i cell transfer enable signal of receive interface 1. this pin inputs a signal that indicates that no more cells will be supplied to the m pd98412 after the current cell has been transferred. uclk1 48 i utopia clock input of receive interface 1. data is transferred/received at the rising edge of this clock. data sheet s14237ej2v0ds00 40 m m m m pd98412 table 1-9. transmit interface signals symbol pin no. i/o function txaddr04 - txaddr00 317, 97, 207, 98, 402 o multi-phy select address of transmit interface 0. txaddr04 is the msb. txdata015 - txdata000 572, 411, 319, 219, 111, 412, 320, 220, 310, 209, 100, 404, 311, 210, 102, 211 o cell data output of transmit interface 0. cell data is output to a phy layer device in 16-bit units. the m pd98412 outputs the data at the rising edge of uclk0. txdata015 is the msb. (3-state buffer) txsoc0 99 o cell transfer start signal of transmit interface 0. this signal is output to a phy layer device in synchronization with the first byte of cell data. (3-state buffer) txenb0_b 403 o transfer enable signal of transmit interface 0. this signal informs a phy layer device that the m pd98412 outputs data in the current clock cycle. txclav0 208 i cell transfer enable signal of transmit interface 0. this pin inputs a signal that indicates that the m pd98412 is ready to receive the next cell after transfer of the current cell is completed. txaddr14 - txaddr10 154, 163, 51, 268, 164 o multi-phy select address of transmit interface 1. txaddr14 is the msb. txdata115 - txdata100 42, 358, 261, 44, 157, 359, 262, 45, 53, 366, 270, 166, 54, 271, 167, 536 o cell data output of transmit interface 1. the m pd98412 outputs the data at the rising edge of uclk1. txdata115 is the msb. (3-state buffer) txsoc1 269 o cell transfer start signal of transmit interface 1. this signal is output to a phy layer device in synchronization with the first byte of cell data. (3-state buffer) txenb1_b 165 o transfer enable signal of transmit interface 1. this signal informs a phy layer device that the m pd98412 outputs data in the current clock cycle. txclav1 52 i cell transfer enable signal of transmit interface 1. this pin inputs a signal that indicates that the m pd98412 is ready to receive the next cell after transfer of the current cell is completed. data sheet s14237ej2v0ds00 41 m m m m pd98412 1.3 memory interface signals the m pd98412 has two types of memory interfaces. one of them is used to store a cell header translation table and an address pointer to the cell buffer to the htt & control memory, and the other is used to store cell data to the cell buffer memory. table 1-10 shows the interface signals of the htt & control memory. table 1-11 shows the interface signals of the cell buffer memory. table 1-10. htt & control memory interface signals symbol pin no. i/o function hta17 - hta00 11, 333, 234, 127, 12, 334, 235, 128, 13, 335, 236, 15, 130, 336, 237, 16, 131, 238 o address output htd31 - htd00 18, 133, 19, 430, 513, 134, 135, 21, 242, 136, 22, 137, 432, 515, 23, 138, 343, 245, 139, 344, 246, 140, 517, 345, 141, 27, 28, 346, 248, 142, 29, 249 i/o data i/o bus (32-bit/word units) (w/pull-down resistor) htp3 - htp0 338, 340, 24, 247 i/o parity i/o (w/pull-down resistor) htcs1_b, htcs0_b 428, 17 o chip select signal htwe_b 132 o write enable signal htoe_b 239 o output enable signal table 1-11. cell buffer memory interface signals symbol pin no. i/o function cba17 - cba00 71, 381, 286, 73, 184, 382, 287, 74, 185, 288, 470, 75, 186, 289, 384, 76, 187, 77 o address output cbd91 - cbd00 145, 251, 349, 439, 55, 272, 168, 56, 457, 369, 273, 170, 274, 538, 59, 171, 275, 172, 276, 372, 540, 373, 277, 62, 174, 278, 374, 63, 175, 279, 542, 463, 176, 65, 177, 281, 377, 66, 178, 179, 544, 465, 68, 180, 69, 379, 284, 181, 472, 551, 188, 189, 79, 386, 292, 190, 80, 191, 474, 553, 294, 192, 82, 389, 295, 193, 83, 296, 194, 555, 391, 297, 195, 85, 478, 392, 298, 197, 299, 557, 88, 198, 300, 199, 301, 395, 90, 559, 302, 200, 91, 201 i/o data bus (92-bit/word units) (w/pull-down resistor) cbcs1_b, cbcs0_b 70, 380 o chip select signal cbwe_b 285 o write enable signal cboe_b 182 o output enable signal data sheet s14237ej2v0ds00 42 m m m m pd98412 1.4 microprocessor interface signals the m pd98412 supports a 32-bit address/data multiplexed synchronous bus type microprocessor interface. table 1-12. microprocessor interface signal symbol pin no. i/o function iocs_b 221 i i/o chip select signal mcs_b 574 i memory chip select signal int 414 o interrupt request signal hclk 497 i microprocessor bus clock (8 to 33 mhz) ad31 - ad0 416, 1, 117, 225, 118, 226, 326, 3, 502, 227, 419, 4, 120, 228, 328, 5, 121, 229, 504, 421, 122, 7, 123, 231, 331, 8, 124, 125, 506, 423, 10, 126 i/o address/data bus r/w_b 114 i read/write select signal uwe_b 115 i high-order word enable signal rdy_b 322 o ready signal (3-state buffer) data sheet s14237ej2v0ds00 43 m m m m pd98412 1.5 jtag table 1-13. jtag interface signals symbol pin no. i/o function jdi 252 i jtag serial data input jdo 146 o jtag serial data output (normally open) (3-state buffer) jck 33 i jtag serial clock input jms 253 i jtag mode select signal jrst_b 351 i jtag reset signal 1.6 others table 1-14. other interface signals symbol pin no. i/o function swclk 437 i system clock input (8 to 40 mhz) reset_b 347 i hardware reset signal (schmitt input buffer) cg 116, 222, 223, 321, 415 i always connect to gnd. pu 30 i always pull up to v dd . ic 224, 250, 348, 350, 500 o internally connected (always open). data sheet s14237ej2v0ds00 44 m m m m pd98412 1.7 recommended connections of unused pins table 1-15. recommended connections of unused pins pin name i/o recommended connections rxdata*** i connect to gnd. rxsoc* i connect to gnd. rxclav* i connect to gnd. uclk* i connect to gnd. txclav* i connect to gnd. htd31 - htd00 i/o (w/pull-down resistor) open. htp3 - htp0 i/o (w/pull-down resistor) open. cbd91 - cbd00 i/o (w/pull-down resistor) open. iocs_b i pull up to v dd. mcs_b i pull up to v dd. ad31 - ad00 i/o pull up to v dd. r/w_b i pull up to v dd. uwe_b i pull up to v dd. jdi i connect to gnd. jck i connect to gnd. jms i connect to gnd. jrst_b i connect to gnd. all output pins o open. data sheet s14237ej2v0ds00 45 m m m m pd98412 1.8 pin status at reset table 1-16. pin status at reset pin name i/o pin status at reset rxaddr* o high level rxenb*_b o high level txaddr* o high level txdata*** o (3-state buffer) hi-z txsoc* o (3-state buffer) hi-z txenb*_b o high level hta17 - hta00 o low level htcs1_b, htcs0_b o high level htwe_b o high level htoe_b o high level htp3 - htp0 i/o (w/pull-down resistor) low level htd31 - htd00 i/o (w/pull-down resistor) low level cbd91 - cbd00 i/o (w/pull-down resistor) low level cba17 - cba00 o low level cboe_b o high level cbwe_b o high level cbcs1_b, cbcs0_b o high level int o low level rdy_b o (3-state buffer) hi-z ad31 - ad00 i/o hi-z jdo o (3-state buffer) hi-z data sheet s14237ej2v0ds00 46 m m m m pd98412 2. electrical specifications absolute maximum ratings parameter symbol test conditions rating unit supply voltage v dd - 0.5 to +4.6 v input voltage v i v i < v dd + 3.0 v - 0.5 to +6.6 v output voltage v o v o < v dd + 3.0 v - 0.5 to +6.6 v storage temperature t stg - 65 to +150 c caution if any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. the absolute maximum ratings are values that may physically damage the product(s). be sure to use the product(s) within the ratings. capacitance parameter symbol test conditions min. typ. max. unit input capacitance c i frequency = 1 mhz - 10 20 pf output capacitance c o frequency = 1 mhz - 10 20 pf input/output capacitance c io frequency = 1 mhz - 10 20 pf recommended operating condition parameter symbol test conditions min. typ. max. unit supply voltage v dd 3.135 3.300 3.465 v low-level input voltage v il other than reset_b signal 0 - 0.8 v high-level input voltage v ih other than reset_b signal 2.0 - 5.5 v negative trigger voltage v n reset_b signal 0.6 1.8 v positive trigger voltage v p reset_b signal 1.2 2.4 v hysteresis voltage v h 0.3 1.5 v operating temperature t a - 40 - +85 c data sheet s14237ej2v0ds00 47 m m m m pd98412 dc characteristics (t a = - - - - 40 to +85 c, v dd = 3.3 v 5%) parameter symbol test conditions min. typ. max. unit output leakage current i oz v o = v dd or gnd -- 10 m a i li1 v i = v dd or gnd, note 1 -- 10 m a input leakage current i li2 v i = v dd note 2 (50 k w pull-down) 25 120 220 m a i ol1 v ol = 0.4 v, note 3 6.0 -- ma i ol2 v ol = 0.4 v, note 4, 5 9.0 -- ma low-level output leakage current i ol3 v ol = 0.4 v, note 6 12.0 -- ma i oh1 v oh = 2.4 v, note 3 - 3.0 -- ma i oh2 v oh = 2.4 v, note 4 - 4.0 -- ma i oh2 v oh = 2.4 v, note 5 (utopia) - 6.0 -- ma high-level output leakage current i oh3 v oh = 2.4 v, note 6 - 5.0 -- ma low-level output leakage voltage v ol i ol = 0 ma -- 0.1 v v oh1 i oh = 0 ma, note 7 v dd - 0.2 -- v high-level output leakage voltage v oh2 i oh = 0 ma, note 8 v dd - 0.4 -- v operating current i dd v i = v dd or gnd - note 9 1300 ma notes 1. rxdata***, rxsoc*, rxclav*, uclk*, tclav*, ad31-ad00, mcs_b, iocs_b, r/w_b, uwe_b, hclk, jdi, jck, jms, jrst_b, swclk, reset_b pins 2. htd31-htd00, htp3-htp0, cbd91-cbd00 pins 3. int, jdo pins 4. hta17-hta00, htwe_b, htoe_b, cba17-cba00, cbcs0_b, cbwe_b, cboe_b, htcs1_b, htcs0_b, cbcs1_b, htd31-htd00, htp3-htp0, cbd91-cbd00 pins 5. rxaddr**, txaddr**, rxenb*_b, txenb*_b, txdata***, txsoc* pins 6. rdy_b, ad31-ad00 pins 7. int, jdo, rxaddr**, txaddr**, rxenb*_b, txenb*_b, txdata***, txsoc*, htcs1_b, htcs0_b, cbcs1_b, hta17-hta00, htwe_b, htoe_b, cba17-cba00, cbcs0_b, cbwe_b, cboe_b, rdy_b, ad31-ad00 pins 8. htd31-htd00, htp3-htp0, cbd91-cbd00 pins 9. the approximate typ. value of the operating current (i dd ) depends on the throughput of switching. for example with the following conditions, it is calculated as shown below. conditions: 8-bit utopia interface 4 ports, swclk = 40 mhz, uclk0 to uclk3 = 50 mhz calculation formula: i dd (typ.) = 267 t + 600 ma, t (throughput): 0 - 1.5 [unit: gbps] data sheet s14237ej2v0ds00 48 m m m m pd98412 ac test output waveform 2.0 v 2.2 v 0.4 v 0.8 v 2.0 v 0.8 v test point ac characteristics (t a = - - - - 40 to +85 c, v dd = 3.3 v 5%) (1) control signal parameter symbol test conditions min. typ. max. unit swclk cycle time t cysl 25 125 ns swclk high-level width t wskh 10.5 - ns swclk low-level width t wskl 10.5 - ns swclk rise time t skr - 2ns swclk fall time t skf - 2ns reset_b low-level width t wrsl 16 - t cysk control signal t cysk swclk in reset_b in t wskl t wskh t skr t skf t wrsl data sheet s14237ej2v0ds00 49 m m m m pd98412 (2) processor interface (32-bit mode, read/write) parameter symbol test conditions min. typ. max. unit hclk cycle time t cyhk 30 125 ns hclk high-level width t whkh 12 - ns hclk low-level width t whkl 12 - ns hclk rise time t hkr - 3ns hclk fall time t hkf - 3ns hclk -? int output delay time t dhkit load capacitance 30 pf 1 17 ns hclk -? rdy_b output delay time t dhkry load capacitance 70 pf 1 17 ns hclk -? rdy_b float output delay time t fhkry load capacitance 70 pf 1 17 ns hclk -? ad output delay time t dhkad load capacitance 70 pf 1 17 ns hclk -? ad float output delay time t fhkad load capacitance 70 pf 1 17 ns ad setup time (vs. hclk - ) t sadhk 8 - ns ad hold time (vs. hclk - ) t hhkad 1 - ns iocs_b setup time (vs. hclk - ) t siohk 8 - ns iocs_b hold time (vs. hclk - ) t hhkio 1 - ns iocs_b recovery time t iorv note - ns mcs_b setup time (vs. hclk - ) t smhk 8 - ns mcs_b hold time (vs. hclk - ) t hhkm 1 - ns mcs_b recovery time t mrv note - ns uwe_b setup time (vs. hclk - ) t suwhk 8 - ns uwe_b hold time (vs. hclk - ) t hhkuw 1 - ns r/w_b setup time (vs. hclk - ) t srwhk 8 - ns r/w_b hold time (vs. hclk - ) t hhkrw 1 - ns note (1) when hclk cycle time (t cyhk ) < 4 swclk cycle time (t cysk ): iocs_b recovery time (t iorv ) = mcs_b recovery time (t mrv ) = t cyhk (2) when hclk cycle time (t cyhk ) 3 4 swclk cycle time (t cysk ): iocs_b recovery time (t iorv ) = mcs_b recovery time (t mrv ) = t cyhk 2 data sheet s14237ej2v0ds00 50 m m m m pd98412 processor interface (32-bit mode, read) hclk in ad31 - ad00 in/out iocs_b in mcs_b in ume_b in r/w_b in rdy_b out hclk in int out t cyhk t whkh t hkr t hkf t whkl t sadhk t siohk t smhk t suwhk t srwhk t dhkry t dhkit t dhkit t dhkry t fhkry t hhkrw t hhkuw t hhkw t hhkio data address t dhkad t fhkad t mrv t iorv (hi-z) (hi-z) address t hhkad data sheet s14237ej2v0ds00 51 m m m m pd98412 processor interface (32-bit mode, write) hclk in ad31 - ad00 in/out iocs_b in mos_b in ume_b in r/w_b in rdy_b out t cyhk t whkh t hkr t hkf t whkl t sadhk t siohk t smhk t suwhk t srwhk t dhkry t dhkry t fhkry t hhkrw t hhkuw t hhkw t hhkio data don? care t sadhk t hhkad t mrv t iorv (hi-z) (hi-z) address t hhkad data sheet s14237ej2v0ds00 52 m m m m pd98412 (3) htt & control memory interface parameter symbol test conditions min. typ. max. unit hta cycle time t cyha load capacitance 50 pf t cysk - 2 ns htd, htp setup time (vs. hta) t shdha 9ns htd, htp hold time (vs. hta) t hhahd 1ns htcs_b cycle time t cyhc load capacitance 50 pf t cysk - 2 ns htd, htp setup time (vs. htcs_b) t shdhc 9ns htd, htp hold time (vs. htcs_b) t hhchd 1ns htoe_b cycle time t cyho load capacitance 50 pf t cysk - 2 ns htd, htp setup time (vs. htoe_b) t shdho 9ns htd, htp hold time (vs. htoe_b) t hhohd 1ns htwe_b low-level width t whwl load capacitance 50 pf t wskl - 1.5 ns data ? htwe_b - output delay time t dhdhw load capacitance 50 pf t wskl - 3 ns htwe_b -? data float output delay time t fhwhd load capacitance 50 pf 0ns hta ? htwe_b output delay time t dhahw load capacitance 50 pf t wskh - 5 ns htcs_b ? htwe_b - output delay time t dhchw load capacitance 50 pf t cysk - 6 ns htoe_b -? htwe_b - output delay time t dhohw load capacitance 50 pf t cysk - 6 ns htwe_b -? hta output delay time t dhwha load capacitance 50 pf 0ns htwe_b -? htcs_b - output delay time t dhwhc load capacitance 50 pf 0ns htwe_b -? htoe_b output delay time t dhwho load capacitance 50 pf 0ns htd float ? htoe_b output delay time t dhdho load capacitance 50 pf 0ns htoe_b -? data output delay time t dhohd load capacitance 50 pf t wskh - 3 ns data sheet s14237ej2v0ds00 53 m m m m pd98412 htt & control memory interface (read) t cyha t cyhc t cyho t shdhc t shdha t hhahd t shdho t hhchd t hhohd address data (hi-z) (hi-z) (swclk) in hta17 - hta00 out htd31 - htd00, htp3-htp0 in/out htcs1_b, htcs0_b out htoe_b out htwe_b out htt & control memory interface (write) t cyha t dhohd t dhchw t dhdhw t fhwhd t dhdho t dhahw t dhdhw t whwl t dhwhc t dhwha t dhwho address valid (hi-z) (hi-z) (swclk) in hta17 - hta00 out htd31 - htd00, htp3 - htp0 in/out htcs1_b, htcs0_b out htoe_b out htwe_b out data sheet s14237ej2v0ds00 54 m m m m pd98412 (4) cell buffer memory interface parameter symbol test conditions min. typ. max. unit cba cycle time t cyca load capacitance 50 pf t cysk - 2 ns cbd setup time (vs. cba) t scdca 9ns cbd hold time (vs. cba) t hcacd 1ns cbcs_b cycle time t cycc load capacitance 50 pf t cysk - 2 ns cbd setup time (vs. cbcs_b) t scdcc 9ns cbd hold time (vs. cbcs_b) t hcccd 1ns cboe_b cycle time t cyco load capacitance 50 pf t cysk - 2 ns cbd setup time (vs. cboe_b) t scdco 9ns cbd hold time (vs. cboe_b) t hcocd 1ns cbwe_b low-level width t wcwl load capacitance 50 pf t wskl - 1.5 ns data ? cbwe_b - output delay time t dcdcw load capacitance 50 pf t wskl - 3 ns cbwe_b -? data float output delay time t fcwcd load capacitance 50 pf 0ns cba ? cbwe_b output delay time t dcacw load capacitance 50 pf t wskh - 5 ns cbcs_b ? cbwe_b - output delay time t dcccw load capacitance 50 pf t cysk - 6 ns cboe_b -? cbwe_b - output delay time t dcocw load capacitance 50 pf t cysk - 6 ns cbwe_b -? cba output delay time t dcwca load capacitance 50 pf 0ns cbwe_b -? cbcs_b - output delay time t dcwcc load capacitance 50 pf 0ns cbwe_b -? cboe_b output delay time t dcwco load capacitance 50 pf 0ns cbd float ? cboe_b output delay time t dcdco load capacitance 50 pf 0ns cboe_b -? data output delay time t dcocd load capacitance 50 pf t wskh - 3 ns data sheet s14237ej2v0ds00 55 m m m m pd98412 cell buffer memory interface (read) t cyca t cycc t cyco t scdcc t scdca t hcacd t scdco t hcccd t hcocd address data (hi-z) (hi-z) (swclk) in cba17 - cba00 out cbd91 - cbd00 in/out cbcs1_b, cbcs0_b out cboe_b out cbwe_b out cell buffer memory interface (write) t cyca t dcocd t dcccw t dcdcw t fcwcd t dcdco t dcacw t dcocw t wcwl t dcwcc t dcwca t dcwco address valid (hi-z) (hi-z) (swclk) in cba17 - cba00 out cbd91 - cbd00, in/out cbcs1_b, cbcs0_b out cboe_b out cbwe_b out data sheet s14237ej2v0ds00 56 m m m m pd98412 (5) utopia interface (reception) parameter symbol test conditions min. typ. max. unit uclk cycle time t cyrk 20 125 ns uclk high-level width t wrkh 8ns uclk low-level width t wrkl 8ns uclk rise time t rkr 2ns uclk fall time t rkf 2ns uclk -? rxaddr output delay time t drka load capacitance 50 pf 114ns uclk -? rxenb_b output delay time t drke load capacitance 50 pf 114ns rxclav setup time (vs. uclk - ) t scark 4ns rxclav hold time (vs. uclk - ) t hrkca 1ns rxdata setup time (vs. uclk - ) t sdrk 4ns rxdata hold time (vs. uclk - ) t hrkd 1ns rxsoc setup time (vs. uclk - ) t sscrk 4ns rxsoc hold time (vs. uclk - ) t hrksc 1ns data sheet s14237ej2v0ds00 57 m m m m pd98412 utopia interface (reception) (n = 0 - 3) 8-bit mode uclkn in rxaddrn3 - rxaddrn0 out rxclavn in rxnbn_b out rxdatan7 - rxdatan0 in rxsocn in t cyrk t wrkh t rkr t rkf ?(h) p47 p48 h1 h2 h3 ?(h) ?(h) n+1 n+2 n t wrkl (hi-z) (hi-z) (hi-z) (hi-z) (hi-z) (hi-z) t drke t drke t hrksc t sscrk t sdrk t hrkd t hrksc t sscrk t drka t scark t hrkca t scark t hrkca 16-bit mode uclkn in rxaddrn4 - rxaddrn0 out rxclavn in rxenbn_b out rxdatan15 - rxdatan8 in rxsocn in rxdatan7 - rxdatan0 in ?f(h) n ?f(h) n+1 ?f(h) n+2 h1 h3 h2 p45 p46 p47 p48 h4 (hi-z) (hi-z) (hi-z) (hi-z) t drke t drke t hrksc t hrksc t drka t scark t hr kca t scark t hrkca t rkr t rkf t cyrk t wrkh t wrkl t sscrk t sdrk t sscrk t sdrk t hrkd t hrkd (hi-z) (hi-z) (hi-z) data sheet s14237ej2v0ds00 58 m m m m pd98412 (6) utopia interface (transmission) parameter symbol test conditions min. typ. max. unit uclk -? txaddr output delay time t dtka load capacitance 50 pf 114ns uclk -? txenb_b output delay time t dtke load capacitance 50 pf 114ns uclk -? txdata output delay time t dtkd load capacitance 50 pf 114ns uclk -? txdata float output delay time t ftkd load capacitance 50 pf 114ns uclk -? txsoc output delay time t dtksc load capacitance 50 pf 114ns uclk -? txsoc float output delay time t ftksc load capacitance 50 pf 114ns txclav setup time (vs. uclk - ) t scatk 4ns txclav hold time (vs. uclk - ) t htkca 1ns data sheet s14237ej2v0ds00 59 m m m m pd98412 utopia interface (transmission) (n = 0 - 3) 8-bit mode uclkn in txaddrn3 - txaddrn0 out txclavn in txenbn_b out txdatan7 - txdatan0 out txsocn out "f(h)" p48 h2 h3 h4 "f(h)" "f(h)" 01 n (hi-z) (hi-z) h1 (hi-z) (hi-z) t dtke t ftkd t ftksc t dtke t dtksc t dtkd t dtksc t dtka t scatk t htkca t scatk t htkca (hi-z) (hi-z) 16-bit mode uclkn in txaddrn4 - txaddrn0 out txclavn in txenbn_b out txdatan15 - txdatan8 out txsocn out txdatan7- txdatan0 out ?f(h) n ?f(h) 0 ?f(h) 1 h1 h3 h2 p47 p48 h4 (hi-z) (hi-z) (hi-z) (hi-z) t dtke t dtke t ftksc t dtksc t ftkd t dtkd t ftkd t dtkd t dtksc t dtka t scatk t htkca t scatk t htkca (hi-z) data sheet s14237ej2v0ds00 60 m m m m pd98412 3. package drawing ks e f item millimeters a d g h j k 40.00 0.20 40.00 0.20 0.80 1.40 0.15 0.60 0.10 b 39.60 0.15 c 39.60 0.15 f 1.27 (t.p.) e 1.585 n 0.25 min. m 0.30 s 2.0 r 2.0 t 3.0 x 22.73 w 22.73 p 0.10 q 3.0 l 0.75 0.15 a 1 23.00 max. a 2 23.00 max. + 0.30 - 0.20 + 0.20 - 0.10 s576n7-127-h6-1 z 0.20 y c 0.40 a q r index area y n detail of a part s t detail of b part (z) a 1 b a s aj ag ae ac aa wu r n l j g e c a ak ah af ad ab yv tpmkhfdb 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 x c j h g a b f m f m f a s l s m p b bw d a 2 data sheet s14237ej2v0ds00 61 m m m m pd98412 4. recommended soldering conditions solder this product under the following recommended conditions. for details of the recommended soldering conditions, refer to information document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended, consult nec. surface-mount type ? m m m m pd98412n7-h6: 576-pin tape bga (40 40) soldering method(s) soldering conditions recommended conditions symbol infrared reflow package peak temperature: 235 c, time: 30 sec max. (210 c min.), number of times: three times max., number of days: 7 note (after that, prebaking is necessary at 125 c for 10 hours) ir35-107-3 partial heating pin temperature: 300 c max. (per device side), time: 3 sec max. (per device side) - note number of days in storage after the dry pack has been opened. the storage conditions are at 25 c, 65% rh max. data sheet s14237ej2v0ds00 62 m m m m pd98412 [memo] data sheet s14237ej2v0ds00 63 m m m m pd98412 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. m m m m pd98412 neascot-x15 is a trademark of nec corporation. the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. ? no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. ? nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. ? descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. ? while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. ? nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7 98. 8 |
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