clk en mr function z l l divide zz h l hold q 0? x x h reset q 0? pin function clk differential clock inputs en synchronous enable mr master reset v bb reference output q 0, q 1 differential 2 outputs q 2, q 3 differential 4/6 outputs divsel frequency select input the sy10/100el38/l are low skew 2, 4/6 clock generation chips designed explicitly for low skew clock generation applications. the internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. the devices can be driven by either a differential or single-ended ecl or, if positive power supplies are used, pecl input signal. in addition, by using the v bb output, a sinusoidal source can be ac- coupled into the device. if a single-ended input is to be used, the v bb output should be connected to the clk input and bypassed to ground via a 0.01 f capacitor. the v bb output is designed to act as the switching reference for the input of the el38/l under single-ended input conditions. as a result, this pin can only source/ sink up to 0.5ma of current. the common enable (en) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the low state. this avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. an internal runt pulse could lead to losing synchronization between the internal divider stages. the internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. the phase_out output will go high for one clock cycle whenever the 2 and the 4/6 outputs are both transitioning from a low to a high. this output allows for clock synchronization within the system. upon start-up, the internal flip-flops will attain a random state; the master reset (mr) input allows for the synchronization of the internal dividers, as well as for multiple el38/ls in a system. pin configuration/block diagram 3.3v and 5v power supply options 50ps output-to-output skew synchronous enable/disable master reset for synchronization internal 75k ? input pull-down resistors available in 20-pin soic package truth table pin names description features rev.: e amendment: /0 issue date: august, 1998 5v/3.3v 2, 4/6 clock generation chip note: z = low-to-high transition zz = high-to-low transition divsel q 2, q 3 outputs 0 divide by 4 1 divide by 6 clockworks sy10el38/l sy100el38/l final v cc q 0 q 0 q 1 q 1 q 2 q 2 q 3 q 3 v ee v cc en divsel clk clk v bb mr v cc phased_out 12345678910 20 19 18 17 16 15 14 13 12 11 phased_out top view soic z20-1 1
2 clockworks sy10el38/l sy100el38/l micrel t a = -40 ct a = 0 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. min. typ. max. unit f max maximum toggle frequency 1000 1000 1000 1000 mhz t plh propagation delay to output ps t phl clk ? output (diff.) 950 1150 950 1150 970 1170 1050 1250 clk ? output (s.e.) 900 1200 900 1200 920 1220 1000 1300 mr ? output 600 900 600 900 600 900 600 900 t skew within-device skew (2) q 0 q 3 50 50 50 50 ps all 75 75 75 75 part-to-part q 0 q 3 (diff.) 200 200 200 200 all 240 240 240 240 t s set-up time en ? clk 300 150 150 150 150 ps divsel ? clk 300 t h hold time clk ? en 400 150 400 150 400 150 400 150 ps clk ? divsel 400 200 400 200 400 200 400 200 v pp minimum input swing (3) clk 250 250 250 250 mv v cmr common mode range (4) clk 1.3 0.4 1.4 0.4 1.4 0.4 1.4 0.4 v t rr reset recovery time 100 100 100 100 ps t pw minimum pulse width clk 800 800 800 800 ps mr 700 700 700 700 t r output rise/fall times q 280 550 280 550 280 550 280 550 ps t f (20% 80%) t a = 40 ct a = 0 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. min. typ. max. unit i ee power supply current ma 10el 35 50 65 35 65 35 65 35 65 100el 35 50 65 35 65 35 65 35 75 v bb output reference v voltage 10el -1.43 -1.30 -1.38 -1.27 -1.35 -1.25 -1.31 -1.19 100el -1.38 -1.26 -1.38 -1.26 -1.38 -1.26 -1.38 -1.26 i ih input high current 150 150 150 150 a dc electrical characteristics (1) v ee = v ee (min.) to v ee (max.); v cc = gnd note: 1. parametric values specified at: 5 volt power supply range 100el38 series: -4.2v to -5.5v. 10el38 series -4.75v to -5.5v. 3 volt power supply range 10/100el38l series: -3.0v to -3.8v. ac electrical characteristics (1) v ee = v ee (min.) to v ee (max.); v cc = gnd notes: 1. parametric values specified at: 5 volt power supply range 100el38 series: -4.2v to -5.5v. 10el38 series -4.75v to -5.5v. 3 volt power supply range 10/100el38l series: -3.0v to -3.8v. 2. skew is measured between outputs under identical transitions. 3. minimum input swing for which ac parameters are guaranteed. the device will function reliably with differential inputs down to 100mv. 4. the cmr range is referenced to the most positive side of the differential input signal. normal operation is obtained if the high level falls within the specified range and the peak-to-peak voltage lies between v pp min. and 1v. the lower end of the cmr range varies 1:1 with v ee . the numbers in the spec table assume a nominal v ee = 3.3v. note for pecl operation, the v cmr (min) will be fixed at 3.3v iv cmr (min)i.
3 clockworks sy10el38/l sy100el38/l micrel logic diagram timing diagrams clk clk en r mr divsel q 0 r r phase out logic r q 0 q 1 q 1 q 2 q 2 q 3 q 3 phased_out phased_out ( 2) ( 4/6) clk q ( 2) q ( 4) q ( 6) phase_out( 4) phase_out( 6) product ordering code ordering package operating v ee range code type range (v) sy10el38zc z20-1 commercial -4.75 to -5.5 sy10el38zctr z20-1 commercial -4.75 to -5.5 sy100el38zc z20-1 commercial -4.2 to -5.5 sy100el38zctr z20-1 commercial -4.2 to -5.5 5v ordering package operating v ee range code type range (v) sy10el38lzc z20-1 commercial -3.0 to -3.8 sy10el38lzctr z20-1 commercial -3.0 to -3.8 sy100el38lzc z20-1 commercial -3.0 to -3.8 sy100el38lzctr z20-1 commercial -3.0 to -3.8 3.3v
4 clockworks sy10el38/l sy100el38/l micrel 20 lead soic .300" wide (z20-1) rev. 03 micrel-synergy 3250 scott boulevard santa clara ca 95054 usa tel + 1 (408) 980-9191 fax + 1 (408) 914-7878 web http://www.micrel.com this information is believed to be accurate and reliable, however no responsibility is assumed by micrel for its use nor for an y infringement of patents or other rights of third parties resulting from its use. no license is granted by implication or otherwise under any patent or pat ent right of micrel inc. ? 2000 micrel incorporated
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