1/6 preliminary data october 2000 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. STW40NS15 n-channel 150v - 0.042 w - 40a to-247 mesh overlay? mosfet i nternal schematic diagram n typical r ds (on) = 0.042 w n extremely high dv/dt capability n very low intrinsic capacitances n gate charge minimized description this powermos mosfet is designed using the companys consolidated strip layout-based mesh overlay ? process. this technology matches and improves the performances compared with standard parts from various sources. applications n high current switching n uninterruptible power supply (ups) n primaryswitch in isolated dc-dc converters absolute maximum ratings (?)pulse width limited by safe operating area type v dss r ds(on) i d STW40NS15 150 v <0.052 w 40a symbol parameter value unit v ds drain-source voltage (v gs = 0) 150 v v dgr drain-gate voltage (r gs = 20 k w ) 150 v v gs gate- source voltage 20 v i d drain current (continuos) at t c = 25c 40 a i d drain current (continuos) at t c = 100c 25 a i dm (1) drain current (pulsed) 160 a p tot total dissipation at t c = 25c 180 w derating factor 0.933 w/c dv/dt peak diode recovery voltage slope 9 v/ns t stg storage temperature C65 to 175 c t j max. operating junction temperature 175 c 1 2 3 to-247
STW40NS15 2/6 thermal data avalanche characteristics electrical characteristics (tcase = 25 c unless otherwise specified) off on (1) dynamic rthj-case thermal resistance junction-case max 0.83 c/w rthj-amb thermal resistance junction-ambient max 62.5 c/w rthc-sink thermal resistance case-sink typ 0.5 c/w t l maximum lead temperature for soldering purpose 300 c symbol parameter max value unit i ar avalanche current, repetitive or not-repetitive (pulse width limited by t j max) 40 a e as single pulse avalanche energy (starting t j = 25 c, i d = i ar , v dd = 50 v) 500 mj symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage i d = 250 a, v gs = 0 150 v i dss zero gate voltage drain current (v gs = 0) v ds = max rating 1a v ds = max rating, t c = 125 c 10 a i gss gate-body leakage current (v ds = 0) v gs = 20v 100 na symbol parameter test conditions min. typ. max. unit v gs(th) gate threshold voltage v ds = v gs , i d = 250a 234v r ds(on) static drain-source on resistance v gs = 10v, i d = 40 a 0.044 0.052 w i d(on) on state drain current v ds > i d(on) x r ds(on)max, v gs =10v 40 a symbol parameter test conditions min. typ. max. unit g fs (1) forward transconductance v ds > i d(on) x r ds(on)max, i d = 20a 20 s c iss input capacitance v ds = 25v, f = 1 mhz, v gs = 0 2400 pf c oss output capacitance 380 pf c rss reverse transfer capacitance 160 pf
3/6 STW40NS15 electrical characteristics (continued) switching on switching off source drain diode note: 1. pulsed: pulse duration = 300 s, duty cycle 1.5 %. 2. pulse width limited by safe operating area. symbol parameter test conditions min. typ. max. unit t d(on) turn-on delay time rise time v dd = 75v, i d = 20a r g = 4.7 w , v gs = 10v (see test circuit, figure 3) 25 ns t r 45 ns q g total gate charge v dd = 120v, i d = 40a, v gs = 10v 100 110 nc q gs gate-source charge 17 nc q gd gate-drain charge 47 nc symbol parameter test conditions min. typ. max. unit t d(off) turn-off delay time v dd = 75v, i d = 20a r g =4.7 w , v gs = 10v (see test circuit, figure 3) 85 t f fall time t r(voff) off-voltage rise time v clamp = 120v, i d = 20 a, r g =4.7 w, v gs = 10v (see test circuit, figure 5) 47 ns t f fall time 35 ns t c cross-over time 70 ns symbol parameter test conditions min. typ. max. unit i sd source-drain current 40 a i sdm (2) source-drain current (pulsed) 160 a v sd (1) forward on voltage i sd = 40a, v gs = 0 1.5 v t rr reverse recovery time i sd = 40a, di/dt = 100a/s, v dd = 50v, t j = 150c (see test circuit, figure 5) 270 ns q rr reverse recovery charge 200 nc i rrm reverse recovery current 1.5 a
STW40NS15 4/6 fig. 5: test circuit for inductive load switching and diode recovery times fig. 4: gate charge test circuit fig. 2: unclamped inductive waveform fig. 1: unclamped inductive load test circuit fig. 3: switching times test circuit for resistive load
5/6 STW40NS15 dim. mm inch min. typ. max. min. typ. max. a 4.7 5.3 0.185 0.209 d 2.2 2.6 0.087 0.102 e 0.4 0.8 0.016 0.031 f 1 1.4 0.039 0.055 f3 2 2.4 0.079 0.094 f4 3 3.4 0.118 0.134 g 10.9 0.429 h 15.3 15.9 0.602 0.626 l 19.7 20.3 0.776 0.779 l3 14.2 14.8 0.559 0.582 l4 34.6 1.362 l5 5.5 0.217 m 2 3 0.079 0.118 p025p to-247 mechanical data
STW40NS15 6/6 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsib ility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectroni cs. specifi cation mentio ned in this publication are subject to change without notice. this publication supersedes and replaces all in formation previou sly supplied. stmicroel ectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectron ics. the st logo is a trademark of stmicroelectronics ? 2000 stmicroelectronics C pr inted in italy C all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malay sia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com
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