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september 2001 copyright ? alliance semiconductor. all rights reserved. ? as6wa5128 3.0v to 3.6v 512k 8 intelliwatt? low-power cmos sram 9/21/01; v.1.2 alliance semiconductor p. 1 of 9 features ? as6wa5128 intelliwatt? active power circuitry industrial and commercial temperature ranges available organization: 524,288 words 8 bits 3.0v to 3.6v at 55 ns low power consumption: active - 144 mw at 3.6v and 55 ns low power consumption: standby - 72 w max at 3.6v 1.5v data retention equal access and cycle times easy memory expansion with cs , oe inputs smallest footprint packages - 36(48)-ball fbga esd protection 2000 volts latch-up current 200 ma logic block diagram sense amp input buffer a10 a11 a12 a13 a14 a15 a16 i/o1 i/o8 oe cs we row decoder control circuit a9 a0 a1 a2 a3 a4 a5 a6 a7 v cc gnd a8 column decoder 512k 8 array (4,194,304) 36(48)-csp/bga package (shading indicates no ball) 123456 aa 0 a 1 nc a 3 a 6 a 8 bi/o 5 a 2 we a 4 a 7 i/o 1 ci/o 6 nc a 5 i/o 2 dv ss v cc ev cc v ss fi/o 7 a 18 a 17 i/o 3 gi/o 8 oe cs a 16 a 15 i/o 4 ha 9 a 10 a 11 a 12 a 13 a 14 selection guide product v cc range speed (ns) power dissipation min (v) typ 2 (v) max (v) operating (i cc )standby (i sb1 ) max (ma) max ( a) as6wa5128 3.0 3.3 3.6 55 2 20
? as6wa5128 9/21/01; v.1.2 alliance semiconductor p. 2 of 9 functional description the as6wa5128 is a low-power cmos 4,194,304-bit static random access memory (sram) device organized as 524,288 words 8 bits. it is designed for memory applications where slow data access, low power, and simple interfacing are desired. equal address access and cycle times (t aa , t rc , t wc ) of 55 ns are ideal for low-power applications. active high and low chip selects (cs ) permit easy memory expansion with multiple-bank memory systems. when cs is high, the device enters standby mode: the as6wa5128 is guaranteed not to exceed 72 w power consumption at 3.6v and 55ns. the device also returns data when v cc is reduced to 1.5v for even lower power consumption. a write cycle is accomplished by asserting write enable (we ) and chip select (cs ) low. data on the input pins i/o1?i/o8 is written on the rising edge of we (write cycle 1) or cs (write cycle 2). to avoid bus contention, external devices should drive i/ o pins only after outputs have been disabled with output enable (oe ) or write enable (we ). a read cycle is accomplished by asserting output enable (oe ), chip select (cs ), with write enable (we ) high. the chip drives i/ o pins with the data word referenced by the input address. when either chip select or output enable is inactive, or write enabl e is active, output drivers stay in high-impedance mode. all chip inputs and outputs are cmos-compatible, and operation is from a single 3.0 to 3.6v supply. the device is available in the jedec standard 36(48)-ball fbga package. absolute maximum ratings note: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional oper- ation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. truth table key: x = don?t care, l = low, h = high. parameter device symbol min max unit vol tag e o n v cc relative to v ss v tin ?0.5 v cc + 0.5 v voltage on any i/o pin relative to gnd v ti/o ?0.5 v power dissipation p d ?1.0w storage temperature (plastic) t stg ?65 +150 c te m p e r a t u r e w i t h v cc applied t bias ?55 +125 c dc output current (low) i out ?20ma cs we oe supply current i/o1?i/o8 mode hxxi sb high z standby (i sb ) lxxi sb high z standby (i sb ) lhhi cc high z output disable (i cc ) lhli cc d out read (i cc ) llxi cc d in write (i cc )
? as6wa5128 9/21/01; v.1.2 alliance semiconductor p. 3 of 9 recommended operating condition (over the operating range) capacitance (f = 1 mhz, t a = room temperature, v cc = nominal) parameter description test conditions min max unit v oh output high voltage i oh = ?2.1ma v cc = 3.0 - 3.6v 2.4 v v ol output low voltage i ol = 2.1ma v cc = 3.0 - 3.6v 0.4 v v ih input high voltage v cc = 3.0 - 3.6v 2.2 v cc + 0.5 v v il input low voltage v cc = 3.0 - 3.6v ?0.5 0.8 v i ix input load current gnd < v in < v cc ?1 +1 a i oz output load current gnd < v o < v cc ; outputs high z ?1 +1 a i cc v cc operating supply current cs = v il , i out = 0ma, f = 0, v in = v il or v ih v cc = 3.6v 2 ma i cc1 @ 1mhz average v cc operating supply current at 1 mhz cs < 0.2v, v in < 0.2v, or v in > v cc ? 0.2v, f = 1 ms v cc = 3.6v 5 ma i cc2 average v cc operating supply current cs v il , v in = v il or v ih , f = f max v cc = 3.6v 40 ma i sb cs power down current; ttl inputs cs > v ih , other inputs = 0v ? v cc v cc = 3.6v 150 a i sb1 cs power down current; cmos inputs cs > v cc ? 0.2v, other inputs = 0v ? v cc , f = f max v cc = 3.6v 20 a parameter symbol signals test conditions max unit input capacitance c in a, cs , we , oe v in = 0v 5 pf i/o capacitance c i/o i/o v in = v out = 0v 7 pf
? as6wa5128 9/21/01; v.1.2 alliance semiconductor p. 4 of 9 read cycle (over the operating range) key to switching waveforms read waveform 1 (address controlled) read waveform 2 (cs , oe controlled) parameter symbol min max unit notes read cycle time t rc 55 ? ns address access time t aa ?55ns3 chip select (cs ) access time t acs ?55ns3 output enable (oe ) access time t oe ?25ns output hold from address change t oh 10 ? ns 5 cs low to output in low z t clz 10 ? ns 4, 5 cs high to output in high z t chz 020ns4, 5 oe low to output in low z t olz 5 ? ns 4, 5 oe high to output in high z t ohz 020ns4, 5 power up time t pu 0 ? ns 4, 5 power down time t pd ?55ns4, 5 undefined/don?t care falling input rising input t oh t aa t rc t oh d out address data valid previous data valid current supply oe d out t oe t olz t ace t chz t clz t pu t pd i cc i sb 50% 50% t ohz data valid t rc1 cs
? as6wa5128 9/21/01; v.1.2 alliance semiconductor p. 5 of 9 write cycle (over the operating range) write waveform 1 (we controlled)
write waveform 2 (cs controlled)
parameter symbol min max unit notes write cycle time t wc 55 ? ns chip select to write end t cw 40 ? ns 12 address setup to write end t aw 40 ? ns address setup time t as 0?ns12 write pulse width t wp 35 ? ns write recovery time t wr 0?ns address hold from end of write t ah 0?ns data valid to write end t dw 25 ? ns data hold time t dh 0 ? ns 4, 5 write enable to output in high z t wz 020ns4, 5 output active from write end t ow 5 ? ns 4, 5 t aw t ah t wc address we d out t dh t ow t dw t wz t wp t as data valid d in t wr t aw address cs we d out t cw t wp t dw t dh t ah t wz t wc t as data valid d in t wr
? as6wa5128 9/21/01; v.1.2 alliance semiconductor p. 6 of 9 data retention characteristics (over the operating range) data retention waveform ac test loads and waveforms notes 1during v cc power-up, a pull-up resistor to v cc on cs is required to meet i sb specification. 2 this parameter is sampled, but not 100% tested. 3 for test conditions, see ac test conditions . 4t clz and t chz are specified with c l = 5pf as in figure c. transition is measured 500 mv from steady-state voltage. 5 this parameter is guaranteed, but not tested. 6we is high for read cycle. 7cs and oe are low for read cycle. 8 address valid prior to or coincident with cs transition low. 9 all read cycle timings are referenced from the last valid address to the first transitioning address. 10 cs or we must be high during address transitions. either cs or we asserting high terminates a write cycle. 11 all write cycle timings are referenced from the last valid address to the first transitioning address. 12 n/a. 13 1.5v data retention applies to commercial and industrial temperature range operations. 14 c = 30pf, except at high z and low z parameters, where c = 5pf. parameter symbol test conditions min max unit v cc for data retention v dr v cc = 1.5v cs v cc ? 0.1v or v in v cc ? 0.1v or v in 0.1v 1.5v - v data retention current i ccdr ?10 a chip deselect to data retention time t cdr 0? operation recovery time t r t rc ?ns parameters v cc = 3.6v unit r1 1523 ohms r2 1142 ohms r th 476 ohms v th 1.4v volts v cc cs t r t cdr data retention mode v cc v cc v dr 1.5v v ih v ih v dr v cc r1 r2 output 30 pf including jig and scope (a) v cc r1 r2 output 5 pf all input pulses (b) 10% 90% 10% 90% gnd v cc ty p < 5 ns (c) thevenin equivalent: output r th v th including jig and scope
? as6wa5128 9/21/01; v.1.2 alliance semiconductor p. 7 of 9 typical dc and ac characteristics v cc = v cc typ supply voltage (v) 1.7 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i cc normalized supply current supply voltage (v) 0.0 0.25 0.5 0.75 1.0 normalized t aa normalized access time vs. supply voltage vs. supply voltage ambient temperature (c) ? 55 105 25 0.5 1.0 0.0 1.5 2.0 2.5 normalized i sb2 normalized standby current vs. ambient temperature supply voltage (v) 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i sb normalized standby current vs. supply voltage i sb2 supply voltage (v) 0.10 0.50 1.0 1.5 normalized i cc normalized i cc vs. cycle time 2.2 2.7 3.2 3.7 1.7 2.2 2.7 3.2 3.7 t a = 25 c 3.0 ? 0.5 v in = v cc typ 1 5 10 15 11.9 2.8 3.7 v in = v cc typ t a = 25 c v in = 3.6v t a = 25 c v in = v cc typ t a = 25 c
? as6wa5128 9/21/01; v.1.2 alliance semiconductor p. 8 of 9 package diagrams and dimensions minimum typical maximum a?0.75? b 6.90 7.00 7.10 b1 ? 3.75 ? c 10.90 11.00 11.10 c1 ? 5.25 ? d 0.30 0.35 0.40 e??1.20 e1 ? 0.68 ? e2 0.22 0.25 0.27 y??0.08 notes 1. bump counts: 36(48) (8 row 6 column). 2. pitch: (x,y) = 0.75 mm 0.75 mm (typ). 3. units: millimeters. 4. all tolerance are 0.050 unless otherwise specified. 5. typ: typical. 6. y is coplanarity: 0.08 (max). 36(48)-ball fbga bottom view top view 1 2 3 4 5 6 a b c d e f g h a b1 a1 c1 ball #a1 ball #a1 index sram die c elastomer b side view detail view e2 e e1 d die die e e2 a y 0.3/typ
? as6wa5128 9/21/01; v.1.2 alliance semiconductor p. 9 of 9 ? copyright alliance semiconductor corporation. all rights reserved. our three-point logo, our name and intelliwatt are tradema rks or registered trademarks of alliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make changes to this document and its products at any time withou t notice. alliance assumes no responsibility for any errors that may appear in this document. the data contained herein represents alliance's best data and/or estimates at the time of issuance. alliance reserves the right to chang e or correct this data at any time, without notice. if the product described herein is under development, significant changes to these specifications are possible. the information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpo se, merchantability, or infringement of any intellectual property rights, except as express agreed to in alliance's terms and conditions of sale (which are available from alliance). all sales of alliance products are made exclusivel y according to alliance's terms and conditions of sale. the purchase of products from alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of alliance or third parties. alliance does not authorize its products for use as critical components in life- supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and t he inclusion of alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify alliance against all claims arising from such use. ordering codes part numbering system speed (ns) ordering code package type operating range 55 as6wa5128-bc 48-ball fine pitch bga commercial 55 AS6WA5128-BI 48-ball fine pitch bga industrial as6wa 5128 b c, i sram intelliwatt? prefix device number package: b: csp/bga temperature range: c: commercial: 0 c to 70 c i: industrial: ? 40c to 85 c

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