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1 features ? 16-megabit (x16) flash and 2-megabit/4-megabit sram 2.7v to 3.3v operating voltage low operating power ? 40 ma operating current (maximum) ? 50 a standby current (maximum) industrial temperature range flash 2.7v to 3.3v read/write access time ? 70 ns sector erase architecture ? thirty-one 32k word (64k byte) sectors with individual write lockout ? eight 4k word (8k byte) sectors with individual write lockout fast word program time ? 20 s fast sector erase time ? 300 ms suspend/resume feature for erase and program ? supports reading and programming from any sector by suspending erase of a different sector ? supports reading any word by suspending programming of any other word low-power operation ?30 ma active ? 10 a standby data polling, toggle bit, ready/busy for end of program detection vpp pin for write protection and accelerated program/erase operations reset input for device initialization sector lockdown support top boot block configuration 128-bit protection register sram 2-megabit (128k x 16)/4-megabit (256k x 16) 2.7v to 3.3v v cc operating voltage 70 ns access time fully static operation and tri-state output 1.2v (min) data retention device number flash boot location flash plane architecture sram configuration at52br1662t top 16m 128k x 16 at52br1664t top 16m 256k x 16 16-megabit flash + 2-megabit/ 4-megabit sram stack memory at52br1662t at52br1664t rev. 2212a?11/01
2 at52br1662t/1664t 2212a?11/01 cbga top view pin configurations a14 a9 i/o11 a6 a0 a b c d e f g h 3 45678910 a15 a10 a19 soe a7 a4 a13 i/o15 i/o13 i/o12 i/o9 a3 ce a12 swe i/o6 scs2 i/o10 i/o8 a2 gnd gnd i/o14 i/o4 svcc i/o2 i/o0 a1 oe nc i/o7 i/o5 vcc i/o3 i/o1 scs1 nc nc a16 we sgnd nc slb a18 nc a11 a8 rdy busy reset vpp sub a17 a5 nc nc nc nc nc nc nc nc 1 2 11 12 pin name function a0 - a15 flash/sram common address input for 2m sram a0 - a16 flash/sram common address input for 4m sram a17 - a19 flash address input ce flash chip enable oe /soe flash/sram, output enable we /swe flash/sram, write enable vcc flash power supply vpp optional flash power supply for faster program/erase operations i/o0-i/o15 data inputs/outputs scs1 , scs2 sram chip select rdy/busy flash ready/busy output svcc sram power supply gnd/sgnd flash/sram gnd sub sram upper byte slb sram lower byte nc no connect reset flash reset
3 at52br1662t/1664t 2212a ? 11/01 description the at52br1662t combines a single plane 16-megabit flash and a 2-megabit sram in a stacked 66-ball cbga package; while the at52br1664t combines a single plane 16-megabit flash and a 4-megabit sram in a stacked 66-ball cbga package. both devices operate at 2.7v to 3.3 in the industrial temperature range. block diagram absolute maximum ratings temperature under bias .................................. -40 c to +85 c *notice: stresses beyond those listed under ? absolute maximum ratings ? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -55 c to +150 c all input voltages except v pp and reset (including nc pins) with respect to ground .....................................-0.2v to +3.3v voltage on v pp with respect to ground ..................................-0.2v to + 6.25v voltage on reset with respect to ground ...................................-0.2v to +13.5v all output voltages with respect to ground .....................................-0.2v to +0.2v flash sram address data reset ce rdy/busy scs1 we oe swe soe dc and ac operating range at52br1662t/1664t-70, -90 operating temperature (case) industrial -40 c - 85 c v cc power supply 2.7v to 3.3v
4 at52br1662t/1664t 2212a ? 11/01 16-megabit flash memory block diagram identifier register status register data comparator output multiplexer output buffer input buffer command register data register y-gating write state machine program/erase voltage switch ce we oe reset byte rdy/busy vpp vcc gnd y-decoder x-decoder input buffer address latch i/o0 - i/o15 a0 - a19 main memory
5 at52br1662t/1664t 2212a ? 11/01 16-megabit flash description the 16-megabit flash memory is organized as 1,048,576 words of 16 bits each. the x16 data appears on i/o0 - i/o15. the memory is divided into 39 sectors for erase operations. the device has ce and oe control signals to avoid any bus contention. this device can be read or reprogrammed using a single 2.7v power supply, making it ideally suited for in-system programming. the device powers on in the read mode. command sequences are used to place the device in other operation modes such as program and erase. the device has the capability to protect the data in any sector. (see ? sector lockdown ? section.) to increase the flexibility of the device, it contains an erase suspend and program suspend feature. this feature will put the erase or program on hold for any amount of time and let the user read data from or program data to any of the remaining sectors within the memory. the end of a program or an erase cycle is detected by the ready/busy pin, data polling or by the toggle bit. the vpp pin provides data protection and faster programming. when the v pp input is below 0.8v, the program and erase functions are inhibited. when v pp is at 1.65v or above, normal program and erase operations can be performed. with v pp at 5.0v or 12.0v, the program and erase operations are accelerated. a six-byte command (enter single pulse program mode) sequence to remove the requirement of entering the three-byte program sequence is offered to further improve programming time. after entering the six-byte code, only single pulses on the write control lines are required for writing into the device. this mode (single pulse word program) is exited by powering down the device, or by pulsing the reset pin low for a minimum of 500 ns and then bringing it back to v cc . erase, erase suspend/resume, and program suspend/resume commands will not work while in this mode; if entered, they will result in data being programmed into the device. it is not recommended that the six-byte code reside in the software of the final product but only exist in external programming code. device operation read: the 16-megabit flash is accessed like an eprom. when ce and oe are low and we is high, the data stored at the memory location determined by the address pins are asserted on the outputs. the outputs are put in the high-impedance state whenever ce or oe is high. this dual-line control gives designers flexibility in preventing bus contention. command sequences: when the device is first powered on, it will be reset to the read or standby mode, depending upon the state of the control line inputs. in order to perform other device functions, a series of command sequences are entered into the device. the command sequences are shown in the ? command definition in hex ? table on page 13 (i/o8 - i/o15 are don ? t care inputs for the command codes). the command sequences are written by applying a low pulse on the we or ce input with ce or we low (respectively) and oe high. the address is latched on the falling edge of ce or we , whichever occurs last. the data is latched by the first rising edge of ce or we . standard microprocessor write timings are used. the address locations used in the command sequences are not affected by entering the command sequences. reset: a reset input pin is provided to ease some system applications. when reset is at a logic high level, the device is in its standard operating mode. a low level on the reset input halts the present device operation and puts the outputs of the device in a high-impedance state. when a high level is reasserted on the reset pin, the device returns to the read or standby mode, depending upon the state of the control inputs. erasure: before a word can be reprogrammed, it must be erased. the erased state of memory bits is a logical ? 1 ? . the entire device can be erased by using the chip erase com- mand or individual sectors can be erased by using the sector erase command.
6 at52br1662t/1664t 2212a ? 11/01 chip erase: the entire device can be erased at one time by using the six-byte chip erase software code. after the chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. the maximum time to erase the chip is t ec . if the sector lockdown has been enabled, the chip erase will not erase the data in the sector that has been locked out; it will erase only the unprotected sectors. after the chip erase, the device will return to the read or standby mode. sector erase: as an alternative to a full chip erase, the device is organized into 39 sec- tors (sa0 - sa38) that can be individually erased. the sector erase command is a six-bus cycle operation. the sector address is latched on the falling we edge of the sixth cycle while the 30h data input command is latched on the rising edge of we . the sector erase starts after the rising edge of we of the sixth cycle. the erase operation is internally controlled; it will automatically time to completion. the maximum time to erase a sector is t sec . when the sec- tor programming lockdown feature is not enabled, the sector will erase (from the same sector erase command). an attempt to erase a sector that has been protected will result in the oper- ation terminating in 2 s. word programming: once a memory block is erased, it is programmed (to a logical ? 0 ? ) on a word-by-word basis. programming is accomplished via the internal device command reg- ister and is a four-bus cycle operation. the device will automatically generate the required internal program pulses. any commands written to the chip during the embedded programming cycle will be ignored. if a hardware reset happens during programming, the data at the location being programmed will be corrupted. please note that a data ? 0 ? cannot be programmed back to a ? 1 ? ; only erase operations can convert ? 0 ? s to ? 1 ? s. programming is completed after the specified t bp cycle time. the data polling feature or the toggle bit feature may be used to indicate the end of a program cycle. if the erase/program status bit is a ? 1 ? , the device was not able to verify that the erase or program operation was performed successfully. vpp pin: the circuitry of the 16-megabit flash is designed so that the device can be pro- grammed or erased from the v cc power supply or from the vpp input pin. when v pp is greater than 1.65v and less than or equal to the vcc pin, the device selects the v cc supply for pro- gramming and erase operations. when the vpp pin is greater than the v cc supply, the device will select the v pp input as the power supply for programming and erase operations. the device will allow for some variations between the v pp input and the v cc power supply in its selection of v cc or v pp for program or erase operations. if the vpp pin is within 0.3v of v cc for 2.7v < v cc < 3.6v, then the program or erase operations will use v cc and disregard the v pp input signal. when the v pp signal is used for program and erase operations, the v pp must be in the 5v 0.5v or 12v 0.5v range to ensure proper operation. the v pp pin cannot be left floating. program/erase status: the device provides several bits to determine the status of a program or erase operation: i/o2, i/o3, i/o5, i/o6 and i/o7. the ? status bit table ? on page 12 and the following four sections describe the function of these bits. to provide greater flexibility for system designers, the 16-megabit flash contains a programmable configuration register. the configuration register allows the user to specify the status bit operation. the configuration register can be set to one of two different values, ? 00 ? or ? 01 ? . if the configuration register is set to ? 00 ? , the part will automatically return to the read mode after a successful program or erase operation. if the configuration register is set to a ? 01 ? , a product id exit command must be given after a successful program or erase operation before the part will return to the read mode. it is important to note that whether the configuration register is set to a ? 00 ? or to a ? 01 ? , any unsuccessful program or erase operation requires using the product id exit command to return the device to read mode. the default value (after power-up) for the configuration regis- ter is ? 00 ? . using the four-bus cycle set configuration register command as shown in the ? command definition in hex ? table on page 13, the value of the configuration register can be
7 at52br1662t/1664t 2212a ? 11/01 changed. voltages applied to the reset pin will not alter the value of the configuration regis- ter. the value of the configuration register will affect the operation of the i/o7 status bit as described below. data polling: the 16-megabit features data polling to indicate the end of a program cycle. if the status configuration register is set to a ? 00 ? , during a program cycle an attempted read of the last word loaded will result in the complement of the loaded data on i/o7. once the pro- gram cycle has been completed, true data is valid on all outputs and the next cycle may begin. during a chip or sector erase operation, an attempt to read the device will give a ? 0 ? on i/o7. once the program or erase cycle has completed, true data will be read from the device. data polling may begin at any time during the program cycle. please see ? status bit table ? on page 12 for more details. if the status bit configuration register is set to a ? 01 ? , the i/o7 status bit will be low while the device is actively programming or erasing data. i/o7 will go high when the device has com- pleted a program or erase operation. once i/o7 has gone high, status information on the other pins can be checked. the data polling status bit must be used in conjunction with the erase/program and v pp status bit as shown in the algorithm in figures 1 and 2 on page 10. toggle bit: in addition to data polling, the 16-megabit flash provides another method for determining the end of a program or erase cycle. during a program or erase operation, suc- cessive attempts to read data from the memory will result in i/o6 toggling between one and zero. once the program cycle has completed, i/o6 will stop toggling and valid data will be read. examining the toggle bit may begin at any time during a program cycle. please see ? sta- tus bit table ? on page 12 for more details. the toggle bit status bit should be used in conjunction with the erase/program and v pp status bit as shown in the algorithm in figures 3 and 4 on page 11. erase/program status bit: the device offers a status bit on i/o5, which indicates whether the program or erase operation has exceeded a specified internal pulse count limit. if the status bit is a ? 1 ? , the device is unable to verify that an erase or a word program operation has been successfully performed. the device may also output a ? 1 ? on i/o5 if the system tries to program a ? 1 ? to a location that was previously programmed to a ? 0 ? . only an erase opera- tion can change a ? 0 ? back to a ? 1 ? . if a program (sector erase) command is issued to a protected sector, the protected sector will not be programmed (erased). the device will go to a status read mode and the i/o5 status bit will be set high, indicating the program (erase) opera- tion did not complete as requested. once the erase/program status bit has been set to a ? 1 ? , the system must write the product id exit command to return to the read mode. the erase/program status bit is a ? 0 ? while the erase or program operation is still in progress. please see ? status bit table ? on page 12 for more details. v pp status bit: the 16-megabit flash provides a status bit on i/o3, which provides infor- mation regarding the voltage level of the vpp pin. during a program or erase operation, if the voltage on the vpp pin is not high enough to perform the desired operation successfully, the i/o3 status bit will be a ? 1 ? . once the v pp status bit has been set to a ? 1 ? , the system must write the product id exit command to return to the read mode. on the other hand, if the volt- age level is high enough to perform a program or erase operation successfully, the v pp status bit will output a ? 0 ? . please see ? status bit table ? on page 12 for more details. sector lockdown: each sector has a programming lockdown feature. this feature pre- vents programming of data in the designated sectors once the feature has been enabled. these sectors can contain secure code that is used to bring up the system. enabling the lock- down feature will allow the boot code to stay in the device while data in the rest of the device is updated. this feature does not have to be activated; any sector ? s usage as a write-protected region is optional to the user.
8 at52br1662t/1664t 2212a ? 11/01 at power-up or reset, all sectors are unlocked. to activate the lockdown for a specific sector, the six-bus cycle sector lockdown command must be issued. once a sector has been locked down, the contents of the sector is read-only and cannot be erased or programmed. sector lockdown detection: a software method is available to determine if program- ming of a sector is locked down. when the device is in the software product identification mode (see ? software product identification entry/exit ? sections on page 23), a read from address location 00002h within a sector will show if programming the sector is locked down. if the data on i/o0 is low, the sector can be programmed; if the data on i/o0 is high, the program lockdown feature has been enabled and the sector cannot be programmed. the software product identification exit code should be used to return to standard operation. sector lockdown override: the only way to unlock a sector that is locked down is through reset or power-up cycles. after power-up or reset, the content of a sector that is locked down can be erased and reprogrammed. erase suspend/erase resume: the erase suspend command allows the system to interrupt a sector erase or chip erase operation and then program or read data from a different sector within the memory. after the erase suspend command is given, the device requires a maximum time of 15 s to suspend the erase operation. after the erase operation has been suspended, the system can then read data or program data to any other sector within the device. an address is not required during the erase suspend command. during a sector erase suspend, another sector cannot be erased. to resume the sector erase operation, the system must write the erase resume command. the erase resume command is a one-bus cycle command. the device also supports an erase suspend during a complete chip erase. while the chip erase is suspended, the user can read from any sector within the memory that is pro- tected. the command sequence for a chip erase suspend and a sector erase suspend are the same. program suspend/program resume: the program suspend command allows the system to interrupt a programming operation and then read data from a different word within the memory. after the program suspend command is given, the device requires a maximum of 15 s to suspend the programming operation. after the programming operation has been suspended, the system can then read data from any other word within the device. an address is not required during the program suspend operation. to resume the programming operation, the system must write the program resume command. the program suspend and resume are one-bus cycle commands. the command sequence for the erase suspend and program sus- pend are the same, and the command sequence for the erase resume and program resume are the same. product identification: the product identification mode identifies the device and man- ufacturer as atmel. it may be accessed by hardware or software operation. the hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the atmel product. for details, see ? operating modes ? on page 16 (for hardware operation) or ? software product identification entry/exit ? on page 23. the manufacturer and device codes are the same for both modes. 128-bit protection register: the 16-megabit flash contains a 128-bit register that can be used for security purposes in system design. the protection register is divided into two 64-bit blocks. the two blocks are designated as block a and block b. the data in block a is non-changeable and is programmed at the factory with a unique number. the data in block b is programmed by the user and can be locked out such that data in the block cannot be repro- grammed. to program block b in the protection register, the four-bus cycle program protection register command must be used as shown in the ? command definition in hex ? table on page 13. to lock out block b, the four-bus cycle lock protection register command
9 at52br1662t/1664t 2212a ? 11/01 must be used as shown in the ? command definition in hex ? table on page 13. data bit d1 must be zero during the fourth bus cycle. all other data bits during the fourth bus cycle are don ? t cares. to determine whether block b is locked out, the product id entry command is given followed by a read operation from address 80h. if data bit d1 is zero, block b is locked. if data bit d1 is one, block b can be reprogrammed. please see the ? protection register addressing table ? on page 14 for the address locations in the protection register. to read the protection register, the product id entry command is given followed by a normal read opera- tion from an address within the protection register. after determining whether block b is protected or not, or reading the protection register, the product id exit command must be given prior to performing any other operation. rdy/busy : an open-drain ready/busy output pin provides another method of detecting the end of a program or erase operation. rdy/busy is actively pulled low during the internal program and erase cycles and is released at the completion of the cycle. the open-drain con- nection allows for or-tying of several devices to the same rdy/busy line. please see ? status bit table ? on page 12 for more details. hardware data protection: the hardware data protection feature protects against inadvertent programs to the 16-megabit flash in the following ways: (a) v cc sense: if v cc is below 1.8v (typical), the program function is inhibited. (b) v cc power-on delay: once v cc has reached the v cc sense level, the device will automatically time out 10 ms (typical) before pro- gramming. (c) program inhibit: holding any one of oe low, ce high or we high inhibits program cycles. (d) noise filter: pulses of less than 15 ns (typical) on the we or ce inputs will not initiate a program cycle. (e) program inhibit: v pp is less than v ilpp . (f) v pp power-on delay: once v pp has reached 1.65v, program and erase operations can occur after 100 ns. input levels: while operating with a 2.7v to 3.6v power supply, the address inputs and control inputs (oe , ce and we ) may be driven from 0 to 5.5v without adversely affecting the operation of the device. the i/o lines can only be driven from 0 to v cc + 0.6v. output levels: for the flash, output high levels (v oh ) are equal to v ccq - 0.2v (not v cc ). for 2.7v - 3.6v output levels, v ccq must be tied to v cc . for 1.8v - 2.2v output levels, v ccq must be regulated to 2.0v 10%, while v cc must be regulated to 2.7v - 3.0v (for minimum power).
10 at52br1662t/1664t 2212a ? 11/01 figure 1. data polling algorithm (configuration register = 00) notes: 1. va = valid address for programming. during a sec- tor erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. i/o7 should be rechecked even if i/o5 = ? 1 ? because i/o7 may change simultaneously with i/o5. start read i/o7 - i/o0 addr = va i/o7 = data? i/o3, i/o5 = 1? read i/o7 - i/o0 addr = va i/o7 = data? program/erase operation not successful, write product id exit command no no no yes yes yes program/erase operation successful, device in read mode figure 2. data polling algorithm (configuration register = 01) note: 1. va = valid address for programming. during a sec- tor erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. start read i/o7 - i/o0 addr = va i/o7 = 1? i/o3, i/o5 = 1? program/erase operation not successful, write product id exit command no no yes yes program/erase operation successful, write product id exit command
11 at52br1662t/1664t 2212a ? 11/01 figure 3. toggle bit algorithm (configuration register = 00) note: 1. the system should recheck the toggle bit even if i/o5 = ? 1 ? because the toggle bit may stop toggling as i/o5 changes to ? 1 ? . start read i/o7 - i/o0 read i/o7 - i/o0 toggle bit = toggle? i/o3, i/o5 = 1? read i/o7 - i/o0 twice toggle bit = toggle? program/erase operation not successful, write product id exit command program/erase operation successful no no no yes yes yes figure 4. toggle bit algorithm (configuration register = 01) note: 1. the system should recheck the toggle bit even if i/o5 = ? 1 ? because the toggle bit may stop toggling as i/o5 changes to ? 1 ? . start read i/o7 - i/o0 read i/o7 - i/o0 toggle bit = toggle? i/o3, i/o5 = 1? read i/o7 - i/o0 twice toggle bit = toggle? program/erase operation not successful, write product id exit command program/erase operation successful, write product id exit command no no no yes yes yes
12 at52br1662t/1664t 2212a ? 11/01 notes: 1. i/o5 switches to a ? 1 ? when a program or an erase operation has exceeded the maximum time limits or when a program or sector erase operation is performed on a protected sector. 2. i/o3 switches to a ? 1 ? when the v pp level is not high enough to successfully perform program and erase operations. status bit table status bit i/o7 i/o7 i/o6 i/o5 (1) i/o3 (2) i/o2 rdy/busy configuration register: 00 01 00/01 00/01 00/01 00/01 00/01 programming i/o7 0toggle0010 erasing 0 0 toggle 0 0 toggle 0 erase suspended & read erasing sector 11100toggle1 erase suspended & read non-erasing sector data data data data data data 1 erase suspended & program non-erasing sector i/o7 0 toggle 0 0 toggle 0
13 at52br1662t/1664t 2212a ? 11/01 notes: 1. the data format shown for each bus cycle is as follows; i/o7 - i/o0 (hex). in word operation i/o15 - i/o8 are don ? t care. the address format shown for each bus cycle is as follows: a11 - a0 (hex). address a19 through a11 are don ? t care. 2. since a11 is a don ? t care, aaa can be replaced with 2aa. 3. sa = sector address. any word address within a sector can be used to designate the sector address (see page 15 for details). 4. once a sector is in the lockdown mode, data in the protected sector cannot be changed unless the chip is reset or power cycled. 5. either one of the product id exit commands can be used. 6. if data bit d1 is ? 0 ? , block b is locked. if data bit d1 is ? 1 ? , block b can be reprogrammed. 7. the default state (after power-up) of the configuration register is ? 00 ? . command definition in hex (1) command sequence bus cycles 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle addr data addr data addr data addr data addr data addr data read 1 addr d out chip erase 6 555 aa aaa (2) 55 555 80 555 aa aaa 55 555 10 sector erase 6 555 aa aaa 55 555 80 555 aa aaa 55 sa (3)(4) 30 word program 4 555 aa aaa 55 555 a0 addr d in enter single pulse program mode 6 555 aa aaa 55 555 80 555 aa aaa 55 555 a0 single pulse word program 1 addr d in sector lockdown 6 555 aa aaa 55 555 80 555 aa aaa 55 sa (3)(4) 60 erase/program suspend 1 xxx b0 erase/program resume 1xxx30 product id entry 3 555 aa aaa 55 555 90 product id exit (5) 3 555 aa aaa 55 555 f0 product id exit (5) 1xxxf0 program protection register 4 555 aa aaa 55 555 c0 addr d in lock protection register - block b 4 555 aa aaa 55 555 c0 080 x0 status of block b protection 4 555 aa aaa 55 555 90 80 d out (6) set configuration register 4 555 aa aaa 55 555 d0 xxx 00/01 (7) absolute maximum ratings* temperature under bias ................................ -55 c to +125 c *notice: stresses beyond those listed under ? absolute maximum ratings ? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65 c to +150 c all input voltages (including nc pins) with respect to ground ...................................-0.6v to +6.25v all output voltages with respect to ground .............................-0.6v to v cc + 0.6v voltage on oe and v pp with respect to ground ...................................-0.6v to +13.0v
14 at52br1662t/1664t 2212a ? 11/01 note: 1. all address lines not specified in the above table must be ? 0 ? when accessing the protection register, i.e., a19 - a8 = 0. protection register addressing table word use block a7 a6 a5 a4 a3 a2 a1 a0 0 factory a 10000001 1 factory a 10000010 2 factory a 10000011 3 factory a 10000100 4 user b 10000101 5 user b 10000110 6 user b 10000111 7 user b 10001000
15 at52br1662t/1664t 2212a ? 11/01 top boot 16-megabit flash ? sector address table sector size (words) x16 address range (a19 - a0) sa0 32k 00000 - 07fff sa1 32k 08000 - 0ffff sa2 32k 10000 - 17fff sa3 32k 18000 - 1ffff sa4 32k 20000 - 27fff sa5 32k 28000 - 2ffff sa6 32k 30000 - 37fff sa7 32k 38000 - 3ffff sa8 32k 40000 - 47fff sa9 32k 48000 - 4ffff sa10 32k 50000 - 57fff sa11 32k 58000 - 5ffff sa12 32k 60000 - 67fff sa13 32k 68000 - 6ffff sa14 32k 70000 - 77fff sa15 32k 78000 - 7ffff sa16 32k 80000 - 87fff sa17 32k 88000 - 8ffff sa18 32k 90000 - 97fff sa19 32k 98000 - 9ffff sa20 32k a0000 - a7fff sa21 32k a8000 - affff sa22 32k b0000 - b7fff sa23 32k b8000 - bffff sa24 32k c0000 - c7fff sa25 32k c8000 - cffff sa26 32k d0000 - d7fff sa27 32k d8000 - dffff sa28 32k e0000 - e7fff sa29 32k e8000 - effff sa30 32k f0000 - f7fff sa31 4k f8000 - f8fff sa32 4k f9000 - f9fff sa33 4k fa000 - fafff sa34 4k fb000 - fbfff sa35 4k fc000 - fcfff sa36 4k fd000 - fdfff sa37 4k fe000 - fefff sa38 4k ff000 - fffff
16 at52br1662t/1664t 2212a ? 11/01 notes: 1. x can be v il or v ih . 2. refer to ac programming waveforms on page 22. 3. v h = 12.0v 0.5v. 4. manufacturer code: 001fh, device code: 00c2h. 5. see details under ? software product identification entry/exit ? on page 23. 6. v ihpp (min) = 1.65v; v ihpp (max) = 3.6v. for faster erase/program operations, v pp can be set to 5.0v 0.5v or 12v 0.5v. 7. v ilpp (max) = 0.8v. dc and ac operating range at52br1662t/1664t-70 at52br1662t/1664t-90 operating temperature (case) ind. -40 c - 85 c-40 c - 85 c v cc power supply 2.7v to 3.3v 2.7v to 3.3v operating modes mode ce oe we reset v pp ai i/o read v il v il v ih v ih xaid out program/erase (2) v il v ih v il v ih v ihpp (6) ai d in standby/program inhibit v ih x (1) xv ih x x high-z program inhibit xxv ih v ih x xv il xv ih x xxx v ih v ilpp (7) output disable x v ih xv ih x high-z reset xxx v il x x high-z product identification hardware v il v il v ih v ih a1 - a19 = v il , a9 = v h (3) , a0 = v il manufacturer code (4) a1 - a19 = v il , a9 = v h (3) , a0 = v ih device code (4) software (5) v ih a0 = v il , a1 - a19 = v il manufacturer code (4) a0 = v ih , a1 - a19 = v il device code (4)
17 at52br1662t/1664t 2212a ? 11/01 notes: 1. in the erase mode, i cc is 50 ma. 2. for 3.3v < v cc < 3.6v, i cc (max) = 35 ma dc characteristics symbol parameter condition min max units i li input load current v in = 0v to v cc 10 a i lo output leakage current v i/o = 0v to v cc 10 a i sb1 v cc standby current cmos ce = v cc - 0.3v to v cc 10 a i sb2 v cc standby current ttl ce = 2.0v to v cc 1ma i sb3 v cc standby current ttl ce = 2.0v to v cc , v cc = 2.85v 10 a i cc (1)(2) v cc active read current f = 5 mhz; i out = 0 ma, 3.3v v cc 30 ma i cc1 v cc programming current (v pp = v cc ) 45 ma i pp1 v pp input load current v pp = 0v, v cc = 3.0v 10 a v pp = v cc = 3.0v 10 a i cc2 v cc programming current (v pp = 5.0v 0.5v) 40 ma i pp2 v pp programming current (v pp = 5.0v 0.5v) 5ma i cc3 v cc programming current (v pp = 12.0v 0.5v) 40 ma i pp3 v pp programming current (v pp = 12.0v 0.5v) 6ma v il input low voltage 0.6 v v ih input high voltage 2.0 v v ol1 output low voltage i ol = 2.1 ma 0.45 v v ol2 output low voltage i ol = 1.0 ma 0.20 v v oh1 output high voltage i oh = -400 a i oh = -400 a v ccq < 2.6v v ccq 2.6v v ccq - 0.2 2.4 v v v v oh2 output high voltage i oh = -100 a i oh = -100 a v ccq < 2.6v v ccq 2.6v v ccq - 0.1 2.5 v v v
18 at52br1662t/1664t 2212a ? 11/01 . ac read waveforms (1)(2)(3)(4) notes: 1. ce may be delayed up to t acc - t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce or by t acc - t oe after an address change without impact on t acc . 3. t df is specified from oe or ce , whichever occurs first (cl = 5 pf). 4. this parameter is characterized and is not 100% tested. ac read characteristics symbol parameter at52br1662t/1664t-70 at52br1662t/1664t-90 units min max min max t rc read cycle time 70 90 ns t acc address to output delay 70 90 ns t ce (1) ce to output delay 70 90 ns t oe (2) oe to output delay 0 35 0 40 ns t df (3)(4) ce or oe to output float 0 25 0 25 ns t oh output hold from oe , ce or address, whichever occurred first 00ns t ro reset to output delay 100 100 ns output valid output high z reset oe toe tce trc address valid tdf toh tacc tro ce address
19 at52br1662t/1664t 2212a ? 11/01 input test waveforms and measurement level output test load pin capacitance note: 1. this parameter is characterized and is not 100% tested f = 1 mhz, t = 25 c (1) symbol typ max units conditions c in 46pfv in = 0v c out 812pfv out = 0v
20 at52br1662t/1664t 2212a ? 11/01 . ac word load waveforms we controlled ce controlled ac word load characteristics symbol parameter min max units t as , t oes address, oe setup time 0 ns t ah address hold time 40 ns t cs chip select setup time 0 ns t ch chip select hold time 0 ns t wp write pulse width (we or ce )40ns t ds data setup time 30 ns t dh , t oeh data, oe hold time 0 ns t wph write pulse width high 30 ns
21 at52br1662t/1664t 2212a ? 11/01 program cycle waveforms sector or chip erase cycle waveforms notes: 1. oe must be high only when we and ce are both low. 2. for chip erase, the address should be 555. for sector erase, the address depends on what sector is to be erased. (see note 3 under command definitions.) 3. for chip erase, the data should be 10h, and for sector erase, the data should be 30h. program cycle characteristics symbol parameter min typ max units t bp word programming time (v ihpp < v pp < 4.5v) 20 200 s t bpvpp word programming time (v pp > 4.5v) 10 100 s t as address setup time 0ns t ah address hold time 40 ns t ds data setup time 30 ns t dh data hold time 0ns t wp write pulse width 40 ns t wph write pulse width high 30 ns t wc write cycle time 70 ns t rp reset pulse width 500 ns t rh reset high time before read 50 ns t ec chip erase cycle time (v pp < 4.5v) 12 seconds t ecvpp chip erase cycle time (v pp > 4.5v) 6 seconds t sec sector erase cycle time (v pp < 4.5v) 300 400 ms t eps erase or program suspend time 15 s oe program cycle input data address a0 55 555 555 aa aaa t bp t wph t wp ce we a0 -a19 data t as t ah t wc t dh t ds 555 aa oe (1) aa 80 note 3 55 55 555 555 note 2 aa word 0 word 1 word 2 word 3 word 4 word 5 aaa aaa t wph t wp ce we a0-a19 data t as t ah t ec t dh t ds 555 t wc
22 at52br1662t/1664t 2212a ? 11/01 notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ? ac read characteristics ? on page 18. data polling waveforms notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ? ac read characteristics ? on page 18. toggle bit waveforms (1)(2)(3) notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. the t oehp specification must be met by the toggling input(s). 2. beginning and ending state of i/o6 will vary. 3. any address location may be used but the address should not vary. data polling characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t wr write recovery time 0 ns toggle bit characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 50 ns t wr write recovery time 0 ns
23 at52br1662t/1664t 2212a ? 11/01 software product identification entry (1) software product identification exit (1)(6) notes: 1. data format: i/o15 - i/o8 (don ? t care); i/o7 - i/o0 (hex) address format: a11 - a0 (hex) and a11 - a19 (don ? t care). 2. a1 - a19 = v il . manufacturer code is read for a0 = v il ; device code is read for a0 = v ih . additional device code is read for address 0003h. 3. the device does not remain in identification mode if powered down. 4. the device returns to standard operation mode. 5. manufacturer code: 001fh. device code: 00c2h. additional device code: 0008h. 6. either one of the product id exit commands can be used. load data aa to address 555 load data 55 to address aaa load data 90 to address 555 enter product identification mode (2)(3)(5) load data aa to address 555 load data 55 to address aaa load data f0 to address 555 exit product identification mode (4) or load data f0 to any address exit product identification mode (4) sector lockdown enable algorithm (1) notes: 1. data format: i/o15 - i/o8 (don ? t care); i/o7 - i/o0 (hex) address format: a11 - a0 (hex) and a11 - a19 (don ? t care). 2. sector lockdown feature enabled. load data aa to address 555 load data 55 to address aaa load data 80 to address 555 load data aa to address 555 load data 55 to address aaa load data 60 to sector address pause 200 s (2)
24 at52br1662t/1664t 2212a ? 11/01 2-megabit sram description the 2-megabit sram is a high-speed, super low-power cmos sram organized as 128k words by 16 bits. the sram uses high-performance full cmos process technology and is designed for high-speed and low-power circuit technology. it is particularly well-suited for the high-density low-power system application. this device has a data retention mode that guar- antees data to remain valid at a minimum power supply voltage of 1.2v. features fully static operation and tri-state output ttl compatible inputs and outputs battery backup ? 1.2v (min) data retention block diagram voltage (v) speed (ns) operation current/i cc (ma) (max) standby current (a) (max) temperature ( c) 2.7 - 3.3 70 10 10 -40 - 85 memory array 512k x 16 i/o0 sub slb soe scs2 scs1 swe data i/o buffer sense amp write driver i/o7 i/o8 i/o15 row decoder column decoder block decoder pre decoder add input buffer a0 a16
25 at52br1662t/1664t 2212a ? 11/01 note: 1. stresses greater than those listed under ? absolute maximum ratings ? may cause permanent damage to the device. this is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. exposure to the absolute maximum rating conditions for extended period may affect reliability. notes: 1. h = v ih , l = v il , x = don't care (v il or v ih ) 2. sub , slb (upper, lower byte enable). these active low inputs allow individual bytes to be written or read. when slb is low, data is written or read to the lower byte, i/o0 - i/o8. when sub is low, data is written or read to the upper byte, i/o9 - i/o16. note: 1. undershoot: v il = -1.5v for pulse width less than 30 ns. undershoot is sampled, not 100% tested. absolute maximum ratings (1) symbol parameter rating unit v in , v out input/output voltage -0.3 to 3.6 v v cc power supply -0.3 to 4.6 v t a operating temperature -40 to 85 c t stg storage temperature -55 to 150 c p d power dissipation 1.0 w truth table scs1 scs2 swe soe slb (2) sub (2) mode i/o pin power i/o0 - i/o7 i/o8 - i/o15 h (1) x xx xx deselected high-z high-z standby x (1) l xx hh l (1) hhh lh output disabled high-z high-z active hl ll lhlx lh write d in high-z active hl high-z d in ll d in d in lhhl lh read d out high-z active hl high-z d out ll d out d out recommended dc operating condition symbol parameter min typ max unit v cc supply voltage 2.3 3.0 3.3 v v ss ground 0 0 0 v v ih input high voltage 2.2 v cc + 0.3 v v il (1) input low voltage -0.2 (1) 0.4 v
26 at52br1662t/1664t 2212a ? 11/01 note: 1. typical values are at v cc = 3.0v, t a = 25 c. typical values are not 100% tested. note: 1. these parameters are sampled and not 100% tested. dc electrical characteristics t a = -40 c to 85 c symbol parameter test condition min typ (1) max unit i li input leakage current v ss < v in < v cc -1 1 a i lo output leakage current v ss < v out < v cc , scs1 = v ih or scs2=v il or soe = v ih or swe = vil or sub = v ih , slb = v ih -1 1 a i cc operating power supply current scs1 = v il , scs2=v ih , v in = v ih or v il , i i/o = 0 ma 510ma i cc1 average operating current cycle time = 1 s i i/o = 0 ma, scs1 = 0.2v, scs2 = v cc -0.2v, v in 0.2v or v in v cc - 0.2v 46ma cycle time = min, 100% duty, i i/o = 0 ma scs1 = v il , scs2 = v ih , v in = v ih or v il 30 45 ma i sb standby current (ttl input) scs1 = v ih or scs2 = v il 0.5 ma i sb1 standby current (cmos input) scs1 v cc - 0.2v or scs2 v ss + 0.2v ll 0.4 10 a sl 2 a v ol output low i ol = 0.5 ma 0.4 v v oh output high i oh = -0.5 ma 2.0 v capacitance (1) (temp = 25 c, f = 1.0 mhz) symbol parameter condition max unit c in input capacitance (add, scs1 , scs2, slb , sub , swe , soe ) v in = 0 v 8 pf c out output capacitance (i/o) v i/o = 0 v 10 pf
27 at52br1662t/1664t 2212a ? 11/01 ac characteristics t a = -40 c to 85 c, unless otherwise specified # symbol parameter 70 ns unit min max 1t rc read cycle time 70 ns 2t aa address access time 70 ns 3t acs chip select access time 70 ns 4t oe output enable to output valid 35 ns 5t ba slb , sub access time 35 ns 6t clz chip select to output in low z 5 ns 7t olz output enable to output in low z 0 ns 8t blz slb , sub enable to output in low z 0 ns 9t chz chip deselection to output in high z 0 30 ns 10 t ohz out disable to output in high z 0 30 ns 11 t bhz slb , sub disable to output in high z 0 30 ns 12 t oh output hold from address change 10 ns 13 t wc write cycle time 70 ns 14 t cw chip selection to end of write 60 ns 15 t aw address valid to end of write 60 ns 16 t bw slb , sub valid to end of write 60 ns 17 t as address setup time 0 ns 18 t wp write pulse width 50 ns 19 t wr write recovery time 0 ns 20 t whz write to output in high z 0 25 ns 21 t dw data to write time overlap 30 ns 22 t dh data hold from write time 0 ns 23 t ow output active from end of write 5 ns ac test conditions ta = - 4 0 c to 85 c, unless otherwise specified parameter value input pulse level 0.4v to 2.2v input rise and fall time 5 ns input and output timing reference level 1.5v output load cl = 5 pf + 1 ttl load cl = 5 pf + 1 ttl load cl = 30 pf + 1 ttl load cl = 30 pf + 1 ttl load
28 at52br1662t/1664t 2212a ? 11/01 output test load timing diagrams read cycle 1 (1) , (4) read cycle 2 (1) , (2) , (4) read cycle 3 (1) , (2) , (4) notes: 1. read cycle occurs whenever a high on the swe and soe is low, while sub and/or slb and scs1 and scs2 are in active status. 2. soe = v il . 3. transition is measured + 200 mv from steady state voltage. this parameter is sampled and not 100% tested. 4. scs1 in high for the standby, low for active. scs2 in low for the standby, high for active. sub and slb in high for the standby, low for active. address soe sub, slb scs1 scs2 data out high-z data valid t aa t rc t ba t acs t oe t olz t blz t clz t bhz t chz t oh t ohz (3) (3) (3) (3) (3) (3) data out address t aa previous data t oh data valid t oh t rc sub, slb scs1 scs2 data out t acs t clz (3) data valid t chz (3)
29 at52br1662t/1664t 2212a ? 11/01 write cycle 1 (swe controlled) (1) , (4) , (8) write cycle 2 (scs1 , scs2 controlled) (1) , (4) , (8) notes: 1. a write occurs during the overlap of a low swe , a low scs1 , a high scs2 and a low sub and/or slb . 2. t wr is measured from the earlier of scs1 , slb , sub , or swe going high or scs2 going low to the end of write cycle. 3. during this period, i/o pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. if the scs1 , slb and sub low transition and scs2 high transition occur simultaneously with the swe low transition or after the swe transition, outputs remain in a high impedance state. 5. q (data out) is the same phase with the write data of this write cycle. 6. q (data out) is the read data of the next address. 7. transition is measured + 200 mv from steady state. this parameter is sampled and not 100% tested. 8. scs1 in high for the standby, low for active scs2 in low for the standby, high for active. sub and slb in high for the standby, low for active. address swe sub, slb data in scs1 scs2 data out t wc t cw t aw t bw t wp t as t whz t wr t dw t dh t ow data valid high-z t as (2) (5) (5) (3)(7) address swe sub, slb data in scs1 scs2 data out t wc t cw t aw t bw t wp t as t wr t dw t dh data valid high-z (2) high-z
30 at52br1662t/1664t 2212a ? 11/01 notes: 1. typical values are under the condition of t a = 25 c. typical values are sampled and not 100% tested. 2. t rc is read cycle time. data retention timing diagram 1 data retention timing diagram 2 data retention electric characteristic t a = -40 c to 85 c symbol parameter test condition min typ max unit v dr v cc for data retention scs1 > v cc -0.2v, scs2 0.2v or v cc - 0.2v, v ss v in v cc 1.2 3.3 v i ccdr data retention current v cc = 3.0v, scs1 > v cc - 0.2v or scs2 v ss + 0.2v or v ss v in v cc 9.5 a 0.4 (1) 0.7 a t cdr chip deselect to data retention time see data retention timing diagram 0ns t r operating recovery time t rc (2) ns data retention mode t r t cdr vcc scs1 > vcc - 0.2v 2.3v ih vdr scs1 vss vcc 2.3v vdr scs2 vss 0.4v data retention mode t r t cdr scs2 < 0.2v
31 at52br1662t/1664t 2212a ? 11/01 4-megabit sram description the 4-megabit sram is a high-speed, super low-power cmos sram organized as 256k words by 16 bits. the sram uses high-performance full cmos process technology and is designed for high-speed and low-power circuit technology. it is particularly well-suited for the high-density low-power system application. this device has a data retention mode that guar- antees data to remain valid at a minimum power supply voltage of 1.2v. features fully static operation and tri-state output ttl compatible inputs and outputs battery backup ? 1.2v (min) data retention block diagram voltage (v) speed (ns) operation current/i cc (ma) (max) standby current (a) (max) temperature ( c) 2.7 - 3.3 70 5 15 -40 - 85 memory array 256k x 16 i/o0 sub slb soe scs2 scs1 swe data i/o buffer sense amp write driver i/o7 i/o8 i/o15 row decoder column decoder block decoder pre decoder add input buffer a0 a17
32 at52br1662t/1664t 2212a ? 11/01 note: 1. stresses greater than those listed under ? absolute maximum ratings ? may cause permanent damage to the device. this is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. exposure to the absolute maximum rating conditions for extended period may affect reliability. notes: 1. h = v ih , l = v il , x = don't care (v il or v ih ) 2. sub , slb (upper, lower byte enable). these active low inputs allow individual bytes to be written or read. when slb is low, data is written or read to the lower byte, i/o0 - i/o7. when sub is low, data is written or read to the upper byte, i/o8 - i/o15. note: 1. undershoot: v il = -1.5v for pulse width less than 30 ns. undershoot is sampled, not 100% tested. absolute maximum ratings (1) symbol parameter rating unit v in , v out input/output voltage -0.3 to 3.6 v v cc power supply -0.3 to 4.6 v t a operating temperature -40 to 85 c t stg storage temperature -55 to 150 c p d power dissipation 1.0 w truth table scs1 scs2 swe soe slb (2) sub (2) mode i/o pin power i/o0 - i/o7 i/o8 - i/o15 h (1) x xx xx deselected high-z high-z standby x (1) l xx hh l (1) hhh lh output disabled high-z high-z active hl ll lhlx lh write d in high-z active hl high-z d in ll d in d in d in high-z lhhl lh read d out high-z active hl high-z d out ll d out d out d out high-z recommended dc operating condition symbol parameter min typ max unit v cc supply voltage 2.7 3.0 3.3 v v ss ground 0 0 0 v v ih input high voltage 2.2 v cc + 0.3 v v il (1) input low voltage -0.31 (1) 0.6 v
33 at52br1662t/1664t 2212a ? 11/01 note: 1. these parameters are sampled and not 100% tested. dc electrical characteristics t a = -40 c to 85 c symbol parameter test condition min max unit i li input leakage current v ss < v in < v cc -1 1 a i lo output leakage current v ss < v out < v cc , scs1 = v ih or scs2=v il or soe = v ih or swe = vil or sub = v ih , slb = v ih -1 1 a i cc operating power supply current scs1 = v il , scs2=v ih , v in = v ih or v il , i i/o = 0 ma 5ma i cc1 average operating current scs1 = v il , scs2 = v ih , v in = v ih or v il , cycle time = min 100% duty, i i/o = 0 ma 35 ma scs1 < 0.2v, scs2 > v cc - 0.2v v in < 0.2v or v in > v cc - 0.2v, cycle time = 1 s 100% duty, i i/o = 0 ma 5ma i sb standby current (ttl input) scs1 = v ih or scs2 = v il or sub , slb = v ih v in = v ih or v il 0.5 ma i sb1 standby current (cmos input) scs1 > v cc - 0.2v or scs2 < v ss + 0.2v or sub , slb > v cc - 0.2v v in > v cc - 0.2v or v in < v ss + 0.2v sl 4 a ll 15 a v ol output low i ol = 0.1 ma 0.4 v v oh output high i oh = -0.1 ma 2.4 v capacitance (1) (temp = 25 c, f = 1.0 mhz) symbol parameter condition max unit c in input capacitance (add, scs1 , scs2, slb , sub , swe , soe ) v in = 0 v 8 pf c out output capacitance (i/o) v i/o = 0 v 10 pf
34 at52br1662t/1664t 2212a ? 11/01 ac characteristics t a = -40 c to 85 c, unless otherwise specified # symbol parameter 70 ns unit min max 1t rc read cycle time 70 ns 2t aa address access time 70 ns 3t acs chip select access time 70 ns 4t oe output enable to output valid 35 ns 5t ba slb , sub access time 70 ns 6t clz chip select to output in low z 10 ns 7t olz output enable to output in low z 5 ns 8t blz slb , sub enable to output in low z 10 ns 9t chz chip deselection to output in high z 0 30 ns 10 t ohz out disable to output in high z 0 30 ns 11 t bhz slb , sub disable to output in high z 0 30 ns 12 t oh output hold from address change 10 ns 13 t wc write cycle time 70 ns 14 t cw chip selection to end of write 60 ns 15 t aw address valid to end of write 60 ns 16 t bw slb , sub valid to end of write 60 ns 17 t as address setup time 0 ns 18 t wp write pulse width 50 ns 19 t wr write recovery time 0 ns 20 t whz write to output in high z 0 20 ns 21 t dw data to write time overlap 30 ns 22 t dh data hold from write time 0 ns 23 t ow output active from end of write 5 ns ac test conditions ta = - 4 0 c to 85 c, unless otherwise specified parameter value input pulse level 0.4v to 2.2v input rise and fall time 5 ns input and output timing reference level 1.5v output load cl = 5 pf + 1 ttl load cl = 5 pf + 1 ttl load cl = 30 pf + 1 ttl load cl = 30 pf + 1 ttl load
35 at52br1662t/1664t 2212a ? 11/01 output test load timing diagrams read cycle 1 (1) , (4) read cycle 2 (1) , (2) , (4) read cycle 3 (1) , (2) , (4) notes: 1. read cycle occurs whenever a high on the swe and soe is low, while sub and/or slb and scs1 and scs2 are in active status. 2. soe = v il . 3. transition is measured + 200 mv from steady state voltage. this parameter is sampled and not 100% tested. 4. scs1 in high for the standby, low for active. scs2 in low for the standby, high for active. sub and slb in high for the standby, low for active. address soe sub, slb scs1 scs2 data out high-z data valid t aa t rc t ba t acs t oe t olz t blz t clz t bhz t chz t oh t ohz (3) (3) (3) (3) (3) (3) data out address t aa previous data t oh data valid t oh t rc sub, slb scs1 scs2 data out t acs t clz (3) data valid t chz (3)
36 at52br1662t/1664t 2212a ? 11/01 write cycle 1 (swe controlled) (1) , (4) , (8) write cycle 2 (scs1 , scs2 controlled) (1) , (4) , (8) notes: 1. a write occurs during the overlap of a low swe , a low scs1 , a high scs2 and a low sub and/or slb . 2. t wr is measured from the earlier of scs1 , slb , sub , or swe going high or scs2 going low to the end of write cycle. 3. during this period, i/o pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. if the scs1 , slb and sub low transition and scs2 high transition occur simultaneously with the swe low transition or after the swe transition, outputs remain in a high impedance state. 5. q (data out) is the same phase with the write data of this write cycle. 6. q (data out) is the read data of the next address. 7. transition is measured + 200 mv from steady state. this parameter is sampled and not 100% tested. 8. scs1 in high for the standby, low for active scs2 in low for the standby, high for active. sub and slb in high for the standby, low for active. address swe sub, slb data in scs1 scs2 data out t wc t cw t aw t bw t wp t as t whz t wr t dw t dh t ow data valid high-z t as (2) (5) (5) (3)(7) address swe sub, slb data in scs1 scs2 data out t wc t cw t aw t bw t wp t as t wr t dw t dh data valid high-z (2) high-z
37 at52br1662t/1664t 2212a ? 11/01 note: 1. typical values are under the condition of t a = 25 c. typical values are sampled and not 100% tested. 2. t rc is read cycle time. data retention timing diagram 1 data retention timing diagram 2 data retention electric characteristic t a = -40 c to 85 c symbol parameter test condition min typ (1) max unit v dr v cc for data retention scs1 > v cc - 0.2v or scs2 < v ss + 0.2v or sub , slb > v cc - 0.2v v in > v cc - 0.2v or v in < v ss + 0.2v 1.2 3.3 v i ccdr data retention current vcc=1.5v, scs1 > v cc - 0.2v or scs2 < v ss + 0.2v or sub , slb > v cc - 0.2v v in > v cc - 0.2v or v in < v ss + 0.2v sl 0.1 2 a ll 0.1 10 a t cdr chip deselect to data retention time see data retention timing diagram 0ns t r operating recovery time t rc (2) ns data retention mode t r t cdr vcc scs1 > vcc - 0.2v 2.7v ih vdr scs1 vss vcc 2.7v vdr scs2 vss 0.4v data retention mode t r t cdr scs2 < 0.2v
38 at52br1662t/1664t 2212a ? 11/01 ordering information t acc (ns) voltage range ordering code package operation range 70 2.7v - 3.3v at52br1662t-70ci 66c5 industrial (-40 to 85 c) 90 2.7v - 3.3v at52br1662t-90ci 66c5 industrial (-40 to 85 c) 70 2.7v - 3.3v AT52BR1664T-70CI 66c5 industrial (-40 to 85 c) 90 2.7v - 3.3v at52br1664t-90ci 66c5 industrial (-40 to 85 c) package type 66c5 66-ball, plastic chip-scale ball grid array package (cbga)
39 at52br1662t/1664t 2212a ? 11/01 packaging information 66c5 ? cbga 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 66c5 , 66-ball (12 x 8 array), 10 x 8 x 1.2 mm body, 0.8 mm ball pitch chip-scale ball grid array package (cbga) a 66c5 09/19/01 side view a a1 0.12 seating plane c c top view bottom view 0.60 ref e d a1 ball corner ?b marked a1 identifier a b c d e f g h 1 2 3 4 5 6 7 8 9 10 11 12 d1 1.20 ref e e e1 common dimensions (unit of measure = mm) symbol min nom max note e 9.90 10.00 10.10 e1 ? 8.80 ? d 7.90 8.00 8.10 d1 ? 5.60 ? a ? ? 1.20 a1 0.25 ? ? e 0.80 bsc b ? 0.40 ?
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