 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| preliminary 1 hd66750/1 (128 x 128-dot graphics lcd controller/driver with four-grayscale functions) rev 0.7 july 26th, 1999 description the hd66750/1, dot-matrix graphics lcd controller and driver lsi, displays 128-by-128-dot graphics for four monochrome grayscales. since the hd66750/1 incorporates bit-operation functions and a 16-bit high-speed bus interface, it enables efficient data transfer and high-speed rewriting of data in the graphics ram. the following functions allow the user to easily see a variety of information: a smooth scroll display function that fixed-displays a part of the graphics icons and perform vertical smooth scrolling of the remaining bit-map areas, a double-height display function, and a hardware-supported window cursor display function. the hd66750/1 has various functions to reduce the power consumption of an lcd system such as low- voltage operation of 1.8 v min., a booster to generate maximum seven-times lcd drive voltage from the supplied voltage, and voltage-followers to decrease the direct current flow in the lcd drive bleeder- resistors. combining these hardware functions with software functions, such as a partial display with low-duty drive and standby and sleep modes, allows precise power control. the hd66750/1 is suitable for any mid-sized or small portable battery-driven product requiring long-term driving capabilities, such as digital cellular phones supporting a www browser, bidirectional pagers, and small pdas. features 128 128-dot graphics display lcd controller/driver for four monochrome grayscales fixed display of graphics icons (pictograms) 16-/8-bit high-speed bus interface capability bit-operation functions for graphics processing incorporated: ? write-data mask function in bit units ? bit rotation function ? bit logic-operation function low-power operation support: ? vcc = 1.8 to 3.6 v (low voltage) ? v lcd = 5 to 15.5 v (liquid crystal drive voltage) ? two-, five-, six-, or seven-times booster for liquid crystal drive voltage ? 64-step contrast adjuster and voltage followers to decrease direct current flow in the lcd drive bleeder-resistors
hd66750/1 2 ? power-save functions such as the standby mode and sleep mode supported ? programmable drive duty ratios and bias values displayed on lcd 128-segment 128-common liquid crystal display driver n-raster-row ac liquid-crystal drive (c-pattern waveform drive) duty ratio and drive bias (selectable by program) window cursor display supported by hardware vertical smooth scroll partial smooth scroll control (fixed display of graphics icons) vertical double-height display by each display raster-row black-and-white reversed display no wait time for instruction execution and ram access internal oscillation and hardware reset shift change of segment and common driver table 1 progammable display sizes and duty ratios graphics display duty ratio optimum drive bias bit-map display area 12 x 12-dot font width 12 x 13-dot font width 14 x 15-dot font width 16 x 16-dot font width 8 x 10-dot font width 1/16 1/5 128 x 16 dots 1 line x 10 characters 1 line x 10 characters 1 line x 9 characters 1 line x 8 characters 1 line x 16 characters 1/24 1/6 128 x 24 dots 2 lines x 10 characters 1 line x 10 characters 1 line x 9 characters 1 line x 8 characters 2 lines x 16 characters 1/32 1/6 128 x 32 dots 2 lines x 10 characters 2 lines x 10 characters 2 lines x 9 characters 2 lines x 8 characters 3 lines x 16 characters 1/72 1/9 128 x 72 dots 6 lines x 10 characters 5 lines x 10 characters 4 lines x 9 characters 4 lines x 8 characters 7 lines x 16 characters 1/80 1/10 128 x 80 dots 6 lines x 10 characters 6 lines x 10 characters 5 lines x 9 characters 5 lines x 8 characters 8 lines x 16 characters 1/88 1/10 128 x 88 dots 7 lines x 10 characters 6 lines x 10 characters 5 lines x 9 characters 5 lines x 8 characters 8 lines x 16 characters 1/96 1/10 128 x 96 dots 8 lines x 10 characters 7 lines x 10 characters 6 lines x 9 characters 6 lines x 8 characters 9 lines x 16 characters 1/104 1/11 128 x 104 dots 8 lines x 10 characters 8 lines x 10 characters 6 lines x 9 characters 6 lines x 8 characters 10 lines x 16 characters 1/112 1/11 128 x 112 dots 9 lines x 10 characters 8 lines x 10 characters 7 lines x 9 characters 7 lines x 8 characters 11 lines x 16 characters 1/120 1/11 128 x 120 dots 10 lines x 10 characters 9 lines x 10 characters 8 lines x 9 characters 7 lines x 8 characters 12 lines x 16 characters 1/128 1/11 128 x 128 dots 10 lines x 10 characters 9 lines x 10 characters 8 lines x 9 characters 8 lines x 8 characters 12 lines x 16 characters hd66750/1 3 hd66750/1 4 lcd family comparison items hd66705u hd66717 hd66727 character display sizes 12 characters x 2 lines 12 characters x 4 lines 12 characters x 4 lines graphic display sizes ? ? ? grayscale display ? ? ? multiplexing icons 40 40 40 annunciator static: 10 static: 10 static: 12 key scan control ? ? 4 x 8 led control ports ? ? 3 general output ports ? ? 3 operating power voltages 2.4 v to 5.5 v 2.4 v to 5.5 v 2.4 v to 5.5 v liquid crystal drive voltages 3 v to 9 v 3 v to 13 v 3 v to 13 v serial bus clock-synchronized serial i2c, clock-synchronized serial i2c, clock-synchronized serial parallel bus 4 bits, 8 bits 4 bits, 8 bits ? liquid crystal drive duty ratios 1/10, 18 1/10, 18, 26, 34 1/10, 18, 26, 34 liquid crystal drive biases 1/4 1/4, 1/6 1/4, 1/6 liquid crystal drive waveforms b b b liquid crystal voltage booster two- or three-times two- or three-times two- or three-times bleeder-resistor for liquid crystal drive incorporated (external) incorporated (external) incorporated (external) liquid crystal drive operational amplifier incorporated incorporated incorporated liquid crystal contrast adjuster incorporated incorporated incorporated horizontal smooth scroll ? ? ? vertical smooth scroll line unit line unit line unit double-height display yes yes yes ddram 60 x 8 60 x 8 60 x 8 cgrom 9,600 9,600 11,520 cgram 32 x 5 32 x 5 32 x 6 segram 8 x 5 8 x 5 8 x 6 no. of cgrom fonts 240 240 240 no. of cgram fonts 4 4 4 font sizes 5 x 8 5 x 8 5 x 8, 6 x 8 bit map area ? ? ? r-c oscillation resistor/ oscillation frequency external resistor (40, 80 khz) external resistor (40-160 khz) external resistor (40-160 khz) reset function external external external low power control partial display off, oscillation off, liquid crystal power off partial display off, oscillation off, liquid crystal power off partial display off, oscillation off, liquid crystal power off, key wake-up interrupt seg/com direction switching seg only seg only seg, com qfp package ? ? ? tqfp package ? ? ? tcp package tcp-153 tcp-153 tcp-158 bare chip yes yes yes bumped chip yes yes yes no. of pins 153 153 158 chip sizes 9.69 x 2.73 10.88 x 2.89 11.39 x 2.89 pad intervals 120 m m 120 m m 120 m m hd66750/1 5 lcd family comparison (cont) items hd66724 hd66725 hd66726 character display sizes 12 characters x 3 lines 16 characters x 3 lines 16 characters x 5 lines graphic display sizes 72 x 26 dots 96 x 26 dots 96 x 42 dots grayscale display ? ? ? multiplexing icons 144 192 192 annunciator 1/2 duty: 144 1/2 duty: 192 1/2 duty: 192 key scan control 8 x 4 8 x 4 8 x 4 led control ports ? ? ? general output ports 3 3 3 operating power voltages 1.8 v to 5.5 v 1.8 v to 5.5 v 1.8 v to 5.5 v liquid crystal drive voltages 3 v to 6.5 v 3 v to 6.5 v 4.5 v to 11 v serial bus clock-synchronized serial clock-synchronized serial clock-synchronized serial parallel bus 4 bits, 8 bits 4 bits, 8 bits 4 bits, 8 bits liquid crystal drive duty ratios 1/2, 10, 18, 26 1/2, 10, 18, 26 1/2, 10, 18, 26, 34, 42 liquid crystal drive biases 1/4 to 1/6.5 1/4 to 1/6.5 1/2 to 1/8 liquid crystal drive waveforms b b b liquid crystal voltage booster single, two-, or three-times single, two-, or three-times single, two-, three-, or four- times bleeder-resistor for liquid crystal drive incorporated (external) incorporated (external) incorporated (external) liquid crystal drive operational amplifier incorporated incorporated incorporated liquid crystal contrast adjuster incorporated incorporated incorporated horizontal smooth scroll 3-dot unit 3-dot unit ? vertical smooth scroll line unit line unit line unit double-height display yes yes yes ddram 80 x 8 80 x 8 80 x 8 cgrom 20,736 20,736 20,736 cgram 384 x 8 384 x 8 480 x 8 segram 72 x 8 96 x 8 96 x 8 no. of cgrom fonts 240 + 192 240 + 192 240 + 192 no. of cgram fonts 64 64 64 font sizes 6 x 8 6 x 8 6 x 8 bit map areas 72 x 26 96 x 26 96 x 42 r-c oscillation resistor/ oscillation frequency external resistor, incorporated (32 khz) external resistor, incorporated (32 khz) external resistor (50 khz) reset function external external external low power control partial display off, oscillation off, liquid crystal power off, key wake-up interrupt partial display off, oscillation off, liquid crystal power off, key wake-up interrupt partial display off, oscillation off, liquid crystal power off, key wake-up interrupt seg/com direction switching seg, com seg, com seg, com qfp package ? ? ? tqfp package ? ? ? tcp package tcp-146 tcp-170 tcp-188 bare chip ? ? yes bumped chip yes yes yes no. of pins 146 170 188 chip sizes 10.34 x 2.51 10.97 x 2.51 13.13 x 2.51 pad intervals 80 m m 80 m m 100 m m hd66750/1 6 lcd family comparison (cont) (ws available) items hd66728 hd66729 character display sizes 16 characters x 10 lines ? graphic display sizes 112 x 80 dots 105 x 68 dots grayscale display ? ? multiplexing icons ? ? annunciator ? ? key scan control 8 x 4 ? led control ports ? ? general output ports 3 ? operating power voltages 1.8 v to 5.5 v 1.8 v to 5.5 v liquid crystal drive voltages 4.5 v to 15 v 4.0 v to 13 v serial bus clock-synchronized serial clock-synchronized serial parallel bus 4 bits, 8 bits 4 bits, 8 bits liquid crystal drive duty ratios 1/8, 16, 24, 32, 40, 48, 56, 64, 72, 80 1/8, 16, 24, 32, 40, 48, 56, 64, 68 liquid crystal drive biases 1/4 to 1/10 1/4 to 1/9 liquid crystal drive waveforms b, c b, c liquid crystal voltage booster three-, four-, or five-times two-, three-, four-, or five- times bleeder-resistor for liquid crystal drive incorporated (external) incorporated (external) liquid crystal drive operational amplifier incorporated incorporated liquid crystal contrast adjuster incorporated incorporated horizontal smooth scroll ? ? vertical smooth scroll line unit line unit double-height display yes yes ddram 160 x 8 ? cgrom 20,736 ? cgram 1,120 x 8 1,050 x 8 segram ? ? no. of cgrom fonts 240 + 192 ? no. of cgram fonts 64 ? font sizes 6 x 8 ? bit map areas 112 x 80 105 x 68 r-c oscillation resistor/ oscillation frequency external resistor (70e90 khz) external resistor (75 khz) reset function external external low power control partial display off, oscillation off, liquid crystal power off, key wake-up interrupt partial display off, oscillation off, liquid crystal power off seg/com direction switching seg, com seg, com qfp package ? ? tqfp package ? ? tcp package tcp-243 tcp-213 bare chip ? ? bumped chip yes yes no. of pins 243 213 chip sizes 13.67 x 2.78 12.23 x 2.52 pad intervals 70 m m 70 m m hd66750/1 7 lcd family comparison (cont) (under development) items hd66741 hd66750/751 character display sizes ? ? graphic display sizes 128 x 80 dots 128 x 128 dots grayscale display ? four monochrome grayscales multiplexing icons ? ? annunciator ? ? key scan control ? ? led control ports ? ? general output ports 3 ? operating power voltages 1.8 v to 5.5 v 1.8 v to 3.6 v liquid crystal drive voltages 4.5 v to 15 v 5 v to 15.5 v serial bus clock-synchronized serial ? parallel bus 4 bits, 8 bits 8 bits, 16 bits liquid crystal drive duty ratios 1/8, 16, 24, 32, 40, 48, 56, 64, 72, 80 1/16, 24, 72, 80, 88, 96, 104, 112, 120, 128 liquid crystal drive biases 1/4 to 1/10 1/4 to 1/11 liquid crystal drive waveforms b, c b, c liquid crystal voltage booster three-, four-, or five-times two-, five-, six-, or seven-times bleeder-resistor for liquid crystal drive incorporated (external) incorporated (external) liquid crystal drive operational amplifier incorporated incorporated liquid crystal contrast adjuster incorporated incorporated horizontal smooth scroll ? ? vertical smooth scroll line unit line unit double-height display yes yes ddram ? ? cgrom ? ? cgram 1,280 x 8 4,096 x 8 segram ? ? no. of cgrom fonts ? ? no. of cgram fonts ? ? font sizes ? ? bit map areas 128 x 80 128 x 128 r-c oscillation resistor/ oscillation frequency external resistor (70e90 khz) external resistor (70 khz) reset function external external low power control partial display off, oscillation off, liquid crystal power off partial display off, oscillation off, liquid crystal power off seg/com direction switching seg, com seg, com qfp package ? ? tqfp package ? ? tcp package tcp-254 tcp-308 bare chip ? ? bumped chip yes yes no. of pins 243 308 chip sizes 14.30 x 2.78 10.97 x 4.13 pad intervals 70 m m 60 m m hd66750/1 8 hd66750/1 block diagram rs rw/rd* e/wr* vcc v lcd 16 12 16 vci c1+ im1-0 c1- +- +- +- +- vlout +- gnd vr rrr 0 r r v1out v2out v3out v4out v5out opoff db0-db15 vtest c2+ c2- cs* c3+ c3- c4+ c4- 16 c5+ c5- 16 16 16 16 c6+ c6- instruction register (ir) timing generator cpg instruction decoder osc1 osc2 reset* test system interface 16-bit bus 8-bit bus address counter (ac) graphic ram (cgram) 4,096 bytes 128-bit latch circuit 128-bit bidirectional common shift register common driver segment driver lcd drive voltage selector com1/128e com128/1 seg1/128- seg128/1 two-, five-, six-, and seven-times booster contrast adjuster drive bias controller window cursor control four grayscale control circuit read data latch bit operation chip size: 10.97 mm x 4.13 mm pad coordinates: pad center coordinate origin: chip center au bump size: 40 m m x 90 m m chip corner bump size : 90 m m x 90 m m (dummy1, dummy22, dummy23 and dummy 48) au bump pitch: 60 m m (min.) au bump height: 20 m m (typ.) (top view) hd66750 y x hd66750/1 hitachi 9 hd66750 pad arrangement com29/100 com28/101 com27/102 com26/103 com25/104 com24/105 com23/106 com22/107 com21/108 com20/109 com19/110 com18/111 com17/112 com119/10 com118/11 com117/12 com116/13 com115/14 com114/15 com113/16 seg72/57 seg128/1 seg127/2 seg126/3 seg87/42 seg88/41 seg89/40 seg125/4 seg124/5 seg123/6 seg122/7 seg121/8 seg120/9 seg119/10 seg118/11 seg117/12 seg116/13 seg115/14 seg114/15 seg113/16 seg112/17 seg111/18 seg110/19 seg109/20 seg108/21 seg107/22 seg106/23 seg105/24 seg104/25 seg103/26 seg102/27 seg101/28 seg100/29 seg99/30 seg98/31 seg97/32 seg96/33 seg95/34 seg94/35 seg93/36 seg92/37 seg91/38 seg90/39 seg86/43 seg85/44 seg84/45 seg83/46 seg82/47 seg81/48 seg80/49 seg79/50 seg78/51 seg77/52 seg76/53 seg75/54 seg74/55 seg73/56 seg71/58 seg70/59 seg69/60 seg68/61 seg67/62 seg66/63 seg65/64 seg64/65 seg63/66 seg62/67 seg61/68 seg60/69 seg59/70 seg58/71 seg57/72 seg56/73 seg55/74 seg54/75 seg53/76 seg52/77 seg51/78 seg50/79 seg49/80 seg48/81 seg47/82 seg46/83 seg45/84 seg44/85 seg43/86 seg42/87 seg41/88 seg40/89 seg39/90 seg38/91 seg37/92 seg36/93 seg35/94 seg34/95 seg33/96 seg32/97 seg31/98 seg30/99 seg29/100 seg28/101 seg27/102 seg26/103 seg25/104 seg24/105 seg23/106 seg22/107 seg21/108 seg20/109 seg19/110 seg18/111 seg17/112 seg16/113 seg15/114 seg14/115 seg13/116 seg12/117 seg11/118 seg10/119 seg9/120 seg8/121 seg7/122 seg6/123 seg5/124 seg4/125 seg3/126 seg2/127 seg1/128 com64/65 com63/66 com62/67 com61/68 com60/69 com59/70 com58/71 com57/72 com56/73 com55/74 com54/75 com53/76 com52/77 com51/78 com50/79 com49/80 com48/81 com47/82 com46/83 com45/84 com44/85 com43/86 com42/87 com41/88 com40/89 com39/90 com38/91 com37/92 com36/93 com35/94 com34/95 com33/96 com32/97 com31/98 com30/99 com16/113 com15/114 com14/115 com13/116 com12/117 com11/118 com10/119 com9/120 com8/121 com7/122 com6/123 com5/124 com4/125 com3/126 com2/127 com1/128 com128/1 com127/2 com126/3 com125/4 com124/5 com123/6 com122/7 com121/8 com120/9 com112/17 com111/18 com110/19 com109/20 com108/21 com107/22 com106/23 com105/24 com72/57 com71/58 com70/59 com69/60 com68/61 com67/62 com66/63 com65/64 com87/42 com88/41 com89/40 com104/25 com103/26 com102/27 com101/28 com100/29 com99/30 com98/31 com97/32 com96/33 com95/34 com94/35 com93/36 com92/37 com91/38 com90/39 com86/43 com85/44 com84/45 com83/46 com82/47 com81/48 com80/49 com79/50 com78/51 com77/52 com76/53 com75/54 com74/55 com73/56 osc2 osc1 e/wr* rw/rd* gnd rs cs* reset* db0 db1 db2 db3 db4 db5 db6 db7 gnddum1 im1 im0 vccdum1 opoff test gnddum2 db8 db9 db10 db11 db12 db13 db14 db15 gnddum3 dummy1 c1+ c2- c2+ vci vtest c1- vlout v lcd vcc c3- c3+ v1out v2out v3out v4out v5out c4- c4+ c5- c5+ c6- c6+ dummy22 v lcd vlout c1- c1+ c2- c2+ c3- c3+ c4- c4+ c5- c5+ c6- c6+ vci vcc gnd gnd gnd gnd rw/rd* e/wr* rs cs* reset* db0 db1 db2 db4 db3 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 test opoff im0 im1 dummy21 dummy20 dummy19 dummy18 dummy17 dummy15 dummy16 dummy14 dummy13 dummy12 dummy11 osc1 osc2 gnd gnd gnd gnd dummy2 dummy3 dummy4 dummy5 dummy6 dummy7 dummy8 dummy9 dummy10 dummy29 dummy28 dummy27 dummy25 dummy26 dummy23 dummy24 dummy31 dummy32 dummy33 dummy34 dummy35 dummy30 dummy48 dummy47 dummy43 dummy42 dummy41 dummy40 dummy39 dummy38 dummy46 dummy45 dummy44 dummy37 dummy36 (note) this figure is shown pad arrangement from chip top view which has au-bumps and lsi pattern layer. osc2 osc1 e/wr* rw/rd* gnd rs cs* reset* db0 db1 db2 db3 db4 db5 db6 db7 gnddum1 im1 im0 vccdum1 opoff test seg128/1 seg72/57 dummy48 gnddum2 db8 db9 db10 db11 db12 db13 db14 db15 gnddum3 seg127/2 seg126/3 seg87/42 dummy1 seg88/41 seg89/40 c1+ c2- c2+ vci vtest c1- vlout v lcd vcc c3- c3+ v1out v2out v3out v4out v5out c4- c4+ c5- c5+ c6- c6+ seg125/4 seg124/5 seg123/6 seg122/7 seg121/8 seg120/9 seg119/10 seg118/11 seg117/12 seg116/13 seg115/14 seg114/15 seg113/16 seg112/17 seg111/18 seg110/19 seg109/20 seg108/21 seg107/22 seg106/23 seg105/24 seg104/25 seg103/26 seg102/27 seg101/28 seg100/29 seg99/30 seg98/31 seg97/32 seg96/33 seg95/34 seg94/35 seg93/36 seg92/37 seg91/38 seg90/39 seg86/43 seg85/44 seg84/45 seg83/46 seg82/47 seg81/48 seg80/49 seg79/50 seg78/51 seg77/52 seg76/53 seg75/54 seg74/55 seg73/56 seg71/58 seg70/59 seg69/60 seg68/61 seg67/62 seg66/63 seg65/64 seg64/65 seg63/66 seg62/67 seg61/68 seg60/69 seg59/70 seg58/71 seg57/72 seg56/73 seg55/74 seg54/75 seg53/76 seg52/77 seg51/78 seg50/79 seg49/80 seg48/81 seg47/82 seg46/83 seg45/84 seg44/85 seg43/86 seg42/87 seg41/88 seg40/89 seg39/90 seg38/91 seg37/92 seg36/93 seg35/94 seg34/95 seg33/96 seg32/97 seg31/98 seg30/99 seg29/100 seg28/101 seg27/102 seg26/103 seg25/104 seg24/105 seg23/106 seg22/107 seg21/108 seg20/109 seg19/110 seg18/111 seg17/112 seg16/113 seg15/114 seg14/115 seg13/116 seg12/117 seg11/118 seg10/119 seg9/120 seg8/121 seg7/122 seg6/123 seg5/124 seg4/125 seg3/126 seg2/127 seg1/128 dummy29 dummy22 com72/57 com71/58 com70/59 com69/60 com68/61 com67/62 com66/63 com65/64 com64/65 com63/66 com62/67 com61/68 com60/69 com59/70 com58/71 com57/72 com56/73 com55/74 com54/75 com53/76 com52/77 com51/78 com50/79 com49/80 com48/81 com47/82 com46/83 com45/84 com44/85 com43/86 com42/87 com41/88 com40/89 com39/90 com38/91 com37/92 com36/93 com35/94 com34/95 com33/96 com32/97 com31/98 com30/99 com29/100 com28/101 com27/102 com26/103 com25/104 com24/105 com23/106 com22/107 com21/108 com20/109 com19/110 com18/111 com17/112 com16/113 com15/114 com14/115 com13/116 com12/117 com11/118 com10/119 com9/120 com8/121 com7/122 com6/123 com5/124 com4/125 com3/126 com2/127 com1/128 com128/1 com127/2 com126/3 com87/42 com88/41 com89/40 com125/4 com124/5 com123/6 com122/7 com121/8 com120/9 com119/10 com118/11 com117/12 com116/13 com115/14 com114/15 com113/16 com112/17 com111/18 com110/19 com109/20 com108/21 com107/22 com106/23 com105/24 com104/25 com103/26 com102/27 com101/28 com100/29 com99/30 com98/31 com97/32 com96/33 com95/34 com94/35 com93/36 com92/37 com91/38 com90/39 com86/43 com85/44 com84/45 com83/46 com82/47 com81/48 com80/49 com79/50 com78/51 com77/52 com76/53 com75/54 com74/55 com73/56 dummy28 dummy27 dummy25 vlout c1- c1+ c2- c2+ c3- c3+ c4- c4+ c5- c5+ c6- c6+ vci vcc gnd gnd gnd gnd rw/rd* e/wr* rs cs* reset* db0 db1 db2 db4 db3 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 test opoff im0 im1 v lcd dummy47 dummy36 dummy43 dummy42 dummy41 dummy26 dummy23 dummy21 dummy20 dummy19 dummy18 dummy17 dummy15 dummy16 dummy14 dummy13 dummy12 dummy11 osc1 osc2 gnd gnd gnd gnd dummy2 dummy3 dummy4 dummy5 dummy6 dummy7 dummy8 dummy9 dummy10 dummy24 dummy31 dummy32 dummy33 dummy34 dummy35 dummy40 dummy39 dummy38 dummy37 dummy46 dummy45 dummy44 dummy30 (top view) HD66751 y x hd66750/1 hitachi 10 HD66751 pad arrangement chip size: 10.97 mm x 4.13 mm pad coordinates: pad center coordinate origin: chip center au bump size: 40 m m x 90 m m chip corner bump size : 90 m m x 90 m m (dummy1, dummy22, dummy23 and dummy 48) au bump pitch: 60 m m (min.) au bump height: 20 m m (typ.) (note) this figure is shown pad arrangement from chip top view which has au-bumps and lsi pattern layer. hd66750/1 hd66750 pad coordinate pad name x y pad name x y pad name x y pad name x y pad name x y 1 dummy1 -5269 -1895 83 c6+ 1582 -1849 165 com54/75 5269 571 247 seg43/86 1310 1849 329 seg125/4 -3655 1849 2 dummy2 -5089 -1895 84 c6- 1703 -1849 166 com55/74 5269 631 248 seg44/85 1250 1849 330 seg126/3 -3715 1849 3 dummy3 -5029 -1895 85 c6- 1763 -1849 167 com56/73 5269 691 249 seg45/84 1190 1849 331 seg127/2 -3775 1849 4 dummy4 -4969 -1895 86 c5+ 1883 -1849 168 com57/72 5269 752 250 seg46/83 1130 1849 332 seg128/1 -3835 1849 5 dummy5 -4909 -1895 87 c5+ 1943 -1849 169 com58/71 5269 812 251 seg47/82 1070 1849 333 com112/17 -3931 1849 6 dummy6 -4848 -1895 88 c5- 2063 -1849 170 com59/70 5269 872 252 seg48/81 1010 1849 334 com111/18 -3991 1849 7 dummy7 -4788 -1895 89 c5- 2124 -1849 171 com60/69 5269 932 253 seg49/80 950 1849 335 com110/19 -4051 1849 8 dummy8 -4728 -1895 90 c4+ 2244 -1849 172 com61/68 5269 992 254 seg50/79 889 1849 336 com109/20 -4111 1849 9 dummy9 -4668 -1895 91 c4+ 2304 -1849 173 com62/67 5269 1052 255 seg51/78 829 1849 337 com108/21 -4171 1849 10 dummy10 -4608 -1895 92 c4- 2424 -1849 174 com63/66 5269 1112 256 seg52/77 769 1849 338 com107/22 -4232 1849 11 gnddum1 -4454 -1895 93 c4- 2484 -1849 175 com64/65 5269 1172 257 seg53/76 709 1849 339 com106/23 -4292 1849 12 im1 -4394 -1895 94 c3+ 2605 -1849 176 com113/16 5269 1232 258 seg54/75 649 1849 340 com105/24 -4352 1849 13 im1 -4334 -1895 95 c3+ 2665 -1849 177 com114/15 5269 1293 259 seg55/74 589 1849 341 dummy36 -4428 1895 14 im0 -4210 -1895 96 c3- 2785 -1849 178 com115/14 5269 1353 260 seg56/73 529 1849 342 dummy37 -4488 1895 15 im0 -4150 -1895 97 c3- 2845 -1849 179 com116/13 5269 1413 261 seg57/72 469 1849 343 dummy38 -4548 1895 16 vccdum1 -4086 -1895 98 c2+ 2965 -1849 180 com117/12 5269 1473 262 seg58/71 409 1849 344 dummy39 -4608 1895 17 opoff -4026 -1895 99 c2+ 3025 -1849 181 com118/11 5269 1533 263 seg59/70 348 1849 345 dummy40 -4668 1895 18 opoff -3966 -1895 100 c2- 3146 -1849 182 com119/10 5269 1593 264 seg60/69 288 1849 346 dummy41 -4728 1895 19 test -3842 -1895 101 c2- 3206 -1849 183 com120/9 5269 1653 265 seg61/68 228 1849 347 dummy42 -4788 1895 20 test -3782 -1895 102 c1+ 3326 -1849 184 dummy23 5269 1895 266 seg62/67 168 1849 348 dummy43 -4848 1895 21 gnddum2 -3722 -1895 103 c1+ 3386 -1849 185 dummy24 5089 1895 267 seg63/66 108 1849 349 dummy44 -4909 1895 22 db15 -3658 -1895 104 c1- 3506 -1849 186 dummy25 5029 1895 268 seg64/65 48 1849 350 dummy45 -4969 1895 23 db15 -3598 -1895 105 c1- 3566 -1849 187 dummy26 4969 1895 269 seg65/64 -48 1849 351 dummy46 -5029 1895 24 db14 -3474 -1895 106 vlout 3687 -1849 188 dummy27 4909 1895 270 seg66/63 -108 1849 352 dummy47 -5089 1895 25 db14 -3414 -1895 107 vlout 3747 -1849 189 dummy28 4848 1895 271 seg67/62 -168 1849 353 dummy48 -5269 1895 26 db13 -3290 -1895 108 vlcd 3867 -1849 190 dummy29 4788 1895 272 seg68/61 -228 1849 354 com104/25 -5269 1653 27 db13 -3230 -1895 109 vlcd 3927 -1849 191 dummy30 4728 1895 273 seg69/60 -288 1849 355 com103/26 -5269 1593 28 db12 -3106 -1895 110 v1out 4047 -1849 192 dummy31 4668 1895 274 seg70/59 -348 1849 356 com102/27 -5269 1533 29 db12 -3046 -1895 111 v2out 4108 -1849 193 dummy32 4608 1895 275 seg71/58 -409 1849 357 com101/28 -5269 1473 30 db11 -2922 -1895 112 v3out 4168 -1849 194 dummy33 4548 1895 276 seg72/57 -469 1849 358 com100/29 -5269 1413 31 db11 -2862 -1895 113 v4out 4228 -1849 195 dummy34 4488 1895 277 seg73/56 -529 1849 359 com99/30 -5269 1353 32 db10 -2738 -1895 114 v5out 4288 -1849 196 dummy35 4428 1895 278 seg74/55 -589 1849 360 com98/31 -5269 1293 33 db10 -2678 -1895 115 vtest 4348 -1849 197 com121/8 4352 1849 279 seg75/54 -649 1849 361 com97/32 -5269 1232 34 db9 -2554 -1895 116 dummy11 4488 -1895 198 com122/7 4292 1849 280 seg76/53 -709 1849 362 com96/33 -5269 1172 35 db9 -2494 -1895 117 dummy12 4548 -1895 199 com123/6 4232 1849 281 seg77/52 -769 1849 363 com95/34 -5269 1112 36 db8 -2370 -1895 118 dummy13 4608 -1895 200 com124/5 4171 1849 282 seg78/51 -829 1849 364 com94/35 -5269 1052 37 db8 -2310 -1895 119 dummy14 4668 -1895 201 com125/4 4111 1849 283 seg79/50 -889 1849 365 com93/36 -5269 992 38 db7 -2186 -1895 120 dummy15 4728 -1895 202 com126/3 4051 1849 284 seg80/49 -950 1849 366 com92/37 -5269 932 39 db7 -2126 -1895 121 dummy16 4788 -1895 203 com127/2 3991 1849 285 seg81/48 -1010 1849 367 com91/38 -5269 872 40 db6 -2002 -1895 122 dummy17 4848 -1895 204 com128/1 3931 1849 286 seg82/47 -1070 1849 368 com90/39 -5269 812 41 db6 -1942 -1895 123 dummy18 4909 -1895 205 seg1/128 3835 1849 287 seg83/46 -1130 1849 369 com89/40 -5269 752 42 db5 -1818 -1895 124 dummy19 4969 -1895 206 seg2/127 3775 1849 288 seg84/45 -1190 1849 370 com88/41 -5269 691 43 db5 -1758 -1895 125 dummy20 5029 -1895 207 seg3/126 3715 1849 289 seg85/44 -1250 1849 371 com87/42 -5269 631 44 db4 -1634 -1895 126 dummy21 5089 -1895 208 seg4/125 3655 1849 290 seg86/43 -1310 1849 372 com86/43 -5269 571 45 db4 -1574 -1895 127 dummy22 5269 -1895 209 seg5/124 3595 1849 291 seg87/42 -1370 1849 373 com85/44 -5269 511 46 db3 -1450 -1895 128 com17/112 5269 -1653 210 seg6/123 3535 1849 292 seg88/41 -1431 1849 374 com84/45 -5269 451 47 db3 -1390 -1895 129 com18/111 5269 -1593 211 seg7/122 3475 1849 293 seg89/40 -1491 1849 375 com83/46 -5269 391 48 db2 -1266 -1895 130 com19/110 5269 -1533 212 seg8/121 3415 1849 294 seg90/39 -1551 1849 376 com82/47 -5269 331 49 db2 -1206 -1895 131 com20/109 5269 -1473 213 seg9/120 3354 1849 295 seg91/38 -1611 1849 377 com81/48 -5269 271 50 db1 -1083 -1895 132 com21/108 5269 -1413 214 seg10/119 3294 1849 296 seg92/37 -1671 1849 378 com80/49 -5269 210 51 db1 -1022 -1895 133 com22/107 5269 -1353 215 seg11/118 3234 1849 297 seg93/36 -1731 1849 379 com79/50 -5269 150 52 db0 -899 -1895 134 com23/106 5269 -1293 216 seg12/117 3174 1849 298 seg94/35 -1791 1849 380 com78/51 -5269 90 53 db0 -838 -1895 135 com24/105 5269 -1232 217 seg13/116 3114 1849 299 seg95/34 -1851 1849 381 com77/52 -5269 30 54 gnddum3 -775 -1895 136 com25/104 5269 -1172 218 seg14/115 3054 1849 300 seg96/33 -1912 1849 382 com76/53 -5269 -30 55 reset* -715 -1895 137 com26/103 5269 -1112 219 seg15/114 2994 1849 301 seg97/32 -1972 1849 383 com75/54 -5269 -90 56 reset* -654 -1895 138 com27/102 5269 -1052 220 seg16/113 2934 1849 302 seg98/31 -2032 1849 384 com74/55 -5269 -150 57 cs* -531 -1895 139 com28/101 5269 -992 221 seg17/112 2873 1849 303 seg99/30 -2092 1849 385 com73/56 -5269 -210 58 cs* -471 -1895 140 com29/100 5269 -932 222 seg18/111 2813 1849 304 seg100/29 -2152 1849 386 com72/57 -5269 -271 59 rs -347 -1895 141 com30/99 5269 -872 223 seg19/110 2753 1849 305 seg101/28 -2212 1849 387 com71/58 -5269 -331 60 rs -287 -1895 142 com31/98 5269 -812 224 seg20/109 2693 1849 306 seg102/27 -2272 1849 388 com70/59 -5269 -391 61 e/wr* -163 -1895 143 com32/97 5269 -752 225 seg21/108 2633 1849 307 seg103/26 -2332 1849 389 com69/60 -5269 -451 62 e/wr* -103 -1895 144 com33/96 5269 -691 226 seg22/107 2573 1849 308 seg104/25 -2392 1849 390 com68/61 -5269 -511 63 rw/rd* 21 -1895 145 com34/95 5269 -631 227 seg23/106 2513 1849 309 seg105/24 -2453 1849 391 com67/62 -5269 -571 64 rw/rd* 81 -1895 146 com35/94 5269 -571 228 seg24/105 2453 1849 310 seg106/23 -2513 1849 392 com66/63 -5269 -631 65 gnd 151 -1895 147 com36/93 5269 -511 229 seg25/104 2392 1849 311 seg107/22 -2573 1849 393 com65/64 -5269 -691 66 gnd 211 -1895 148 com37/92 5269 -451 230 seg26/103 2332 1849 312 seg108/21 -2633 1849 394 com16/113 -5269 -752 67 gnd 271 -1895 149 com38/91 5269 -391 231 seg27/102 2272 1849 313 seg109/20 -2693 1849 395 com15/114 -5269 -812 68 gnd 332 -1895 150 com39/90 5269 -331 232 seg28/101 2212 1849 314 seg110/19 -2753 1849 396 com14/115 -5269 -872 69 gnd 392 -1895 151 com40/89 5269 -271 233 seg29/100 2152 1849 315 seg111/18 -2813 1849 397 com13/116 -5269 -932 70 gnd 452 -1895 152 com41/88 5269 -210 234 seg30/99 2092 1849 316 seg112/17 -2873 1849 398 com12/117 -5269 -992 71 gnd 512 -1895 153 com42/87 5269 -150 235 seg31/98 2032 1849 317 seg113/16 -2934 1849 399 com11/118 -5269 -1052 72 gnd 572 -1895 154 com43/86 5269 -90 236 seg32/97 1972 1849 318 seg114/15 -2994 1849 400 com10/119 -5269 -1112 73 gnd 632 -1895 155 com44/85 5269 -30 237 seg33/96 1912 1849 319 seg115/14 -3054 1849 401 com9/120 -5269 -1172 74 osc2 702 -1895 156 com45/84 5269 30 238 seg34/95 1851 1849 320 seg116/13 -3114 1849 402 com8/121 -5269 -1232 75 osc2 762 -1895 157 com46/83 5269 90 239 seg35/94 1791 1849 321 seg117/12 -3174 1849 403 com7/122 -5269 -1293 76 osc1 886 -1895 158 com47/82 5269 150 240 seg36/93 1731 1849 322 seg118/11 -3234 1849 404 com6/123 -5269 -1353 77 osc1 946 -1895 159 com48/81 5269 210 241 seg37/92 1671 1849 323 seg119/10 -3294 1849 405 com5/124 -5269 -1413 78 vcc 1119 -1849 160 com49/80 5269 271 242 seg38/91 1611 1849 324 seg120/9 -3354 1849 406 com4/125 -5269 -1473 79 vcc 1179 -1849 161 com50/79 5269 331 243 seg39/90 1551 1849 325 seg121/8 -3415 1849 407 com3/126 -5269 -1533 80 vci 1342 -1849 162 com51/78 5269 391 244 seg40/89 1491 1849 326 seg122/7 -3475 1849 408 com2/127 -5269 -1593 81 vci 1402 -1849 163 com52/77 5269 451 245 seg41/88 1431 1849 327 seg123/6 -3535 1849 409 com1/128 -5269 -1653 82 c6+ 1522 -1849 164 com53/76 5269 511 246 seg42/87 1370 1849 328 seg124/5 -3595 1849 11 hd66750/1 HD66751 pad coordinate pad name x y pad name x y pad name x y pad name x y pad name x y 1 dummy1 -5269 -1895 83 c6+ 1582 -1849 165 com38/91 5269 571 247 com107/22 1310 1849 329 seg61/68 -3655 1849 2 dummy2 -5089 -1895 84 c6- 1703 -1849 166 com39/90 5269 631 248 com108/21 1250 1849 330 seg62/67 -3715 1849 3 dummy3 -5029 -1895 85 c6- 1763 -1849 167 com40/89 5269 691 249 com109/20 1190 1849 331 seg63/66 -3775 1849 4 dummy4 -4969 -1895 86 c5+ 1883 -1849 168 com41/88 5269 752 250 com110/19 1130 1849 332 seg64/65 -3835 1849 5 dummy5 -4909 -1895 87 c5+ 1943 -1849 169 com42/87 5269 812 251 com111/18 1070 1849 333 seg65/64 -3931 1849 6 dummy6 -4848 -1895 88 c5- 2063 -1849 170 com43/86 5269 872 252 com112/17 1010 1849 334 seg66/63 -3991 1849 7 dummy7 -4788 -1895 89 c5- 2124 -1849 171 com44/85 5269 932 253 com113/16 950 1849 335 seg67/62 -4051 1849 8 dummy8 -4728 -1895 90 c4+ 2244 -1849 172 com45/84 5269 992 254 com114/15 889 1849 336 seg68/61 -4111 1849 9 dummy9 -4668 -1895 91 c4+ 2304 -1849 173 com46/83 5269 1052 255 com115/14 829 1849 337 seg69/60 -4171 1849 10 dummy10 -4608 -1895 92 c4- 2424 -1849 174 com47/82 5269 1112 256 com116/13 769 1849 338 seg70/59 -4232 1849 11 gnddum1 -4454 -1895 93 c4- 2484 -1849 175 com48/81 5269 1172 257 com117/12 709 1849 339 seg71/58 -4292 1849 12 im1 -4394 -1895 94 c3+ 2605 -1849 176 com49/80 5269 1232 258 com118/11 649 1849 340 seg72/57 -4352 1849 13 im1 -4334 -1895 95 c3+ 2665 -1849 177 com50/79 5269 1293 259 com119/10 589 1849 341 dummy36 -4428 1895 14 im0 -4210 -1895 96 c3- 2785 -1849 178 com51/78 5269 1353 260 com120/9 529 1849 342 dummy37 -4488 1895 15 im0 -4150 -1895 97 c3- 2845 -1849 179 com52/77 5269 1413 261 com121/8 469 1849 343 dummy38 -4548 1895 16 vccdum1 -4086 -1895 98 c2+ 2965 -1849 180 com53/76 5269 1473 262 com122/7 409 1849 344 dummy39 -4608 1895 17 opoff -4026 -1895 99 c2+ 3025 -1849 181 com54/75 5269 1533 263 com123/6 348 1849 345 dummy40 -4668 1895 18 opoff -3966 -1895 100 c2- 3146 -1849 182 com55/74 5269 1593 264 com124/5 288 1849 346 dummy41 -4728 1895 19 test -3842 -1895 101 c2- 3206 -1849 183 com56/73 5269 1653 265 com125/4 228 1849 347 dummy42 -4788 1895 20 test -3782 -1895 102 c1+ 3326 -1849 184 dummy23 5269 1895 266 com126/3 168 1849 348 dummy43 -4848 1895 21 gnddum2 -3722 -1895 103 c1+ 3386 -1849 185 dummy24 5089 1895 267 com127/2 108 1849 349 dummy44 -4909 1895 22 db15 -3658 -1895 104 c1- 3506 -1849 186 dummy25 5029 1895 268 com128/1 48 1849 350 dummy45 -4969 1895 23 db15 -3598 -1895 105 c1- 3566 -1849 187 dummy26 4969 1895 269 seg1/128 -48 1849 351 dummy46 -5029 1895 24 db14 -3474 -1895 106 vlout 3687 -1849 188 dummy27 4909 1895 270 seg2/127 -108 1849 352 dummy47 -5089 1895 25 db14 -3414 -1895 107 vlout 3747 -1849 189 dummy28 4848 1895 271 seg3/126 -168 1849 353 dummy48 -5269 1895 26 db13 -3290 -1895 108 vlcd 3867 -1849 190 dummy29 4788 1895 272 seg4/125 -228 1849 354 seg73/56 -5269 1653 27 db13 -3230 -1895 109 vlcd 3927 -1849 191 dummy30 4728 1895 273 seg5/124 -288 1849 355 seg74/55 -5269 1593 28 db12 -3106 -1895 110 v1out 4047 -1849 192 dummy31 4668 1895 274 seg6/123 -348 1849 356 seg75/54 -5269 1533 29 db12 -3046 -1895 111 v2out 4108 -1849 193 dummy32 4608 1895 275 seg7/122 -409 1849 357 seg76/53 -5269 1473 30 db11 -2922 -1895 112 v3out 4168 -1849 194 dummy33 4548 1895 276 seg8/121 -469 1849 358 seg77/52 -5269 1413 31 db11 -2862 -1895 113 v4out 4228 -1849 195 dummy34 4488 1895 277 seg9/120 -529 1849 359 seg78/51 -5269 1353 32 db10 -2738 -1895 114 v5out 4288 -1849 196 dummy35 4428 1895 278 seg10/119 -589 1849 360 seg79/50 -5269 1293 33 db10 -2678 -1895 115 vtest 4348 -1849 197 com57/72 4352 1849 279 seg11/118 -649 1849 361 seg80/49 -5269 1232 34 db9 -2554 -1895 116 dummy11 4488 -1895 198 com58/71 4292 1849 280 seg12/117 -709 1849 362 seg81/48 -5269 1172 35 db9 -2494 -1895 117 dummy12 4548 -1895 199 com59/70 4232 1849 281 seg13/116 -769 1849 363 seg82/47 -5269 1112 36 db8 -2370 -1895 118 dummy13 4608 -1895 200 com60/69 4171 1849 282 seg14/115 -829 1849 364 seg83/46 -5269 1052 37 db8 -2310 -1895 119 dummy14 4668 -1895 201 com61/68 4111 1849 283 seg15/114 -889 1849 365 seg84/45 -5269 992 38 db7 -2186 -1895 120 dummy15 4728 -1895 202 com62/67 4051 1849 284 seg16/113 -950 1849 366 seg85/44 -5269 932 39 db7 -2126 -1895 121 dummy16 4788 -1895 203 com63/66 3991 1849 285 seg17/112 -1010 1849 367 seg86/43 -5269 872 40 db6 -2002 -1895 122 dummy17 4848 -1895 204 com64/65 3931 1849 286 seg18/111 -1070 1849 368 seg87/42 -5269 812 41 db6 -1942 -1895 123 dummy18 4909 -1895 205 com65/64 3835 1849 287 seg19/110 -1130 1849 369 seg88/41 -5269 752 42 db5 -1818 -1895 124 dummy19 4969 -1895 206 com66/63 3775 1849 288 seg20/109 -1190 1849 370 seg89/40 -5269 691 43 db5 -1758 -1895 125 dummy20 5029 -1895 207 com67/62 3715 1849 289 seg21/108 -1250 1849 371 seg90/39 -5269 631 44 db4 -1634 -1895 126 dummy21 5089 -1895 208 com68/61 3655 1849 290 seg22/107 -1310 1849 372 seg91/38 -5269 571 45 db4 -1574 -1895 127 dummy22 5269 -1895 209 com69/60 3595 1849 291 seg23/106 -1370 1849 373 seg92/37 -5269 511 46 db3 -1450 -1895 128 com1/128 5269 -1653 210 com70/59 3535 1849 292 seg24/105 -1431 1849 374 seg93/36 -5269 451 47 db3 -1390 -1895 129 com2/127 5269 -1593 211 com71/58 3475 1849 293 seg25/104 -1491 1849 375 seg94/35 -5269 391 48 db2 -1266 -1895 130 com3/126 5269 -1533 212 com72/57 3415 1849 294 seg26/103 -1551 1849 376 seg95/34 -5269 331 49 db2 -1206 -1895 131 com4/125 5269 -1473 213 com73/56 3354 1849 295 seg27/102 -1611 1849 377 seg96/33 -5269 271 50 db1 -1083 -1895 132 com5/124 5269 -1413 214 com74/55 3294 1849 296 seg28/101 -1671 1849 378 seg97/32 -5269 210 51 db1 -1022 -1895 133 com6/123 5269 -1353 215 com75/54 3234 1849 297 seg29/100 -1731 1849 379 seg98/31 -5269 150 52 db0 -899 -1895 134 com7/122 5269 -1293 216 com76/53 3174 1849 298 seg30/99 -1791 1849 380 seg99/30 -5269 90 53 db0 -838 -1895 135 com8/121 5269 -1232 217 com77/52 3114 1849 299 seg31/98 -1851 1849 381 seg100/29 -5269 30 54 gnddum3 -775 -1895 136 com9/120 5269 -1172 218 com78/51 3054 1849 300 seg32/97 -1912 1849 382 seg101/28 -5269 -30 55 reset* -715 -1895 137 com10/119 5269 -1112 219 com79/50 2994 1849 301 seg33/96 -1972 1849 383 seg102/27 -5269 -90 56 reset* -654 -1895 138 com11/118 5269 -1052 220 com80/49 2934 1849 302 seg34/95 -2032 1849 384 seg103/26 -5269 -150 57 cs* -531 -1895 139 com12/117 5269 -992 221 com81/48 2873 1849 303 seg35/94 -2092 1849 385 seg104/25 -5269 -210 58 cs* -471 -1895 140 com13/116 5269 -932 222 com82/47 2813 1849 304 seg36/93 -2152 1849 386 seg105/24 -5269 -271 59 rs -347 -1895 141 com14/115 5269 -872 223 com83/46 2753 1849 305 seg37/92 -2212 1849 387 seg106/23 -5269 -331 60 rs -287 -1895 142 com15/114 5269 -812 224 com84/45 2693 1849 306 seg38/91 -2272 1849 388 seg107/22 -5269 -391 61 e/wr* -163 -1895 143 com16/113 5269 -752 225 com85/44 2633 1849 307 seg39/90 -2332 1849 389 seg108/21 -5269 -451 62 e/wr* -103 -1895 144 com17/112 5269 -691 226 com86/43 2573 1849 308 seg40/89 -2392 1849 390 seg109/20 -5269 -511 63 rw/rd* 21 -1895 145 com18/111 5269 -631 227 com87/42 2513 1849 309 seg41/88 -2453 1849 391 seg110/19 -5269 -571 64 rw/rd* 81 -1895 146 com19/110 5269 -571 228 com88/41 2453 1849 310 seg42/87 -2513 1849 392 seg111/18 -5269 -631 65 gnd 151 -1895 147 com20/109 5269 -511 229 com89/40 2392 1849 311 seg43/86 -2573 1849 393 seg112/17 -5269 -691 66 gnd 211 -1895 148 com21/108 5269 -451 230 com90/39 2332 1849 312 seg44/85 -2633 1849 394 seg113/16 -5269 -752 67 gnd 271 -1895 149 com22/107 5269 -391 231 com91/38 2272 1849 313 seg45/84 -2693 1849 395 seg114/15 -5269 -812 68 gnd 332 -1895 150 com23/106 5269 -331 232 com92/37 2212 1849 314 seg46/83 -2753 1849 396 seg115/14 -5269 -872 69 gnd 392 -1895 151 com24/105 5269 -271 233 com93/36 2152 1849 315 seg47/82 -2813 1849 397 seg116/13 -5269 -932 70 gnd 452 -1895 152 com25/104 5269 -210 234 com94/35 2092 1849 316 seg48/81 -2873 1849 398 seg117/12 -5269 -992 71 gnd 512 -1895 153 com26/103 5269 -150 235 com95/34 2032 1849 317 seg49/80 -2934 1849 399 seg118/11 -5269 -1052 72 gnd 572 -1895 154 com27/102 5269 -90 236 com96/33 1972 1849 318 seg50/79 -2994 1849 400 seg119/10 -5269 -1112 73 gnd 632 -1895 155 com28/101 5269 -30 237 com97/32 1912 1849 319 seg51/78 -3054 1849 401 seg120/9 -5269 -1172 74 osc2 702 -1895 156 com29/100 5269 30 238 com98/31 1851 1849 320 seg52/77 -3114 1849 402 seg121/8 -5269 -1232 75 osc2 762 -1895 157 com30/99 5269 90 239 com99/30 1791 1849 321 seg53/76 -3174 1849 403 seg122/7 -5269 -1293 76 osc1 886 -1895 158 com31/98 5269 150 240 com100/29 1731 1849 322 seg54/75 -3234 1849 404 seg123/6 -5269 -1353 77 osc1 946 -1895 159 com32/97 5269 210 241 com101/28 1671 1849 323 seg55/74 -3294 1849 405 seg124/5 -5269 -1413 78 vcc 1119 -1849 160 com33/96 5269 271 242 com102/27 1611 1849 324 seg56/73 -3354 1849 406 seg125/4 -5269 -1473 79 vcc 1179 -1849 161 com34/95 5269 331 243 com103/26 1551 1849 325 seg57/72 -3415 1849 407 seg126/3 -5269 -1533 80 vci 1342 -1849 162 com35/94 5269 391 244 com104/25 1491 1849 326 seg58/71 -3475 1849 408 seg127/2 -5269 -1593 81 vci 1402 -1849 163 com36/93 5269 451 245 com105/24 1431 1849 327 seg59/70 -3535 1849 409 seg128/1 -5269 -1653 82 c6+ 1522 -1849 164 com37/92 5269 511 246 com106/23 1370 1849 328 seg60/69 -3595 1849 12 hd66750/1 13 tcp dimensions (hd66750tb0) (seg126/3) (com128/1) seg127/2 bending slit 4.0 mm com1/128 com16/113 seg128/1 seg1/128 com17/112 0.14-mm pitch h h i i t t a a c c h h i i h h d d 6 6 6 6 7 7 5 5 0 0 com65/64 com104/25 im1 im0 opoff test db7 db6 db5 db4 db3 db2 db1 db0 reset* cs* rs e/wr* rw/rd* gnd osc2 osc1 vcc vci c2+ c2- c1+ c1- vlout vlcd v1out v2out v3out v4out v5out vtest 0.65-mm pitch dummy dummy c3+ c3- com128/1 com113/16 com64/65 seg126/3 seg125/4 seg2/127 seg3/126 seg4/125 c4+ c4- db8 db9 db10 db11 db12 db13 db14 db15 c5+ c5- c6+ c6- (seg128/1) (seg1/128) (com1/128) (dummy) (dummy) (seg127/2 (seg125/4) (seg2/127) (seg3/126) (seg4/125) (com127/2) (com126/3) (com2/127) (com3/126) hd66750 (HD66751) i/o, power supply 0.65p x (50 - 1) = 31.85 mm lcd drive 0.12p x (258 - 1) = 30.784 mm hd66750/1 14 pin functions table 2 pin functional description signals number of pins i/o connected to functions im1, im0 2 i gnd or v cc selects the mpu interface mode: im1 gnd gnd vcc vcc im0 gnd vcc gnd vcc mpu interface mode 68-system 16-bit bus interface 68-system 8-bit bus interface 80-system 16-bit bus interface 80-system 8-bit bus interface cs* 1 i mpu selects the hd66750/1: low: hd66750/1 is selected and can be accessed high: hd66750/1 is not selected and cannot be accessed must be fixed at gnd level when not in use. rs 1 i mpu selects the register. low: index/status high: control e/wr* 1 i mpu for a 68-system bus interface, serves as an enable signal to activate data read/write operation. for an 80-system bus interface, serves as a write strobe signal and writes data at the low level. rw/rd* 1 i mpu for a 68-system bus interface, serves as a signal to select data read/write operation. low: write high: read for an 80-system bus interface, serves as a read strobe signal and reads data at the low level. db0edb15 16 i/o mpu serves as a 16-bit bidirectional data bus. for an 8-bit bus interface, data transfer uses db15- db8; fix unused db7-db0 to the vcc or gnd level. com1/128e com128/1 128 o lcd output signals for common drive: all the unused pins output unselected waveforms. in the display-off period (d = 0), sleep mode (slp = 1), or standby mode (stb = 1), all pins output gnd level. the cms bit can change the shift direction of the common signal. for example, if cms = 0, com1/128 is com1, and com128/1 is com128. if cms = 1, com1/128 is com128, and com128/1 is com1. note that the start position of the common output is shifted by cn1ecn0 bits. seg1/128e seg128/1 128 o lcd output signals for segment drive. in the display-off period (d = 0), sleep mode (slp = 1), or standby mode (stb = 1), all pins output gnd level. the sgs bit can change the shift direction of the segment signal. for example, if sgs = 0, seg1/128 is seg1. if sgs = 1, seg1/128 is seg128. hd66750/1 15 table 2 pin functional description (cont) signals number of pins i/o connected to functions v1out v5out 5 i or o open or external bleeder-resistor used for output from the internal operational amplifiers when they are used (opoff = gnd); attach a capacitor to stabilize the output. when the amplifiers are not used (opoff = v cc ), v1 to v5 voltages can be supplied to these pins externally. v lcd 1 power supply power supply for lcd drive. v lcd gnd = 17 v max. v cc , gnd 2 power supply v cc : +1.8 v to +5.5 v; gnd (logic): 0 v osc1, osc2 2 i or o oscillation- resistor or clock for r-c oscillation using an external resistor, connect an external resistor. for external clock supply, input clock pulses to osc1. vci 1 i power supply inputs a reference voltage and supplies power to the booster; generates the liquid crystal display drive voltage from the operating voltage. the boosting output voltage must not be larger than the absolute maximum ratings. must be left disconnected when the booster is not used. vlout 1 o v lcd pin/booster capacitance potential difference between vci and gnd is two- to seven-times-boosted and then output. magnitude of boost is selected by instruction. c1+, c1 2 booster capacitance external capacitance should be connected here for boosting. c2+, c2 2 booster capacitance external capacitance should be connected here for boosting. c3+, c3 2 booster capacitance external capacitance should be connected here for boosting. c4+, c4 2 booster capacitance external capacitance should be connected here for boosting. c5+, c5 2 booster capacitance external capacitance should be connected here for boosting. c6+, c6 2 booster capacitance external capacitance should be connected here for boosting. reset* 1 i mpu or external r-c circuit reset pin. initializes the lsi when low. must be reset after power-on. opoff 1 i v cc or gnd turns the internal operational amplifier off when opoff = v cc , and turns it on when opoff = gnd. if the amplifier is turned off (opoff = v cc ), v1 to v5 must be supplied to the v1out to v5out pins. vccdum 2 o input pins outputs the internal v cc level; shorting this pin sets the adjacent input pin to the v cc level. gnddum 4 o input pins outputs the internal gnd level; shorting this pin sets the adjacent input pin to the gnd level. dummy 4 dummy pad. must be left disconnected. test 1 i gnd test pin. must be fixed at gnd level. vtest 1 test pin. must be left disconnected. hd66750/1 16 block function description system interface the hd66750/1 has four high-speed system interfaces: an 80-system 16-bit/8-bit bus and a 68-system 16- bit/8-bit bus. the interface mode is selected by the im1-0 pins. the hd66750/1 has three 16-bit registers: an index register (ir), a write data register (wdr), and a read data register (rdr). the ir stores index information from the control registers and the cgram. the wdr temporarily stores data to be written into control registers and the cgram, and the rdr temporarily stores data read from the cgram. data written into the cgram from the mpu is first written into the wdr and then is automatically written into the cgram by internal operation. data is read through the rdr when reading from the cgram, and the first read data is invalid and the second and the following data are normal. when a logic operation is performed inside of the hd66750/1 by using the display data set in the cgram and the data written from the mpu, the data read through the rdr is used. accordingly, the mpu does not need to read data twice nor to fetch the read data into the mpu. this enables high-speed processing. execution time for instruction excluding oscillation start is 0 clock cycle and instructions can be written in succession. table 3 register selection by rs and r/w bits r/w bits rs bits operations 0 0 writes indexes into ir 1 0 disabled 0 1 writes into control registers and cgram through wdr 1 1 reads from cgram through rdr bit operation the hd66750/1 supports the following functions: a bit rotation function that writes the data written from the mpu into the cgram by moving the display position in bit units, a write data mask function that selects and writes data into the cgram in bit units, and a logic operation function that performs logic operations on the display data set in the cgram and writes into the cgram. with the 16-bit bus interface, these functions can greatly reduce the processing loads of the mpu graphics software and can rewrite the display data in the cgram at high speed. for details, see the graphics operation function section. address counter (ac) the address counter (ac) assigns addresses to the cgram. when an address set instruction is written into the ir, the address information is sent from the ir to the ac. after writing into the cgram, the ac is automatically incremented by 1 (or decremented by 1). after reading from the data, the rdm bit automatically updates or does not update the ac. hd66750/1 17 graphic ram (cgram) the graphic ram (cgram) stores bit-pattern data of 128 x 120 dots. it has two bits/pixel and 4096-byte capacity. grayscale control circuit the grayscale control circuit performs four-grayscale control with the frame rate control (frc) method for four-monochrome grayscale display. for details, see the four grayscale display function section. timing generator the timing generator generates timing signals for the operation of internal circuits such as the cgram. the ram read timing for display and internal operation timing by mpu access are generated separately to avoid interference with one another. oscillation circuit (osc) the hd66750/1 can provide r-c oscillation simply through the addition of an external oscillation-resistor between the osc1 and osc2 pins. the appropriate oscillation frequency for operating voltage, display size, and frame frequency can be obtained by adjusting the external-resistor value. clock pulses can also be supplied externally. since r-c oscillation stops during the standby mode, current consumption can be reduced. for details, see the oscillation circuit section. liquid crystal display driver circuit the liquid crystal display driver circuit consists of 128 common signal drivers (com1 to com128) and 128 segment signal drivers (seg1 to seg128). when the number of lines are selected by a program, the required common signal drivers automatically output drive waveforms, while the other common signal drivers continue to output unselected waveforms. display pattern data is latched when 128-bit data has arrived. the latched data then enables the segment signal drivers to generate drive waveform outputs. the shift direction of 128-bit data can be changed by the sgs bit. the shift direction for the common driver can also be changed by the cms bit by selecting an appropriate direction for the device mounting configuration. when multiplexing drive is not used, or during the standby or sleep mode, all the above common and segment signal drivers output the gnd level, halting the display. booster (dc-dc converter) the booster generates two-, five-, six-, or seven-times voltage input to the vci pin. with this, both the internal logic units and lcd drivers can be controlled with a single power supply. boost output level from twice to seven-times boost can be selected by software. for details, see the power supply for liquid crystal display drive section. hd66750/1 18 v-pin voltage follower a voltage follower for each voltage level (v1 to v5) reduces current consumption by the lcd drive power supply circuit. no external resistors are required because of the internal bleeder-resistor, which generates different levels of lcd drive voltage. this internal bleeder-resistor can be software-specified from 1/4 bias to 1/11 bias, according to the liquid crystal display drive duty value. the voltage followers can be turned off while multiplexing drive is not being used. for details, see the power supply for liquid crystal display drive section. contrast adjuster the contrast adjuster can be used to adjust lcd contrast in 64 steps by varying the lcd drive voltage by software. this can be used to select an appropriate lcd brightness or to compensate for temperature. "001"h "011"h "021"h "031"h "041"h "051"h "061"h "071"h "081"h "091"h "0a1"h "0b1"h "0c1"h "0d1"h "0e1"h "0f1"h "101"h "111"h "121"h "131"h "7c1"h "7d1"h "7e1"h "7f1"h table 4 relationship between display position and cgram address hd66750/1 cgram address map note: upper bits: db15, db13, db11, db9, db7, db5, db3, db1 lower bits: db14, db12, db10, db8, db6, db4, db2, db0 hitachi 19 table 5 relationship between cgram data and display contents com1 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d0 seg1/128 seg2/127 seg3/126 seg4/125 seg5/124 seg6/123 seg7/122 seg8/121 seg9/120 segment driver bit sgs="0" sgs="1" d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d1 d14 d15 seg16/113 d0 d0 seg17/112 d15 d1 d14 d15 seg24/105 d0 d0 seg121/8 d15 d1 d14 d15 seg128/1 d0 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 com17 com18 com19 com20 com126 com127 com128 com125 address: "000"h address: "010"h address: "020"h address: "030"h address: "040"h address: "050"h address: "060"h address: "070"h address: "080"h address: "090"h address: "0a0"h address: "0b0"h address: "0c0"h address: "0d0"h address: "0e0"h address: "0f0"h address: "100"h address: "110"h address: "120"h address: "130"h address: "7c0"h address: "7d0"h address: "7e0"h address: "7f0"h "002"h "012"h "022"h "032"h "042"h "052"h "062"h "072"h "082"h "092"h "0a2"h "0b2"h "0c2"h "0d2"h "0e2"h "0f2"h "102"h "112"h "122"h "132"h "7c2"h "7d2"h "7e2"h "7f2"h "00f"h "01f"h "02f"h "03f"h "04f"h "05f"h "06f"h "07f"h "08f"h "09f"h "0af"h "0bf"h "0cf"h "0df"h "0ef"h "0ff"h "10f"h "11f"h "12f"h "13f"h "7cf"h "7df"h "7ef"h "7ff"h 0 0 01 10 11 non-selection display (unlit) 1/3- or 1/2-level grayscale display (selected by the gs bit) 2/3-level grayscale display selection display (lit) upper bit lower bit lcd hd66750/1 20 instructions outline the hd66750/1 uses the 16-bit bus architecture. before the internal operation of the hd66750/1 starts, control information is temporarily stored in the registers described below to allow high-speed interfacing with a high-performance microcomputer. the internal operation of the hd66750/1 is determined by signals sent from the microcomputer. these signals, which include the register selection signal (rs), the read/write signal (r/w), and the data bus signals (db15 to db7), make up the hd66750/1 instructions. there are seven categories of instructions that: specify the index read the status control the display control power management process the graphics data set internal cgram addresses transfer data to and from the internal cgram normally, instructions that write data are used the most. however, an auto-update of internal cgram addresses after each data write can lighten the microcomputer program load. because instructions are executed in 0 cycles, they can be written in succession. hd66750/1 21 instruction descriptions index the index instruction specifies the ram control indexes (r00 to r12). it sets the register number in the range of 00000 to 10010 in biniary form. 0 0 * ** ** * * * * id4 id3 id2 id1 id0 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 * * figure 1 index instruction status read the status read instruction reads the internal status of the hd66750/1. l6e0: indicate the driving raster-row position where the liquid crystal display is being driven. c5e0: read the contrast setting values (ct5e0). 1 0 l6 l5 l4 l3 l2 l1 l0 0 0 c5 c4 c3 c2 c1 c0 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 0 figure 2 status read instruction start oscillation the start oscillation instruction restarts the oscillator from the halt state in the standby mode. after issuing this instruction, wait at least 10 ms for oscillation to stabilize before issuing the next instruction. (see the standby mode section.) if this register is read forcibly when r/w = 1, 0750h is read. 0 1 * * * * * * * 1 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 * * * * * * * * 1 1 0 0 0 0 1 0 1 0 1 1 1 0 0 0 0 0 figure 3 start oscillation instruction hd66750/1 22 driver output control cms: selects the output shift direction of a common driver. when cms = 0, com1/128 shifts to com1, and com128/1 to com128. when cms = 1, com1/128 shifts to com128, and com128/1 to com1. output position of a common driver shifts depending on the cn bit setting. sgs: selects the output shift direction of a segment driver. when sgs = 0, seg1/128 shifts to seg1, and seg128/1 to seg128. when sgs = 1, seg1/128 shifts to seg128, and seg128/1 to seg1. cn: when cn = 1, the display position is shifted down by 32 raster-rows and display starts from com33. when the liquid crystal is driven at a low duty ratio in the system wait state, it can be partially displayed at the center of the screen. for details, see the partial-display-on function section. nl3-0: specify the lcd drive duty ratio. the duty ratio can be adjusted for every eight raster-rows. cgram address mapping does not depend on the setting value of the drive duty ratio. 0 1 cms sgs r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 nl0 nl1 nl2 nl3 cn * * * * * * *** figure 4 driver output control instruction table 6 nl bits and drive duty nl3 nl2 nl1 nl0 display size lcd drive duty common driver used 0000 128 x 8 dots 1/8 duty com1ecom8 0001 128 x 16 dots 1/16 duty com1ecom16 0010 128 x 24 dots 1/24 duty com1ecom24 0011 128 x 32 dots 1/32 duty com1ecom32 0100 128 x 40 dots 1/40 duty com1ecom40 0101 128 x 48 dots 1/48 duty com1ecom48 0110 128 x 56 dots 1/56 duty com1ecom56 0111 128 x 64 dots 1/64 duty com1ecom64 1000 128 x 72 dots 1/72 duty com1ecom72 1001 128 x 80 dots 1/80 duty com1ecom80 1010 128 x 88 dots 1/88 duty com1ecom88 1011 128 x 96 dots 1/96 duty com1ecom96 1100 128 x 104 dots 1/104 duty com1ecom104 1101 128 x 112 dots 1/112 duty com1ecom112 1110 128 x 120 dots 1/120 duty com1ecom120 1111 128 x 128 dots 1/128 duty com1ecom128 hd66750/1 23 lcd-driving-waveform control b/c: when b/c = 0, a b-pattern waveform is generated and alternates in every frame for lcd drive. when b/c = 1, a c-pattern waveform is generated and alternates in each raster-row specified by bits eor and nw4enw0 in the lcd-driving-waveform control register. for details, see the n-raster-row reversed ac drive section. eor: when the c-pattern waveform is set (b/c = 1) and eor = 1, the odd/even frame-select signals and the n-raster-row reversed signals are eored for alternating drive. eor is used when the lcd is not alternated by combining the set values of the lcd drive duty ratio and the n raster-row. for details, see the n-raster-row reversed ac drive section. nw4e0: specify the number of raster-rows n that will alternate at the c-pattern waveform setting (b/c = 1). nw4enw0 alternate for every set value + 1 raster-row, and the first to the 32nd raster-rows can be selected. 0 1 nw1 nw0 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 nw2 nw3 nw4 eor * b/c ** * * * * * * figure 5 lcd-driving-waveform control instruction hd66750/1 24 table 7 common driver pin function common driver pin function cn = 0 (normal output) cn = 1 (center output) common driver pin cms = 0 cms = 1 cms = 0 cms = 1 com1/128 com1 com128 com97 com96 com8/121 com8 com121 com104 com89 com9/120 com9 com120 com105 com88 com16/113 com16 com113 com112 com81 com17/112 com17 com112 com113 com80 com24/105 com24 com105 com120 com73 com25/104 com25 com104 (com121) com72 com32/97 com32 com97 (com128) com65 com33/96 com33 com96 com1 com64 com40/89 com40 com89 com8 com57 com41/88 com41 com88 com9 com56 com48/81 com48 com81 com16 com49 com49/80 com49 com80 com17 com48 com56/73 com56 com73 com24 com41 com57/72 com57 com72 com25 com40 com64/65 com64 com65 com32 com33 com65/64 com65 com64 com33 com32 com72/57 com72 com57 com40 com25 com73/56 com73 com56 com41 com24 com80/49 com80 com49 com48 com17 com81/48 com81 com48 com49 com16 com88/41 com88 com41 com56 com9 com89/40 com89 com40 com57 com8 com96/33 com96 com33 com64 com1 hd66750/1 25 table 7 common driver pin function (cont) common driver pin function cn = 0 (normal output) cn = 1 (center output) common driver pin cms = 0 cms = 1 cms = 0 cms = 1 com97/32 com97 com32 com65 (com128) com104/25 com104 com25 com72 (com121) com105/24 com105 com24 com73 com120 com112/17 com112 com17 com80 com113 com113/16 com113 com16 com81 com112 com120/9 com120 com9 com88 com105 com121/8 com121 com8 com89 com104 com128/1 com128 com1 com96 com97 power control bs2e0: the lcd drive bias value is set within the range of a 1/4 to 1/11 bias. the lcd drive bias value can be selected according to its drive duty ratio and voltage. for details, see the liquid crystal display drive bias selector section. bt1-0: the output factor of v5out between two-times, three-times, four-times, five-times, six-times, and seven-times boost is switched. the lcd drive voltage level can be selected according to its drive duty ratio and bias. lower amplification of the booster consumes less current. dc1-0: the operating frequency in the booster is selected. when the boosting operating frequency is high, the driving ability of the booster and the display quality become high, but the current consumption is increased. adjust the frequency considering the display quality and the current consumption. ap1-0: the amount of fixed current from the fixed current source in the operational amplifier for v pins (v1 to v5) is adjusted. when the amount of fixed current is large, the driving ability of the booster and the display quality become high, but the current consumption is increased. adjust the fixed current considering the display quality and the current consumption. during no display, when ap1e0 = 00, the current consumption can be reduced by ending the operational amplifier and booster operation. hd66750/1 26 table 8 bs bits and lcd drive bias value bs2 bs1 bs0 lcd drive bias value 0 0 0 1/11 bias drive 0 0 1 1/10 bias drive 0 1 0 1/9 bias drive 0 1 1 1/8 bias drive 1 0 0 1/7 bias drive 1 0 1 1/6 bias drive 1 1 0 1/5 bias drive 1 1 1 1/4 bias drive table 9 bt bits and output level bt1 bt0 v5out output level 0 0 two-times boost 0 1 five-times boost 1 0 six-times boost 1 1 seven-times boost table 10 dc bits and operating clock frequency dc1 dc0 operating clock frequency in the booster 0 0 32-divided clock 0 1 16-divided clock 1 0 8-divided clock 1 1 4-divided clock table 11 ap bits and amount of fixed current ap1 ap0 amount of fixed current in the operational amplifier 0 0 operational amplifier and booster do not operate. 0 1 small 1 0 middle 1 1 large slp: when slp = 1, the hd66750/1 enters the sleep mode, where the internal display operations are halted except for the r-c oscillator, thus reducing current consumption. for details, see the sleep mode section. only the following instructions can be executed during the sleep mode. power control (bs2e0, bt1e0, dc1e0, ap1e0, slp, and stb bits) during the sleep mode, the other cgram data and instructions cannot be updated although they are hd66750/1 27 retained. stb: when stb = 1, the hd66750/1 enters the standby mode, where display operation completely stops, halting all the internal operations including the internal r-c oscillator. further, no external clock pulses are supplied. for details, see the standby mode section. only the following instructions can be executed during the standby mode. a. standby mode cancel (stb = 0) b. start oscillation c. power control (bs2e0, bt1e0, dc1e0, ap1e0, slp, and stb bits) during the standby mode, the cgram data and instructions may be lost. to prevent this, they must be set again after the standby mode is canceled. 0 1 * * * bs2 bs1 bs0 slp stb r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 ap0 ap1 * * dc0 dc1 bt1 bt0 figure 6 power control instruction hd66750/1 28 contrast control ct5e0: these bits control the lcd drive voltage (potential difference between v1 and gnd) to adjust 64-step contrast. for details, see the contrast adjuster section. 0 1 * ct1 ct0 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 ct2 ct3 ct4 ct5 ********* figure 7 contrast control instruction v lcd v1 v2 v3 v4 v5 vr r r r 0 r r - + - + - + - + - + gnd hd66750/1 gnd figure 8 contrast adjuster hd66750/1 29 table 12 ct bits and variable resistor value of contrast adjuster ct set value ct5 ct4 ct3 ct2 ct1 ct0 variable resistor (vr) 000000 3.20 x r 000001 3.15 x r 000010 3.10 x r 000011 3.05 x r 000100 3.00 x r 011111 1.65 x r 100000 1.60 x r 100001 1.55 x r 100010 1.50 x r 111101 0.15 x r 111110 0.10 x r 111111 0.05 x r entry mode rotation the write data sent from the microcomputer is modified in the hd66750/1 and written to the cgram. the display data in the cgram can be quickly rewritten to reduce the load of the microcomputer software processing. for details, see the graphics operation function section. i/d: when i/d = 1, the address counter (ac) is automatically incremented by 1 after the data is written to the cgram. when i/d = 0, the ac is automatically decremented by 1 after the data is written to the cgram. am1e0: set the automatic update method of the ac after the data is written to the cgram. when am1e0 = 00, the data is continuously written in parallel. when am1e0 = 01, the data is continuously written vertically. when am1e0 = 10, the data is continuously written vertically with two-word width (32-bit length). lg1e0: write again the data read from the cgram and the data written from the microcomputer to the cgram by a logical operation. when lg1e0 = 00, replace (no logical operation) is done. ored when lg1e0 = 01, anded when lg1e0 = 10, and eored when lg1e0 = 11. rt2e0: write the data sent from the microcomputer to the cgram by rotating in a bit unit. rt3e0 specify rotation. for example, when rt2e0 = 001, the data is rotated in the upper side by two bits. when rt2e0 = 111, the data is rotated in the upper side by 14 bits. the upper bit overflown in the most significant bit (msb) side is rotated in the least significant bit (lsb) side. hd66750/1 30 0 1 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 lg0 lg1 am0 i/d am1 * * 0 1 rt1 rt0 rt2 * * * * * * ***** * * * * * ****** figure 9 entry mode and rotation instructions 00011 db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 10011100011 00 0 11 10011100011 logical operation lg1e0 = 00: replace lg1e0 = 01: ored lg1e0 = 10: anded lg1e0 = 11: eored write data mask (wm15e0) cgram write data sent from the microcomputer (db15e0) rotation (rt2e0 = 001) logical operation (lg1e0) write data mask* (wm15e0) note: the write data mask (wm15e0) is set by the register in the ram write data mask section. figure 10 logical operation and rotation for the cgram hd66750/1 31 display control ps1e0: when ps1e0 = 01, only the upper eight raster-rows (com1ecom8) are fixed-displayed in vertical smooth scrolling, and the other display raster-rows are smooth-scrolled. when ps1e0 = 10, the upper 16 raster-rows (com1ecom16) are fixed-displayed. when ps1e0 = 11, the upper 24 raster-rows (com1e com24) are fixed-displayed. for details, see the partial smooth scroll display function section. dhe: when dhe = 1, the double height between raster-rows specified in the double-height display position section is displayed. for details, see the double-height display section. gs: when gs = 0, the grayscale level at a weak-colored display (db = 01) is 1/3. when gs = 1, the grayscale level at weak-colored display is 1/2, and at strong-colored display (when db = 10) it is 2/3. rev: displays all character and graphics display sections with black-and-white reversal when rev = 1. for details, see the reversed display function section. d: display is on when d = 1 and off when d = 0. when off, the display data remains in the cgram, and can be displayed instantly by setting d = 1. when d is 0, the display is off with the seg1 to seg128 outputs and com1 to com128 outputs set to the gnd level. because of this, the hd66750/1 can control the charging current for the lcd with ac driving. 0 1 d r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 * * * * * * * rev gs dhe ps1 ps0 *** figure 11 display control instruction hd66750/1 32 cursor control c: when c = 1, the window cursor display is started. the display mode is selected by the cm1e0 bits, and the display area is specified in a dot unit by the horizontal cursor position register (hs6e0 and he6e0 bits) and vertical cursor position register (vs6e0 and ve6e0 bits). for details, see the window cursor display section. cm1e0: the display mode of the window cursor is selected. these bits can display a white-blink cursor, black-blink cursor, black-and-white reversed cursor, and black-and-white-reversed blink cursor. 0 1 cm0 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 cm1 **** * * * * **c *** figure 12 cursor control instruction table 13 cm bits and window cursor display mode cm1 cm0 window cursor display mode 0 0 white-blink cursor (alternately blinking between the normal display and an all-white display (all unlit)) 0 1 black-blink cursor (alternately blinking between the normal display and an all-black display (all lit)) 1 0 black-and-white reversed cursor (black-and-white-reversed normal display (no blinking)) 1 1 black-and-white-reversed blink cursor (alternately blinking the black-and-white- reversed normal display) double-height display position ds6e0: specify any common raster-row position where the double-height display starts. note that no scrolling is done by vertical scrolling. for details, see the double-height display section. de6-0: specify any common raster-row position where the double-height display ends. set the end position of the double-height display after the start position of the double-height display, satisfying the relationship ds6e0 de6e0. when the area specifying the double height has an odd number of raster- rows, the double-height display is done for the de6e0 + 1 raster-rows. when the double-height display is not used, set the dhe bit in the display-control instruction register to 0. 0 1 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 * ds6 ds5 ds4 ds3 ds2 ds1 ds0 * de6 de5 de4 de3 de2 de1 de0 figure 13 double-height display position instruction hd66750/1 33 vertical scroll control sl6e0: specify the display start raster-row for vertical smooth scrolling. any raster-row from the first to 128th can be selected (table 14). after the 128th raster-row is displayed, the display restarts from the first raster-row. for details, see the vertical smooth scroll section. in partial smooth scrolling, these bits specify the display start raster-row of the next fixed-display raster- row. for details, see the partial smooth scroll display function section. 0 1 sl1 sl0 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 sl2 * sl6 sl5 sl4 sl3 * * * * * * * * figure 14 vertical scroll control instruction table 14 sl bits and display-start raster-row sl6 sl5 sl4 sl3 sl2 sl1 sl0 display-start raster-row 0000000 1st raster-row 0000001 2nd raster-row 0000010 3rd raster-row 0000011 4th raster-row 0000100 5th raster-row :::::::: 1111110 127th raster-row 1111111 128th raster-row hd66750/1 34 horizontal cursor position vertical cursor position hs6-0: specify the start position for horizontally displaying the window cursor in a dot unit. the cursor is displayed from the 'set value + 1' dot. ensure that hs6e0 he6e0. he6-0: specify the end position for horizontally displaying the window cursor in a dot unit. the cursor is displayed to the 'set value + 1' dot. ensure that hs6e0 he6e0. vs6-0: specify the start position for vertically displaying the window cursor in a dot unit. the cursor is displayed from the 'set value + 1' dot. ensure that vs6e0 ve6e0. ve6-0: specify the end position for vertically displaying the window cursor in a dot unit. the cursor is displayed to the 'set value + 1' dot. ensure that vs6e0 ve6e0. in vertical scrolling, rewrite vs6e0 and ve6e0 since this window cursor does not move vertically. 0 1 hs1 hs0 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 hs2 * hs6 hs5 hs4 hs3 0 1 vs1 vs0 vs2 * vs6 vs5 vs4 vs3 he1 he0 he2 * he6 he5 he4 he3 ve1 ve0 ve2 * ve6 ve5 ve4 ve3 figure 15 horizontal cursor position and vertical cursor position instructions window cursor hs1+1 he1+1 vs1+1 ve1+1 figure 16 window cursor position hd66750/1 35 ram write data mask wm15-0: in writing to the cgram, these bits mask writing in a bit unit. when wm15 = 1, this bit masks the write data of db15 and does not write to the cgram. similarly, the wm14e0 bits mask the write data of db14e0 in a bit unit. however, when am = 10, the write data is masked with the set values of vm15e0 for the odd-times cgram write. it is also masked automatically with the reversed set values of vm15e0 for the even-times cgram write. for details, see the graphics operation function section. 0 1 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 vm 7 vm 6 vm 5 vm 4 vm 3 vm 2 vm 1 vm 0 vm 15 vm 14 vm 13 vm 12 vm 11 vm 10 vm 9 vm 8 figure 17 ram write data mask instruction ram address set ad10-0: initially set cgram addresses to the address counter (ac). once the cgram data is written, the ac is automatically updated according to the am1e0 and i/d bit settings. this allows consecutive accesses without resetting addresses. once the cgram data is read, the ac is not automatically updated. cgram address setting is not allowed in the sleep mode or standby mode. 0 1 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 ad 10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 * * ** * figure 18 ram address set instruction table 15 ad bits and cgram settings ad10ead0 cgram setting "000"he"00f"h bitmap data for com1 "010"he"01f"h bitmap data for com2 "020"he"02f"h bitmap data for com3 "030"he"03f"h bitmap data for com4 :: "760"he"76f"h bitmap data for com119 "770"he"77f"h bitmap data for com120 "780"he"78f"h 121st raster-row data (appeared at vertical scrolling) "790"he"79f"h 122nd raster-row data (appeared at vertical scrolling) "7a0"he"7af"h 123rd raster-row data (appeared at vertical scrolling) "7b0"he"7bf"h 124th raster-row data (appeared at vertical scrolling) "7c0"he"7cf"h 125th raster-row data (appeared at vertical scrolling) "7d0"he"7df"h 126th raster-row data (appeared at vertical scrolling) "7e0"he"7ef"h 127th raster-row data (appeared at vertical scrolling) "7f0"he"7ff"h 128th raster-row data (appeared at vertical scrolling) hd66750/1 36 write data to cgram wd15-0 : write 16-bit data to the cgram. after a write, the address is automatically updated according to the am1e0 and i/d bit settings. during the sleep and standby modes, the cgram cannot be accessed. 0 1 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 wd 15 wd 14 wd 13 wd 12 wd 11 wd 10 wd 9 wd 8 wd 7 wd 6 wd 5 wd 4 wd 3 wd 2 wd 1 wd 0 figure 19 write data to cgram instruction hd66750/1 37 read data from cgram rd15-0 : read 16-bit data from the cgram. when the data is read to the microcomputer, the first-word read immediately after the cgram address setting is latched from the cgram to the internal read-data latch. the data on the data bus (db15e0) becomes invalid and the second-word read is normal. when bit processing, such as a logical operation, is performed within the hd66750/1, only one read can be processed since the latched data in the first word is used. 1 1 r/w rs db7 db0 db6 db5 db4 db3 db2 db1 db8 db9 db10 db11 db12 db13 db14 db15 rd 15 rd 14 rd 13 rd 12 rd 11 rd 10 rd 9 rd 8 rd 7 rd 6 rd 5 rd 4 rd 3 rd 2 rd 1 rd 0 figure 20 read data from cgram instruction address: n set dummy read (invalid data) cgram -> read-data latch read (data of address n) read-data latch -> db15e0 first word second word i) data read to the microcomputer ii) logical operation processing in the hd66750/1 address: m set dummy read (invalid data) cgram -> read-data latch read (data of address) read-data latch -> db15e0 first word second word sets the i/d and am1e0 bits address: n set dummy read (invalid data) cgram -> read-data latch sets the i/d and am1e0 bits read (data of address n) db15e0 -> cgram dummy read (invalid data) cgram -> read-data latch write (data of address n) db15e0 -> cgram automatic address update: m + a first word second word first word second word figure 21 cgram read sequence table 16 instruction list reg. upper code lower code no. register name r/w rs db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 description ir index 0 0 ***********id4id3id2id1id0 sets the index register value. 0 sr status read 1 0 0 l6 l5 l4 l3 l2 l1 l0 0 0 c5 c4 c3 c2 c1 c0 reads the driving raster-row position (l6e0) and contrast setting (c5e0). 0 r00 start oscillation 0 1 ***************1 starts the oscillation mode. 10 ms device code read 110000011101010000 reads 0750h. 0 r01 driver output 0 1 ******cmssgs*cn**nl3nl2nl1nl0 sets the common driver shift direction (cms), segment driver shift direction 0 control (sgs), driving duty ratio (nl3e0), and centering (cn). r02 lcd-driving- 0 1 *********b/ceornw4nw3nw2nw1nw0 sets the lcd drive ac waveform (b/c), and eor output (eor) or the 0 waveform control number of n-raster-rows (nw4e0) at c-pattern ac drive. r03 power control 0 1 * * * bs2 bs1 bs0 bt1 bt0 * * dc1 dc0 ap1 ap0 slp stb sets the sleep mode (slp), standby mode (stb), lcd power on (ap1e0), 0 boosting cycle (dc1e0), boosting ouput multiplying factor (bt1e0), and lcd drive bias value (bs2e0). r04 contrast control 0 1 **********ct5ct4ct3ct2ct1ct0 sets the contrast adjustment (ct5e0). 0 r05 entry mode 0 1 ***********i/dam1am0lg1lg0 specifies the logical operation (lg1e0), ac counter mode (am1e0), and 0 increment/decrement mode (i/d). r06 rotation 0 1 *************rt2rt1rt0 specifies the amount of write-data rotation (rt2e0). 0 r07 display control 0 1 **********ps1ps0dhegsrevd specifies display on (d), black-and-white reversed display (rev), grayscale 0 mode (gs), double-height display on (dhe), and partial scroll (ps1e0). r08 cursor control 0 1 *************ccm1cm0 specifies cursor display on (c) and cursor display mode (cm1e0). r09 double-height display position 0 1 * de6 de5 de4 de3 de2 de1 de0 * ds6 ds5 ds4 ds3 ds2 ds1 ds0 specifies double-height display start (ds6e0) an d end (de6e0). 0 r0a vertical scroll 0 1 *********sl6sl5sl4sl3sl2sl1sl0 sets the display-start raster-row (sl6e0). 0 r0b horizontal cursor position 0 1 * he6 he5 he4 he3 he2 he1 he0 * hs6 hs5 hs4 hs3 hs2 hs1 hs0 sets horizontal cursor start (hs6e0) and end (he6e0) .0 r0c vertical cursor position 0 1 * ve6 ve5 ve4 ve3 ve2 ve1 ve0 * vs6 vs5 vs4 vs3 vs2 vs1 vs0 sets vertical cursor start (vs6e0) and end (ve6e0). 0 r10 ram write data 0 1 wm wm wm wm wm wm wm9 wm8 wm7 wm6 wm5 wm4 wm3 wm2 wm1 wm0 specifies write data mask (wm15e0) at ram write. 0 mask 15 14 13 12 11 10 r11 ram address set 0 1 ***** ad10e8 (upper) ad7e0 (lower) initially sets the ram address to the address counter (ac). 0 r12 ram data write 0 1 write data (upper) write data (lower) writes data to the ram. 0 ram data read 1 1 read data (upper) read data (lower) reads data from the ram. 0 note: '*' means 'doesn't matter'. execu- tion cycle hitachi 38 hd66750/1 39 reset function the hd66750/1 is internally initialized by reset input. because the busy flag (bf) indicates a busy state (bf = 1) during the reset period, no instruction or cgram data access from the mpu is accepted. the reset input must be held for at least 1 ms. do not access the cgram or initially set the instructions until the r-c oscillation frequency is stable after power has been supplied (10 ms). instruction set initialization: 1. start oscillation executed 2. driver output control (cn = 0, nl3e0 = 1111, sgs = 0, cms = 0) 3. b-pattern waveform ac drive (b/c = 0, ecr = 0, nw4e0 = 00000) 4. power control (dc1e0 = 00, ap1e0 = 00: lcd power off, slp = 0: sleep mode off, stb = 0: standby mode off) 5. 1/11 bias drive (bs2e0 = 000), two-times boost (bt1e0 = 00), weak contrast (ct5e0 = 000000) 6. entry mode set (i/d = 1: increment by 1, am1e0 = 00: horizontal move, lg1e0 = 00: replace mode) 7. rotation (rt2e0 = 000: no shift) 8. display control (dhe = 0: double-height display off, rev = 0, gs = 0, d = 0: display off, ps1e0 = 00: partial scroll off) 9. cursor control (c = 0: cursor display off, cm1e0 = 00: white blink cursor) 10. double-height display position (ds6e0 = 0000000, de6e0 = 0000000) 11. vertical scroll control (sl6e0 = 0000000: first raster-row displayed at the top) 12. window cursor display position (hs6e0 = he6e0 = vs6e0 = ve6e0 = 0000000) 13. ram write data mask (wm15e0 = 0000h: no mask) 14. ram address set (ad10e0 = 000h) cgram data initialization: this is not automatically initialized by reset input but must be initialized by software while display is off (d = 0). output pin initialization: 1. lcd driver output pins (seg/com): outputs gnd level 2. booster output pins (vlout): outputs vcc level 3. oscillator output pin (osc2): outputs oscillation signal hd66750/1 40 parallel data transfer 16-bit bus interface setting the im2? (interface mode) to the gnd/gnd level allows 68-system e-clock-synchronized 16-bit parallel data transfer. setting the im1/0 to the vcc/gnd level allows 80-system 16-bit parallel data transfer. when the number of buses or the mounting area is limited, use an 8-bit bus interface. csn* a1 hwr* (rd*) d15?0 cs* rs wr* (rd*) db15?b0 h8/2245 hd66750/1 16 figure 22 interface to 16-bit microcomputer 8-bit bus interface setting the im1/0 (interface mode) to the gnd/vcc level allows 68-system e-clock-synchronized 8-bit parallel data transfer using pins db15?b8. setting the im1/0 to the vcc/vcc level allows 80-system 8- bit parallel data transfer. the 16-bit index register, instructions and ram data are divided into eight upper/lower bits and the transfer starts from the upper eight bits. fix unused pins db7?b0 to the vcc or gnd level. csn* a1 hwr* (rd*) d15?8 cs* rs wr* (rd*) db15?b8 db7? h8/2245 hd66750/1 8 8 gnd figure 23 interface to 8-bit microcomputer note: transfer synchronization function for an 8-bit bus interface the hd66750/1 supports the transfer synchronization function which resets the upper/lower counter to count upper/lower 8-bit data transfer in the 8-bit bus interface. noise causing transfer mismatch between the eight upper and lower bits can be corrected by a reset triggered by consecutively writing a 00h instruction four times. the next transfer starts from the upper eight bits. executing synchronization function periodically can recover any runaway in the display system. hd66750/1 41 00h 00h 00h 00h rs r/w e db15e db8 upper lower (8-bit transfer synchronization) (1) (2) (3) (4) upper/ lower figure 24 8-bit transfer synchronization hd66750/1 42 graphics operation function the hd66750/1 can greatly reduce the load of the microcomputer graphics software processing through the 16-bit bus architecture and graphics-bit operation function. this function supports the following: 1. a write data mask function that selectively rewrites some of the bits in the 16-bit write data. 2. a bit rotation function that shifts and writes the data sent from the microcomputer in a bit unit. 3. a logical operation function that writes the data sent from the microcomputer and the original ram data by a logical operation. s inc e t he di s pla y dat a i n t he gra phi cs r am (c gr am ) ca n be qui ckl y re wri t t en, t he l oad of t he m i croc om pute r proc es s i ng ca n be re duce d i n t he l ar ge di s pla y s cr ee n whe n a font pat t er n, s uch as k anj i characters, is developed for any position (bitblt processing). the gra phi cs bi t oper at i on ca n be cont r oll e d by com bi ni ng t he ent r y m ode re gi st e r, t he bi t s et va l ue of t he ram-write-data mask register, and the read/write from the microcomputer. table 17 graphics operation bit setting operation mode i/d am lg operation and usage write mode 1 0/1 00 00 horizontal data replacement, horizontal-border drawing write mode 2 0/1 01 00 vertical data replacement, font development, vertical- border drawing write mode 3 0/1 10 00 vertical data replacement with two-word width, kanji- font development read/write mode 1 0/1 00 01 10 11 horizontal data replacement with logical operation, horizontal-border drawing read/write mode 2 0/1 01 01 10 11 vertical data replacement with logical operation, vertical-border drawing read/write mode 3 0/1 10 01 10 11 horizontal data replacement with two-word-width logical operation hd66750/1 43 read- data latch bit rotation logical operation write bit mask write-data latch graphics ram (cgram) microcomputer address counter (ac) rotation bit (rt2e0) logical operation bit (lg1e0) 2 3 16 16 write-mask register (wm15e0) 16 11 16 +1/e1 +16 16 16 16 hd66750/1 00: through 01: or 10: and 11: eor figure 25 data processing flow of the graphics bit operation 1. write mode 1: am1e0 = 00, lg1e0 = 00 this mode is used when the data is horizontally written at high speed. it can also be used to initialize the gra phi cs r am (c gr am ) or t o dra w borde rs . the rot a ti on func t ion (r t2e0) or wr it e -dat a m as k func t ion (w m 15e0) ar e al s o ena bl ed i n t hes e oper at i ons . af te r wr it i ng, t he addr es s count e r (a c) aut om at i ca l ly i ncr em ent s by 1 (i /d = 1) or dec re me nt s by 1 (i /d = 0), and aut om at i ca l ly j um ps t o t he counter edge one-raster-row below after it has reached the left edge of the graphics ram. hd66750/1 44 wm0 wm15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 db0 db15 1 0 0 1 1 0 0 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 0 1 1 1 1 1 000h 001h 002h cgram 1) i/d = 1, am1e0 = 00, lg1e0 = 00, rt2e0 = 000 2) wm15e0 = 0000h 3) ac = 000h operation examples: write data mask: write data (1) : write data (2) : write data (3) : write data (1) write data (2) write data (3) figure 26 writing operation of write mode 1 2. write mode 2: am1e0 = 01, lg1e0 = 00 thi s m ode i s us ed whe n t he dat a i s ver t ic al l y wr it t en at hi gh s pee d. it ca n al s o be us ed t o i ni ti a li z e t he gra phi cs r am (c gr am ), deve l op t he font pat t er n i n t he ver t ic al di re ct i on, or dra w borde rs . the rotation function (rt2e0) or write-data mask function (wm15e0) are also enabled in these operations. after writing, the address counter (ac) automatically increments by 16, and automatically jumps to the upper-right edge (i/d = 1) or upper-left edge (i/d = 0) following the i/d bit after it has reached the lower edge of the graphics ram. wm0 wm15 1) i/d = 1, am1e0 = 01, lg1e0 = 00, rt2e0 = 010 2) wm15e0 = f007h 3) ac = 000h write data mask: 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 db0 db15 write data (1) : 1 0 0 1 1 0 0 1 0 1 0 0 0 0 1 1 write data (2) : 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 write data (3) : 0 1 1 1 0 1 0 0 0 0 0 1 1 1 1 1 000h cgram 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 1 0 1 0 0 1 4-bit rotation 010h 020h * * * * * * * * * * * * * * * * * * * * * 1 0 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 1 0 1 0 0 1 4-bit rotation 4-bit rotation operation examples: write data (1) write data (2) write data (3) notes: 1. the bit area data in the ram indicated by '*' is not changed. 2. after writing to address 7f0h, the ac jumps to 001h. figure 27 writing operation of write mode 2 hd66750/1 45 3. write mode 3: am1e0 = 10, lg1e0 = 00 this mode is used when the data is written at high speed by vertically shifting bits. it can also be used to wr it e t he 16-bi t dat a for t wo wor ds i nt o t he gra phi cs r am (c gr am ), deve l op t he font pat t er n, or transfer the bitblt as a bit unit. the rotation function (rt2e0) or write-data mask function (wm15e0) ar e al s o ena bl ed i n t hes e oper at i on. howe ver , al t hough t he wr it e -dat a m as k func t ion m as ks t he bi t pos i ti on s et wi t h t he wr it e -dat a m as k re gi st e r (w m 15e0) at t he odd-t i m es (s uc h as t he fi rs t o r t hi rd) wr it e , t he func t ion m as ks t he bi t pos i ti on t hat re ver se d t he s et t i ng val ue of t he wr it e -dat a m as k re gi st e r (w m 15e0) at t he eve n-t i m es (s uc h as t he s ec ond or four th) wr it e . af ter t he odd-t i m es wr it i ng, t he addr es s count e r (a c) aut om at i ca l ly i ncr em ent s by 1 (i /d = 1) or dec re me nt s by 1 (i /d = 0). af te r t he even-times writing, the ac automatically increments or decrements by e1 + 16 (i/d = 1) or +1 + 16 (i/d = 0). the ac automatically jumps to the upper edge after it has reached the lower edge of the graphics ram. wm0 wm15 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 db0 db15 1 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 000h write data (1), (2) cgram 010h 020h write data (3), (4) write data (5), (6) * 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 1 1 1 1 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 000h 001h 0 0 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 1 0 0 0 * * * * * * * * * * * * * * * * 0 0 1 0 0 0 0 1 1 1 1 1 1 0 0 0 7f0h 1) i/d = 1, am1e0 = 10, lg1e0 = 00, rt2e0 = 010 2) wm15e0 = 0007h 3) ac = 000h write data mask: write data (1) : write data (2) : write data (3) : 4-bit rotation 4-bit rotation 4-bit rotation operation examples: write data (4) : write data (5) : write data (6) : 4-bit rotation 4-bit rotation 4-bit rotation notes: 1. the bit area data in the ram indicated by '*' is not changed. 2. after writing to address 7f0h, the ac jumps to 001h. figure 28 writing operation of write mode 3 hd66750/1 46 4. read/write mode 1: am1e0 = 00, lg1e0 = 01/10/11 this mode is used when the data is horizontally written at high speed by performing a logical operation wi t h t he ori gi nal dat a . it re ads t he di s pla y dat a (or igi na l dat a ), whi ch has al r eady bee n wr it t e n i n t he gra phi cs r am (c gr am ), per form s a l ogi cal oper at i on wi t h t he wr it e dat a s ent fr om t he microcomputer, and rewrites the data to the cgram. this mode can read the data during the same bus cycle as for the write operation since the read operation of the original data does not latch the read data into the microcomputer and temporarily holds it in the read-data latch. the rotation function (rt2e0) or wr it e -dat a m as k func t ion (w m 15e0) ar e al s o ena bl ed i n t hes e oper at i ons . af te r wr it i ng, t he addr es s count e r (a c) aut om at i ca l ly i ncr em ent s by 1 (i /d = 1) or dec re ment s by 1 (i /d = 0), and aut om at i ca l ly jumps to the counter edge one-raster-row below after it has reached the left or right edges of the graphics ram. wm0 wm15 write data mask: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 db0 db15 write data (1): 1 0 1 1 1 1 0 0 0 1 1 0 0 0 0 1 write data (2): 1 1 0 0 0 0 1 1 1 0 0 0 1 1 0 0 write data (3): 0 1 1 1 0 1 0 0 0 0 0 1 1 1 1 1 000h 001h 002h read data (1) + write data (1) cgram read data (1): 1 0 0 1 1 0 0 1 0 1 0 0 0 0 1 1 read data (2): 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 read data (3): 0 0 0 0 1 1 1 0 1 0 0 0 0 1 1 0 1 0 1 1 1 1 0 1 0 1 1 0 0 0 1 1 1 1 0 0 1 1 1 1 1 0 0 0 1 1 0 0 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1 1 logical operation (or) logical operation (or) logical operation (or) 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 1 1 1 0 1 0 1 1 0 0 0 1 1 read data (2) + write data (2) read data (3) + write data (3) 1) i/d = 1, am1e0 = 00, lg1e0 = 01 (or), rt2e0 = 000 2) wm15e0 = 0000h 3) ac = 000h operation examples: figure 29 writing operation of read/write mode 1 5. read/write mode 2: am1e0 = 01, lg1e0 = 01/10/11 thi s m ode i s us ed whe n t he dat a i s ver t ic al l y wr it t en at hi gh s pee d by per form i ng a l ogi cal oper at i on wi t h t he ori gi nal dat a . it re ads t he di s pla y dat a (or igi na l dat a ), whi ch has al r eady bee n wr it t e n i n t he gra phi cs r am (c gr am ), per form s a l ogi cal oper at i on wi t h t he wr it e dat a s ent fr om t he microcomputer, and rewrites the data to the cgram. this mode can read the data during the same bus cycle as for the write operation since the read operation of the original data does not latch the read data into the microcomputer and temporarily holds it in the read-data latch. the rotation function (rt2e0) or wr it e -dat a m as k func t ion (w m 15e0) ar e al s o ena bl ed i n t hes e oper at i ons . af te r wr it i ng, t he addr es s counter (ac) automatically increments by 16, and automatically jumps to the upper-right edge (i/d = 1) or upper -l ef t edge (i /d = 0) fol l owi ng t he i/ d bi t af t er i t has re ac hed t he l ower edge of t he gra phi cs ram. hd66750/1 47 wm0 wm15 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 db0 db15 1 0 1 1 1 1 0 0 0 1 1 0 0 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 0 0 1 1 0 000h cgram 010h 020h * * * * * * * * * * * * * * * * * * 4-bit rotation 4-bit rotation 4-bit rotation 1 1 0 1 1 1 1 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 0 1 1 1 0 0 0 1 1 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 * * * * * * 1 1 0 1 1 1 1 0 0 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 7f0h 101111000110 00 0 1 11 00 00 1 110 00 1 100 01 1 10 100 00 0 1 1111 000h 001h write data mask: write data (1): write data (2): write data (3): read data (1) + write data (1) read data (1): read data (2): read data (3): logical operation (or) logical operation (or) logical operation (or) read data (2) + write data (2) read data (3) + write data (3) 1) i/d = 1, am1e0 = 01, lg1e0 = 01 (or), rt2e0 = 010 2) wm15e0 = fc03h 3) ac = 000h operation examples: notes: 1. the bit area data in the ram indicated by '*' is not changed. 2. after writing to address 7f0h, the ac jumps to 001h. figure 30 writing operation of read/write mode 2 6. read/write mode 3: am1e0 = 10, lg1e0 = 01/10/11 this mode is used when the data is written with high speed by vertically shifting bits and by performing logical operation with the original data. it can be also used to write the 16-bit data for two words into the graphics ram (cgram), develop the font pattern, or transfer the bitblt as a bit unit. this mode can read the data during the same bus cycle as for the write operation since the read operation of the original data does not latch the read data into the microcomputer and temporarily holds it in the read-data latch. the rot a ti on func t ion (r t2e0) or wr it e -dat a m as k func t ion (w m 15e0) ar e al s o ena bl ed i n t hes e oper at i ons . howe ver, al t hough t he wr it e -dat a m as k func t ion m as ks t he bi t pos i ti on s et wi t h t he wr it e - data mask register (wm15e0) at the odd-times (such as the first or third) write, the function masks the bit pos i ti on whi ch re ver se d t he s et t i ng val ue of t he wr it e -dat a m as k re gi st e r (w m 15e0) at t he eve n-t i m es (s uc h as t he s ec ond or four th) wr it e . af te r t he odd-t i m es wr it i ng, t he addr es s count e r (a c) automatically increments by 1 (i/d = 1) or decrements by 1 (i/d = 0). after the even-times writing, the ac aut om at i ca l ly i ncr em ent s or dec re me nt s by e1 + 16 (i /d = 1) or + 1 + 16 (i /d = 0). the ac automatically jumps to the upper edge after it has reached the lower edge of the graphics ram. hd66750/1 48 wm0 wm15 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 db0 db15 1 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 000h write data (1), (2) cgram 010h write data (3), (4) * 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 000h 001h 7f0h 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 1 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 0 0 1 1 0 1 1 0 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 0 0 0 0 0 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 1 0 1 1 0 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 4-bit rotation 4-bit rotation 4-bit rotation write data mask: write data (1): write data (2): write data (3): read data (1): read data (2): read data (3): logical operation (or) logical operation (or) logical operation (or) 1) i/d = 1, am1e0 = 10, lg1e0 = 01, rt2e0 = 010 2) wm15e0 = 000fh 3) ac = 000h operation examples: write data (4): read data (4): 4-bit rotation logical operation (or) notes: 1. the bit area data in the ram indicated by '*' is not changed. 2. after writing to address 7f0h, the ac jumps to 001h. figure 31 writing operation of read/write mode 3 hd66750/1 49 oscillation circuit the hd66750/1 can either be supplied with operating pulses externally (external clock mode) or oscillate using an internal r-c oscillator with an external oscillator-resistor (external resistor oscillation mode). note that in r-c oscillation, the oscillation frequency is changed according to the internal capacitance value, the external resistance value, or operating power-supply voltage. 1) external clock mode 2) external resistor oscillation mode osc1 osc1 osc2 clock (70 khz) rf the oscillator frequency can be adjusted by oscillator resistor (rf). if rf is increased or power supply voltage is decreased, the oscillation frequency decreases. for the relationship between rf resistor value and oscillation frequency, see the electric characteristics notes section. hd66750/1 hd66750/1 dumping resistance (1.5 k w ) figure 32 oscillation circuits table 18 relationship between liquid crystal drive duty ratio and frame frequency lcd duty nl3e0 set value recommended drive bias value frame frequency one-frame clock 1/16 0001 1/6 70 hz 1024 1/24 0010 1/6 70 hz 1032 1/32 0011 1/6 70 hz 1024 1/40 0100 1/7 69 hz 1040 1/48 0101 1/8 71 hz 1008 1/56 0110 1/8 71 hz 1008 1/64 0111 1/9 70 hz 1024 1/72 1000 1/9.5 71 hz 1008 1/80 1001 1/10 69 hz 1040 1/88 1010 1/10 68 hz 1056 1/96 1011 1/10 68 hz 1056 1/104 1100 1/11 69 hz 1040 1/112 1101 1/11 71 hz 1008 1/120 1110 1/11 67 hz 1080 1/128 1111 1/11 70 hz 1024 note: the frame frequency above is for 72-khz operation and proportions the oscillation frequency (fosc). hd66750/1 50 1 2 3 4 127 128 1 2 3 127 128 v1 v2 v5 gnd com1 v2 v5 gnd com2 1 frame 1 frame v1 v2 v5 gnd com127 v1 v2 v5 gnd com128 v1 figure 33 lcd drive output waveform (b-pattern ac drive with 1/128 multiplexing duty ratio) hd66750/1 51 n-raster-row reversed ac drive the hd66750/1 supports not only the lcd reversed ac drive in a one-frame unit (b-pattern waveform) but also the n-raster-row reversed ac drive which alternates in an n-raster-row unit from one to 32 raster- rows (c-pattern waveform). when a problem affecting display quality occurs, such as crosstalk at high- duty driving of more than 1/64 duty, the n-raster-row reversed ac drive (c-pattern waveform) can improve the quality. determine the number of raster-rows n (nw bit set value + 1) for alternating after confirmation of the display quality with the actual lcd panel. however, if the number of ac raster-rows is reduced, the lcd alternating frequency becomes high. because of this, the charge or discharge current is increased in the lcd cells. 1 2 3 4 5 6 7 8 9 10111213 7980 1 2 3 4 5 6 7 8 9 10111213 7980 1 2 3 b-pattern waveform drive 1/80 duty 1 frame 1 frame c-pattern waveform drive 1/80 duty 11-raster-row reversal without eors c-pattern waveform drive 1/80 duty 11-raster-row reversal with eors note: specify the number of ac drive raster-rows and the necessity of eor so that the dc bias is not generated for the liquid crystal. figure 34 example of an ac signal under n-raster-row reversed ac drive hd66750/1 52 liquid crystal display voltage generator when external power supply and internal operational amplifiers are used to supply lcd drive voltage directly from the external power supply without using the internal booster, circuits should be connected as shown in figure 35. here, contrast can be adjusted by software through the ct bits of the contrast adjustment register. the hd66750/1 incorporates a voltage-follower operational amplifier for each v1 to v5 to reduce current flowing through the internal bleeder-resistors, which generate different levels of liquid-crystal drive voltages. thus, potential difference between v lcd and v1 must be 0.1 v or higher, and that between v4 and gnd must be 1.4 v or higher. note that the opoff pin must be grounded when using the operational amplifiers. place a capacitor of about 0.47 m f (b characteristics) between each internal operational amplifier (v1out to v5out outputs) and gnd and stabilize the output level of the operational amplifier. adjust the capacitance value of the stabilized capacitor after the lcd panel has been mounted and the screen quality has been confirmed. hd66750/1 53 c1+ v lcd v lcd vr r 0 r r r - + - + - + - + - + gnd opoff = gn d r hd66750/1 v 1out v 2out v 3out v 4out v 5out seg1 to seg128 com1 to com12 gnd vci c1- c2+ c2- v lout 0.47 m f* (b characteristics) c3+ c3- c4+ c4- c5+ c5- c6+ c6- note: a djust the capacitance value of the capacitor after the lcd p anel has b een mounted. the capacitors connected to v 1out to v 5out/gnd should b e more the v lcd voltage. the voltage of these capacitors should b e determined with fluctuation of voltage. booste r lc d driver v1 v3 v4 v2 v5 gnd figure 35 external power supply circuit for lcd drive voltage generation when an internal booster and internal operational amplifiers are used to supply lcd drive voltage using the internal booster, circuits should be connected as shown in figure 36. here, contrast can be adjusted through the ct bits of the contrast control instruction. temperature can be compensated either through the ct bits or by controlling the reference voltage for the booster (vci pin) using a thermistor. note that vci is both a reference voltage and power supply for the booster. the reference voltage must therefore be adjusted using an emitter-follower or a similar element so that sufficient current can be supplied. in this case, vci must be equal to or smaller than the v cc level. hd66750/1 54 the hd66750/1 incorporates a voltage-follower operational amplifier for each of v1 to v5 to reduce current flowing through the internal bleeder-resistors, which generate different liquid-crystal drive voltages. thus, potential difference between v lcd and v1 must be 0.1 v or higher, and that between v4 and gnd must be 1.4 v or higher. note that the opoff pin must be grounded when using the operational amplifiers. place a capacitor of about 0.47 m f (b characteristics) between each internal operational amplifier (v1out to v5out outputs) and gnd and stabilize the output level of the operational amplifier. adjust the capacitance value of the stabilized capacitor after the lcd panel has been mounted and the screen quality has been confirmed. hd66750/1 55 v lcd vr r 0 r r r - + - + - + - + - + gnd c1+ c1- vci vlou t gnd c2+ c2- (+) booster o po ff = g nd r hd6 6750/1 v1out v2out v3out v4out v5out lcd driver seg1 to seg128 co m 1 to co m12 8 v1 v3 v4 v2 v5 gnd 0.47 m f* (b characteristics ) gnd vci c3+ c3- c4+ c4- 1 m f (b charac- teris tic s) no t es : 1. the reference voltage input (vci) mus t be adjus ted s o that the outp ut voltage after boos ting will not ex c the ab solute maximum rating f or the liquid-crystal power s up ply v oltage (16.5 v) . 2. vci is both a reference v oltage and p ow er supp ly for the boost er; connect it to vcc directly or comb ine i t with a t rans istor so t hat suff icient current can b e obt ained. 3. polariz ed capacitors m us t be connected correctly. 4. circuits for temp erature comp ensat ion s hould b e b as ed on the sampl e circuits in figure 37. 5. adjust the capacitance value of the stab ilized capacitor aft er the lcd panel has been m ounted. 6. the cap acitors connected to c3+/ c3e and c 6+ /c 6e should three times or more the vci v oltage. 7. the cap acitors connected to c1+/ c1e, c2+/ c2e, c 4+ /c 4e and c5+/ c5e s hould b e more the v ci volt a 8. the cap acitors connected to vlou t/gnd and v 1ou t to v5out/ gnd should be more the n times vci v oltage. (n: b oost ing factor) 9. the v oltage of these capacitors should be determi ned with fluctuation of voltage. c5+ c5- c6 + c6- (+) 1 m f (b charac- teristics) (+) 1 m f (b charac- teristics) (+) 1 m f (b charac- teristic s) (+) 1 m f (b charac- teristic s) (+) 1 m f (b charac- teristic s) (+) 1 m f (b charac- teristics) figure 36 internal booster for lcd drive voltage generation hd66750/1 56 vcc thermistor gnd tr vcc vci hd66750/1 1 m f (b charac-teristics) thermistor gnd tr vcc vci hd66750/1 gnd (+) (examp le 1) (examp le 2) figure 37 temperature compensation circuits switching the boosting factor instruction bits (bt1/0 bits) can optionally select the boosting factor of the internal booster. according to the display status, power consumption can be reduced by changing the lcd drive duty and the lcd drive bias, and by controlling the boosting factor for the minimum requirements. for details, see the partial- display-on function section. because of the maximum boosting factor, external capacitors need to be connected. for example, when the maximum boosting is six times or five times, capacitors between c6+ and c6e or between c5+ and c5e are needed as well, as in the case of the seven-times boosting. when the boosting is two-times boosting, capacitors between c1+ and c1e or between c4+ and c4e are not needed. place a capacitor with a voltage of three times or more the vci-gnd voltage between c6+ and c6e and between c3+ and c3e, and a capacitor with a voltage larger than the vci-gnd voltage between c1+ and c1e, c2+ and c2e, c4+ and c4e, and c5+ and c5e. place a capacitor with a voltage of n times thevci-gnd voltage between vlout and gnd. (n: boosting factor) note that each capacitors with a voltage should be determined with a voltage fluctuation. table 19 vlout output status bt1 bt0 vlout output status 0 0 two-times boosting output 0 1 five-times boosting output 1 0 six-times boosting output 1 1 seven-times boosting output hd66750/1 57 ii) maximum six-times boosting iii) maximum five-times boosting iv) maximum two-times boosting c1+ c1- vci vlout gnd c2+ c2- vci c3+ c3- i) maximum seven-times boosting c4+ c4- c5+ c5- c6+ c6- (+) 1 m f (b charac- teristics) (+) 1 m f (b charac- teristics) (+) 1 m f (b charac- teristics) (+) 1 m f (b charac- teristics) (+) 1 m f (b charac- teristics) (+) 1 m f (b charac- teristics) (+) 1 m f (b charac- teristics) c1+ c1- vci vlout gnd c2+ c2- vci c3+ c3- c4+ c4- c5+ c5- c6+ c6- (+) 1 m f (b charac- teristics) (+) 1 m f (b charac- teristics) (+) 1 m f (b charac- teristics) (+) 1 m f (b charac- teristics) (+) 1 m f (b charac- teristics) (+) 1 m f (b charac- teristics) (+) 1 m f (b charac- teristics) c1+ c1- vci vlout gnd c2+ c2- vci c3+ c3- c4+ c4- c5+ c5- c6+ c6- (+) 1 m f (b charac- teristics) (+) 1 m f (b charac- teristics) (+) 1 m f (b charac- teristics) (+) 1 m f (b charac- teristics) (+) 1 m f (b charac- teristics) (+) 1 m f (b charac- teristics) (+) 1 m f (b charac- teristics) c1+ c1- vci vlout gnd c2+ c2- vci c3+ c3- c4+ c4- c5+ c5- c6+ c6- (+) 1 m f (b charac- teristics) (+) 1 m f (b charac- teristics) (+) 1 m f (b charac- teristics) (+) 1 m f (b charac- teristics) (+) 1 m f (b charac- teristics) figure 38 booster output factor switching hd66750/1 58 example of power-supply voltage generator for more than seven-times boosting output the hd66750/1 incorporates a booster for up to seven-times boosting. however, the lcd drive voltage (vlcd) will not be enough for seven-times boosting from vcc when the power-supply voltage of vcc is low or when the lcd drive voltage is high for the high-contrast lcd display. in this case, the reference voltage (vci) for boosting can be set higher than the power-supply voltage of vcc. when the boosting factor is high, the current driving ability is lowered and insufficient display quality may result. in this case, the boosting ability can be improved by decreasing the boosting factor as shown in the booster in figure 39. set the vci input voltage for the booster to 3.6 v or less within the range of vcc + 1.0 v. control the vci voltage so that the boosting output voltage (vlout) should be less than the absolute maximum ratings (16.5 v). c1+ c1 e vci vlout gnd c2+ c2 e b ooster c3+ c3 e c4+ c4 e lcd driver se g 1 t o se g 1 2 8 com1 t o com12 8 regu- lator (2) vci regu- lator (1) vcc l ogic circuit 1. 8 v 2. 2 v vlcd gnd gnd gnd 2.2 v x 7 = 15.4 v b attery 3. 6 v gnd (= 0 v) vcc (= 1. 8 v) vci (= 2. 2 v) hd66750/ 1 vlcd (= 15.4 v) c5+ c5 e c6+ c6 e note: i n pract ice, t he lcd drive current lowers t he volt age in t he bo ost ing out pu t volt age. (+) 1 m f (b charac- teri s tics ) (+) 1 m f (b chara c- teristic s) (+) 1 m f (b chara c- teristic s) (+) 1 m f (b ch arac- teristi cs) (+) 1 m f (b ch arac- teristi cs) (+) 1 m f (b ch arac- teristi cs) (+) 1 m f (b charac- teri s tics ) figure 39 usage example of booster at vci > vcc hd66750/1 59 contrast adjuster software can adjust 64-step contrast for an lcd by varying the liquid-crystal drive voltage (potential difference between v lcd and v1) through the ct bits of the contrast adjustment register (electron volume function). the value of a variable resistor between v lcd and v1 (vr) can be precisely adjusted in a 0.05 x r unit within a range from 0.05 x r through 3.20 x r, where r is a reference resistance obtained by dividing the total resistance. the hd66750/1 incorporates a voltage-follower operational amplifier for each of v1 to v5 to reduce current flowing through the internal bleeder resistors, which generate different liquid-crystal drive voltages. thus, ct5-0 bits must be adjusted so that potential difference between v lcd and v1 is 0.1 v or higher and that between v4 and gnd is 1.4 v or higher when liquid-crystal drives, particularly when the vr is small. vlcd vr r r r0 r r - + - + - + - + - + gnd hd66750/1 ct v1 v2 v3 v4 v5 gnd figure 40 contrast adjuster hd66750/1 60 table 20 contrast adjustment bits (ct) and variable resistor values 0 ct3 0 ct2 0 ct1 0 ct0 3.20 x r ct set value variable resistor value (vr) 0 001 3.15 x r 0 010 3.10 x r 0 011 3.05 x r 0 100 3.00 x r 0 101 2.95 x r 0 110 2.90 x r 0 111 2.85 x r 0 ct4 0 0 0 0 0 0 0 100 1 2.75 x r 0 1010 2.70 x r 0 potential difference between v1 and gnd display color (small) (large) (light) (deep) 1 01 2.65 x r 0 1100 2.60 x r 0 1111 1.65 x r 1 0000 1.60 x r 0 0001 1.55 x r 0 0 010 1.50 x r 0 0 011 1.45 x r 0 0100 1.40 x r 0 0101 1.35 x r 0 0110 1.30 x r 0 0 111 1.25 x r 0 1 000 1.20 x r 0 100 1 1.15x r 1 1100 0.20 x r 1 1101 0.15 x r 1 1 110 0.10 x r 1 1 111 0.05 x r 1 100 0 2.80 x r 0 1 0 ct5 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 hd66750/1 61 liquid-crystal-display drive-bias selector an optimum liquid-crystal-display bias value can be selected using the bs2-0 bits, according to the liquid crystal drive duty ratio setting (nl3-0 bits). the liquid-crystal-display drive duty ratio and bias value can be displayed while switching software applications to match the lcd panel display status. the optimum bias value calculated using the following expression is a logical optimum value. driving by using a lower value than the optimum bias value provides lower logical contrast and lower liquid-crystal-display voltage (the potential difference between v1 and gnd), which results in better image quality. when the liquid- crystal-display voltage is insufficient even if a seven-times booster is used, when the boosting driving ability is lowered by setting a high factor for the booster, or when the output voltage is lowered because the battery life has been reached, the display can be made easier to see by lowering the liquid-crystal-display bias. the liquid crystal display can be adjusted by using the contrast adjustment register (ct5-0 bits) and selecting the booster output level (bt1/0 bits). optimum bias value for 1/n duty ratio drive voltage = 1 n + 1 table 21 optimum drive bias values lcd drive duty ratio 1/128 1/120 1/112 1/104 1/96 1/88 1/80 1/72 1/64 1/32 1/24 1/16 (nl3-0 set value) 1111 1110 1101 1100 1011 1010 1001 1000 0111 0100 0011 0010 optimum drive bias value 1/11 1/11 1/11 1/11 1/10 1/10 1/10 1/9 1/9 1/6 1/6 1/5 (bs2-0 set value) 000 000 000 000 001 001 001 010 010 101 101 100 hd66750/1 62 vr v1 v2 v3 v4 v5 r r 7r r r v1 v2 v3,v4 v5 gnd r r r r i) 1/ 11 bias (bs2e0 = 000) vi) 1/ 4 bias (bs2e0 = 111) gnd vr vlc d vlcd n ote: r = reference resistor vr v1 v2 v3 v4 v5 r r 6r r r ii) 1/ 10 bias (bs2e0 = 001) vlcd vr v1 v2 v3 v4 v5 r r 5r r r iii) 1/ 9 bias (bs2e0 = 010) vlcd vr v1 v2 v3 v4 v5 r r 4r r r iv) 1/ 8 bias (bs2e0 = 011) vlcd vr gnd v1 v2 v3 v4 v5 r r 3r r r v) 1/7 bias (bs2e0 = 100) vlcd gnd gn d gnd gnd gnd gnd gnd gn d gnd vr gnd v1 v2 v3 v4 v5 r r 2r r r v) 1/6 bias (bs2e0 = 101) vlcd gnd vr gnd v1 v2 v3 v4 v5 r r r r r v) 1/5 bias (bs2e0 = 110) vlcd gnd figure 41 liquid crystal display drive bias circuit hd66750/1 63 table 22 contrast adjustment per bias drive voltage 10 x r + vr 10 x r x (v lcd - gnd) 0.757 x (v lcd -gnd) v dr 0.995 x (v lcd -gnd) 3 1.4 [v] 3 0.1 [v] 10 x r + vr vr x (v lcd -gnd) 10 x r + vr 2 x r x (v lcd -gnd) 5 x r + vr 5 x r x (v lcd - gnd) 0.610 x (v lcd -gnd ) v dr 0.990 x (v lcd -gnd) 3 1.4 [v] 3 0.1 [v] 5 x r + vr vr x (v lcd -gnd ) 5 x r + vr 2 x r x (v lcd -gnd ) 4 x r + vr 4 x r x (v lcd - gnd) 0.556 x (v lcd -gnd) v dr 0.988 x (v lcd -gnd) 3 1.4 [v] 3 0.1 [v] 4 x r + vr vr x (v lcd -gnd) 4 x r + vr 2 x r x (v lcd -gnd) 9 x r + vr 9 x r x (v lcd - gnd) 0.737 x (v lcd -gnd) v dr 0.994 x (v lcd -gnd) 3 1.4 [v] 3 0.1 [v] 9 x r + vr vr x (v lcd -gnd) 9 x r + vr 2 x r x (v lcd -gnd) 11 x r + vr 11 x r x (v lcd - gnd) 0.775 x (v lcd -gnd) v dr 0.995 x (v lcd -gnd) 3 1.4 [v] 3 0.1 [v] vr x (v lcd -gnd) 11 x r + vr 2 x r x (v lcd -gnd) 11 x r + vr bias lcd drive voltage: v dr contrast adjustment range 1/11 bias drive 1/10 bias drive 1/9 bias drive 1/5 bias drive 1/4 bias drive - lcd drive voltage adjustment range - limit of potential difference between v4 and gnd - limit if potential difference between vlcd and v1 : : : - lcd drive voltage adjustment range - limit of potential difference between v4 and gnd - limit if potential difference between vlcd and v1 : : : 8 x r + vr 8 x r x (v lcd - gnd) 0.714 x (v lcd -gnd) v dr 0.993 x (v lcd -gnd) 3 1.4 [v] 3 0.1 [v] 8 x r + vr vr x (v lcd -gnd) 8 x r + vr 2 x r x (v lcd -gnd) 1/8 bias drive - lcd drive voltage adjustment range - limit of potential difference between v4 and gnd - limit if potential difference between vlcd and v1 : : : 6 x r + vr 6 x r x (v lcd - gnd) 0.652 x (v lcd -gnd) v dr 0.992 x (v lcd -gnd) 3 1.4 [v] 3 0.1 [v] vr x (v lcd -gnd) 6 x r + vr 6 x r + vr 2 x r x (v lcd -gnd) 7 x r + vr 7 x r x (v lcd - gnd) 0.686 x (v lcd -gnd) v dr 0.993 x (v lcd -gnd) 3 1.4 [v] 3 0.1 [v] vr x (v lcd -gnd) 7 x r + vr 2 x r x (v lcd -gnd) 7 x r + vr 1/7 bias drive 1/6 bias drive - lcd drive voltage adjustment range - limit of potential difference between v4 and gnd - limit if potential difference between vlcd and v1 : : : - lcd drive voltage adjustment range - limit of potential difference between v4 and gnd - limit if potential difference between vlcd and v1 : : : - lcd drive voltage adjustment range - limit of potential difference between v4 and gnd - limit if potential difference between vlcd and v1 : : : - lcd drive voltage adjustment range - limit of potential difference between v4 and gnd - limit if potential difference between vlcd and v1 : : : - lcd drive voltage adjustment range - limit of potential difference between v4 and gnd - limit if potential difference between vlcd and v1 : : : hd66750/1 64 four-grayscale display function the hd66750/1 supports the four-grayscale monochrome display function. the four-grayscale monochrome display is used for the display data of the two-bit pixel set sent to the cgram. there are four grayscale levels: always unlit, weak middle level, strong middle level, and always lit. in the weak middle-level grayscale display, the gs bit can select the 1/3 or 1/2 level. the frame rate control (frc) method is used for grayscale control. table 23 relationships between the cgram data and the display contents upper bit lower bit liquid crystal display 0 0 non-selected (unlit) 0 1 gs = 0: 1/3-level grayscale (one frame lit during a three-frame period) gs = 1: 1/2-level grayscale (one frame lit during a two-frame period) 1 0 2/3-level grayscale (two frames lit during a three-frame period) 1 1 selected (lit) note: upper bits: db15, db13, db11, db9, db7, db5, db3, and db1 lower bits: db14, db12, db10, db8, db6, db4, db2, and db0 0 0 1 0 0 1 1 1 1 1 0 1 1 0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 1 1 1 1 cgram grayscal e c ontrol circuit lsb db 0 msb db15 lsb db0 msb db15 lcd panel display figure 42 four-grayscale monochrome display window cursor display function the hd66750/1 displays the window cursor by specifying a window area. the horizontal display position of the window cursor is specified with the horizontal cursor position register (hs6e0 to he6e0), and the vertical display position is specified with the vertical cursor position register (vs6e0 or ve6e0). in these display position setting registers, ensure that hs6e0 he6e0 and vs6e0 ve6e0. if these relationships are not satisfied, normal display cannot be attained. in addition, if the setting is vs6e0 = ve6e0 = 00h, a cursor is displayed on a raster-row at the most-upper edge of the screen. this window cursor can automatically display the hardware-supported block cursor, highlight window, or menu bar. the cm1e0 bits select the following four displays in each window cursor: 1. white-blink cursor (cm1e0 = 00): alternately blinks between the normal display and an all-white (unlit) display 2. black-blink cursor (cm1e0 = 01): alternately blinks between the normal display and an all-black (all lit) display 3. black-and-white reversed cursor (cm1-0 = 10): black-and-white-reversed normal display (no blinking) 4. black-and-white-reversed blink cursor (cm1e0 = 11): alternately blinks between the normal display and a black-and-white-reversed display the above blinking display is switched in a 32-frame unit. in vertical scrolling, note that this window cursor does not automatically move vertically. figure 43 white blink cursor display vs+1 => ve+1 => vs+1 => ve+1 => hs+1 he+1 hs+1 he+1 blink display hd66750/1 hitachi 65 hd66750/1 hitachi 66 vs+1 => ve+1 => vs+1 => ve+1 => hs+1 he+1 hs+1 he+1 blink display figure 44 black blink cursor display vs+1 => ve+1 => hs+1 he+1 figure 45 black-and-white reversed cursor display hd66750/1 hitachi 67 figure 46 black-and-white reversed blink cursor display vs+1 => ve+1 => hs+1 he+1 hs+1 he+1 blink display hd66750/1 68 vertical smooth scroll display the hd66750/1 can scroll the graphics display vertically in units of raster-rows. the data storage capacity of the cgram is 128 raster-rows. continuous smooth vertical scrolling is achieved by writing display data into a raster-row area that is not being used for display. after the 128th raster-row is displayed, the first raster-row is displayed again. using the status read, the user can check the display raster-rows (l6-0) that are currently driving the lcd, and flicker can be eliminated by writing the display data in the cgram while the lcd is not driven. additionally, when display areas of a graphics icon such as a pictogram or a menu bar are partially fixed- displayed, the remaining areas can be displayed. for details, see the partial smooth scroll display function section. specifically, this function is controlled by incrementing or decrementing the value in the display-start raster-row bits (sl6-0) by 1. for example, to smoothly scroll up, increment display-start raster-row bits (sl6-0) by 1 from 0000000 to 1111111 to scroll 128 raster-rows. note that the vertical double-height display or window cursor display is not automatically changed in synchronization with the vertical scrolling. when the response speed of the liquid crystal is low or when high-speed scrolling is needed, two- to four- raster-row scrolling is recommended. hd66750/1 69 1) not scrolled sl6 to 0 = 0000000 2) two raster-rows scrolled up sl6 to 0 = 0000010 3) four raster-rows scrolled up sl6 to 0 = 0000100 4) eight raster-rows scrolled up sl6 to 0 = 0001000 figure 47 vertical smooth scroll hd66750/1 70 partial smooth scroll display function the hd66750/1 can partially fixed-display the areas of a graphics icon such as a pictogram or a menu bar, and perform vertical smooth scrolling of the remaining bit-map areas. since the ps1 to ps0 bits are not used for smooth scrolling of the upper first to 24th display raster-rows but are used for fixed-display, pictograms can be placed on the screen. this function can largely control the rewrite frequencies of the bit-map data during smooth scrolling and reduce the software load of the mpu. hd66750/1 71 table 24 bit setting and display lines not es: 1. the shadow raster-rows above are fixed-displayed. they do not depend on the setting values of the sl6 to 0 bits. 2. the sl6 to 0 bits specify the next first scroll display rast er-row of the fixed-displayed rast er-rows. 1st r aster- row 2nd raster-row 3rd raster -row 1 19th raster-r ow 120th raster -row ps1 to 0 = 00 sl6 to 0 = 00h 2 nd raster -row 3rd raster-r o w 4th raster-row 1 21th raster-row 1 20th raster-row sl6 to 0 = 01h sl6 to 0 = 02h com1 com 12 0 1 21th raster-row 1 22th raster-row 3rd raster-r ow 4th raster-r o w 5th raster-r o w 1st to 8th rast er-rows 1st r aster- row 2 nd raster-row 3rd ras ter -row 4th raster- row 110 th raster-row ps1 to 0 = 01 2 nd raster -row 3rd raster-r ow 4th raster-row 5th raster-row 1 11th raster -row 112th raster -row 3rd raster-row 4th raster-row 5th raster-row 6th raster-row 1st raster-row 2 nd r a ster- row 3rd raster-row ps1 to 0 = 10 3rd raster-r o w 4th raster-row 1 03th raster-row 4th raster-row 5th raster-row 1 04th raster-row 1st r aster- row 2 nd raster-row ps1 to 0 = 11 2nd raster-r ow 3rd raster-row 97th raster-row 98th raster-r ow 3rd r aster- row 4th raster-r ow 102th raster-row 2 nd raster -row sl6 t o 0 = 04h 123th raster-row 124th raster-row 5th raster-row 6th raster-row 7th raster-row 5th raster-row 6th raster-row 7th raster-row 8th raster-row 5th raster-row 6th raster-row 7th raster-row 5th raster-row 6th raster-row 100th raster-row 114th raster-row sl6 to 0 = 07h 126th raster-row 127th raster-row 8th raster-row 9th raster-row 10th raster-row 117th raster-row 8th r aster- row 9th r aster- row 10t h r aster- row 11th raster-row 110th raster -row 11 1th raster-r ow 8th raster-row 9th raster-row 10th raster-row 103th raster-row 8th raster-row 9th raster-row sl6 to 0 = 7fh 3rd raster-row 108th raster-row 96th raster -row bit set ting com position 94th raster -row 96th raster-r ow 98th raster-row 101th raster-row 95th raster-row 95th raster -row 97th raster-r ow 99th raster-row 102th raster-row 96th raster-row 1 11th raster-row 1 12th raster-row 113th raster -row 115th raster-row 118th raster-row 112 th raster-row 1 13th raster-row 1 14 th raster-row 116th raster-row 119th raster-row 109th raster-row 106th raster-row 107th raster-row 1 04th raster-row 1 05th raster-row 103th raster-row 1 05th raster-row 1 06th raster-row 104th raster-row sl6 to 0 = 7eh com1 com 12 0 com1 com 12 0 com1 com 12 0 117th raster -row 118th raster -row 127th raster-row 128th raster-row 1st raster-row 118th raster -row 119th raster -row 128th raster-row 1st raster-row 2rd raster-row 116th r aster- row 127th raster-row 128th raster-row 9th raster-row 10th raster-row 117th r aster- row 118th r aster- row 1 17th raster-r ow 128th raster -row 9th raster -row 1 0th raster -row 11th raster-r ow 1 18th raster-r ow 1 19th raster-r ow 117th raster -row 118th raster -row 127th raster-row 128th raster-row 17th raster-row 116th raster -row 118th raster-row 119th raster-row 128th raster-row 17th raster-row 18th raster-row 117th raster-row sl6 to 0 = 08h 127th r aster- row 128th r aster- row 9th r aster- row 10th r aster- row 1 1th raster-r o w 118th r aster- row 9th raster-row 10th raster-row 11th raster -row 12th raster-row 11 1th raster-r ow 112th r aster- row 9th raster-row 10th raster-row 11th raster -row 104th r aster- row 9th raster-r ow 10th r aster- row 102th r aster- row 103th r aster- row 119th r aster- row 120th raster-row 110th r aster- row 118th r aster- row 127th raster -row 128th raster -row 116th r aster- row 117th r aster- row 1 19th raster-r ow 128th raster -row 2 5th raster -row 1 17th raster-r ow 1 18th raster-r ow 3rd rast er -row 4th raster-row 5th raster-r ow 7th raster-row 10th raster-row 1 1th raster-r o w 2 5th raster -row 2 6th raster -row 1st to 8th raster-rows 1st to 8th rast er-rows 1st to 8th raster-rows 1 st to 8th rast er-rows 1st to 8th rast er-rows 1st to 8th rast er-rows 1st to 8th raster-rows 1st to 16t h raster-rows 1st to 16th raster-rows 1st to 16th rast er-rows 1st to 16th raster-rows 1 st to 16th rast er-rows 1st to 16th rast er-rows 1st to 16th rast er-rows 1st to 16t h raster-rows 1st to 24t h raster-rows 1st to 24th raster-rows 1st to 24th rast er-rows 1st to 24th raster-rows 1 st to 24th rast er-rows 1st to 24th rast er-rows 1st to 24th rast er-rows 1st to 24t h raster-rows hitachi 72 partial smooth scroll display examples table 25 data setting to the cgram 000 to 07f 080 to 0ff 100 to 17f 180 to 1ff 200 to 27f 280 to 2ff 300 to 37f 380 to 3ff 400 to 47f 480 to 4ff cgram address cgram data 500 to 57f 580 to 5ff hd66750/1 hd66750/1 hitachi 73 figure 48 example of initial screen in the partial smooth scroll mode i) initial screen display ps1 to 0 = 01: fixed-displays the first to eighth raster-rows sl6 to 0 = 0001000: starts display from the ninth raster-row scroll area fixed display area (1st to 8th raster-rows) display-start setting position (9th raster-row) figure 49 example of display screen in the partial smooth scroll mode (1) ii) four-dot partial scroll up ps1 to 0 = 01: fixed-displays the first to eighth raster-rows sl6 to 0 = 0001100: starts display from the 13th raster-row fixed display area (1st to 8th raster-rows) display-start setting position (13th raster-row) figure 50 example of display screen in the partial smooth scroll mode (2) hitachi 74 hd66750/1 iii) eight-dot partial scroll up ps1 to 0 = 01: fixed-displays the first to eighth raster-rows sl6 to 0 = 0010000: starts display from the 17th raster-row fixed display area (1st to 8th raster-rows) display-start setting position (17th raster-row) hd66750/1 75 double-height display function the hd66750/1 can double the height of any desired area in units of raster-rows (dots). the double-height display is done by setting the dhe bit in the display control register to 1. the start position of the double-height display is set by the ds6 to ds0 bits of the double-height display position register, and the double-height display starts at the (the setting value plus one)-th raster-row. the end position is set by the de6 to de0 bits of the double-height display position register, and the display ends at the (the setting value plus one)-th raster-row. here, the end position of the double-height display must be after the start position, so set the register setting values so that ds6-0 de6-0. when the area specified to be doubled in height is an odd number of raster-rows, the double-height display is done up to the (de6-0 plus one)-th raster-row. in vertical smooth scrolling, the double-height display position does not automatically move up or down. figure 51 double-height display (9th to 40th raster-rows) hitachi 76 hd66750/1 double-height display on: dhe = 1 double-height display start: ds6 to 0 = 0001000 double-height display end: de6 to 0 = 0010111 start double- height display (9th raster-row) double-height display area end double- height display (40th raster-row) hd66750/1 77 reversed display function the hd66750/1 can display graphics display sections by black-and-white reversal. black-and-white reversal can be easily displayed when the rev bit in the display control register is set to 1. figure 52 reversed display hitachi 78 hd66750/1 rev = 1 (reversed display) hd66750/1 79 partial-display-on function the hd66750/1 can program the liquid crystal display drive duty ratio setting (nl3-0 bits), the liquid crystal display drive bias value selection (bs2-0 bits), the boost output level selection (bt1-0 bits), and the contrast adjustment (ct5-0 bits). for example, when the 128 x 120-dot screen is normally displayed with a 1/120 duty ratio, the hd66750/1 can selectively drive only the center of the screen or the top of the screen by combining these register functions and the centering display function (cn bit). this is called partial- display-on. lowering the liquid crystal display drive duty ratio reduces the liquid crystal display drive voltage, thus reducing internal current consumption. this is suitable for a 16 raster-row display (1/16 duty ratio) of a calendar or time in the system-standby state, or the display of only graphics icons (pictograms) at the top of the screen, which enables continuous display with minimal current consumption. the non-displayed lines are constantly driven by the unselected level voltage, thus turning off the lcd for these lines. in general, lowering the liquid crystal display drive duty ratio decreases the optimum liquid crystal display drive voltage and liquid crystal display drive bias value. this reduces output multiplying factors in the booster and greatly controls consumption current. table 26 partial-display-on function (1/120-duty normal drive) item normal display partial-on display (limited to four-line display) lcd screen 128 x 120 dots 128 x 16 dots only on the center of the screen 128 x 16 dots only at the top of the screen lcd drive position shift not necessary (cn = 0) necessary (cn = 1) not necessary (cn = 0) lcd drive duty ratio 1/120 (nl3 to 0 = 1110) 1/16 (nl3 to 0 = 0001) 1/16 (nl3 to 0 = 0001) lcd drive bias value (optimum) 1/11 (bs2 to 0 = 000) 1/5 (bs2 to 0 = 110) 1/5 (bs2 to 0 = 110) lcd drive voltage* 13.5 v to 15.5 v (precisely adjustable using ct5 to 0) 4 v to 5 v (precisely adjustable using ct5 to 0) 4 v to 5 v (precisely adjustable using ct5 to 0) boosting output multiplying factor six times (bt1 to 0 = 10) two times (bt1 to 0 = 00) two times (bt1 to 0 = 00) frame frequency (fosc = 70 khz) 68 hz 68 hz 68 hz note: the lcd drive voltage depends on the lcd materials used. since the lcd drive voltage is high when the lcd drive duty ratio is high, a low duty ratio enables low-power consumption. figure 53 partial-on display (date and time indicated) (1) hitachi 80 hd66750/1 figure 54 partial-on display (date and time indicated) (2) i) 1/16-duty drive at the top of the screen always applying non-selection level 1/16-duty drive ii) 1/16-duty drive at the center of the screen (centering display) always applying non- selection level 1/16-duty drive always applying non- selection level hd66750/1 81 sleep mode setting the sleep mode bit (slp) to 1 puts the hd66750/1 in the sleep mode, where the device stops all internal display operations, thus reducing current consumption. specifically, lcd operation is completely halted. here, all the seg (seg1 to seg128) and com (com1 to com128) pins output the gnd level, resulting in no display. if the ap1-0 bits in the power control register are set to 00 in the sleep mode, the lcd drive power supply can be turned off, reducing the total current consumption of the lcd module. table 27 comparison of sleep mode and standby mode function sleep mode (slp = 1) standby mode (stb = 1) lcd control turned off turned off r-c oscillation circuit operates normally operation stopped standby mode setting the standby mode bit (stb) to 1 puts the hd66750/1 in the standby mode, where the device stops completely, halting all internal operations including the r-c oscillation circuit, thus further reducing current consumption compared to that in the sleep mode. specifically, all the seg (seg1 to seg128) and com (com1 to com128) pins for the multiplexing drive output the gnd level, resulting in no display. if the ap1-0 bits are set to 00 in the standby mode, the lcd drive power supply can be turned off. during the standby mode, no instructions can be accepted other than the start-oscillation instruction. to cancel the standby mode, issue the start-oscillation instruction to stabilize r-c oscillation before setting the stb bit to 0. standby mode wait at least 10 ms turn off the lcd power supply: ap1 to 0 = 00 set standby mode: stb = 1 issue the start-oscillation instruction cancel standby mode: stb = 0 turn on the lcd power supply: ap1 to 0 = 01 / 10 / 11 figure 55 procedure for setting and canceling standby mode hd66750/1 82 absolute maximum ratings item symbol unit value notes* power supply voltage (1) v cc v e0.3 to +4.6 1, 2 power supply voltage (2) v lcd e gnd v e0.3 to +16.5 1, 3 input voltage vt v e0.3 to v cc + 0.3 1 operating temperature topr c e40 to +85 1, 4 storage temperature tstg c e55 to +110 1, 5 notes: 1. if the lsi is used above these absolute maximum ratings, it may become permanently damaged. using the lsi within the following electrical characteristics limits is strongly recommended for normal operation. if these electrical characteristic conditions are also exceeded, the lsi will malfunction and cause poor reliability. 2. vcc > gnd must be maintained. 3. vlcd > gnd must be maintained. 4. for bare die and wafer products, specified up to 85?c. 5. this temperature specifications apply to the tcp package. hd66750/1 83 dc characteristics (v cc = 1.8 to 3.6 v, ta = e40 to +85 c* 1 ) item symbol min typ max unit test condition notes input high voltage v ih 0.7 v cc ?v cc v 2, 3 input low voltage v il e0.3 ? 0.15 v cc vv cc = 1.8 to 2.4 v 2, 3 e0.3 ? 0.15 v cc vv cc = 2.4 to 3.6 v 2, 3 output high voltage (1) (db0-15 pins) v oh1 0.75 v cc ??vi oh = e0.1 ma 2 output low voltage (1) (db0-15 pins) v ol1 ? ? 0.2 v cc vv cc = 1.8 to 2.4 v, i ol = 0.1 ma 2 ? ? 0.15 v cc vv cc = 2.4 to 3.6 v, i ol = 0.1 ma 2 driver on resistance (com pins) r com ? 3 10 k w id = 0.05 ma, v lcd = 10 v 4 driver on resistance (seg pins) r seg ? 3 10 k w id = 0.05 ma, v lcd = 10 v 4 i/o leakage current i li e1 ? 1 m a vin = 0 to v cc 5 current consumption during normal operation (v cc e gnd) i op ?50 (t.b.d.) 90 (t.b.d.) m a r-c oscillation, v cc = 3 v, ta = 25 c, f osc = 70 khz (1/120 duty) 6, 7 current consumption during sleep mode (v cc e gnd) i sl ?10? m a r-c oscillation, v cc = 3 v, ta = 25 c, f osc = 70 khz (1/120 duty) 6, 7 current consumption during standby mode (v cc e gnd) i st ? 0.1 5 m av cc = 3 v, ta = 25 c 6, 7 lcd drive power supply current (v lcd e gnd) i lcd ?25 (t.b.d.) 40 (t.b.d.) m av lcd = 15 v, 1/11 bias, ta = 25 c, f osc = 70 khz 7 lcd drive voltage (v lcd e gnd) v lcd 5.0 ? 15.5 v 8 note: for the numbered notes, refer to the electrical characteristics notes section following these tables. hd66750/1 84 booster characteristics (t. b. d.) item symbol min typ max unit test condition notes two-times-boost output voltage (vlout pin) v up2 3.9 4.3 4.4 v v cc = vci = 2.2 v, i o = 30 m a, c = 1 m f, f osc = 70 khz, ta = 25 c 11 five-times-boost output voltage (vlout pin) v up5 10.5 10.8 11.0 v v cc = vci = 2.2 v, i o = 30 m a, c = 1 m f, f osc = 70 khz, ta = 25 c 11 six-times-boost output voltage (vlout pin) v up6 12.7 12.9 13.2 v v cc = vci = 2.2 v, i o = 30 m a, c = 1 m f, f osc = 70 khz, ta = 25 c 11 seven-times- boost output voltage (vlout pin) v up7 13.9 15.1 15.4 v v cc = vci = 2.2 v, i o = 30 m a, c = 1 m f, f osc = 70 khz, ta = 25 c 11 use range of boost output voltages v up2 v up5 v up6 v up7 vcc ? 15.5 v for two- to seven-times boost 11 note: for the numbered notes, refer to the electrical characteristics notes section following these tables. hd66750/1 85 ac characteristics (v cc = 1.8 to 3.6 v, ta = e40 to +85 c* 1 ) clock characteristics (v cc = 1.8 to 3.6 v) item symbol min typ max unit test condition notes external clock frequency fcp 50 75 150 khz 9 external clock duty ratio duty 45 50 55 % 9 external clock rise time trcp ? ? 0.2 m s9 external clock fall time tfcp ? ? 0.2 m s9 r-c oscillation clock f osc 59 74 89 khz rf = 390 k w , v cc = 3 v 10 note: for the numbered notes, refer to the electrical characteristics notes section following these tables. 68-system bus interface timing characteristics (vcc = 1.8 to 2.4 v) item symbol min typ max unit test condition enable cycle time write t cyce 600 ? ? ns figure 62 read t cyce 800 ? ? enable high-level pulse width write pw eh 120 ? ? ns figure 62 read pw eh 350 ? ? enable low-level pulse width write pw el 300 ? ? ns figure 62 read pw el 300 ? ? enable rise/fall time t er , t ef ? ? 25 ns figure 62 setup time (rs, r/w to e, cs*) t ase 50 ? ? ns figure 62 address hold time t ahe 20 ? ? ns figure 62 write data setup time t dswe 60 ? ? ns figure 62 write data hold time t he 20 ? ? ns figure 62 read data delay time t ddre ? ? 300 ns figure 62 read data hold time t dhre 5 ? ? ns figure 62 hd66750/1 86 (vcc = 2.4 to 3.6 v) item symbol min typ max unit test condition enable cycle time write t cyce 380 ? ? ns figure 62 read t cyce 500 ? ? enable high-level pulse width write pw eh 70 ? ? ns figure 62 read pw eh 250 ? ? enable low-level pulse width write pw el 150 ? ? ns figure 62 read pw el 150 ? ? enable rise/fall time t er , t ef ? ? 25 ns figure 62 setup time (rs, r/w to e, cs*) t ase 50 ? ? ns figure 62 address hold time t ahe 20 ? ? ns figure 62 write data setup time t dswe 60 ? ? ns figure 62 write data hold time t he 20 ? ? ns figure 62 read data delay time t ddre ? ? 200 ns figure 62 read data hold time t dhre 5 ? ? ns figure 62 hd66750/1 87 80-system bus interface timing characteristics (vcc = 1.8 to 2.4 v) item symbol min typ max unit test condition bus cycle time write t cycw 600 ? ? ns figure 63 read t cycr 800 ? ? ns figure 63 write low-level pulse width pw lw 120 ? ? ns figure 63 read low-level pulse width pw lr 350 ? ? ns figure 63 write high-level pulse width pw hw 300 ? ? ns figure 63 read high-level pulse width pw hr 300 ? ? ns figure 63 write/read rise/fall time t wrr , wrf ? ? 25 ns figure 63 setup time (rs to cs*, wr*, rd*) t as 50 ? ? ns figure 63 address hold time t ah 20 ? ? ns figure 63 write data setup time t dsw 60 ? ? ns figure 63 write data hold time t h 20 ? ? ns figure 63 read data delay time t ddr ? ? 300 ns figure 63 read data hold time t dhr 5 ? ? ns figure 63 (vcc = 2.4 to 3.6 v) item symbol min typ max unit test condition bus cycle time write t cycw 380 ? ? ns figure 63 read t cycr 500 ? ? ns figure 63 write low-level pulse width pw lw 70 ? ? ns figure 63 read low-level pulse width pw lr 250 ? ? ns figure 63 write high-level pulse width pw hw 150 ? ? ns figure 63 read high-level pulse width pw hr 150 ? ? ns figure 63 write/read rise/fall time t wrr, wrf ? ? 25 ns figure 63 setup time (rs to cs*, wr*, rd*) t as 50 ? ? ns figure 63 address hold time t ah 20 ? ? ns figure 63 write data setup time t dsw 60 ? ? ns figure 63 write data hold time t h 20 ? ? ns figure 63 read data delay time t ddr ? ? 200 ns figure 63 read data hold time t dhr 5 ? ? ns figure 63 reset timing characteristics (v cc = 1.8 to 3.6 v) item symbol min typ max unit test condition reset low-level width t res 1 ? ? ms figure 64 hd66750/1 88 electrical characteristics notes 1. for bare die products, specified up to 85?c. 2. the following three circuits are i/o pin configurations (figure 56). pins: reset*, cs*, e/wr, rw/rd, rs, osc1, opoff, im1/0, test pin: osc2 pmos nmos vcc gnd pins: db15 to db0 pmos nmos vcc gnd nmos pmos vcc vcc pmos nmos (tri-state output circuit) output data output enable gnd pmos (input circuit) figure 56 i/o pin configuration hd66750/1 89 3. the test pin must be grounded and the im1/0 and opoff pins must be grounded or connected to vcc. 4. applies to the resistor value (rcom) between power supply pins v1out, v2out, v5out, gnd and common signal pins, and resistor value (rseg) between power supply pins v1out, v3out, v4out, gnd and segment signal pins. 5. this excludes the current flowing through output drive moss. 6. this excludes the current flowing through the input/output units. the input level must be fixed high or low because through current increases if the cmos input is left floating. 7. the following shows the relationship between the operation frequency (fosc) and current consumption (icc) (figure 57). r-c oscillation frequencies: fosc (khz) 60 40 20 0 iop ( m a) vcc = 3v 0 display on (typ.) sleep (typ.) 30 20 10 0 ilcd ( m a) vcc = 3 v, fosc = 70 khz 11.0 lcd drive voltage: vlcd (v) 13.0 15.0 17.0 standby (typ.) 40 20 60 80 100 typ. hd66750/1 90 10. applies to the internal oscillator operations using external oscillation resistor rf (figure 59 and table 28). osc1 osc2 rf since the oscillation frequency varies depending on the osc1 and osc2 pin capacitance, the wiring length to these pins should be minimized. figure 59 internal oscillation table 28 external resistance value and r-c oscillation frequency (referential data) external r-c oscillation frequency: fosc resistance (rf) vcc = 1.8 v vcc = 2.2 v vcc = 3.0 v vcc = 4.0 v 200 k w 86 khz 111 khz 130 khz 140 khz 270 k w 70 khz 86 khz 100 khz 108 khz 300 k w 64 khz 79 khz 92 khz 98 khz 330 k w 60 khz 74 khz 86 khz 91 khz 360 k w 57 khz 69 khz 79 khz 84 khz 390 k w 54 khz 64 khz 74 khz 78 khz 430 k w 49 khz 59 khz 67 khz 71 khz 470 k w 46 khz 54 khz 61 khz 65 khz 11. booster characteristics test circuits are shown in figure 60. (five to seven times b oostin g vcc 1 m f vci c1+ c1- + gnd v lout v lcd 1 m f + 1 m f c2+ c2- 1 m f c3+ c3- c4+ c4- + + c5+ c5- c6+ c6- 1 m f + 1 m f + 1 m f + figure 60 booster hd66750/1 91 vup6 = vlcd - gnd, vup7 = vlcd - gnd (i) relation between the obtained voltage and input voltage vci = vcc = 2.4 v, fosc = 70 khz, io = 30 m a, dc1 to 0= 00 (ii) relation between the obtained voltage and temperature vci = vcc = 2.4 v, fosc = 70 khz, io = 30 m a, dc1 to 0 = 00 referential data 3.0 2.5 2.0 1.5 9.0 12.0 15.0 18.0 vci (v) vup6 (v) typ. vci = vcc, fosc = 70 khz, ta = 25 c, dc1 to 0= 00 3.0 2.5 2.0 1.5 8.0 13.0 typ. vci = vcc, fosc = 70 khz, ta = 25 c, dc1 to 0 = 00 vup7 (v) vci (v) six-times boosting seven-times boosting 18.0 six-times boosting seven-times boosting ta ( c) vup6 (v) 100 60 20 0 -20 -60 11.0 13.0 15.0 17.0 typ. ta ( c) vup7 (v) 100 60 20 0 -20 -60 14.0 16.0 18.0 typ. hd66750/1 92 (iv) relation between the obtained voltage and current vci = vcc = 2.4 v, fosc = 70 khz, ta = 25 c, dc1 to 0 = 00 vci = vcc = 2.4 v, fosc = 70 khz, ta = 25 c, dc1 to 0 = 00 io ( m a) vup6 (v) 200 150 100 50 0 13.0 13.5 14.0 14.5 15.0 io ( m a) vup7 (v) 200 150 100 50 0 15.5 16.0 16.5 17.0 17.5 six-times boosting seven-times boosting hd66750/1 93 timing characteristics 68-system bus operation rs r/w cs* e db0 to db15 db0 to db15 v ih v il t ase t ahe pw eh t ef t er t dswe t he write data t cyce t d dre t dhr e v oh1 v ol1 v oh1 v ol1 read data v ih v il v il v il v ih v ih v il v ih v il v ih v il pw el note 1: pw eh is specified in the overlapped period when cs* is low and e is high. v il v il *1 figure 62 68-system bus timing hd66750/1 94 80-system bus operation rs cs* wr* rd* v ih v il t as t ah pw lw, pw lr t wrf t wrr t dsw t hwr write data t cyc w, t cycr t ddr t d hr v oh1 v ol1 v oh1 v ol1 read data v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih pw hw pw hr note 1: pw lw and pw lr are specified in the overlapped period when cs* is low and wr* or rd* is low. db0 to db15 db0 to db15 *1 figure 63 80-system bus timing reset operation reset* v il v il t re s figure 64 reset timing when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all right reserved: no one is permitted to reproduce or duplicated, in any form, the whole or part of this document without hitachi's permission. 3. hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachi's semiconductor products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party of hitachi, ltd. 6. medical applications: hitachi's products are not authorized for use in medical applications without the written consent of the appropriate officer of hitachi's sales company. such use includes, but is not limited to use in life support systems. buyers of hitachi's products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications. |
Price & Availability of HD66751
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |