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| data sheet july 2000 LU6612 fastcat tm single-fet for 10base-t/100base-tx features 10 mbits/s transceiver n compatible with ieee * 802.3u 10base-t standard for twisted-pair cable n autopolarity detection and correction n adjustable squelch level for extended wire line length capability (2 levels) n interfaces with ieee 802.3u media independent interface (mii) n on-chip filtering eliminates the need for external fil- ters n half- and full-duplex operations 100 mbits/s transceiver n compatible with ieee 802.3u mii (clause 22), pcs (clause 23), pma (clause 24), autonegotiation (clause 28), and pmd (clause 25) specifications n scrambler/descrambler bypass n encoder/decoder bypass n 3-statable mii in 100 mbits/s mode n selectable carrier sense signal generation (crs asserted during either transmission or reception in half duplex, crs asserted during reception only in full duplex) n selectable mii or 5-bit code group interface n half- or full-duplex operations n on-chip filtering and adaptive equalization that eliminates the need for external filters general n autonegotiation ( ieee 802.3u clause 28): fast link pulse (flp) burst generator arbitration function accepts preamble suppression operates up to 12.5 mhz n supports the station management protocol and frame format (clause 22): basic and extended registers supports next-page function accepts preamble suppression operates up to 12.5 mhz n supports the following management functions via pins if station management is unavailable: speed select encoder/decoder bypass scrambler/descrambler bypass full duplex autonegotiation n supports half- and full-duplex operations n provides four status signals: receive/transmit activ- ity, full duplex, link integrity, and speed indication n powerdown mode for 10 mbits/s and 100 mbits/s operation n loopback for 10 mbits/s and 100 mbits/s operation n 0.35 m m low-power cmos technology n 64-pin tqfp n single 5 v power supply * ieee is a registered trademark of the institute of electrical and electronics engineers, inc. note: advisories are issued as needed to update product information. when using this data sheet for design purposes, please con tact your lucent technologies microelectronics group account manager to obtain the latest advisory on this product.
table of contents contents page LU6612 data sheet fastcat single-fet for 10base-t/100base-tx july 2000 2 lucent technologies inc. features ....................................................................................................................... ............................................. 1 10 mbits/s transceiver ......................................................................................................... ................................... 1 100 mbits/s transceiver ........................................................................................................ .................................. 1 general ........................................................................................................................ ........................................... 1 description.................................................................................................................... .............................................4 pin information and descriptions............................................................................................... ................................ 8 mii station management ......................................................................................................... ................................13 basic operations............................................................................................................... ....................................13 mii management frames .......................................................................................................... ............................13 mode selection ................................................................................................................. .....................................23 absolute maximum ratings (t a = 25 c) ................................................................................................................24 electrical characteristics ..................................................................................................... ....................................24 timing characteristics (preliminary)........................................................................................... .............................25 outline diagram................................................................................................................ .......................................34 64-pin tqfp .................................................................................................................... .....................................34 technical document types ....................................................................................................... ..............................35 ordering information........................................................................................................... .....................................36 list of tables ta bl es page table 1. mii/serial interface pins (17) ...................................................................................... ............................... 9 table 2. mii management pins (2) ............................................................................................. ........................... 10 table 3. 10/100 mbits/s twisted-pair (tp) interface pins (4) ................................................................. ............... 10 table 4. ground and power pins (21) .......................................................................................... ......................... 11 table 5. miscellaneous pins (20) ............................................................................................. ............................. 11 table 5 . miscellaneous pins (20) (continued) ................................................................................. ...................... 12 table 6. mii management frame fields and format ............................................................................... .............. 13 table 7. mii management frame descriptions .................................................................................... .................. 13 table 8. mii management registers (mr) ........................................................................................ ..................... 14 table 9. mr0control register bit descriptions ................................................................................ .................. 15 table 10. mr1status register bit descriptions ................................................................................ ................. 16 table 11. mr2, 3phy identifier registers (1 and 2) bit descriptions .......................................................... ...... 17 table 12. mr4autonegotiation advertisement register bit descriptions......................................................... .. 17 table 13. mr5autonegotiation link partner (lp) ability register bit descriptions (base_page) ...................... 18 table 14. mr5autonegotiation link partner (lp) ability register bit descriptions (next_page) ....................... 18 table 15. mr6autonegotiation expansion register bit descriptions............................................................. .... 19 table 16. mr7next_page transmit register bit descriptions.................................................................... ........ 19 table 17. mr28device-specific register 1 (status register) bit descriptions ................................................. 20 table 18. mr29device-specific register 2 (100 mbits/s control) bit descriptions ........................................... 21 table 19. mr30device-specific register 3 (10 mbits/s control) bit descriptions ............................................. 22 table 20. operation modes of LU6612 .......................................................................................... ....................... 23 table 21. LU6612 crystal specifications ....................................................................................... ........................ 23 table 22 . absolute maximum ratings ........................................................................................... ....................... 24 table 23 . operating conditions ............................................................................................... ............................. 24 table 24. dc characteristics.................................................................................................. ................................. 24 table 25. mii management interface timing (25 pf load) ........................................................................ ............ 25 table 26. mii data timing (25 pf load) ........................................................................................ ........................ 26 table 27. serial 10 mbits/s timing for rx/ry, crs, and rx_clk ................................................................. ....... 28 table of contents (continued) tables (continued) page data sheet LU6612 july 2000 fastcat single-fet for 10base-t/100base-tx lucent technologies inc. 3 table 28. serial 10 mbits/s timing for tx_en, tx/ty, crs, and rx_clk .......................................................... .28 table 29. serial 10 mbits/s timing for tx_en, rx/ry, and col.................................................................. ......... 29 table 30. serial 10 mbits/s timing for rx_clk, crs, rxd, tx_clk, tx_en, and txd (25 pf load) ............... 30 table 31. serial 10 mbits/s timing for rx_clk and tx_clk (25 pf load)......................................................... .31 table 32. 100 mbits/s mii transmit timing..................................................................................... ........................ 32 table 33. 100 mbits/s mii receive timing ...................................................................................... ....................... 33 list of figures figures page figure 1. functional block diagram: device overview ............................................................................. ............... 4 figure 2. functional block diagram: device detail ............................................................................... ................... 5 figure 3. typical twisted-pair (tp) interface ................................................................................... ........................ 6 figure 4. onboard universal twisted-pair interface circuit to interchange lucent and quality semiconductor inc. parts ....................................................................................................... ................... 7 figure 5. LU6612 pinout......................................................................................................... .................................. 8 figure 6. mdio input timing ..................................................................................................... ............................. 25 figure 7. mdio output timing .................................................................................................... ........................... 25 figure 8. mdio during ta (turnaround) of a read transaction ..................................................................... ...... 25 figure 9. mii timing requirements for LU6612 .................................................................................... ................. 27 figure 10. serial 10 mbits/s timing for rx/ry, crs, and rx_clk .................................................................. .... 28 figure 11. serial 10 mbits/s timing for tx_en, tx/ty, crs, and rx_clk.......................................................... 2 8 figure 12. serial 10 mbits/s timing for tx_en, rx/ry, and col ................................................................... ...... 29 figure 13. serial 10 mbits/s timing for rx_clk, crs, rxd, tx_clk, tx_en, and txd ................................... 30 figure 14. serial 10 mbits/s timing diagram for rx_clk and tx_clk............................................................... .31 figure 15. 100 mbits/s mii transmit timing ...................................................................................... ..................... 32 figure 16. 100 mbits/s mii receive timing ....................................................................................... ..................... 33 4 4 lucent technologies inc. LU6612 data sheet fastcat single-fet for 10base-t/100base-tx july 2000 description the LU6612 is a single-channel, single-chip complete transceiver designed specifically for dual-speed 10base-t and 100base-tx repeaters and switches. LU6612 implements: n the 10base-t transceiver function of ieee 802.3u. n the physical coding sublayer (pcs) of ieee 802.3u. n the physical medium attachment (pma) of ieee 802.3u. n autonegotiation of ieee 802.3u. n mii management of ieee 802.3u. n physical medium dependent (pmd) of ieee 802.3u. this device supports operation over category 3 unshielded twisted-pair (utp) cable, according to ieee 802.3u 10base-t specification, and over category 5, type 1, utp and type 1 shielded twisted-pair cable, according to ieee 802.3u 100base-x specification. figure 1 illustrates a functional overview of the LU6612 while figure 2 details the functions. figure 3 shows how the LU6612 interfaces to the twisted pair. 5-5600(f).r1 figure 1. functional block diagram: device overview 10 mbits/s transceiver autonegotiation pma tx mux management pcs dpll 25 mhz 125 mhz lsclk pmd mii/serial interface 25 mhz driver and filters driver and filters 20 mhz to/from magnetics lucent technologies inc. 5 data sheet LU6612 july 2000 fa st cat single-fet for 10base-t/100base-tx description (continued) 5-5136(f).cr1 figure 2. functional block diagram: device detail autonegotiation and link monitor txd[3:0] 4b/5b encoder far-end fault gen scrambler pdt dcru sd pdr descrambler aligner 5b/4b decoder far-end fault detect 10 mbits/s transceiver rxc rxd txc ten txd clk20 mdc mdio mii rx/ry tx state machine sd collision detect sd rx state machine mii tx_er/txd[4] tx_en txd[3:0] tx_clk rx_clk rx_er/rxd[4] rx_dv rxd[3:0] col crs ref10 management 25 mhz 125 mhz lsclk pmd tx pmd rx sd tx/ty 100 mbits/s transceiver lc10 ls10 lc100 ls100 carrier cim detect rxerr_st car_stat mii interface serial interface dpll 20 mh z management interface LU6612 data sheet fastcat single-fet for 10base-t/100base-tx july 2000 6 lucent technologies inc. description (continued) 5-5433.i.r3 figure 3. typical twisted-pair (tp) interface LU6612 rj-45 1 2 3 4 5 6 7 8 75 w 75 w 0.01 m f 1:1 1:1 0.001 m f 0.01 m f 0.001 m f 220 w rx ry tx ty 220 w 50 w 50 w v dd 75 w 0.01 m f 75 w 63 64 50 w 50 w 9 8 0.01 m f lucent technologies inc. 7 data sheet LU6612 july 2000 fa st cat single-fet for 10base-t/100base-tx description (continued) 5-5433.j key: l = lucents LU6612. q = quality semiconductor inc. qs6612. figure 4. onboard universal twisted-pair interface circuit to interchange lucent and quality semiconductor inc. parts LU6612 rj-45 1 2 3 4 5 6 7 8 l = q = 1:1 l = 1:1; q = 1.25:1 rx ry tx ty l = 50 w vdd 63 64 8 9 vdd q = 0 w l = open q = 86.6 w l = 0 w q = open l = 50 w q = 86.6 w l = 220 w q = 39 w l = 220 w q = open q = 0.1 m f l = 0 w q = open l = q = 75 w l = q = 75 w l = q = 75 w l = q = 75 w q = 1000 pf l = 0.01 w q = 0.1 m f l = 0 w q = 20 w l = 0 w q = 20 w q = 0 w l = open l = 0 w q = open q = 0 w l = open l = 0.001 m f l = 0.001 m f q = 60 w l = 50 w l = 50 w q = 0 w l = 0 w q = 20 w l = 0.01 m f l = 0.01 m f l = 0.01 m f q = open qs6612 LU6612 data sheet fastcat single-fet for 10base-t/100base-tx july 2000 8 lucent technologies inc. pin information 5-5866.r2 figure 5. LU6612 pinout v cc bg iset_100 gndbg linkled/phyad[0] actled/phyad[1] v cc ioa gndioa tx ty gndt v cc t clkref gndbt v cc bt test[0] test[1] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 gnddigb tx_clk rx_er/rxd[4] rx_dv rx_clk col crs gndioc rxd[0] rxd[1] rxd[2] rxd[3] gnddiga v cc diga txd[0] txd[1] 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 phyad[4] pcsen test[2] v cc pll lsclk1 lsclk2 gndpll iset_10 mdio mdc reset rx_en tx_er/txd[4] tx_en txd[3] txd[2] 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 v cc digb mode[0] mode[1] mode[2] gndiob v cc iob fudupled/phyad[3] speedled/phyad[2] bgref[1] bgref[0] gndrec v cc rec v cc eqap ry rx gndeqap 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 LU6612 lucent technologies inc. 9 data sheet LU6612 july 2000 fa st cat single-fet for 10base-t/100base-tx pin information (continued) pin descriptions table 1. mii/serial interface pins (17) signal type pin description col o 43 collision detect. this signal signifies in half-duplex mode that a collision has occurred on the network. col is asserted high whenever there is transmit and receive activity on the utp media. col is the logical and of tx_en and receive activity, and is an asynchronous output. when serial_sel (register 30, bit 1) is high and in 10base-t mode, this signal indicates the jabber timer has expired. this signal is held low in full-duplex mode. crs o 42 carrier sense. when crs_sel (register 29, bit 10) is low, crs is asserted high when either the transmit or receive is nonidle. this signal remains asserted through- out a collision condition. when crs_sel (register 29, bit 10) is high, crs is asserted on receive activity only. rx_clk o 44 receive clock. 25 mhz clock output in 100 mbits/s mode, 2.5 mhz output in 10 mbits/s nibble mode, 10 mhz in 10 mbits/s serial mode. rx_clk has a worst-case 45/55 duty cycle. rx_clk provides the timing reference for the transfer of rx_dv, rxd, and rx_er signals. rxd[3:0] o 37:40 receive data. 4-bit parallel data outputs that are synchronous to the falling edge of rx_clk. when rx_er is asserted high in 100 mbits/s mode, an error code will be presented on rxd[3:0] where appropriate. the codes are as follows: n packet errors: error_codes = 2h; n link errors: error_codes = 3h (packet and link error codes will only be repeated if registers [29.9] and [29.8] are enabled.); n premature end errors: error_codes = 4h; n code errors: error_codes = 5h. when serial_sel (register 30, bit 1) is active-high and 10 mbits/s mode is selected, rxd[0] is used for data output and rxd[3:1] are 3-stated. rx_dv o 45 receive data valid. when this pin is high, it indicates the LU6612 is recovering and decoding valid nibbles on rxd[3:0], and the data is synchronous with rx_clk. rx_dv is synchronous with rx_clk. this pin is not used in serial 10 mbits/s mode. rx_er/ rxd[4] o46 receive error. when high, rx_er indicates the LU6612 has detected a coding error in the frame presently being transferred. rx_er is synchronous with rx_clk. when the encode/decode bypass (edb) is selected through the mii management interface, this output serves as the rxd[4] output. this pin is only valid when LU6612 is in 100 mbits/s mode. tx_clk o 47 transmit clock. 25 mhz clock output in 100 mbits/s mode, 2.5 mhz output in 10 mbits/s mii mode, 10 mhz output in 10 mbits/s serial mode. tx_clk provides tim- ing reference for the transfer of the tx_en, txd, and tx_er signals. these signals are sampled on the rising edge of tx_clk. txd[3:0] i 31:34 transmit data. 4-bit parallel input synchronous with tx_clk. when serial_sel (register 30, bit 1) is active-high and 10 mbits/s mode is selected, only txd[0] is valid. tx_en i 30 transmit enable. when driven high, this signal indicates there is valid data on txd[3:0]. tx_en is synchronous with tx_clk. when serial_sel (register 30, bit 1) is active-high and 10 mbits/s mode is selected, this pin indicates there is valid data on txd[0]. LU6612 data sheet fastcat single-fet for 10base-t/100base-tx july 2000 10 lucent technologies inc. table 2. mii management pins (2) table 3. 10/100 mbits/s twisted-pair (tp) interface pins (4) tx_er/ txd[4] i29 transmit coding error. when driven high, this signal causes the encoder to inten- tionally corrupt the byte being transmitted across the mii (00100 will be transmitted). when the encoder/decoder bypass bit is set, this input serves as the txd[4] input. when in 10 mbits/s mode and serial_sel (register 30, bit 1) is active-high, this pin is ignored. rx_en i 28 receive enable. when this pin is high, the outputs (rxd[3:0], rx_er, rx_clk, rx_dv) are enabled. this pin has an internal 100 k w pull-up resistor. signal type pin description mdc i 26 management data clock. this is the timing reference for the transfer of data on the mdio signal. this signal may be asynchronous to rx_clk and tx_clk. the standard clock rate is 2.5 mhz, the maximum clock rate is 12.5 mhz. when running mdc above 6.25 mhz, mdc must be synchronous with lsclk and have a setup time of 15 ns and a hold time of 5 ns with respect to lsclk. mdio io 25 management data input/output. this i/o is used to transfer control and status infor- mation between LU6612 and the station management. control information is driven by the station management synchronous with mdc. status information is driven by the LU6612 synchronous with mdc. signal type pin description rx i 63 received data. positive differential received 125 mbaud mlt3 or 10 mbaud manchester data from magnetics. ry i 62 received data. negative differential received 125 mbaud mlt3 or 10 mbaud manchester data from magnetics. tx o 8 transmit data. positive differential transmit 125 mbaud mlt3 or 10 mbaud manchester data to magnetics. ty o 9 transmit data. negative differential transmit 125 mbaud mlt3 or 10 mbaud manchester data to magnetics. signal type pin description pin information (continued) table 1. mii/serial interface pins (17) (continued) lucent technologies inc. 11 data sheet LU6612 july 2000 fa st cat single-fet for 10base-t/100base-tx pin information (continued) table 4. ground and power pins (21) table 5. miscellaneous pins (20) * - indicates there is an internal pull-up; indicates there is an internal pull-down. signal type pin description v cc ioa pwr 6 digital +5 v power supply for i/o gndioa pwr 7 digital ground for i/o v cc iob pwr 54 digital +5 v power supply for i/o gndiob pwr 53 digital ground for i/o gndioc pwr 41 digital ground for i/o v cc diga pwr 35 digital +5 v power supply for logic gnddiga pwr 36 digital ground for logic v cc digb pwr 49 digital +5 v power supply for logic gnddigb pwr 48 digital ground for logic v cc rec pwr 60 digital +5 v power supply for clock recovery circuit gndrec pwr 59 digital ground for clock recovery circuit v cc pll pwr 20 analog +5 v power supply for 10 mhz and 100 mhz pll clock synthesizer gndpll pwr 23 analog ground for 10 mhz and 100 mhz pll clock synthesizer v cc t pwr 11 analog +5 v power supply for transmitter gndt pwr 10 analog ground for transmitter v cc eqap pwr 61 analog +5 v power supply for equalizer and adaptation circuit gndeqap pwr 64 analog ground for adaptation circuit. v cc bg pwr 1 analog +5 v power supply for band-gap circuit gndbg pwr 3 analog ground band-gap circuit v cc bt pwr 14 analog +5 v power supply for 10base-t transmitter gndbt pwr 13 analog ground for 10base-t transmitter signal type * pin description lsclk1 i 21 local symbol clock. 25 mhz clock, 100 ppm, 40%60% duty cycle. this input is connected to one terminal of a 25 mhz crystal or an external 25 mhz clock source. lsclk2 o 22 local symbol clock. 25 mhz crystal feedback. this output is connected to the other terminal of a 25 mhz crystal or an external 25 mhz. if lsclk1 is driven from an external clock source, lsclk2 is left unconnected. linkled/ phyad[0] i/o 4 link led. this pin indicates g ood link status. at powerup/reset, this pin is sampled as input and to set the phyad [ 0 ] bit. if pulled hi g h throu g h a resistor, this pin will set phyad [ 0 ] to a hi g h or if pulled low throu g h a resistor, will set phyad [ 0 ] to a zero. when this pin is pulled hi g h the led output will be active-low, when pulled low the led output will be active-hi g h. actled/ phyad[1] i/o 5 activit y led. this pin indicates transmit/receive activit y . at powerup/reset, this pin is sampled as input to set the phyad [ 1 ] bit. if pulled hi g h throu g h a resistor, this pin will set phyad [ 1 ] to a hi g h or if pulled low throu g h a resistor, will set phyad [ 1 ] to a zero. when this pin is pulled hi g h the led output will be active-low, when pulled low the led output will be active-hi g h. LU6612 data sheet fastcat single-fet for 10base-t/100base-tx july 2000 12 lucent technologies inc. pin information (continued) table 5. miscellaneous pins (20) (continued) signal type * pin description speed- led/ phyad[2] i/o 56 s p eed led. this pin indicates the operatin g speed of LU6612: n led is active when in 100 mbits/s operation. n led is not active when in 10 mbits/s operation. at powerup/reset, this pin is sampled as input and to set the phyad [ 2 ] bit. if pulled hi g h throu g h a resistor, this pin will set phyad [ 2 ] to a hi g h or if pulled low throu g h a resistor, will set phyad [ 2 ] to a zero. when this pin is pulled hi g h, the led output will be active-low, when pulled low, the led output will be active-hi g h. fudu- pled/ phyad[3] i/o 55 full-du p lex led. this pin indicates the operatin g mode of LU6612 and is onl y valid when link is up: n led is active when in full-duplex mode of operation. n led is not active when in half-duplex mode of operation. at powerup/reset, this pin is sampled as an input to set the phyad [ 3 ] bit. if pulled hi g h throu g h a resistor, this pin will set phyad [ 3 ] to a hi g h or if pulled low throu g h a resistor, will set phyad [ 3 ] to a zero. when this pin is pulled hi g h, the led output will be active-low, when pulled low, the led output will be active-hi g h. phyad[4] i - 17 phyad[4]. at powerup/reset, this pin is sampled as an input to set the phyad[4] bit. if pulled high through a resistor, this pin will set phyad[4] to a high or if pulled low through a resistor, will set phyad[4] to a zero. this pin has an internal 100 k w pull- up resistor. mode[2:0] i - 52:50 mode selection. these pins carry encoded signals that are latched into the LU6612 upon powerup/reset and define specific modes of operation: half/full duplex, autone- gotiation enabled/disabled, and transceiver isolation. refer to table 20 for the various modes and how various registers are affected. pins [52:50] have internal 100 k w pull- ups. if left floating, LU6612 will default to all capable, autonegotiation enabled mode. test[0] i - 15 test enable pin for factory testing. this pin has an internal 100 k w pull-down resistor. the pin can be either left floating or tied down. test[2:1] i 19, 16 test enable pin for factory testing. these two pins have internal 50 k w pull-down resistors. these pins can either be left floating or tied low. clkref i 12 clock reference. connect this pin to a 1 nf 10% capacitor to ground. reset i27 full chip reset (active-low). reset is an active-low signal. reset must be asserted low for at least five lsclk cycles. the LU6612 will come out of reset after 400 m s. lsclk1 must remain running during reset. bgref[1:0] i 57:58 band-gap reference. connect these pins to a 24.9 k w 1% resistor to ground. the parasitic load capacitance should be less than 15 pf. iset_100 i 2 current set 100 mbits/s. an external reference resistor (24.9 k w ) is placed from this pin to ground to set the 100 mbits/s tp driver transmit output level. iset_10 i 24 current set 10 mbits/s. an external reference resistor (22.1 k w ) is placed from this pin to ground to set the 10 mbits/s tp driver transmit output level. pcsen i - 18 pcs enable (active-low). when this pin is active-low, the encoded 5-bit symbols appear on rxd[4:0] and txd[4:0]. when this pin high, 4-bit data appears on rxd[3:0] and txd[3:0]. when pcsen is low, LU6612 bypasses the 4b5b encoder/ decoder, the align function, the scrambler/descrambler, and does not detect and gen- erate j/k and r/t code groups at the start or end of frame. this pin has an internal 100 k w pull-up. * - indicates there is an internal pull-up; indicates there is an internal pull-down. lucent technologies inc. 13 data sheet LU6612 july 2000 fa st cat single-fet for 10base-t/100base-tx mii station management basic operations the primary function of station management is to transfer control and status information about the LU6612 to a management entity. this function is accomplished by the mdc clock input, which has a maximum frequency of 12.5 mhz, along with the mdio pin. the management interface (mii) uses mdc and mdio to physically transport information between the phy and the station management entity. a specific set of registers and their contents (described in table 8) defines the nature of the information transferred across this interface. frames transmitted on the mii management interface will have the frame structure shown in table 6. the order of bit transmission is from left to right. note that reading and writing of the management register must be completed without interruption. mii management frames the fields and format for management frames are described in the following tables. table 6. mii management frame fields and format table 7. mii management frame descriptions read/write (r/w) pre st op phyadd regad ta data idle r 1 . . . 1 01 10 aaaaa rrrrr z0 dddddddddddddddd z w 1 . . . 1 01 01 aaaaa rrrrr 10 dddddddddddddddd z field description pre preamble. the preamble is a series of 32 1s. the LU6612 will accept frames with no preamble. this is indicated by a 1 in register 1, bit 6. st start of frame. the start of frame is indicated by a 01 pattern. op operation code. the operation code for a read transaction is 10. the operation code for a write transaction is 01. phyadd phy address. the phy address is 5 bits, allowing for 32 unique addresses. the first phy address bit transmitted and received is the msb of the address. a station management entity, which is attached to multiple phy entities, must have prior knowledge of the appropriate phy address for each entity. the address 00000 is the broadcast address. this address will produce a match regardless of the local address. regad register address. the register address is 5 bits, allowing for 32 unique registers within each phy. the first register address bit transmitted and received is the msb of the address. ta turnaround. the turnaround time is a 2-bit time spacing between the register address field and the data field of a frame to avoid drive contention on mdio during a read transaction. during a write to the LU6612, these bits are driven to a 10 by the station. during a read, the mdio is not driven dur- ing the first bit time and is driven to a 0 by the LU6612 during the second bit time. data data. the data field is 16 bits. the first bit transmitted and received is bit 15 of the register being addressed. LU6612 data sheet fastcat single-fet for 10base-t/100base-tx july 2000 14 lucent technologies inc. mii station management (continued) register overview the mii management 16-bit register (mr) set is implemented as described in table 8 below. table 8. mii management registers (mr) register address symbol name default (hex code) 0 mr0 control register 3000 1 mr1 status register 7849 2 mr2 phy identifier register 1 0180 3 mr3 phy identifier register 2 7641 4 mr4 autonegotiation advertisement register 01e1 5 mr5 autonegotiation link partner ability register (base_page) 0000 5 mr5 autonegotiation link partner ability register (next_page) 6 mr6 autonegotiation expansion register 0000 7 mr7 next-page transmit register 0000 827 mr8mr27 reserved 0000 28 mr28 device specific register 1 0000 29 mr29 device specific register 2 1000 30 mr30 device specific register 3 0000 lucent technologies inc. 15 data sheet LU6612 july 2000 fa st cat single-fet for 10base-t/100base-tx mii station management (continued) this section provides a detailed discussion of each management register and its bit definitions. table 9. mr0control register bit descriptions 1. note that the format for the pin descriptions is as follows: the first number is the register number, the second number is t he bit position in the register, and the name of the instantiated pad is in capital letters. 2. r = read, w = write, na = not applicable. bit 1 type 2 description 0.15 (sw_reset) r/w reset. setting this bit to a 1 will reset the LU6612. all registers will be set to their default state. this bit is self-clearing. the default is 0. 0.14 (loopback) r/w loopback. when this bit is set to 1, no data transmission will take place on the media. any receive data will be ignored. the loopback signal path will contain all circuitry up to, but not including, the pmd. the autonegotiation must be turned off, before loopback can be initiated, transmit data can be started 2 ms after loopback is initiated. the default value is a 0. 0.13 (speed100) r/w speed selection. the value of this bit reflects the current speed of operation (1 = 100 mbits/s; 0 = 10 mbits/s). this bit will only affect operating speed when the autonegotiation enable bit (register 0, bit 12) is disabled (0). this bit is ignored when autonegotiation is enabled (register 0, bit 12). the bit is set high when mode[2:0] is 010 or 011 or 100. the default is 1. 0.12 (nway_ena) r/w autonegotiation enable. the autonegotiation process will be enabled by set- ting this bit to a 1. this bit overrides speed100 bit (register 0, bit 13) and full_dup bit (register 0, bit 8). this bit is set high when mode[2:0] is 100 or 111. autonegotiation must be disabled before loopback can be initiated. the default state is a 1. 0.11 (pwrdn) r/w powerdown. the LU6612 may be placed in a low-power state by setting this bit to a 1, both the 10 mbits/s transceiver and the 100 mbits/s transceiver will be powered down. while in the powerdown state, the LU6612 will respond to management transactions. the default state is a 0. 0.10 (isolate) r/w isolate. when this bit is set to a 1, the mii outputs will be brought to the high- impedance state. the default state is a 0. 0.9 (redonway) r/w restart autonegotiation. normally, the autonegotiation process is started at powerup. the process may be restarted by setting this bit to a 1. the default state is a 0. the nwaydone bit (register 1, bit 5) is reset when this bit goes to a 1. this bit is self-cleared when autonegotiation restarts. 0.8 (full_dup) r/w duplex mode. this bit reflects the mode of operation (1 = full duplex; 0 = half duplex). this bit is ignored when the autonegotiation enable bit (register 0, bit 12) is enabled. the default state is a 0. this bit is set as a 1 during powerup/ reset, when mode[2:0] is 001 or 011. 0.7 (coltst) r/w collision test. when this bit is set to a 1, the LU6612 will assert the col sig- nal in response to tx_en. this bit should only be set when in loopback mode. 0.6:0 na reserved. all bits will read 0. LU6612 data sheet fastcat single-fet for 10base-t/100base-tx july 2000 16 lucent technologies inc. mii station management (continued) table 10. mr1status register bit descriptions 1. note that the format for the pin descriptions is as follows: the first number is the register number, the second number is t he bit position in the register, and the name of the instantiated pad is in capital letters. 2. r = read. bit 1 type 2 description 1.15 (t4able) r 100base-t4 ability. this bit will always be a 0. 0: not able 1: able 1.14 (txfuldup) r 100base-tx full-duplex ability. this bit will always be a 1. 0: not able 1: able 1.13 (txhafdup) r 100base-tx half-duplex ability. this bit will always be a 1. 0: not able 1: able 1.12 (enfuldup) r 10base-t full-duplex ability. this bit will always be a 1. 0: not able 1: able 1.11 (enhafdup) r 10base-t half-duplex ability. this bit will always be a 1. 0: not able 1: able 1.10:7 r reserved. all bits will read as a 0. 1.6 (no_pa_ok) r suppress preamble. this bit is set to a 1, indicating that the LU6612 accepts management frames with the preamble suppressed. (this function is not sup- ported by qs6611.) 1.5 (nwaydone) r autonegotiation complete. when this bit is a 1, it indicates the autonegotiation process has been completed. the contents of registers mr4, mr5, mr6, and mr7 are now valid. the default value is a 0. this bit is reset when autonegotia- tion is started. 1.4 (rem_flt) r remote fault. when this bit is a 1, it indicates a remote fault has been detected. this bit will remain set until cleared by reading the register. the default is a 0. 1.3 (nwayable) r autonegotiation ability. when this bit is a 1, it indicates the ability to perform autonegotiation. the value of this bit is always a 1. 1.2 (lstat_ok) r link status. when this bit is a 1, it indicates a valid link has been established. this bit has a latching function: a link failure will cause the bit to clear and stay cleared until it has been read via the management interface. 1.1 (jabber) r jabber detect. this bit will be a 1 whenever a jabber condition is detected. it will remain set until it is read, and the jabber condition no longer exists. 1.0 (ext_able) r extended capability. this bit indicates that the LU6612 supports the extended register set (mr2 and beyond). it will always read a 1. lucent technologies inc. 17 data sheet LU6612 july 2000 fa st cat single-fet for 10base-t/100base-tx mii station management (continued) table 11. mr2, 3phy identifier registers (1 and 2) bit descriptions 1. note that the format for the pin descriptions is as follows: the first number is the register number, the second number is t he bit position in the register, and the name of the instantiated pad is in capital letters. 2. r = read. table 12. mr4autonegotiation advertisement register bit descriptions 1. note that the format for the pin descriptions is as follows: the first number is the register number, the second number is t he bit position in the register, and the name of the instantiated pad is in capital letters. 2. r = read, w = write. bit 1 type 2 description 2.15:0 (oui[3:18]) r organizationally unique identifier. the third through the 24th bits of the oui assigned to the phy manufacturer by the ieee are to be placed in bits 2.15:0 and 3.15:10. the value for bits 15:0 of register 2 is 0180h. 3.15:10 (oui[19:24]) r organizationally unique identifier. the remaining 6 bits of the oui. the value for bits 15:10 of register 3 is 1dh. 3.9:4 (model[5:0]) r model number. 6-bit model number of the device. the model number is 12 decimal. 3.3:0 (version[3:0]) r revision number. the value of the present revision number. the value is 0001b for the first version. bit 1 type 2 description 4.15 (next_page) r/w next page. the next page function is activated by setting this bit to a 1. this will allow the exchange of arbitrary pieces of data. data is carried by optional next pages of information. (this function is not supported by qs6611.) 4.14 (ack) r/w acknowledge. this bit is written to a logic zero and ignored on read. 4.13 (rem_fault) r/w remote fault. when set to 1, the LU6612 indicates to the link partner a remote fault condition. 4.12:10 (pause) r/w pause. when set to 1, indicates that the LU6612 wishes to exchange flow control information with its link partner. 4.9 (100baset4) r/w 100base-t4. this bit should always be set to a 0. 4.8 (100baset_fd) r/w 100base-tx full duplex. if written to 1, autonegotiation will advertise that the LU6612 is capable of 100base-tx full-duplex operation. this bit is set high when mode[2:0] is 111. 4.7 (100basetx) r/w 100base-tx. if written to 1, autonegotiation will advertise that the LU6612 is capable of 100base-tx operation. 4.6 (10baset_fd) r/w 10base-t full duplex. if written to 1, autonegotiation will advertise that the LU6612 is capable of 10base-t full-duplex operation. this bit is set high when mode[2:0] is 111. 4.5 (10baset) r/w 10base-t. if written to 1, autonegotiation will advertise that the LU6612 is capable of 10base-t operation. this bit is set high when mode[2:0] is 111. 4.4:0 (select) r/w selector field. reset with the value 00001 for ieee 802.3. LU6612 data sheet fastcat single-fet for 10base-t/100base-tx july 2000 18 lucent technologies inc. mii station management (continued) table 13. mr5autonegotiation link partner (lp) ability register bit descriptions (base_page) 1. note that the format for the pin descriptions is as follows: the first number is the register number, the second number is t he bit position in the register, and the name of the instantiated pad is in capital letters. 2. r = read. table 14. mr5autonegotiation link partner (lp) ability register bit descriptions (next_page) 1. note that the format for the pin descriptions is as follows: the first number is the register number, the second number is t he bit position in the register, and the name of the instantiated pad is in capital letters. 2. r = read. bit 1 type 2 description 5.15 (lp_next_page) r link partner next page. when this bit is set to 1, it indicates that the link partner wishes to engage in next page exchange. 5.14 (lp_ack) r link partner acknowledge. when this bit is set to 1, it indicates that the link partner has successfully received at least three consecutive and consistent flp bursts. 5.13 (lp_rem_fault) r link partner remote fault. when this bit is set to 1, it indicates that the link partner has a fault. 5.12:10 r reserved. these bits are reserved. 5.9 (lp_100baset4) r link partner 100base-t4. when this bit is set to 1, it indicates that link part- ner is capable of 100base-t4 operation. 5.8 (lp_100baset_fd) r link partner 100base-tx full duplex. when this bit is set to 1, it indicates that link partner is capable of 100base-tx full-duplex operation. 5.7 (lp_100basetx) r link partner 100base-tx. when this bit is set to 1, it indicates that link part- ner is capable of 100base-tx operation. 5.6 (lp_10baset_fd) r link partner 10base-t full duplex. when this bit is set to 1, it indicates that link partner is capable of 10base-t full-duplex operation. 5.5 (lp_10baset) r link partner 10base-t. when this bit is set to 1, it indicates that link partner is capable of 10base-t operation. 5.4:0 (lp_select) r selector field. this field contains the type of message sent by the link part- ner. for ieee 802.3 compliant link partners, this field should read 00001. bit 1 type 2 description 5.15 (lp_next_page) r next page. when this bit is set to a logic 0, it indicates that this is the last page to be transmitted. a logic 1 indicates that additional pages will follow. 5.14 (lp_ack) r acknowledge. when this bit is set to a logic 1, it indicates that the link part- ner has successfully received its partners link code word. 5.13 (lp_mes_page) r message page. this bit is used by the next_page function to differentiate a message page (logic one) from an unformatted page (logic zero). 5.12 (lp_ack2) r acknowledge 2. this bit is used by next_page function to indicate that a device has the ability to comply with the message (logic one) or not (logic zero). 5.11 (lp_toggle) r toggle. this bit is used by the arbitration function to ensure synchronization with the link partner during next page exchange. logic 0 indicates that the previous value of the transmitted link code word was logic 1. logic 1 indicates that the previous value of the transmitted link code word was logic 0. 5.10:0 (mcf) r message/unformatted code field. with these 11 bits, there are 2048 possi- ble messages. message code field definitions are described in annex 28c of the ieee 802.3u standard. lucent technologies inc. 19 data sheet LU6612 july 2000 fa st cat single-fet for 10base-t/100base-tx mii station management (continued) table 15. mr6autonegotiation expansion register bit descriptions 1. note that the format for the pin descriptions is as follows: the first number is the register number, the second number is t he bit position in the register, and the name of the instantiated pad is in capital letters. 2. r = read, lh = latched high. table 16. mr7next_page transmit register bit descriptions 1. note that the format for the pin descriptions is as follows: the first number is the register number, the second number is t he bit position in the register, and the name of the instantiated pad is in capital letters. 2. r = read, w = write. bit 1 type 2 description 6.15:5 r reserved. 6.4 (par_det_fault) r/lh parallel detection fault. when this bit is set to 1, it indicates that a fault has been detected in the parallel detection function. this fault is due to more than one technology detecting concurrent link conditions. this bit can only be cleared by reading this register. 6.3 (lp_next_page_able) r link partner next page able. when this bit is set to 1, it indicates that the link partner supports the next page function. 6.2 (next_page_able) r next page able. this bit is set to 1, indicating that this device supports the next page function. 6.1 (page_rec) r/lh page received. when this bit is set to 1, it indicates that a next page has been received. 6.0 (lp_nway_able) r link partner autonegotiation capable. when this bit is set to 1, it indi- cates that the link partner is autonegotiation capable. bit 1 type 2 description 7.15 (next_page) r/w next page. this bit indicates whether or not this is the last next page to be trans- mitted. when this bit is 0, it indicates that this is the last page. when this bit is 1, it indicates there is an additional next page. 7.14 (ack) r acknowledge. this bit is the acknowledge bit from the link code word. 7.13 (message) r/w message page. this bit is used to differentiate a message page from an unfor- matted page. when this bit is 0, it indicates an unformatted page. when this bit is 1, it indicates a formatted page. 7.12 (ack2) r/w acknowledge 2. this bit is used by the next page function to indicate that a device has the ability to comply with the message. acknowledge 2 will be set as follows: n when this bit is 0, it indicates the device cannot comply with the message. n when this bit is 1, it indicates the device will comply with the message. 7.11 (toggle) r toggle. this bit is used by the arbitration function to ensure synchronization with the link partner during next page exchange. this bit will always take the opposite value of the toggle bit in the previously exchanged link code word: n if the bit is a logic 0, the previous value of the transmitted link code word was a logic 1. n if the bit is a 1, the previous value of the transmitted link code word was a 0. the initial value of the toggle bit in the first next page transmitted is the inverse of the value of bit 11 in the base link code word and, therefore, may assume a value of 1 or 0. 7.10:0 (mcf) r/w message/unformatted code field. with these 11 bits, there are 2048 possible messages. message code field definitions are described in annex 28c of the ieee 802.3u standard. LU6612 data sheet fastcat single-fet for 10base-t/100base-tx july 2000 20 lucent technologies inc. mii station management (continued) table 17. mr28device-specific register 1 (status register) bit descriptions 1. note that the format for the pin descriptions is as follows: the first number is the register number, the second number is t he bit position in the register, and the name of the instantiated pad is in capital letters. 2. r = read, lh = latched high. bit 1 type 2 description 28.15:9 (r28[15:9]) r unused. read as 0. 28.8 (bad_frm) r/lh bad frame. if this bit is a 1, it indicates a packet has been received without an sfd. this bit is only valid in 10 mbits/s mode. this bit is latching high and will only clear after it has been read or the device has been reset. the default is 0. 28.7 (code) r/lh code violation. when this bit is a 1, it indicates a manchester code violation has occurred. the error code will be output on the rxd lines. refer to table 1 for a detailed description of the rxd pin error codes. this bit is only valid in 10 mbits/s mode. this bit is latching high and will only clear after it has been read or the device has been reset. the default is 0. 28.6 (aps) r autopolarity status. when register 30, bit 3 is set and this bit is a 1, it indicates the LU6612 has detected and corrected a polarity reversal on the twisted pair. if the apf_en bit (register 30, bit 3) is set, the reversal will be corrected inside the LU6612. this bit is not valid in 100 mbits/s operation. the default is 0. 28.5 (discon) r/lh disconnect. if this bit is a 1, it indicates a disconnect. this bit will latch high until read. this bit is only valid in 100 mbits/s mode. the default is 0. 28.4 (unlocked) r/lh unlocked. indicates that the tx scrambler lost lock. this bit will latch high until read. this bit is only valid in 100 mbits/s mode. the default is 0. 28.3 (rxerr_st) r/lh rx error status. indicates a false carrier. this bit will latch high until read. this bit is only valid in 100 mbits/s mode. the default is 0. 28.2 (frc_jam) r/lh force jam. this bit will latch high until read. this bit is only valid in 100 mbits/s mode. the default is 0. 28.1 (lnk100up) r link up 100. this bit, when set to a 1, indicates a 100 mbits/s transceiver is up and operational. the default is 0. 28.0 (lnk10up) r link up 10. this bit, when set to a 1, indicates a 10 mbits/s transceiver is up and operational. the default is 0. lucent technologies inc. 21 data sheet LU6612 july 2000 fa st cat single-fet for 10base-t/100base-tx mii station management (continued) table 18. mr29device-specific register 2 (100 mbits/s control) bit descriptions 1. note that the format for the pin descriptions is as follows: the first number is the register number, the second number is t he bit position in the register, and the name of the instantiated pad is in capital letters. 2. r = read, w = write. bit 1 type 2 description 29.15 (localrst) r/w management reset. this is the local management reset bit. writing a logic 1 to this bit will cause the lower 16 registers and registers 28 and 29 to be reset to their default values. this bit is self-clearing. the default is 0. 29.14 (rst1) r/w generic reset 1. this register is used for manufacture test only. the default is 0. 29.13 (rst2) r/w generic reset 2. this register is used for manufacture test only. the default is 0. 29.12 (100off) r/w 100 mbits/s transmitter off. when this bit is set to 0, it forces rx low and ry high. this bit defaults to 1. 29.11 r/w reserved. program to zero. 29.10 (crs_sel) r/w carrier sense select. crs will be asserted on receive only when this bit is set to a 1. if this bit is set to logic 0, crs will be asserted on receive or transmit. the default is 0. 29.9 (link_err) r/w link error indication. when this bit is a 1, a link error code will be reported on rxd[3:0] of the LU6612 when rx_er is asserted on the mii. the specific error codes are listed in the rxd pin description. if it is 0, it will disable this function. the default is 0. 29.8 (pkt_err) r/w packet error indication enable. when this bit is a 1, a packet error code, which indicates that the scrambler is not locked, will be reported on rxd[3:0] of the LU6612 when rx_er is asserted on the mii. when this bit is 0, it will disable this function. the default is 0. 29.7 (reserved) r/w reserved. this bit must remain as a zero. the default is 0. 29.6 (edb) r/w encoder/decoder bypass. when this bit is set to 1, the 4b/5b encoder and 5b/4b decoder function will be disabled. the default is a zero. at powerup/reset, if pcsen is strapped low, then this bit is set to a 1. the default is 0. 29.5 (sab) r/w symbol aligner bypass. when this bit is set to 1, the aligner function will be dis- abled. the default is 0. 29.4 (sdb) r/w scrambler/descrambler bypass. when this bit is set to 1, the scrambling/ descrambling functions will be disabled. the default is a zero. at powerup/reset, if pcsen is strapped low, then this bit is set to a 1. the default is 0. 29.3 (carin_en) r/w carrier integrity enable. when this bit is set to a 1, carrier integrity is enabled. (this function is not supported by qs6611.) the default is 0. 29.2 (jam_col) r/w jam enable. when this bit is a 1, it enables jam associated with carrier integrity to be ored with col. the default is 0. 29.1 (reserved) r/w reserved. this bit must remain as a zero. the default is 0. 29.0 (reserved) r/w reserved. this bit must remain as a zero. the default is 0. LU6612 data sheet fastcat single-fet for 10base-t/100base-tx july 2000 22 lucent technologies inc. mii station management (continued) table 19. mr30device-specific register 3 (10 mbits/s control) bit descriptions 1. note that the format for the pin descriptions is as follows: the first number is the register number, the second number is t he bit position in the register, and the name of the instantiated pad is in capital letters. 2. r = read, w = write. bit 1 type 2 description 30.15:6 (r30[15:6]) r/w unused. read as 0. 30.5 (hbt_en) r/w heartbeat enable. when this bit is a 1, the heartbeat function will be enabled. valid in 10 mbits/s mode only. the default is 0. 30.4 (ell_en) r/w extended line length enable. when this bit is a 1, the receive squelch lev- els are reduced from a nominal 435 mv to 350 mv, allowing reception of sig- nals with a lower amplitude. valid in 10 mbits/s mode only. the default is 0. 30.3 (apf_en) r/w autopolarity function enable. when this bit is a 1 and the LU6612 is in 10 mbits/s mode, the autopolarity function will determine if the tp link is wired with a polarity reversal. if there is a polarity reversal, the LU6612 will assert the aps bit (register 28, bit 6) and correct the polarity reversal. if this bit is a 0 and the device is in 10 mbits/s mode, the reversal will not be corrected. the default is 0. 30.2 (ref_sel) r/w reference select. when this bit is a 1, the external 10 mhz reference of pin ref10 is used for phase alignment. this bit defaults to a 0. 30.1 (serial _sel) r/w serial select. when this bit is set to a 1, 10 mbits/s serial mode will be selected. when the LU6612 is in 100 mbits/s mode, this bit will be ignored. the default is 0. 30.0 (ena_no_lp) r/w no link partner mode. setting this bit to a 1 will allow 10 mbits/s operation with link pulses disabled. if the LU6612 is configured for 100 mbits/s opera- tion, setting this bit will not affect operation. the default is 0. lucent technologies inc. 23 data sheet LU6612 july 2000 fa st cat single-fet for 10base-t/100base-tx mode selection LU6612 can be forced to operate in specific operating modes. this is achieved by configuring the mode pins to the appropriate values at powerup/reset. the strapping options of the mode pins are latched on reset to set the default values of various registers. the values can be modified by writing into the registers. the mode[2:0] pins have 100 k w internal pull-ups. if mode[2:0] are left floating, LU6612 will default to all capable, autonegotiation enabled mode. the different modes of operation of LU6612 and the register bits affected are presented in the following table. table 20. operation modes of LU6612 table 21. LU6612 crystal specifications mode [2:0] definition register.bit 0.8 0.10 0.12 0.13 4.5 4.6 4.8 000 10base-t, half-duplex with autonegotiation disabled 0 0 0 0101 00110base-t, full-duplex with autonegotiation disabled 1000111 010100base-tx, half-duplex with autonegotiation disabled 0001001 011 100base-tx, full-duplex with autonegotiation disabled 1 0 0 1001 100advertise 100base-tx, half-duplex autonegotiation enabled 0011000 101reserved 110isolate mii 0101110 111 all capable, autonegotiation enabled 0 0 1 1111 parameter requirement type quartz fundamental mode frequency 25 mhz stability 25 ppm, 070 c shunt capacitor 7 pf load capacitor 20 pf series resistance <30 w LU6612 data sheet fastcat single-fet for 10base-t/100base-tx july 2000 24 lucent technologies inc. absolute maximum ratings (t a = 25 c) stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. table 22. absolute maximum ratings table 23. operating conditions * typical power dissipations are specified at 5.0 v and 25 c. this is the power dissipated by the LU6612 transmitting over 100 meters of cable. electrical characteristics the following specifications apply for v dd = 5 v 5%. table 24. dc characteristics parameter symbol min max unit ambient operating temperature t a 070 c storage temperature t stg C40 125 c voltage on any pin with respect to ground C0.5 v dd + 0.5 v maximum supply voltage 5.5 v parameter symbol min typ * max unit operating supply voltage 4.75 5.0 5.25 v power dissipation: 100 mbits/s tx 10 mbits/s autonegotiating p d p d p d 1.4 1.0 1.0 1.6 1.35 w w mw parameter symbol min typ max unit ttl inputs: input high voltage input low voltage input high current input low current input leakage current v ih v il i ih i il i l 2.0 0.8 50 C400 50 v v m a m a m a ttl outputs: output high voltage output low voltage output short-circuit current v oh v ol i sc 2.4 C15 0.45 C85 v v ma 10 mbits/s twisted pair: input voltage v diff 0.35 2.0 v 100 mbits/s twisted pair: input voltage v diff 1.5 v 10 mbits/s twisted pair: output current v diff 45 50 55 ma 100 mbits/s twisted pair: output current v diff 19 20 21 ma lucent technologies inc. 25 data sheet LU6612 july 2000 fa st cat single-fet for 10base-t/100base-tx timing characteristics (preliminary) table 25. mii management interface timing (25 pf load) * when operating mdc above 6.25 mhz, mdc must be synchronous with lsclk and have a setup time of 15 ns and a hold time of 5 ns, with respect to lsclk. 5-4959(f).a figure 6. mdio input timing 5-4960(f).c figure 7. mdio output timing 5-5312(f).r1 note: mdio turnaround (ta) time is a 2-bit time spacing between the register address field, and the data field of a frame to avo id drive conten- tion on mdio during a read transaction. during a write to the LU6612, these bits are driven to a 10 by the station. during a re ad, the mdio is not driven during the first bit time and is driven to a 0 by the LU6612 during the second bit time. figure 8. mdio during ta (turnaround) of a read transaction name parameter min typ max unit t1 mdio valid to rising edge of mdc (setup) 10 ns t2 rising edge of mdc to mdio invalid (hold) 10 ns t3 mdc falling edge to mdio valid (prop. delay) 0 40 ns t4 mdc high* 200 ns t5 mdc low* 40 200 ns t6 mdc period* 80 400 ns mdc mdio t1 t2 mdc mdio t5 t4 t6 t3 mdc mdio < r > < z > < o > LU6612 data sheet fastcat single-fet for 10base-t/100base-tx july 2000 26 lucent technologies inc. timing characteristics (preliminary) (continued) table 26. mii data timing (25 pf load) * 100 mbits/s only. name parameter min typ max unit t1 rxd[3:0], rx_er, rx_dv, valid to rx_clk high 10/100 ns t2 rx_clk high to rxd[3:0], rx_dv, rx_er invalid 10/100 ns t3 rx_clk high 14/180 26/220 ns t4 rx_clk low 14/180 26/220 ns t5 rx_clk period 40 ns t6 tx_clk high 14/180 26/220 ns t7 tx_clk low 14/180 26/220 ns t8 tx_clk period 40 ns t9 txd[3:0], tx_en, tx_er, setup to tx_clk 15/140 ns t10 txd[3:0], tx_en, tx_er, hold to tx_clk 0/0 ns t11 txd[3:0], tx_en, tx_er setup to lsclk* 10 ns t12 txd[3:0], tx_en, tx_er, hold to lsclk* 0 ns t13 first bit of j on rx/ry while transmitting data to col assert (half-duplex mode) 170ns t14 first bit of t received on rx/ry while transmitting to col deasserted (half-duplex mode) 210ns lucent technologies inc. 27 data sheet LU6612 july 2000 fa st cat single-fet for 10base-t/100base-tx timing characteristics (preliminary) (continued) 5-5432(f).cr1 figure 9. mii timing requirements for LU6612 rx/ry t13 col 1st bit of j t7 tx_clk txd[3:0] t6 t8 rx_clk rxd[3:0] t1 t2 tx_en t3 t4 t5 rx_dv rx_er tx_er t9 t10 lsclk txd[3:0] t11 tx_en tx_er t12 1st bit of t t14 LU6612 data sheet fastcat single-fet for 10base-t/100base-tx july 2000 28 lucent technologies inc. timing characteristics (preliminary) (continued) table 27. serial 10 mbits/s timing for rx/ry, crs, and rx_clk 5-5293(f).mr1 figure 10. serial 10 mbits/s timing for rx/ry, crs, and rx_clk table 28. serial 10 mbits/s timing for tx_en, tx/ty, crs, and rx_clk 5-5293(f).nr1 figure 11. serial 10 mbits/s timing for tx_en, tx/ty, crs, and rx_clk name parameter min max unit t15 rx/ry activity to crs assertion 40 500 ns t16 rx/ry activity to rx_clk valid 800 2300 ns t17 idl to crs deassertion 200 550 ns t18 dead signal to crs deassertion 400 1000 ns name parameter min max unit t19 tx_en asserted to transmit pair activity 50 400 ns t20 tx_en asserted to crs asserted due to internal loopback 5 1900 ns t21 tx_en asserted to rx_clk valid due to internal loopback 1000 1700 ns t22 tx_en deasserted to idl transmission 50 300 ns t23 idl pulse width 250 350 ns rx/ry crs (receivestart of packet) (receiveend of packet) (receivedead signal) (not idl) idl t15 t17 t16 t18 rx_clk tx/ty crs (transmitstart of packet) (transmitend of packet) idl t19 t22 t20 t21 t23 tx_en rx_clk lucent technologies inc. 29 data sheet LU6612 july 2000 fa st cat single-fet for 10base-t/100base-tx timing characteristics (preliminary) (continued) table 29. serial 10 mbits/s timing for tx_en, rx/ry, and col 5-5293(f).l figure 12. serial 10 mbits/s timing for tx_en, rx/ry, and col name parameter min max unit t24 time to assert col; LU6612 is transmitting; receive activity starts 40 400 ns t25 time to deassert col; LU6612 is transmitting; receive activity ceases 300 900 ns t26 time to assert col; LU6612 is receiving; transmit activity starts 5 400 ns t27 time to deassert col; LU6612 is receiving; transmit activity ceases 5 900 ns t28 col pulse width 100 ns rx/ry col (transmittingreceive collision detected) (receivingtransmit collison detected) idl t24 t25 t26 t27 t28 tx_en LU6612 data sheet fastcat single-fet for 10base-t/100base-tx july 2000 30 lucent technologies inc. timing characteristics (preliminary) (continued) table 30. serial 10 mbits/s timing for rx_clk, crs, rxd, tx_clk, tx_en, and txd (25 pf load) 5-2736(f).d figure 13. serial 10 mbits/s timing for rx_clk, crs, rxd, tx_clk, tx_en, and txd name parameter min max unit t29 rxd setup before rx_clk rising edge 30 ns t30 rxd held past rx_clk edge 30 ns t31 rx_clk low to crs deassertion (at end of received packet) 40 ns t32 tx_en setup before tx_clk rising edge 30 ns t33 tx_en held past tx_clk rising edge 0 ns t34 txd setup before tx_clk rising edge 30 ns t35 txd held past tx_clk rising edge 0 ns t31 t30 t29 rx_clk crs rxd t32 t34 t33 t35 last bit tx_clk tx_en txd (start of packet) (end of packet) lucent technologies inc. 31 data sheet LU6612 july 2000 fa st cat single-fet for 10base-t/100base-tx timing characteristics (preliminary) (continued) table 31. serial 10 mbits/s timing for rx_clk and tx_clk (25 pf load) 5-2737(f).dr1 figure 14. serial 10 mbits/s timing diagram for rx_clk and tx_clk name parameter min max unit t36 rx_clk low pulse width 45 55 ns t37 rx_clk high pulse width 45 55 ns t38 tx_clk low pulse width 45 55 ns t39 tx_clk high pulse width 45 55 ns rx/ry col (transmittingreceive collision detected) (receivingtransmit collison detected) idl t24 t25 t26 t27 t28 tx_en LU6612 data sheet fastcat single-fet for 10base-t/100base-tx july 2000 32 lucent technologies inc. timing characteristics (preliminary) (continued) table 32. 100 mbits/s mii transmit timing 5-3745(f).er1 figure 15. 100 mbits/s mii transmit timing name parameter min max unit t40 rising edge of tx_clk following tx_en assertion to crs assertion 40 ns t41 rising edge of tx_clk following tx_en assertion to tx/ty 60 ns t42 rising edge of tx_clk following tx_en deassertion to crs deassertion 40 ns tx_clk tx_en txd[3:0] crs tx/ty t40 t41 t42 1st bit of j 1st bit of t lucent technologies inc. 33 data sheet LU6612 july 2000 fa st cat single-fet for 10base-t/100base-tx timing characteristics (preliminary) (continued) table 33. 100 mbits/s mii receive timing 5-3747(f).er1 figure 16. 100 mbits/s mii receive timing name parameter min max unit t43 rx/ry 1st bit of j receive activity to crs asserted 170 ns t44 rx/ry receive activity to receive data valid 210 ns t45 rx/ry receive activity cease (1st bit of t) to crs deasserted 210 ns t46 rx/ry receive activity cease (1st bit of t) to receive data not valid 210 ns rx/ry t43 t45 t46 crs rx_clk rx_dv rx_er rxd[3:0] t44 1st bit of j 1st bit of t LU6612 data sheet fastcat single-fet for 10base-t/100base-tx july 2000 34 lucent technologies inc. outline diagram 64-pin tqfp dimensions are in millimeters. 5-3080r5 detail a 0.50 typ 1.60 max seating plane 0.08 detail b 0.05/0.15 1.40 0.05 10.00 0.20 12.00 0.20 1 64 49 16 17 32 48 33 10.00 0.20 12.00 0.20 pin #1 identifier zone detail b 0.19/0.27 0.08 m 0.106/0.200 detail a 0.45/0.75 gage plane seating plane 1.00 ref 0.25 lucent technologies inc. 35 data sheet LU6612 july 2000 fa st cat single-fet for 10base-t/100base-tx technical document types the following descriptions pertain to the types of individual product data sheets. data sheets provide a definition of the particular integrated circuit device by detailing its full electrical and physical specifications. they are intended to be the basic source of information for designers of new systems and to provide data for users requiring information on equipment troubleshooting, training, incoming inspection, equipment test- ing, and system design modification. a data sheet is classified according to the following criteria: advance data sheet: an advance data sheet presents the devices proposed design architecture. it lists target specifications but may not have complete parameter values and is subject to change. preliminary data sheet: preliminary data sheets describe the characteristics of initial prototypes. data sheet: when a data sheet has the specifications of a product in full production and has complete parameter values, it is considered final and is classified as a data sheet. lucent technologies inc. reserves the right to make changes to the product(s) or information contained herein without notice. n o liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. fastcat is a trademark of lucent technologies inc. copyright ? 2000 lucent technologies inc. all rights reserved july 2000 ds00-355lan (replaces ds99-105lan) for additional information, contact your microelectronics group account manager or the following: internet: http://www.lucent.com/micro e-mail: docmaster@micro.lucent.com n. america: microelectronics group, lucent technologies inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18109-3286 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia pacific: microelectronics group, lucent technologies singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singap ore 118256 tel. (65) 778 8833 , fax (65) 777 7495 china: microelectronics group, lucent technologies (china) co., ltd., a-f2, 23/f, zao fong universe building, 1800 zhong shan xi road, shanghai 200233 p. r. china tel. (86) 21 6440 0468 , ext. 325 , fax (86) 21 6440 0652 japan: microelectronics group, lucent technologies japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 europe: data requests: microelectronics group dataline: tel. (44) 1189 324 299 , fax (44) 1189 328 148 technical inquiries: germany: (49) 89 95086 0 (munich), united kingdom: (44) 1344 865 900 (ascot), france: (33) 1 40 83 68 00 (paris), sweden: (46) 8 600 7070 (stockholm), finland: (358) 9 4354 2800 (helsinki), italy: (39) 02 6608131 (milan), spain: (34) 1 807 1441 (madrid) LU6612 data sheet fastcat single-fet for 10base-t/100base-tx july 2000 ordering information device code comcode package temperature LU6612-t64-db 108160680 64-pin tqfp 0 c to 70 c |
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