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high-speed precision difet ? operational amplifier applications precision instrumentation optoelectronics sonar, ultrasound professional audio equipment medical equipment data conversion cascode ?n (2) +in (3) +v s (7) output (6) ? s (4) (1) (5) difet burr-brown corp. features wide bandwidth: 6.5mhz high slew rate: 35v/ s low offset: 250 v max low bias current: 1pa max fast settling time: 1 s to 0.01% unity-gain stable description the opa602 is a precision, wide bandwidth fet operational amplifier. monolithic difet (dielectrically isolated fet) con- struction provides an unusual combination of high-speed and accuracy. its wide-bandwidth design minimizes dynamic errors. high slew rate and fast settling time allow accurate signal process- ing in pulse and data conversion applications. wide band- width and low distortion minimize ac errors. all specifications are rated with a 1k ? resistor in parallel with 500pf load. the opa602 is unity-gain stable and easily drives capacitive loads up to 1500pf. laser-trimmed input circuitry provides offset voltage and drift performance normally associated with precision bipolar op amps. difet construction achieves extremely low input bias currents (1pa max) without compromising input voltage noise. the opa602 s unique input cascode circuitry maintains low input bias current and precise input characteristics over its full input common-mode voltage range. opa602 sbos155a august 1987 revised october 2002 www.ti.com production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. copyright ? 1987, texas instruments incorporated please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. o p a 6 0 2 o p a 6 0 2
opa602 2 sbos155a www.ti.com supply voltage ............................................................................... 18v dc internal power dissipation (t j +175 c) .................................... 1000mw differential input voltage .............................................................. total v s input voltage range ............................................................................ v s storage temperature range p and u packages ....................................................... 40 c to +125 c operating temperature range p and u packages ........................................................ 25 c to + 85 c lead temperature u package, so (3s) .................................................................... +260 c output short-circuit to ground (+25 c) ................................... continuous junction temperature .................................................................... +175 c note: (1) stresses above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum conditions for extended periods may affect device reliability. electrostatic discharge sensitivity this integrated circuit can be damaged by esd. texas instru- ments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degrada- tion to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. offset specified voltage max package temperature package ordering transport product ( v) at 25 c package-lead designator (1) range marking number media, quantity opa602ap 2000 dip-8 p 25 c to +85 c 602ap 602ap tubes, 50 opa602bp 1000 """ 602bp 602bp tubes, 50 opa602au 3000 so-8 d 25 c to +85 c 602au 602au tubes, 100 note: (1) for the most current specifications and package information, refer to our web site at www.ti.com. package/ordering information absolute maximum ratings (1) pin configurations top view dip, so 8 7 5 6 +v s output offset trim nc dip-8 1 2 4 3 in +in v s offset trim 1 2 3 4 8 7 6 5 nc +v s output offset trim offset trim in +in v s so-8 nc = no connection
opa602 3 sbos155a www.ti.com electrical characteristics at v s = 15v dc and t a = +25 c, unless otherwise noted. ? same specifications as opa602bp. note: (1) opa602ap, au ensured by design with a 99% confidence level. opa602bp opa602ap, au parameter conditions min typ max min typ max units input noise voltage: f o = 10hz 23 ? nv/ hz f o = 100hz 19 ? nv/ hz f o = 1khz 13 ? nv/ hz f o = 10khz 12 ? nv/ hz f b = 10hz to 10khz 1.4 ? vrms f b = 0.1hz to 10hz 0.95 ? vp-p current: f b = 0.1hz to 10hz 12 ? fap-p f o = 0.1hz to 20khz 0.6 ? fa/ hz offset voltage input offset voltage: p package 0.5 1 1 2 mv u package 13 mv over specified temperature p, u packages 0.75 1.5 1.5 mv average drift (1) t a = t min to t max 3 5 ? 15 v/ c supply rejection v s = 12v to 18v 80 100 70 ? db bias current input bias current v cm = 0v dc 1 2 2 10 pa over specified temperature 20 200 20 500 pa offset current input offset current v cm = 0v dc 0.5 2 1 10 pa over specified temperature 20 200 20 500 pa input impedance differential 10 13 || 1 ? ? || pf common-mode 10 14 || 3 ? ? || pf input voltage range common-mode input range 10.2 +13, 11 ?? v common-mode rejection v in = 10v dc 88 100 75 ? db open-loop gain, dc open-loop voltage gain r l 1k ? 88 100 75 ? db frequency response gain bandwidth gain = 100 4 6.5 3.5 ? mhz full-power response 20vp-p, r l = 1k ? 570 ? khz slew rate v o = 10v, r l = 1k ? 24 35 20 ? v/ s settling time: 0.1% gain = 1, r l = 1k ? 0.6 ? s 0.01% c l = 500pf, 10v step 1.0 s rated output voltage output r l = 1k ? 11.5 +12.9, 11 ? v 13.8 current output v o = 10v dc 15 20 ?? ma output resistance 1mhz, open loop 80 ? ? load capacitance stability gain = +1 1500 ? pf short-circuit current 30 50 25 ? ma power supply rated voltage 15 ? v dc voltage range, derated performance 5 18 ?? v dc current, quiescent i o = 0madc 3 4 ?? ma over specified temperature 3.5 4.5 ?? ma temperature range specification ambient temperature 25 +85 ?? c operating: p, u packages 25 +85 ?? c storage: p, u packages 40 +125 ?? c ja 200 ? c/w
opa602 4 sbos155a www.ti.com typical characteristics at t a = +25 c and v s = 15v dc , unless otherwise noted. input current noise spectral density 100 10 1 0.1 1 10 100 1k 10k 100k 1m frequency (hz) current noise (fa/ hz) input voltage noise spectral density 1k 100 10 1 1 10 100 1k 10k 100k 1m frequency (hz) voltage noise (nv/ hz) power-supply rejection and common-mode rejection vs temperature 110 75 temperature ( c) cmr and psr (db) 105 100 95 90 50 25 0 25 50 75 100 125 cmr psr e o r s total input voltage noise spectral density at 1khz vs source resistance 1k 100 10 1 100 1k 10k 100k 1m 10m 100m source resistance ( ? ) voltage noise, e o (nv/ hz) opa602 + resistor resistor noise only common-mode rejection vs input common-mode voltage 120 15 10 5 0 +5 +10 +15 common-mode rejection (db) common-mode voltage (v) 110 100 90 80 70 open-loop frequency response 140 1 frequency (hz) voltage gain (db) 10 100 1k 10k 100k 1m 10m 120 100 80 60 40 20 0 45 90 135 180 phase shift (degrees) r l = 1k ? c l = 100pf a ol
opa602 5 sbos155a www.ti.com typical characteristics (cont.) at t a = +25 c and v s = 15v dc , unless otherwise noted. gain bandwidth and slew rate vs temperature 10 75 ambient temperature ( c) gain bandwidth (mhz) slew rate (v/ s) 8 6 4 2 50 25 0 25 50 75 100 125 37 35 33 31 29 gbw slew rate gain bandwidth and slew rate vs supply voltage 8 0 supply voltage ( v cc ) gain bandwidth (mhz) slew rate (v/ s) 5 5 101520 38 32 7 6 36 34 a v = 1 gbw slew rate open-loop gain vs temperature 120 75 ambient temperature ( c) voltage gain (db) 110 100 90 80 50 25 0 25 50 75 100 125 maximum output voltage swing vs frequency 30 10k 100k 1m 10m frequency (hz) output voltage (vp-p) 20 10 0 r l = 1k ? s) 10 0 10 012345 small-signal transient response output voltage (mv) time ( s) 150 100 50 0 50 100 150 025
opa602 6 sbos155a www.ti.com typical characteristics (cont.) at t a = +25 c and v s = 15v dc , unless otherwise noted. settling time vs closed-loop gain 5 4 3 2 1 0 1 10 100 1k closed-loop gain (v/v) settling time ( s) 0.1% r l = 1k ? c l = 100pf 0.01% supply current vs temperature 3.5 3.25 3.0 2.75 2.5 75 ambient temperature ( c) supply current (ma) 50 25 0 25 50 75 100 125 open-loop gain vs supply voltage 104 0 supply voltage ( v cc ) voltage gain 92 5 101520 100 96 total harmonic distortion vs frequency 1 0.1 0.01 0.001 0.1 frequency (hz) thd + noise (%rms) 1 10 100 1k 10k 100k a v = +101v/v a v = +1v/v 6.5vrms 1k ? 402 ? 40.2k ? a v = +101v/v bias and offset current vs temperature 10na bias current (pa) 50 ambient temperature ( c) 10na offset current (pa) 25 0 25 50 75 100 125 1na 100 10 1 0.1 1na 100 10 1 0.1 bias and offset current vs input common mode voltage 10 1 0.1 0.01 bias current (pa) 15 common-mode voltage (v) 10 1 0.1 0.01 offset current (pa) 10 50 51015 bias current offset current
opa602 7 sbos155a www.ti.com typical characteristics (cont.) at t a = +25 c and v s = 15v dc , unless otherwise noted. power-supply rejection vs frequency 140 1 frequency (hz) power-supply rejection (db) 10 100 1k 10k 100k 1m 10m 120 100 80 60 40 20 0 + common-mode rejection vs frequency 140 1 frequency (hz) common-mode rejection (db) 10 100 1k 10k 100k 1m 10m 120 100 80 60 40 20 0 applications information unity-gain stability with good phase margin and excellent output drive characteristics bring freedom from the subtle problems associated with other high-speed amplifiers. how- ever, as with any high-speed, wide bandwidth circuitry, care- ful circuit layout will ensure best performance. make short, direct interconnections and avoid stray wiring capacitance especially at the inverting input pin. power supplies should be bypassed with good high-frequency capacitors positioned close to the op amp pins. in most cases 0.1 f ceramic capacitors are adequate. applications with heavier loads and fast transient waveforms may benefit from use of additional 1.0 f tantalum bypass capacitors. input bias current guarding leakage currents across printed circuit boards can easily exceed the input bias current of the opa602. a circuit board guard pattern, as shown in figure 1, is an effective solution to difficult leakage problems. this guard pattern must be repeated on all layers of a multilayer board. by surrounding critical high impedance input circuitry with a low impedance circuit connection at the same potential, leakage currents will flow harmlessly to the low-impedance node. input bias current may also be degraded by improper han- dling or cleaning. contamination from handling parts and circuit boards may be cleaned with appropriate solvents and deionized water. each rinsing operation should be followed by a 30-minute bake at +85 c. board layout for input guarding: guard top and bottom of board. alternate use teflon standoff for sensitive input pins. teflon e.i. du pont de nemours & co. figure 1. connection of input guard. 2 3 in noninverting 6 out 2 3 in inverting 6 out 2 3 in buffer 6 out opa602 opa602 opa602
opa602 8 sbos155a www.ti.com vv bb b b vv v vv out ref ref out ref =? + + + + ? ? ? ? ? ? ? + ?? 12 3 12 2 4 8 4096 10 10 0 4095 4096 l where: b n = 1 if the b n digital input is high. b n = 0 if the b n digital input is low. application circuits figure 2. offset voltage trim. figure 3. voltage output digital-to-analog converter. 3 6 2 opa602 5 1 4 7 +v s v s (1) 10mv typical trim range 2 opa602 v out 4 5 6 7 8 9 10 11 12 13 14 15 dac7541a 16 17 v reference +15v out 2 r f out 1 c 1 15pf 3 v cc b 1 b 12 msb 1 18 single-point ground 100k ? figure 4. settling time and slew rate test circuit. output +15v 2k ? 47pf 2k ? 15v opa602 high-quality pulse generator pulse in 5v 2k ? 1 f tantalum 1 f tantalum + + 2k ? 51 ? c l 500pf 1 f + + + 1 f 1 f 1 f (2) hp 5082-2835 +15v 1/2 2n5564 1/2 2n5564 15v + 510 ? 510 ? 50 ? error out 0.5mv (0.01%) note: (1) 10k ? to 1m ? trim potentiometer (100k ? recommended).
opa602 9 sbos155a www.ti.com package drawings p (r-pdip-t8) plastic dual-in-line 8 4 0.015 (0,38) gage plane 0.325 (8,26) 0.300 (7,62) 0.010 (0,25) nom max 0.430 (10,92) 4040082/d 05/98 0.200 (5,08) max 0.125 (3,18) min 5 0.355 (9,02) 0.020 (0,51) min 0.070 (1,78) max 0.240 (6,10) 0.260 (6,60) 0.400 (10,60) 1 0.015 (0,38) 0.021 (0,53) seating plane m 0.010 (0,25) 0.100 (2,54) notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. falls within jedec ms-001
opa602 10 sbos155a www.ti.com package drawings (cont) d (r-pdso-g**) plastic small-outline package 8 pins shown 8 0.197 (5,00) a max a min (4,80) 0.189 0.337 (8,55) (8,75) 0.344 14 0.386 (9,80) (10,00) 0.394 16 dim pins ** 4040047/e 09/01 0.069 (1,75) max seating plane 0.004 (0,10) 0.010 (0,25) 0.010 (0,25) 0.016 (0,40) 0.044 (1,12) 0.244 (6,20) 0.228 (5,80) 0.020 (0,51) 0.014 (0,35) 1 4 8 5 0.150 (3,81) 0.157 (4,00) 0.008 (0,20) nom 0 C 8 gage plane a 0.004 (0,10) 0.010 (0,25) 0.050 (1,27) notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). d. falls within jedec ms-012
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third?party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2002, texas instruments incorporated

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