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february 2002 1 ? 2002 actel corporation v3.0 proasic ? 500k family features and benefits high capacity 100,000 to 475,000 system gates 14k to 63k bits of two-port sram 106 to 440 user i/os performance 33 mhz pci 32-bit pci internal system performance up to 250 mhz external system performance up to 100 mhz low power low impedance flash switches segmented hierarchical routing structure small, efficient logic cells high performance routing hierarchy ultra fast local network efficient long line network high speed very long line network high performance global network nonvolatile and reprogrammable flash technology live at power up no configuration device required retains programmed design during power-down/ power-up cycles i/o mixed 2.5v/3.3v support with individually-selectable voltage and slew rate 3.3v, pci compliance (pci revision 2.2) secure programming the industry ? s most effective security key prevents read back of programming bit stream standard fpga and asic design flow flexibility with choice of industry-standard front-end tools efficient design through front-end timing and gate optimization isp support in-system programming (isp) with silicon sculptor and flash pro srams and fifos up to 150 mhz synchronous and asynchronous operation netlist generator ensures optimal usage of embedded memory blocks boundary scan test ieee std. 1149.1 (jtag) compliant proasic product profile device a500k050 a500k130 a500k180 a500k270 maximum system gates 100,000 290,000 370,000 475,000 typical gates 43,000 105,000 150,000 215,000 maximum flip-flops 5,376 12,800 18,432 26,880 embedded ram bits 14k 45k 54k 63k embedded ram blocks (256 x 9) 6202428 logic tiles 5,376 12,800 18,432 26,880 global routing resources 4444 maximum user i/os 204 306 362 440 jtag ye s ye s ye s ye s pci ye s ye s ye s ye s package (by pin count) pqfp pbga fbga 208 272 144 208 272, 456 144, 256 208 456 256 208 456 256, 676
proasic ? 500k family 2v3.0 general description the proasic 500k family ? s nonvolatile flash technology combines the advantages of asics with the benefits of programmable devices. proasic 500k devices shorten time-to-production by enabling designers to create high-density systems using existing asic or fpga design flows and tools. asic migration is not necessary for any volume because the family offers cost effective reprogrammable solutions, ideal for applications in the networking, telecom, computer, and consumer markets. the proasic 500k family consists of four devices ranging from 100k to 475k system gates and with up to 63k bits of embedded two-port memory. these memory blocks include hardwired fifo circuitry as well as circuits to generate or check parity. this minimizes external logic gate count and complexity while maximizing flexibility and utility. process technology the proasic 500k family achieves its nonvolatile and reprogrammability through an advanced 0.25 , four-level metal lvcmos process enhanced with flash technology. the use of standard cmos design techniques to implement logic and control functions results in highly predictable performance and gate array compatibility. ordering information a500k130 pq part number package type bg = plastic ball grid array pq = plastic quad flat pack fg = fine ball grid array 208 package lead count application (ambient temperature range) blank = commercial (0 to +70? c) i = industrial (-40 to +85? c) pp = pre-production es = engineering silicon (room temperature only) 100,000 equivalent system gates a500k050 = a500k180 a500k270 370,000 equivalent system gates 475,000 equivalent system gates a500k130 290,000 equivalent system gates = = =
v3.0 3 proasic ? 500k family product plan plastic device resources application ci a500k050 device 144-pin fine ball grid array (fbga) ?? 208-pin plastic quad flat pack (pqfp) ?? 272-pin plastic ball grid array (pbga) ?? a500k130 device 144-pin fine ball grid array (fbga) ?? 208-pin plastic quad flat pack (pqfp) ?? 272-pin plastic ball grid array (pbga) ?? 256-pin plastic ball grid array (pbga) ?? 456-pin plastic ball grid array (pbga) ?? a500k180 device 208-pin plastic quad flat pack (pqfp) ?? 256-pin plastic ball grid array (pbga) ?? 456-pin plastic ball grid array (pbga) ?? a500k270 device 208-pin plastic quad flat pack (pqfp) ?? 256-pin plastic ball grid array (pbga) ?? 456-pin plastic ball grid array (pbga) ?? 676-pin fine ball grid array (fbga) ?? contact your actel sales representative for package availability. applications: c = commercial availability: ? = available ? contact your actel sale?s representative for the latest i = industrial availability information. user i/os device pqfp 208-pin pbga 272-pin pbga 456-pin fbga 144-pin fbga 256-pin fbga 676-pin a500k050 164 204 ? 106 ? ? a500k130 164 204 306 106 192 ? a500k180 164 ? 362 ? 192 ? a500k270 164 ? 362 ? 192 440 package definitions pqfp = plastic quad flat pack, pbga = plastic ball grid array, fbga = fine ball grid array
proasic ? 500k family 4v3.0 proasic 500k architecture the proasic 500k family ? s proprietary architecture provides granularity comparable to gate arrays. unlike sram-based fpgas that utilize look-up tables or architectural mapping during design, proasic device designs are directly synthesized to gates. that streamlines the design flow, increases design productivity, and eliminates dependencies on vendor-specific design tools. the proasic 500k device core consists of a sea-of-tiles ? ( figure 1 ), each of which can be configured as a 3-input logic function (e.g., nand gate, d-flip-flop, etc.) by programming the appropriate flash switch interconnections (see figure 2 on page 5 and figure 3 on page 5 ). gates and larger functions are connected with four levels of routing hierarchy. flash memory bits are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. flash switches are programmed to connect signal lines to the appropriate logic cell inputs and outputs. dedicated high-performance lines are connected as needed for fast, low-skew global signal distribution throughout the core. maximum core utilization is possible for virtually any design. the proasic 500k devices also contain embedded two-port sram blocks with built-in fifo/ram control logic. programming options include synchronous or asynchronous operation, two-port ram configurations, user defined depth and width, and parity generation or checking. table 3 on page 12 lists the 24 basic memory configurations. flash switch in the proasic flash switch, two transistors share the floating gate which stores the programming information. one is the flash transistor which stores programming information and in which erasing is performed. the second transistor connects/separates routing elements or configuration signal lines ( figure 2 on page 5 ). logic tile the logic tile cell, figure 3 on page 5 , has three inputs (any or all of which can be inverted) and one output (which can connect to both ultra fast local and efficient long line routing resources). any three-input one-output logic function, except a three input xor, can be configured as one tile. two multiplexers with feedback paths through the nand gates allow the tile to be configured as a latch with clear or set, or as a flip-flop with clear or set. thus, the tiles can flexibly map logic and sequential gates of a design. figure 1 ? the proasic device architecture 256x9 two-port sram or fifo block logic tile
v3.0 5 proasic ? 500k family routing resources the routing structure of the proasic 500k devices is designed to provide high performance through a flexible four-level hierarchy of routing resources: ultra fast local resources, efficient long line resources, high speed very long line resources, and high performance global networks. the ultra fast local resources are dedicated lines that allow the output of each tile to connect directly to every input of the eight surrounding tiles ( figure 4 on page 6 ). the efficient long line resources provide routing for longer distances and higher fanout connections. these resources vary in length (spanning 1, 2, or 4 tiles), run both vertically and horizontally, and cover the entire proasic device ( figure 5 on page 6 ). each tile can drive signals onto the efficient long line resources, while the resources can also access every input of any tile. the routing software automatically inserts active buffers to limit loading effects due to distance and fanout. the high speed very long line resources, spanning across the entire device with minimal delay, are used to route very long or very high fanout nets. these resources run vertically and horizontally, providing multiple access to each group of tiles throughout the device ( figure 6 on page 7 ). the high performance global networks ? clock trees are low skew, high fanout nets that are accessible from four dedicated pins or from internal logic ( figure 7 on page 8 ). these nets are typically used to distribute clocks, resets, and other high fanout nets requiring a minimum skew. the global networks are implemented as clock trees, and signals can be introduced at any junction. these can be employed hierarchically, with signals accessing every input on all tiles. clock resources proasic ? s high-drive routing structure provides four global networks, each accessible from either a dedicated global pad or a logic tile. global lines provide optimized worst-case clock skew of 0.3ns. figure 2 flash switch figure 3 core logic tile sel 1 sel 2 switch in switch out word floating gate local routing in 1 in 2 (clk) in 3 (reset) efficient long line routing
proasic ? 500k family 6v3.0 figure 4 ultra fast local resources figure 5 efficient long line resources l l l l l l inputs output ultra fast local lines (connect a tile to the adjacent tile, i/o buffer, or memory block) l l l l lllll l lllll l l llll l l llll l lllll logic cell 1 tile long 2 tiles long 4 tiles long 1 tile long 2 tiles long 4 tiles long logic tile
v3.0 7 proasic ? 500k family figure 6 high speed very long line resources pad ring pad ring pad ring i/o ring i/o ring high speed very long line resouces
proasic ? 500k family 8v3.0 clock trees one of the main architectural benefits of proasic is the set of power and delay friendly global networks. the proasic family offers 4 global trees. each of these trees is based on a network of spines and ribs that reach all the tiles in their regions ( figure 7 ). this flexible clock tree architecture allows users to map up to 56 different internal/external clocks in an a500k270 device ( table 1 ). the flexible use of the proasic clock spine allows the designer to cope with several design requirements. users implementing clock resource intensive applications can easily route external or gated internal clocks using global routing spines. users can also drastically reduce delay penalties and save buffering resources by mapping critical high fanout nets to spines. for design hints on using these features, refer to the efficient use of proasic clock trees application note. figure 7 a500k130 global routing resources table 1 number of clock spines a500k050 a500k130 a500k180 a500k270 top spine height 24 32 40 56 tiles in each top spine 768 1,024 1,280 1,792 bottom spine height 32 40 56 64 tiles in each bottom spine 1,024 1,280 1,792 2,048 global clock networks (trees) 4 4 4 4 clock spines/tree 6 10 12 14 total spines 24 40 48 56 total tiles 5,376 12,800 18,432 26,880 pad ring pad ring pad ring i/o ring i/o ring global pads global pads high performace global network low skew global networks global spine global ribs scope of spine
v3.0 9 proasic ? 500k family input/output blocks to meet complex system design needs, the proasic 500k family offers devices with a large number of i/o pins, up to 440 user i/o pins on the a500k270. if the i/o pad is powered at 3.3v, each i/o can be selectively configured at 2.5v and 3.3v threshold levels. table 2 shows the available supply voltage configurations. figure 8 illustrates i/o interfaces with other devices. the i/o pads are fully configurable to provide the maximum flexibility and speed. each pad can be configured as an input, an output, a three-state driver, or a bidirectional buffer ( figure 9 ). i/o pads configured as inputs have the following features: individually selectable 2.5v or 3.3v threshold levels 1 optional pull-up resistor i/o pads configured as outputs have the following features: individually selectable 2.5v or 3.3v compliant output signals 1 3.3v pci compliant ability to drive lvttl and lvcmos levels selectable drive strengths selectable slew rates tristate i/o pads configured as bidirectional buffers have the following features: individually selectable 2.5v or 3.3v compliant output signals and threshold levels 1 3.3v pci compliant optional pull-up resistor selectable drive strengths selectable slew rates tristate all i/os also include an esd protection circuit. each i/o is tested according to the following model: boundary scan proasic devices are compatible with ieee standard 1149.1, which defines a set of hardware architecture and mechanisms for cost-effective board-level testing. the basic proasic boundary-scan logic circuit is composed of the tap (test access port), tap controller, test data registers, and instruction register ( figure 10 on page 10 ). this circuit supports all mandatory ieee 1149.1 instructions (extest, sample/preload and bypass), the optional idcode instructions and private instructions used for device programming and factory testing. each test section is accessed through the tap, which has five associated pins: tck (test clock input), tdi and tdo (test data input and output), tms (test mode selector) and trst (test reset input). tms, tdi, and trst are equipped table 2 proasic power supply voltages v ddp 2.5v 3.3v input tolerance 2.5v 3.3v, 2.5v output drive 2.5v 3.3v, 2.5v note: v ddl is always 2.5v. 1. if pads are configured for 2.5v operation, they are compliant with 2.5v level signals as defined by jedec jesd 8-5. if pads are configured for 3.3v operation, they are compliant to the standard as defined by jedec jesd 8-a (lvttl and lvcmos). human body model (hbm) (per mil std 883 method 3015) 2000v figure 8 i/o interfaces figure 9 i/o block schematic representation proasic v ddl = 2.5v v ddp = 2.5v proasic v ddl = 2.5v v ddp = 3.3v 2.5v device 2.5v device 2.5v device 3.3v device 2.5v device 3.3v device 3.3v/2.5v signal control pull-up control 3.3v/2.5v signal control drive strength and slew rate control pad y en a
proasic ? 500k family 10 v3.0 with pull-up resistors to ensure proper operation when no input data is supplied to them. these pins are dedicated for boundary-scan test usage. the tap controller is a four-bit state machine (16 states) that operates as shown in figure 11 on page 11 . the ? 1 ? s and ? 0 ? s represent the values that must be present at tms at a rising edge of tck for the given state transition to occur. ir and dr indicate that the instruction register or the data register is operating in that state. the tap controller receives two control inputs (tms and tck) and generates control and clock signals for the rest of the test logic architecture. on power up, the tap controller enters the test-logic-reset state. to guarantee a reset of the controller from any of the possible states, tms must remain high for five tck cycles. the trst pin may also be used to asynchronously place the tap controller in the test-logic-reset state. proasic devices support three types of test data registers: bypass, device identification, and boundary scan. the bypass register is selected when no other register needs to be accessed in a device; this speeds up test data transfer to other devices in a test data path. the 32-bit device identification register is a shift register with four fields (lsb, id number, part number and version). the boundary-scan register observes and controls the state of each i/o pin. each i/o cell has three boundary-scan register cells, each with a serial-in, serial-out, parallel-in, and parallel-out pin. the serial pins are used to serially connect all the boundary-scan register cells in a device into a boundary scan register chain which starts at the tdi pin and ends at the tdo pin. the parallel ports are connected to the internal core logic tile and the input, output, and control ports of an i/o buffer to capture and load data into the register to control or observe the logic state of each i/o. details on the implementation of boundary-scan testing on proasic devices can be found in the actel application note, using jtag boundary-scan with proasic devices . figure 10 proasic jtag boundary scan test logic circuit device logic tdi tck tms trst tdo i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o bypass register instruction register tap controller test data registers
v3.0 11 proasic ? 500k family user security the proasic 500k devices have read-protect bits that, once programmed, lock the entire programmed contents from being read externally. the user can only reprogram the device using the security key. this protects it from being read back and duplicated. since programmed data is stored in nonvolatile flash cells (which act like very small capacitors), rather than in the wiring, physical deconstruction cannot be used to compromise data. that approach would be further hampered by the placement of the flash cells, beneath the four metal layers (whose removal could not be accomplished without disturbing the charge on the floating gate). this is the highest security provided in the industry. for more information, refer to the design security for nonvolatile flash and antifuse fpgas white paper for more information. embedded memory floorplan the embedded memory is located across the top of the device (see figure 1 on page 4 ) in 256x9 blocks. depending upon the device, 6 to 28 blocks are available to support a variety of memory configurations. each block can be programmed as an independent memory or combined (using dedicated memory routing resources) to form larger, more complex memories. embedded memory configurations the embedded memory in the proasic 500k family provides great configuration flexibility. while other programmable vendors typically use single port memories that can only be transformed into two-port memories by sacrificing half the memory, each proasic block is designed and optimized as a two-port memory (1 read, 1 write). this provides 63k bits of total memory for two-port and single port usage in the a500k270 device. each memory can be configured as fifo or sram, with independent selection of synchronous or asynchronous read and write ports ( table 3 on page 12 ). multiple write ports are not supported. additional characteristics include programmable flags as well as parity check and generation. figure 12 and figure 13 on page 13 show the block diagrams of the basic sram and fifo blocks. these memories are designed to operate up to 133 mhz when operated individually. each block contains a 256 word deep by 9-bit wide (1 read, 1 write) memory. the memory blocks may be combined in parallel to form wider memories or stacked to form deeper memories ( figure 14 on page 14 ). this provides optimal bit widths of 9 (1 block), 18, 36, and 72, and optimal depths of 256, 512, 768, and 1024. refer to the macro library guide for more information. figure 11 tap controller state diagram test-logic reset run-test/ idle select-dr- scan capture-dr shift-dr exit-dr pause-dr exit2-dr update-dr select-ir- scan capture-ir shift-ir exit-ir pause-ir exit2-ir update-ir 1 1 1 0 1 0 00 1 1 00 00 1 1 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0
proasic ? 500k family 12 v3.0 figure 15 on page 14 gives an example of optimal memory usage. ten blocks with 23,040 bits have been used to generate three memories of various widths and depths. figure 16 on page 14 shows how memory can be doubled up to create extra read ports. in this example, 10 out of 28 blocks of the a500k270 yield an effective 6,912 bits of multiple port memories. the actgen ? software facilitates building wider and deeper memories for optimal memory usage. table 3 basic memory configurations type write access read access parity library cell name ram asynchronous asynchronous checked ram256x9aa ram asynchronous asynchronous generated ram256x9aap ram asynchronous synchronous transparent checked ram256xast ram asynchronous synchronous transparent generated ram256xastp ram asynchronous synchronous pipelined checked ram256x9asr ram asynchronous synchronous pipelined generated ram256x9asrp ram synchronous asynchronous checked ram256x9sa ram synchronous asynchronous generated ram256xsap ram synchronous synchronous transparent checked ram256x9sst ram synchronous synchronous transparent generated ram256x9sstp ram synchronous synchronous pipelined checked ram256x9ssr ram synchronous synchronous pipelined generated ram256x9ssrp fifo asynchronous asynchronous checked fifo256xaa fifo asynchronous asynchronous generated fifo256x9aap fifo asynchronous synchronous transparent checked fifo256xast fifo asynchronous synchronous transparent generated fifo256x9astp fifo asynchronous synchronous pipelined checked fifo256x9asr fifo asynchronous synchronous pipelined generated fifo256x9asrp fifo synchronous asynchronous checked fifo256x9sa fifo synchronous asynchronous generated fifo256xsap fifo synchronous synchronous transparent checked fifo256x9sst fifo synchronous synchronous transparent generated fifo256x9sstp fifo synchronous synchronous pipelined checked fifo256x9ssr fifo synchronous synchronous pipelined generated fifo256x9ssrp
v3.0 13 proasic ? 500k family note: for memory block interface signal definitions, see table 4 on page 28 . figure 12 example sram block diagrams note: for memory block fifo signal definitions, see table 5 on page 34 . figure 13 basic fifo block diagrams sram (256 x 9) sync write & sync read ports di <0:8> do <0:8> raddr <0:7> waddr <0:7> wrb rdb wblkb rblkb wclks rclks rpe parodd sram (256 x 9) async write & async read ports di <0:8> do <0:8> raddr <0:7> waddr <0:7> wrb wblkb rdb rblkb parodd wpe rpe wpe sram (256 x 9) sync write & async read ports di <0:8> do <0:8> waddr <0:7> wrb rdb wblkb rblkb wclks rpe parodd wpe raddr <0:7> parodd sram (256 x 9) async write & sync read ports di <0:8> do <0:8> raddr <0:7> waddr <0:7> wrb rdb wblkb rblkb rclks rpe wpe fifo (256 x 9) sync write & sync read ports level<0:7> d0 <0:8> d1<0:8> wrb rdb wblkb rblkb rpe parodd wpe lgdep<0:2> full empty eqth geqth wclks rclks reset fifo (256 x 9) sync write & async read ports d1 <0:8> d0 <0:8> level <0:7> wrb rdb wblkb rblkb rpe parodd wpe lgdep<0:2> full empty eqth geqth wclks fifo (256 x 9) async write & async.read ports d1 <0:8> d0 <0:8> level <0:7> wrb rdb wblkb rblkb rpe parodd wpe lgdep<0:2> full empty eqth geqth fifo (256 x 9) async write & sync read ports d1 <0:8> d0 <0:8> level <0:7> wrb rdb wblkb rblkb rpe parodd wpe lgdep<0:2> full empty eqth geqth rclks
proasic ? 500k family 14 v3.0 figure 14 a500k270 memory block architecture figure 15 example showing memories with different width and depth figure 16 multiport memory usage word depth word width 88 blocks 256 9 256 9 256 9 256 9 256 9 256 9 256 9 256 9 256 9 word depth word width 1,024 words x 9bits, 1 read, 1 write 512 words x 18bits, 1 read, 1 write 256 words x 18bits, 1 read, 1 write total memory blocks used = 10 total memory bits = 23,040 256 256 256 256 9 256 256 9 9 256 99 256 9 256 9 total memory blocks used = 10 total memory bits = 6,912 word depth word width write port write port read ports 9 9 read ports 512 words x 9bits, 4 read, 1 write 256 words x 9bits, 2 read, 1 write
v3.0 15 proasic ? 500k family design environment proasic devices are supported by actel ? s designer series software, as well as all of the industry standard third party cae tools. unlike other fpga vendors, no special hdl instantiation or device related attributes are needed when using the standard vhdl or verilog hdl design flow with proasic. as a result, designers can utilize the technology independent of hdl code for proasic devices. this feature and the asic-like design flow ensure a seamless transition to an asic implementation, if production volumes warrant a migration to a gate array or a standard cell product ( figure 17 ). actgen automatically generates memories and fifos with all the various options (width, depth, access mode, parity checking or generation, flags, etc.). for a synchronous read port, the user can choose whether the output is pipelined or transparent. actgen allows any bit width up to 252 (for the a500k270 device). actgen also enables optimal memory stacking in 256-word increments. however, any word depth may be combined for up to 7,168 words. actgen allows the user to generate distributed memory. place and route is performed by actel ? s designer software. available for unix workstations and pc platforms, designer software accepts standard netlists in verilog, vhdl, and in edif format, performs timing driven place and route of the design into the selected device/package, and provides postlayout timing information for backannotated simulation or static timing analysis. the designer software also contains very powerful layout capabilities for the experienced user. a very comprehensive set of floor planning, timing, and routing constraints gives users optimal control over the tools ? capabilities, enabling them to meet their tight design requirements. users have access to constraints that allow them full control of the resources management. see the designer user ? s guide for various constraints and their uses. the proasic devices are also fully supported by actel ? s libero design tool suite. libero is a design management environment that integrates the needed design tools, streamlines the design flow, manages all design and log files, and passes the necessary design data between tools. libero includes synplify, viewdraw, actel ? s designer series, modelsim hdl simulator, and waveformer lite. once the design is finalized, the programming bitstream is downloaded into the device programmer for proasic part programming. proasic 500k devices can be programmed with the silicon sculptor ii and flash pro programmers. on-board programming is also available. refer to the in-system programming proasic 500k with silicon sculptor application note for more information. figure 17 proasic design flow design creation/verification design implementation synthesis tool high-level design (verilog or vhdl) designer (p&r tool) p&r user constraints synthesis library programming silicon sculptor ii flash pro timing libraries simulation library sdf timing file forward constraints programming data timing analyzer timing and simulation backannotation simulation library structural netlist actgen verilog or vhdl simulator verilog or vhdl simulator
proasic ? 500k family 16 v3.0 package thermal characteristics the proasic 500k family is available in a number of package types. actel has selected packages based on high pin count, reliability factors, and superior thermal characteristics. thermal resistance indicates the ability of a package to conduct heat away from the silicon, through the package, to the surrounding air. junction-to-ambient thermal resistance is measured in degrees celsius/watt and is represented as theta ja ( ja ). the lower the thermal resistance, the more efficiently a package will dissipate heat. a package ? s maximum allowed power (p) is a function of maximum junction temperature (t j ), maximum ambient operating temperature (t a ), and junction-to-ambient thermal resistance ja . maximum junction temperature is the maximum allowable temperature on the active surface of the ic and is 110 c. p is defined as : ja is a function of the rate (in linear feet per minute ? lfpm) of airflow in contact with the package. when the estimated power consumption exceeds the maximum allowed power, other means of cooling, such as increasing the airflow rate, must be used. p t j t a ? ja ----------------- = package type pin count jc ja still air ja 300 ft/min units plastic quad flat pack (pqfp) 208 8 30 23 c/w pqfp with heatspreader 208 3.8 20 17 c/w plastic ball grid array (pbga) 272 3 20 16.5 c/w plastic ball grid array (pbga) 456 3 18 14.5 c/w fine ball grid array (fbga) 144 3.8 38.8 26.7 c/w fine ball grid array (fbga) 256 3.0 30 25 c/w
v3.0 17 proasic ? 500k family calculating power dissipation proasic device power is calculated with both a static and an active component. the active component is a function of both the number of tiles utilized and the system speed. power dissipation can be calculated using the following formula: p total = p dc + p ac where: where: p storage = p5 * ms * fs where: p logic = p3 * mc * fs where: p ios = (p4 + c load * v ddp ^2) * p * fp where: p memory = p6 * n mem * f mem where: the following is an example using a shift register design with 13,440 storage tiles and 0 logic tile. this design has one clock at 10 mhz, and 24 outputs toggling at 5 mhz for a a500k270. => pclock = (p1 + p2 * s) * fs = 159.4 mw => pstorage = p5 * ms * fs = 134.4 mw => p logic = 0 mw fp = 5 mhz => p ios = (p4 + cload * v ddp ^2) * p * fp = 54.1 mw => p memory = 0 mw p ac = p clock + p storage + p logic + p ios + p memory = 347.9 mw p dc = 10 mw p total = p dc + p ac = 357.9 mw p dc = 10 mw p ac =p clock + p storage + p logic + p ios + p memory p clock = (p1 + p2 * s) * fs p1 = 2500 uw/mhz the basic power consumption of the clock-tree normalized per mhz of the clock p2 = 1.0 uw/mhz the extra power consumption of the clock-tree per storage-tile normalized per mhz of the clock s = the number of storage tiles clocked by this clock fs = the clock frequency p5 = 1.0 uw/mhz the average power consumption of a storage-tile normalized per mhz of its output ms = the number of storage tiles switching at each fs cycle fs = the clock frequency p3 = 3.0 uw/mhz the average power consumption of a logic-tile normalized per mhz of its output mc = the number of logic tiles switching at each fs cycle fs = the clock frequency p4 = 15.0 uw/mhz the average power consumption of an output-pad normalized per mhz of its output (internal power- load is not included) c load = the output load p = the number of outputs fp = the average output frequency p6 = 100.0 uw/mhz is the average power consumption of a memory block normalized per mhz of the clock n mem = the number of ram/fifo blocks (1 block = 256 words * 9 bits) f mem = the clock frequency of the memory fs = 10 mhz s = 13,440 ms = 13,440 (in a shift register 100% of storage-tiles are toggling at each clock cycle and fs = 10 mhz mc = 0 (no logic tile in this shift-register) c load =40 pf v ddp =3.3 v and p = 24 n mem = 0 (no ram/fifo in this shift-register) power consumption of a 500k device 0 100 200 300 400 500 600 700 800 900 1000 frequency (mhz) power consumption (mw) 20 30 40 50 60 70 80 90 100 120 sram proasic 110 instances of 16-bit binary counters
proasic ? 500k family 18 v3.0 operating conditions absolute maximum ratings parameter condition minimum maximum units supply voltage core (v ddl ) ? 0.3 3.0 v supply voltage i/o ring (v ddp ) ? 0.3 4.0 v dc input voltage ? 0.3 v ddp + 0.3 v pci dc input voltage ? 0.5 v ddp + 0.5 v dc input clamp current v in < 0 or v in > v ddp ? 10 +10 ma note: stresses beyond those listed in the absolute maximum ratings table can cause permanent damage to the device. exposure to maximu m rated conditions for extended periods can adversely affect device reliability. operation of the device at these conditions or a ny others beyond those listed in the recommended operating conditions is not implied. programming and storage temperature limits product grade programming cycles program retention storage temperature min. max. commercial 50 20 years ? 55 c110 c industrial 50 20 years ? 55 c110 c supply voltages mode v ddl v ddp v pp v pn single voltage 2.5v 2.5v 2.5v v pp 16.5v ? 12v v pn 0v mixed voltage 2.5v 3.3v 3.3v v pp 16.5v ? 12v v pn 0v recommended operating conditions parameter symbol limits commercial dc supply voltage (2.5v i/os) v ddl & v ddp 2.3v to 2.7v dc supply voltage (mixed 2.5v and 3.3v i/os) v ddp v ddl 3.0v to 3.6v 2.3v to 2.7v operating ambient temperature range t a 0 c to 70 c maximum operating junction temperature t j 110 c maximum clock frequency f clock 250 mhz maximum ram frequency f ram 150 mhz industrial dc supply voltage (2.5v i/os) v ddl & v ddp 2.3v to 2.7v dc supply voltage (mixed 2.5v and 3.3v i/os) v ddp v ddl 3.0v to 3.6v 2.3v to 2.7v operating ambient temperature range t a ? 40 c to 85 c maximum operating junction temperature t j 110 c maximum clock frequency f clock 250 mhz maximum ram frequency f ram 150 mhz
v3.0 19 proasic ? 500k family dc electrical specifications (v ddp = 2.5v) symbol parameter conditions min. typ. max. units v ddp , v ddl supply voltage 2.3 2.7 v v oh output high voltage high drive (ob25lph) low drive (ob25lpl) i oh = ? 2.0 ma i oh = ? 4.0 ma i oh = ? 8.0 ma i oh = ? 1.0 ma i oh = ? 2.0 ma i oh = ? 4.0 ma 2.1 2.0 1.7 2.1 2.0 1.7 v v ol output low voltage high drive (ob25lph) low drive (ob25lpl) i ol = 5.0 ma i ol = 10.0 ma i ol = 15.0 ma i ol = 2.0 ma i ol = 3.5 ma i ol = 5.0 ma 0.2 0.4 0.7 0.2 0.4 0.7 v v ih input high voltage 1.7 v ddp + 0.3 v v il input low voltage ? 0.3 0.7 v ? i in ? 2 input current with pull-up without pull-up 25 250 10 a a i ddq quiescent supply current v in = v ss 3 or v ddl 4.0 10 ma i oz 3-state output leakage current v oh = v ss or v ddl 10 a ? i osh ? 2 output short circuit current high high drive (ob25lph) low drive (ob25lpl) v in = v ss v in = v ss 120 100 ma i osl output short circuit current low high drive (ob25lph) low drive (ob25lpl) v in = v ddp v in = v ddp 100 30 ma c i/o i/o pad capacitance 10 pf c clk clock input pad capacitance 10 pf notes: 1. all process conditions. junction temperature: ? 40 to +110 c. 2. current is negative. 3. no pull-up resistor.
proasic ? 500k family 20 v3.0 dc electrical specifications (v ddp = 3.3v) symbol parameter conditions min. typ. max. units v ddp supply voltage 3.0 3.6 v v ddl supply voltage, logic array 2.3 2.7 v v oh output high voltage 3.3v i/o, high drive (ob33p) 3.3v i/o, low drive (ob33l) i oh = ? 5.0 ma i oh = ? 10.0 ma i oh = ? 2.5 ma i oh = ? 5.0 ma 0.9v ddp 2.4 0.9v ddp 2.4 v output high voltage 2.5v i/o, high drive (ob25h) 2.5v i/o, low drive (ob25l) i oh = ? 200 a i oh = ? 10.0 ma i oh = ? 2.0 ma i oh = ? 100 a i oh = ? 1.0 ma i oh = ? 2.0 ma 2.1 2.0 1.7 2.1 2.0 1.7 v v ol output high voltage 3.3v i/o, high drive (ob33p) 3.3v i/o, low drive (ob33l) i ol = 7.5 ma i ol = 12.0 ma i ol = 4.0 ma i ol = 5.0 ma 0.1v ddp 0.4 0.1v ddp 0.4 v output high voltage 2.5v i/o, high drive (ob25h) 2.5v i/o, low drive (ob25l) i ol = 5.0 ma i ol = 12.0 ma i ol = 16.0 ma i ol = 2.5 ma i ol = 5.0 ma i ol = 8.0 ma 0.2 0.4 0.7 0.2 0.4 0.7 v v ih input high voltage 3.3v lvttl/lvcmos 2.5v mode 2 1.7 v ddp + 0.3 v ddp + 0.3 v v il input low voltage 3.3v lvttl/lvcmos 2.5v mode ? 0.3 ? 0.3 0.8 0.7 v ? i in ? 2 input current lvttl/lvcmos lvttl/lvcmos with pull-up without pull-up 30 300 10 a a i ddq quiescent supply current v in = v ss 3 or v ddl 4.0 10 ma i ddqi 4 incremental quiescent supply current 70 400 a i oz 3-state output leakage current v oh = v ss or v ddl 10 a notes: 1. all process conditions. junction temperature: ? 40 to +110 c. 2. current is negative. 3. no pull-up resistor. 4. i ddq is augmented by i ddqi for each 2.5v i/o when operating in a mixed voltage environment.
v3.0 21 proasic ? 500k family ? i osh ? 2 output short circuit current high 3.3v high drive 3.3 low drive 2.5v high drive 2.5 low drive 200 140 120 100 ma i osl output short circuit current low 3.3v high drive 3.3 low drive 2.5v high drive 2.5 low drive 160 150 160 50 ma c i/o i/o pad capacitance 10 pf c clk clock input pad capacitance 10 pf dc specifications (3.3v pci operation) symbol parameter condition min. max. units v ddl supply voltage for core 2.3 2.7 v v ddp supply voltage for i/o ring 3.0 3.6 v v ih input high voltage 0.5v dpp v dpp + 0.5 v v il input low voltage ? 0.5 0.3v ddp v i ipu input pull-up voltage 1 0.7v ddp v i il input leakage current 2 0 < v in < v cci ? 10 +10 a v oh output high voltage i out = ? 500 a 0.9v dpp v v ol output low voltage i out = 1500 a 0.1v dpp v c in input pin capacitance 3 10 pf c clk clk pin capacitance 5 12 pf notes: 1. this specification should be guaranteed by design. it is the minimum voltage to which pull-up resistors are calculated to pul l a floated network. applications sensitive to static power utilization should assure that the input buffer is conducting minimum current a t this input voltage. 2. input leakage currents include hi-z output leakage for all bidirectional buffers with tristate outputs. 3. absolute maximum pin capacitance for a pci input is 10 pf (except for clk). dc electrical specifications (v ddp = 3.3v) (continued) symbol parameter conditions min. typ. max. units notes: 1. all process conditions. junction temperature: ? 40 to +110 c. 2. current is negative. 3. no pull-up resistor. 4. i ddq is augmented by i ddqi for each 2.5v i/o when operating in a mixed voltage environment.
proasic ? 500k family 22 v3.0 ac specifications (3.3v pci operation) symbol parameter condition min. max. units i oh(ac) switching current high 0 < v out 0.3v cci 1 ? 12v cci ma 0.3v cci v out < 0.9v cci 1 ( ? 17.1 + (v ddp ? v out )) ma 0.7v cci < v out < v cci 1, 2 equation a on page 23 (test point) v out = 0.7v cc 2 ? 32v cci ma i ol(ac) switching current low v cci > v out 0.6v cci 1 16v ddp ma 0.6v cci > v out > 0.1v cci 1 (26.7v out )ma 0.18v cci > v out > 0 1, 2 equation b on page 23 (test point) v out = 0.18v cc 2 38v cci ma i cl low clamp current ? 3 < v in ? 1 ? 25 + (v in + 1)/0.015 ma i ch high clamp current v cci + 4 > v in v cci + 1 25 + (v in ? v ddp ? 1)/0.015 ma slew r output rise slew rate 0.2v cci to 0.6v cci load 3 14v/ns slew f output fall slew rate 0.6v cci to 0.2v cci load 3 14v/ns notes: 1. refer to the v/i curves in figure 18 on page 23 . switching current characteristics for req# and gnt# are permitted to be one half of that specified here; i.e., half size output drivers may be used on these signals. this specification does not apply to clk and rst#, which are system outputs. ? switching current high ? specifications are not relevant to serr#, inta#, intb#, intc#, and intd#, which are open drain outputs. 2. maximum current requirements must be met as drivers pull beyond the last step voltage. equations defining these maximums (a a nd b) are provided with the respective diagrams in figure 18 on page 23 . the equation defined maxima should be met by design. in order to facilitate component testing, a maximum current test point is defined for each side of the output driver. 3. this parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rat e at any point within the transition range. the specified load (diagram below) is optional; i.e., the designer may elect to meet this paramete r with an unloaded output per the latest revision of the pci local bus specification. however, adherence to both maximum and minimum parameters is required (the maximum is no longer simply a guideline). rise slew rate does not apply to open drain outputs. output buffer 1/2 in. max. 10 pf 1k ? pin 1k ? pin buffer output 10 pf
v3.0 23 proasic ? 500k family figure 18 shows the 3.3v pci v/i curve and the minimum and maximum pci drive characteristics of the proasic family. equation a i oh = (98.0/v cci ) * (v out ? v cci ) * (v out + 0.4v cci ) for 0.7 v cci < v out < v cci equation b i ol = (256/v cci ) * v out * (v cci ? v out ) for 0v < v out < 0.18 v cci timing characteristics timing characteristics for proasic 500k devices fall into three categories: family dependent, device dependent, and design-dependent. the input and output buffer characteristics are common to all proasic 500k family members. internal routing delays are device-dependent. design dependency means that actual delays are not determined until after placement and routing of the user ? s design are completed. design timing attributes may then be determined by using timer, the static analysis tool embedded into designer software, or performing simulation with post-layout delays using modelsim simulator integrated into libero design environment. critical nets and typical nets propagation delays are expressed only for typical nets, which are used for initial design performance evaluation. critical net delays can then be applied to the most critical timing paths. critical nets are determined by net property assignment prior to placement and routing. up to 6 percent of the nets in a design may be designated as critical, while more than 90% of the nets in a design are typical. user ? s can control priorities between critical nets and use routing constraints, such as set_critical to focus the routing optimization on the most critical ones. please see the designer user ? s guide for more information on using constraints. very long lines some nets in the design are very long lines marked using vlls, which are special routing resources that span multiple rows, columns, or modules. this increases capacitance and resistance, resulting in longer net delays for macros connected to long tracks. typically, up to 6 percent of nets in a fully utilized device require long tracks. very long lines contribute between 4 and 8.4ns routing delay depending on the fanout. this additional delay is represented statistically in higher fanout routing delays. timing derating since proasic 500k devices are manufactured with a cmos process, device performance will vary with temperature, voltage, and process. minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and optimal process variations. maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case process variations (within process specifications). figure 18 3.3v pci v/i curve for proasic family 150.0 100.0 50.0 0.0 50.0 100.0 150.0 0 0.5 1 1.5 2 2.5 3 3.5 4 voltage out (v) current (ma) i oh i ol i oh min spec i oh max spec i ol min spec i ol max spec
proasic ? 500k family 24 v3.0 temperature and voltage derating factors (normalized to worst-case commercial, t j = 70 c, v cca = 2.3v) v cca junction temperature (t j ) ?55 c ?40 c0 c25 c70 c85 c110 c125 c 2.3v 0.84 0.86 0.91 0.94 1.00 1.02 1.05 1.07 2.5v 0.81 0.83 0.87 0.90 0.96 0.98 1.01 1.02 2.7v 0.77 0.79 0.84 0.86 0.92 0.93 0.96 0.98 slew rates measured at c out = 10pf (total output load), nominal power supplies and 25 c type trig. lev. rising edge slew rate falling edge slew rate ps v/ns ps v/ns ob33ph 20%-60% 397 3.33 390 -3.38 ob33pn 20%-60% 463 2.85 450 -2.93 ob33pl 20%-60% 567 2.33 527 -2.51 ob33lh 20%-60% 467 2.83 700 -1.89 ob33ln 20%-60% 620 2.13 767 -1.72 ob33ll 20%-60% 813 1.62 1100 -1.20 ob25hh 20%-60% 750 1.33 310 -3.23 ob25hn 20%-60% 850 1.18 390 -2.56 ob25hl 20%-60% 1310 0.76 510 -1.96 ob25lh 20%-60% 793 1.26 430 -2.33 ob25ln 20%-60% 870 1.15 730 -1.37 ob25ll 20%-60% 1287 0.78 1037 -0.96 ob25lphh 20%-60% 470 2.13 433 -2.31 ob25lphn 20%-60% 533 1.81 527 -1.90 ob25lphl 20%-60% 770 1.30 753 -1.33 ob25lplh 20%-60% 597 1.68 707 -1.42 ob25lpln 20%-60% 873 1.15 760 -1.32 ob25lpll 20%-60% 1153 0.87 1563 -0.54 tristate buffer delays pad a otbx a 50% pa d v ol v oh 50% t dlh 50% 50% t dhl en 50% pa d v ol 50% t enzl 50% 10% en 50% pad gnd v oh 50% t enzh 50% 90% v cc en
v3.0 25 proasic ? 500k family tristate buffer delays (worst-case commercial conditions, v ddp = 3.0v, v ddl = 2.3v, t j = 70 c, f clock = 250 mhz) macro type description max t dlh max t dhl max t enzh max t enzl units otb33ph 3.3v, pci output current, high slew rate 4.2 4.1 4.2 3.67 ns otb33pn 3.3v, pci output current, nominal slew rate 4.7 5.9 4.8 5.3 ns otb33pl 3.3v, pci output current, low slew rate 5.3 7.0 5.3 6.6 ns otb33lh 3.3v, low output current, high slew rate 6.0 6.6 6.0 5.9 ns otb33ln 3.3v, low output current, nominal slew rate 6.7 9.2 6.7 8.9 ns otb33ll 3.3v, low output current, low slew rate 7.5 12.0 7.5 11.8 ns otb25hh 2.5v, high output current, high slew rate 6.9 3.6 6.9 3.4 ns otb25hn 2.5v, high output current, nominal slew rate 7.2 5.2 7.2 4.9 ns otb25hl 2.5v, high output current, low slew rate 8.2 6.4 8.2 6.1 ns otb25lh 2.5v, low output current, high slew rate 10.4 5.5 10.4 5.2 ns otb25ln 2.5v, low output current, nominal slew rate 11.0 8.3 11.0 8.1 ns otb25ll 2.5v, low output current, low slew rate 11.9 10.9 11.9 11.7 ns otb25lphh 2.5v, low power, high output current, high slew rate 5.1 5.1 5.1 4.4 ns otb25lphn 2.5v, low power, high output current, nominal slew rate 6.0 7.7 6.0 7.4 ns otb25lphl 2.5v, low power, high output current, low slew rate 6.9 9.8 6.8 9.3 ns otb25lplh 2.5v, low power, low output current, high slew rate 7.4 8.6 7.4 7.8 ns otb25lpln 2.5v, low power, low output current, nominal slew rate 8.6 12.6 8.5 12.3 ns otb25lpll 2.5v, low power, low output current, low slew rate 9.8 17.0 9.8 16.7 ns notes: 1. t dlh = data-to-pad high 2. t dhl = data-to-pad low 3. t enzh = enable-to-pad, z to high 4. t enzl = enable-to-pad, z to low output buffer delays pad a obx a 50% pad v ol v oh 50% t dlh 50% 50% t dhl
proasic ? 500k family 26 v3.0 output buffer delays (worst-case commercial conditions, v ddp = 3.0v, v ddl = 2.3v, t j = 70 c, f clock = 250 mhz) macro type description max. t dlh max. t dhl units ob33ph 3.3v, pci output current, high slew rate 4.2 4.1 ns ob33pn 3.3v, pci output current, nominal slew rate 4.7 5.9 ns ob33pl 3.3v, pci output current, low slew rate 5.3 7.1 ns ob33lh 3.3v, low output current, high slew rate 6.0 6.6 ns ob33ln 3.3v, low output current, nominal slew rate 6.7 9.2 ns ob33ll 3.3v, low output current, low slew rate 7.5 12.1 ns ob25hh 2.5v, high output current, high slew rate 6.9 3.6 ns ob25hn 2.5v, high output current, nominal slew rate 7.2 5.2 ns ob25hl 2.5v, high output current, low slew rate 8.2 6.4 ns ob25lh 2.5v, low output current, high slew rate 10.4 5.5 ns ob25ln 2.5v, low output current, nominal slew rate 11.0 8.3 ns ob25ll 2.5v, low output current, low slew rate 11.9 10.9 ns ob25lphh 2.5v, low power, high output current, high slew rate 5.1 5.1 ns ob25lphn 2.5v, low power, high output current, nominal slew rate 6.0 7.7 ns ob25lphl 2.5v, low power, high output current, low slew rate 6.9 9.8 ns ob25lplh 2.5v, low power, low output current, high slew rate 7.4 8.6 ns ob25lpln 2.5v, low power, low output current, nominal slew rate 8.6 12.6 ns ob25lpll 2.5v, low power, low output current, low slew rate 9.8 17.0 ns notes: 1. t dlh = data-to-pad high 2. t dhl = data-to-pad low input buffer delays input buffer delays (worst-case commercial conditions, v ddp = 3.0v, v ddl = 2.3v, t j = 70 c, f clock = 250 mhz) macro type description max. t inyh max. t inyl units ib25 2.5v, cmos input levels, no pull-up resistor 2.2 0.7 ns ib25lp 2.5v, cmos input levels, low power 2.2 1.4 ns ib33 3.3v, cmos input levels, no pull-up resistor 1.9 1.0 ns notes: 1. t inyh = input pad-to-y high 2. t inyl = input pad-to-y low pad y pad v cc 0v 50% y gnd v cc 50% t inyh 50% 50% t inyl ibx
v3.0 27 proasic ? 500k family global input buffer delays (worst-case commercial conditions, v ddp = 3.0v, v ddl = 2.3v, t j = 70 c, f clock = 250 mhz) macro type description max. t inyh max. t inyl units gl25 2.5v, cmos input levels 2.1 1.6 ns gl25lp 2.5v, cmos input levels 2.3 2.3 ns gl33 3.3v, cmos input levels 3.8 1.2 ns gl25u 2.5v, cmos input levels, with pull-up resistor 2.1 1.6 ns gl25lpu 2.5v, cmos input levels, low power, with pull-up resistor 2.3 2.3 ns gl33u 3.3v, cmos input levels, with pull-up resistor 3.8 1.2 ns predicted global routing delay* (worst-case commercial conditions, v ddp = 3.0v, v ddl = 2.3v, t j = 70 c, f clock = 250 mhz) parameter description max. units t rckh input low to high (fully loaded row ? 32 inputs) 1.2 ns t rckl input high to low (fully loaded row ? 32 inputs) 1.1 ns t rckh input low to high (minimally loaded row ? 1 input) 0.9 ns t rckl input high to low (minimally loaded row ? 1 input) 0.9 ns * the timing delay difference between tile locations is less than 15ps. global routing skew (worst-case commercial conditions, v ddp = 3.0v, v ddl = 2.3v, t j = 70 c, f clock = 250 mhz) parameter description max. units t rckswh maximum skew low to high 0.3 ns t rckshh maximum skew high to low 0.3 ns module delays a b c y a b 50% y 50% 50% 50% 50% 50% t dalh c 50% 50% 50% 50% 50% t dblh t dahl t dbhl t dchl t dclh 50%
proasic ? 500k family 28 v3.0 embedded memory specifications this section focuses on the embedded memory of the proasic 500k family. it describes the sram and fifo interface signals and includes timing diagrams that show the relationships of signals as they pertain to single embedded memory blocks ( table 4 and table 5 on page 34 ). refer to table 3 on page 12 for basic ram configurations. simultaneous read and write to the same location must be done with care. on such accesses the di bus is output to the do bus. enclosed timing diagrams?sram mode: synchronous ram read, access timed output strobe (synchronous transparent) synchronous ram read, pipeline mode outputs (synchronous pipelined) asynchronous ram write asynchronous ram read, address controlled, rdb=0 asynchronous ram read, rdb controlled synchronous ram write note: the difference between synchronous transparent and pipeline modes is the timing of all the output signals from the memory. in transparent mode the outputs will change within the same clock cycle to reflect the data requested by the currently valid access to the memory. however, if clock cycles are short (high clock speed), the data requires most of the clock cycle to change to valid values (stable signals). this makes processing of this data in the same clock cycle nearly impossible. most designers solve this problem by adding registers at all outputs of the memory to push the data processing into the next clock cycle. in this setup, the whole cycle time can be used to process the data. to simplify the use of this kind of memory setup these registers have been implemented as part of the memory primitive and are available to the user in the synchronous pipeline mode. in this mode, the output signals will change shortly after the second rising edge, following the initiation of the read access. sample macrocell library listing (worst-case commercial conditions, v ddl = 2.3v, t j = 70 o c) cell name description maximum intrinsic delay minimum setup/hold units nand2 2-input nand 0.4 ns and2 2-input and 0.4 ns nor3 3-input nor 0.4 ns mux2l 2-1 mux with active low select 0.4 ns oa21 2-input or into a 2-input and 0.4 ns xor2 2-input exclusive or 0.3 ns ldl active low latch (lh/hl) d: 0.3/0.2 t setup 0.5 t hold 0.2 ns dffl negative edge-triggered d-type flip-flop (lh/hl) clk-q: 0.4/0.4 t setup 0.4 t hold 0.2 ns note: assumes fanout of two. table 4 memory block sram interface signals sram signal bits in/out description wclks 1 in write clock used on synchronization on write side rclks 1 in read clock used on synchronization on read side raddr<0:7> 8 in read address rblkb 1 in negative true read block select rdb 1 in negative true read pulse waddr<0:7> 8 in write address wblkb 1 in negative true write block select di<0:8> 9 in input data bits <0:8>, <8> can be used for parity in wrb 1 in negative true write pulse do<0:8> 9 out output data bits <0:8>, <8> can be used for parity out rpe 1 out read parity error wpe 1 out write parity error parodd 1 in selects odd parity generation/detect when high, even when low note: not all signals shown are used in all modes.
v3.0 29 proasic ? 500k family synchronous ram read, access timed output strobe (synchronous transparent) t j = 0 c to 110 c; v ddl = 2.3v to 2.7v symbol t xxx description min. max. units notes ccyc cycle time 7.5 ns cmh clock high phase 3.0 ns cml clock low phase 3.0 ns oca new do access from rclks 7.5 ns och old do valid from rclks 3.0 ns rach raddr hold from rclks 0.5 ns racs raddr setup to rclks 1.0 ns rdch rdb hold from rclks 0.5 ns rdcs rdb setup to rclks 1.0 ns rpca new rpe access from rclks 9.5 ns rpch old rpe valid from rclks 3.0 ns raddr rpe do rclks rb=(rbd+rblkb) new valid data out cycle start old data out new valid address t racs t rdcs t rdch t rach t och t rpch t cmh t oca t rpca t ccyc t cml
proasic ? 500k family 30 v3.0 synchronous ram read, pipeline mode outputs (synchronous pipelined) t j = 0 c to 110 c; v ddl = 2.3v to 2.7v symbol t xxx description min. max. units notes ccyc cycle time 7.5 ns cmh clock high phase 3.0 ns cml clock low phase 3.0 ns oca new do access from rclks 2.0 ns och old do valid from rclks .75 ns rach raddr hold from rclks 0.5 ns racs raddr setup to rclks 1.0 ns rdch rdb hold from rclks 0.5 ns rdcs rdb setup to rclks 1.0 ns rpca new rpe access from rclks 4.0 ns rpch old rpe valid from rclks 1.0 ns rclks rpe do new valid data out cycle start new rpe out raddr new valid address rb=(rdb+rblkb) t racs t oca t rpch t och t rpca t cml t cmh t ccyc t rach t rdch t rdcs old data out old rpe out
v3.0 31 proasic ? 500k family asynchronous ram write t j = 0 c to 110 c; v ddl = 2.3v to 2.7v symbol t xxx description min. max. units notes awrh waddr hold from wb 1.0 ns awrs waddr setup to wb 0.5 ns dwrh di hold from wb 1.5 ns dwrs di setup to wb 0.5 ns pargen is inactive dwrs di setup to wb 2.5 ns pargen is active wpda wpe access from di 3.0 ns wpe is invalid while wpdh wpe hold from di 1.0 ns pargen is active wrcyc cycle time 7.5 ns wrmh wb high phase 3.0 ns inactive wrml wb low phase 3.0 ns active wb=(wrb+wblkb) waddr wpe di t awrs t wpda t awrh t dwrs t wrml t wrmh t wrcyc t wpdh t dwrh
proasic ? 500k family 32 v3.0 asynchronous ram read, address controlled, rdb=0 asynchronous ram read, rdb controlled t j = 0 c to 110 c; v ddl = 2.3v to 2.7v symbol t xxx description min. max. units notes acyc read cycle time 7.5 ns oaa new do access from raddr stable 7.5 ns oah old do hold from raddr stable 3.0 ns rpaa new rpe access from raddr stable 10.0 ns rpah old rpe hold from raddr stable 3.0 ns t j = 0 c to 110 c; v ddl = 2.3v to 2.7v symbol t xxx description min. max. units notes orda new do access from rb 7.5 ns ordh old do valid from rb 3.0 ns rdcyc read cycle time 7.5 ns rdmh rb high phase 3.0 ns inactive setup to new cycle rdml rb low phase 3.0 ns active rprda new rpe access from rb 9.5 ns rprdh old rpe valid from rb 3.0 ns rpe do raddr t oah t rpah t oaa t rpaa t acyc rb=(rdb+rblkb) rpe do t ordh t orda t rprda t rdml t rdcyc t rdmh t rprdh
v3.0 33 proasic ? 500k family synchronous ram write t j = 0 c to 110 c; v ddl = 2.3v to 2.7v symbol t xxx description min. max. units notes ccyc cycle time 7.5 ns cmh clock high phase 3.0 ns cml clock low phase 3.0 ns dch di hold from wclks 0.5 ns dcs di setup to wclks 1.0 ns wach waddr hold from wclks 0.5 ns wdcs waddr setup to wclks 1.0 ns wpca new wpe access from wclks 3.0 ns wpe is invalid while pargen is active wpch old wpe valid from wclks 0.5 ns wrch, wbch wrb & wblkb hold from wclks 0.5 ns wrcs, wbcs wrb & wblkb setup to wclks 1.0 ns note: on simultaneous read and write accesses to the same location di is output to do. wclks wpe waddr, di wrb, wblkb cycle start t wrch , t wbch t wrcs , t wbcs t dcs , t wdcs t wpch t dch , t wach t wpca t cmh t cml t ccyc
proasic ? 500k family 34 v3.0 asynchronous fifo full and empty transitions the asynchronous fifo accepts writes and reads while not full or not empty. when the fifo is full, all writes are inhibited. conversely, when the fifo is empty, all reads are inhibited. a problem is created if the fifo is written during the transition out of full to not full or read during the transition out of empty to not empty. the exact time at which the write (read) operation changes from inhibited to accepted after the read (write) signal which causes the transition from full (empty) to not full (empty) is indeterminate. this indeterminate period starts 1ns after the rb (wb) transition which deactivates full (not empty). for slow cycles, the indeterminate period ends 3ns after the rb (wb) transition. for fast cycles, this period ends either 3ns or (7.5ns - t rdl (t wrl )) after the rb (wb) transition, whichever is later. the timing diagram for write is shown in figure 19 on page 35 . the timing diagram for read is shown in figure 20 on page 35 . for basic ram configurations, see table 3 on page 12 . for memory block interface signals, see table 4 on page 28 , and for memory block fifo signals, see table 5 . enclosed timing diagrams ? fifo mode: asynchronous fifo read asynchronous fifo write synchronous fifo read, access timed output strobe (synchronous transparent) synchronous fifo read, pipeline mode outputs (synchronous pipelined) synchronous fifo write fifo reset table 5 memory block fifo interface signals fifo signal bits in/out description wclks 1 in write clock used to synchronize write side rclks 1 in read clock used to synchronize read side level <0:7> 8 in direct configuration implements static flag logic rblkb 1 in active low read block select rdb 1 in active low read pulse reset 1 in active low reset for fifo pointers wblkb 1 in active low write block select di<0:8> 9 in input data bits <0:8>, <8> can be used for parity in. wrb 1 in active low write pulse full, empty 2 out fifo flags. full prevents write and empty prevents read eqth, geqth 2 out eqth is true when the fifo holds (level) words. geqth is true when the fifo holds (level) words or more do<0:8> 9 out output data bits <0:8>, <8> can be used for parity out. rpe 1 out read parity error wpe 1 out write parity error lgdep <0:2> 3 in configures depth of the fifo to 2 (lgdep+1) parodd 1 in selects odd parity generation/detect when high, even when low
v3.0 35 proasic ? 500k family figure 19 write timing diagram figure 20 read timing diagram write accepted write inhibited full rb write cycle 1ns 3ns wb read accepted read inhibited empty wb read cycle 1ns 3ns rb
proasic ? 500k family 36 v3.0 asynchronous fifo read t j = 0 c to 110 c; v ddl = 2.3v to 2.7v symbol t xxx description min. max. units notes erdh, frdh, thrdh old empty, full, eqth, & geth valid hold time from rb 0.5 ns empty/full/thresh are invalid from the end of hold until the new access is complete erda new empty access from rb 3.0 1 ns frda full access from rb 3.0 1 ns orda new do access from rb 7.5 ns ordh old do valid from rb 3.0 ns rdcyc read cycle time 7.5 ns rdwrs wb , clearing empty, setup to rb 3.0 2 ns enabling the read operation 1.0 ns inhibiting the read operation rdh rb high phase 3.0 ns inactive rdl rb low phase 3.0 ns active rprda new rpe access from rb 9.5 ns rprdh old rpe valid from rb 4.0 ns thrda eqth or geth access from rb 4.5 ns notes: 1. at fast cycles, erda & frda = max ((7.5ns ? rdl), 3.0ns) 2. at fast cycles, rdwrs (for enabling read) = max ((7.5ns ? wrl), 3.0ns) rb=(rdb+rblkb) rpe do empty eqth, geth full (empty inhibits read) cycle start wb t rdwrs t erdh , t frdh t erda , t frda t thrdh t ordh t rprdh t orda t rprda t rdl t rdcyc t rdh t thrda
v3.0 37 proasic ? 500k family asynchronous fifo write t j = 0 c to 110 c; v ddl = 2.3v to 2.7v symbol t xxx description min. max. units notes dwrh di hold from wb 1.5 ns dwrs di setup to wb 0.5 ns pargen is inactive dwrs di setup to wb 2.5 ns pargen is active ewrh, fwrh, thwrh old empty, full, eqth, & geth valid hold time after wb 0.5 ns empty/full/thresh are invalid from the end of hold until the new access is complete ewra empty access from wb 3.0 1 ns fwra new full access from wb 3.0 1 ns thwra eqth or geth access from wb 4.5 ns wpda wpe access from di 3.0 ns wpe is invalid while pargen is active wpdh wpe hold from di 1.0 ns wrcyc cycle time 7.5 ns wrrds rb , clearing full, setup to wb 3.0 2 ns enabling the write operation 1.0 inhibiting the write operation wrh wb high phase 3.0 ns inactive wrl wb low phase 3.0 ns active notes: 1. at fast cycles, ewra, fwra = max ((7.5ns ? wrl), 3.0ns) 2. at fast cycles, wrrds (for enabling write) = max ((7.5ns ? rdl), 3.0ns) wpe di (full inhibits write) wb=(wrb+wblkb) empty eqth, geth full cycle start rb t wrrds t dwrh t wpdh t wpda t dwrs t ewrh , t fwrh t ewra , t fwra t thwrh t thwra t wrh t wrl t wrcyc
proasic ? 500k family 38 v3.0 synchronous fifo read, access timed output strobe (synchronous transparent) t j = 0 c to 110 c; v ddl = 2.3v to 2.7v symbol t xxx description min. max. units notes ccyc cycle time 7.5 ns cmh clock high phase 3.0 ns cml clock low phase 3.0 ns ecba new empty access from rclks 3.0 1 ns fcba full access from rclks 3.0 1 ns ecbh, fcbh, thcbh old empty, full, eqth, & geth valid hold time from rclks 1.0 ns empty/full/thresh are invalid from the end of hold until the new access is complete oca new do access from rclks 7.5 ns och old do valid from rclks 3.0 ns rdch rdb hold from rclks 0.5 ns rdcs rdb setup to rclks 1.0 ns rpca new rpe access from rclks 9.5 ns rpch old rpe valid from rclks 3.0 ns hcba eqth or geth access from rclks 4.5 ns note: 1. at fast cycles, ecba & fcba = max ((7.5ns ? cmh), 3.0ns) rclks rpe do empty eqth, geth full old data out new valid data out (empty inhibits read) rdb cycle start t rdch t och t rpch t rdcs t ecbh , t fcbh t ecba , t fcba t oca t rpca t cmh t cml t ccyc t thcbh t hcba
v3.0 39 proasic ? 500k family synchronous fifo read, pipeline mode outputs (synchronous pipelined) t j = 0 c to 110 c; v ddl = 2.3v to 2.7v symbol t xxx description min. max. units notes ccyc cycle time 7.5 ns cmh clock high phase 3.0 ns cml clock low phase 3.0 ns ecba new empty access from rclks 3.0 1 ns fcba full access from rclks 3.0 1 ns ecbh, fcbh, thcbh old empty, full, eqth, & geth valid hold time from rclks 1.0 ns empty/full/thresh are invalid from the end of hold until the new access is complete oca new do access from rclks 2.0 ns och old do valid from rclks 0.75 ns rdch rdb hold from rclks 0.5 ns rdcs rdb setup to rclks 1.0 ns rpca new rpe access from rclks 4.0 ns rpch old rpe valid from rclks 1.0 ns hcba eqth or geth access from rclks 4.5 ns note: 1. at fast cycles, ecba & fcba = max ((7.5ns ? cms), 3.0ns) rclks rpe do empty eqth, geth full old data out new valid data out rdb cycle start old rpe out new rpe out t ecbh , t fcbh t rdch t rdcs t oca t ecba , t fcba t thcbh t hcba t cmh t cml t ccyc t rpch t och t rpca
proasic ? 500k family 40 v3.0 synchronous fifo write t j = 0 c to 110 c; v ddl = 2.3v to 2.7v symbol t xxx description min. max. units notes ccyc cycle time 7.5 ns cmh clock high phase 3.0 ns cml clock low phase 3.0 ns dch di hold from wclks 0.5 ns dcs di setup to wclks 1.0 ns fcba new full access from wclks 3.0 1 ns ecba empty access from wclks 3.0 1 ns ecbh, fcbh, hcbh old empty, full, eqth, & geth valid hold time from wclks 1.0 ns empty/full/thresh are invalid from the end of hold until the new access is complete hcba eqth or geth access from wclks 4.5 ns wpca new wpe access from wclks 3.0 ns wpe is invalid while pargen is active wpch old wpe valid from wclks 0.5 ns wrch, wbch wrb & wblkb hold from wclks 0.5 ns wrcs, wbcs wrb & wblkb setup to wclks 1.0 ns note: 1. at fast cycles, ecba & fcba = max ((7.5ns ? cmh), 3.0ns) wclks wpe di empty eqth, geth full (full inhibits write) wrb, wblkb cycle start t wrch , t wbch t ecbh , t fcbh t ecba , t fcba t hcba t wrcs , t wbcs t dcs t wpca t cmh t cml t ccyc t wpch t dch t hcbh
v3.0 41 proasic ? 500k family fifo reset t j = 0 c to 110 c; v ddl = 2.3v to 2.7v symbol t xxx description min. max. units notes cbrsh wclks or rclks hold from resetb 1.5 ns synchronous mode only cbrss wclks or rclks setup to resetb 1.5 ns synchronous mode only ersa new empty access from resetb 3.0 ns frsa full access from resetb 3.0 ns rsl resetb low phase 7.5 ns thrsa eqth or geth access from resetb 4.5 ns wbrsh wb hold from resetb 1.5 ns asynchronous mode only wbrss wb setup to resetb 1.5 ns asynchronous mode only resetb empty eqth, geth full cycle start cycle start wclks, rclks t ersa , t frsa t thrsa t cbrss t wbrss t cbrsh t wbrsh t rsl wrb, wblkb
proasic ? 500k family 42 v3.0 pin description i/o user input/output the i/o pin functions as an input, output, three-state, or bidirectional buffer. input and output signal levels are compatible with standard lvttl and lvcmos specifications. unused i/o pins are configured as inputs with pull-up resistors. n/c no connect to maintain compatibility with future actel proasic products it is recommended that this pin not be connected to the circuitry on the board. gl global input pin low skew input pin for clock or other global signals. input only. this pin can be configured with a pull-up resistor. gnd ground common ground supply voltage. v ddl logic array power supply pin 2.5v supply voltage. v ddp i/o pad power supply pin 2.5v or 3.3v supply voltage. v pp programming supply pin this pin must be connected to v ddp during normal operation, or it can remain at 16.5v in an isp application. this pin must not float. v pn programming supply pin this pin must be connected to gnd during normal operation, or it can remain at ? 12v in an isp application. this pin must not float. tms test mode select the tms pin controls the use of boundary scan circuitry. tck test clock clock input pin for boundary scan. tdi test data in serial input for boundary scan. tdo test data out serial output for boundary scan. trst test reset input asynchronous, active low input pin for resetting boundary scan circuitry. rck running clock a free running clock is needed during programming if the programmer cannot guarantee that tck will be uninterrupted.
v3.0 43 proasic ? 500k family package pin assignments 208-pin pqfp 208-pin pqfp 1 208
proasic ? 500k family 44 v3.0 208-pin pqfp pin number a500k050 function a500k130 function a500k180 function a500k270 function pin number a500k050 function a500k130 function a500k180 function a500k270 function 1 gnd gnd gnd gnd 53 v ddp v ddp v ddp v ddp 2 i/o i/o i/o i/o 54 i/o i/o i/o i/o 3 i/o i/o i/o i/o 55 i/o i/o i/o i/o 4 i/o i/o i/o i/o 56 i/o i/o i/o i/o 5 i/o i/o i/o i/o 57 i/o i/o i/o i/o 6 i/o i/o i/o i/o 58 i/o i/o i/o i/o 7 i/o i/o i/o i/o 59 i/o i/o i/o i/o 8 i/o i/o i/o i/o 60 i/o i/o i/o i/o 9 i/o i/o i/o i/o 61 i/o i/o i/o i/o 10 i/o i/o i/o i/o 62 i/o i/o i/o i/o 11 i/o i/o i/o i/o 63 i/o i/o i/o i/o 12 i/o i/o i/o i/o 64 i/o i/o i/o i/o 13 i/o i/o i/o i/o 65 gnd gnd gnd gnd 14 i/o i/o i/o i/o 66 i/o i/o i/o i/o 15 i/o i/o i/o i/o 67 i/o i/o i/o i/o 16 v ddl v ddl v ddl v ddl 68 i/o i/o i/o i/o 17 gnd gnd gnd gnd 69 i/o i/o i/o i/o 18 i/o i/o i/o i/o 70 i/o i/o i/o i/o 19 i/o i/o i/o i/o 71 v ddl v ddl v ddl v ddl 20 i/o i/o i/o i/o 72 v ddp v ddp v ddp v ddp 21 i/o i/o i/o i/o 73 i/o i/o i/o i/o 22 v ddp v ddp v ddp v ddp 74 i/o i/o i/o i/o 23 i/o i/o i/o i/o 75 i/o i/o i/o i/o 24 i/o i/o i/o i/o 76 i/o i/o i/o i/o 25 gl gl gl gl 77 i/o i/o i/o i/o 26 gl gl gl gl 78 i/o i/o i/o i/o 27 i/o i/o i/o i/o 79 i/o i/o i/o i/o 28 i/o i/o i/o i/o 80 i/o i/o i/o i/o 29 gnd gnd gnd gnd 81 gnd gnd gnd gnd 30 i/o i/o i/o i/o 82 i/o i/o i/o i/o 31 i/o i/o i/o i/o 83 i/o i/o i/o i/o 32 i/o i/o i/o i/o 84 i/o i/o i/o i/o 33 i/o i/o i/o i/o 85 i/o i/o i/o i/o 34 i/o i/o i/o i/o 86 i/o i/o i/o i/o 35 i/o i/o i/o i/o 87 i/o i/o i/o i/o 36 v ddl v ddl v ddl v ddl 88 v ddl v ddl v ddl v ddl 37 i/o i/o i/o i/o 89 v ddp v ddp v ddp v ddp 38 i/o i/o i/o i/o 90 i/o i/o i/o i/o 39 i/o i/o i/o i/o 91 i/o i/o i/o i/o 40 v ddp v ddp v ddp v ddp 92 i/o i/o i/o i/o 41 gnd gnd gnd gnd 93 i/o i/o i/o i/o 42 i/o i/o i/o i/o 94 i/o i/o i/o i/o 43 i/o i/o i/o i/o 95 i/o i/o i/o i/o 44 i/o i/o i/o i/o 96 i/o i/o i/o i/o 45 i/o i/o i/o i/o 97 gnd gnd gnd gnd 46 i/o i/o i/o i/o 98 i/o i/o i/o i/o 47 i/o i/o i/o i/o 99 i/o i/o i/o i/o 48 i/o i/o i/o i/o 100 i/o i/o i/o i/o 49 i/o i/o i/o i/o 101 tck tck tck tcko 50 i/o i/o i/o i/o 102 tdi tdi tdi tdi 51 i/o i/o i/o i/o 103 tms tms tms tms 52 gnd gnd gnd gnd 104 v ddp v ddp v ddp v ddp
v3.0 45 proasic ? 500k family 105 gnd gnd gnd gnd 157 v ddp v ddp v ddp v ddp 106 v pp v pp v pp v pp 158 i/o i/o i/o i/o 107 v pn v pn v pn v pn 159 i/o i/o i/o i/o 108 tdo tdo tdo tdo 160 i/o i/o i/o i/o 109 trst trst trst trst 161 i/o i/o i/o i/o 110 rck rck rck rck 162 gnd gnd gnd gnd 111 i/o i/o i/o i/o 163 i/o i/o i/o i/o 112 i/o i/o i/o i/o 164 i/o i/o i/o i/o 113 i/o i/o i/o i/o 165 i/o i/o i/o i/o 114 i/o i/o i/o i/o 166 i/o i/o i/o i/o 115 i/o i/o i/o i/o 167 i/o i/o i/o i/o 116 i/o i/o i/o i/o 168 i/o i/o i/o i/o 117 i/o i/o i/o i/o 169 i/o i/o i/o i/o 118 i/o i/o i/o i/o 170 v ddp v ddp v ddp v ddp 119 i/o i/o i/o i/o 171 v ddl v ddl v ddl v ddl 120 i/o i/o i/o i/o 172 i/o i/o i/o i/o 121 i/o i/o i/o i/o 173 i/o i/o i/o i/o 122 gnd gnd gnd gnd 174 i/o i/o i/o i/o 123 v ddp v ddp v ddp v ddp 175 i/o i/o i/o i/o 124 i/o i/o i/o i/o 176 i/o i/o i/o i/o 125 i/o i/o i/o i/o 177 i/o i/o i/o i/o 126 v ddl v ddl v ddl v ddl 178 gnd gnd gnd gnd 127 i/o i/o i/o i/o 179 i/o i/o i/o i/o 128 i/o i/o i/o i/o 180 i/o i/o i/o i/o 129 i/o i/o i/o i/o 181 i/o i/o i/o i/o 130 gnd gnd gnd gnd 182 i/o i/o i/o i/o 131 i/o i/o i/o i/o 183 i/o i/o i/o i/o 132 i/o i/o i/o i/o 184 i/o i/o i/o i/o 133 gl gl gl gl 185 i/o i/o i/o i/o 134glglglgl 186v ddp v ddp v ddp v ddp 135 i/o i/o i/o i/o 187 v ddl v ddl v ddl v ddl 136 i/o i/o i/o i/o 188 i/o i/o i/o i/o 137 i/o i/o i/o i/o 189 i/o i/o i/o i/o 138 v ddp v ddp v ddp v ddp 190 i/o i/o i/o i/o 139 i/o i/o i/o i/o 191 i/o i/o i/o i/o 140 i/o i/o i/o i/o 192 i/o i/o i/o i/o 141 gnd gnd gnd gnd 193 i/o i/o i/o i/o 142 v ddl v ddl v ddl v ddl 194 i/o i/o i/o i/o 143 i/o i/o i/o i/o 195 gnd gnd gnd gnd 144 i/o i/o i/o i/o 196 i/o i/o i/o i/o 145 i/o i/o i/o i/o 197 i/o i/o i/o i/o 146 i/o i/o i/o i/o 198 i/o i/o i/o i/o 147 i/o i/o i/o i/o 199 i/o i/o i/o i/o 148 i/o i/o i/o i/o 200 i/o i/o i/o i/o 149 i/o i/o i/o i/o 201 i/o i/o i/o i/o 150 i/o i/o i/o i/o 202 i/o i/o i/o i/o 151 i/o i/o i/o i/o 203 i/o i/o i/o i/o 152 i/o i/o i/o i/o 204 i/o i/o i/o i/o 153 i/o i/o i/o i/o 205 i/o i/o i/o i/o 154 i/o i/o i/o i/o 206 i/o i/o i/o i/o 155 i/o i/o i/o i/o 207 i/o i/o i/o i/o 156 gnd gnd gnd gnd 208 v ddp v ddp v ddp v ddp 208-pin pqfp (continued) pin number a500k050 function a500k130 function a500k180 function a500k270 function pin number a500k050 function a500k130 function a500k180 function a500k270 function
proasic ? 500k family 46 v3.0 package pin assignments (continued) 272-pin pbga (bottom view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a b c d e f g h j k l m n p r t u v w y
v3.0 47 proasic ? 500k family 272-pin pbga pin number a500k050 function a500k130 function pin number a500k050 function a500k130 function pin number a500k050 function a500k130 function a1 i/o i/o c7 i/o i/o f17 v ddp v ddp a2 i/o i/o c8 i/o i/o f18 i/o i/o a3 i/o i/o c9 i/o i/o f19 i/o i/o a4 i/o i/o c10 i/o i/o f20 i/o i/o a5 i/o i/o c11 i/o i/o g1 i/o i/o a6 i/o i/o c12 i/o i/o g2 i/o i/o a7 i/o i/o c13 i/o i/o g3 i/o i/o a8 i/o i/o c14 i/o i/o g4 i/o i/o a9 i/o i/o c15 i/o i/o g17 i/o i/o a10 i/o i/o c16 i/o i/o g18 i/o i/o a11 i/o i/o c17 i/o i/o g19 i/o i/o a12 i/o i/o c18 i/o i/o g20 i/o i/o a13 i/o i/o c19 i/o i/o h1 i/o i/o a14 i/o i/o c20 i/o i/o h2 i/o i/o a15 i/o i/o d1 i/o i/o h3 i/o i/o a16 i/o i/o d2 i/o i/o h4 i/o i/o a17 i/o i/o d3 i/o i/o h17 i/o i/o a18 i/o i/o d4 v ddp v ddp h18 i/o i/o a19 i/o i/o d5 v ddp v ddp h19 i/o i/o a20 i/o i/o d6 v ddp v ddp h20 gl gl b1 i/o i/o d7 i/o i/o j1 i/o i/o b2 i/o i/o d8 v ddl v ddl j2 gl gl b3 i/o i/o d9 v ddl v ddl j3 gl gl b4 i/o i/o d10 v ddl v ddl j4 v ddl v ddl b5 i/o i/o d11 v ddl v ddl j9 gnd gnd b6 i/o i/o d12 v ddl v ddl j10 gnd gnd b7 i/o i/o d13 v ddl v ddl j11 gnd gnd b8 i/o i/o d14 i/o i/o j12 gnd gnd b9 i/o i/o d15 v ddp v ddp j17 v ddl v ddl b10 i/o i/o d16 v ddp v ddp j18 gl gl b11 i/o i/o d17 v ddp v ddp j19 i/o i/o b12 i/o i/o d18 i/o i/o j20 i/o i/o b13 i/o i/o d19 i/o i/o k1 i/o i/o b14 i/o i/o d20 i/o i/o k2 i/o i/o b15 i/o i/o e1 i/o i/o k3 i/o i/o b16 i/o i/o e2 i/o i/o k4 v ddl v ddl b17 i/o i/o e3 i/o i/o k9 gnd gnd b18 i/o i/o e4 v ddp v ddp k10 gnd gnd b19 i/o i/o e17 v ddp v ddp k11 gnd gnd b20 i/o i/o e18 i/o i/o k12 gnd gnd c1 i/o i/o e19 i/o i/o k17 v ddl v ddl c2 i/o i/o e20 i/o i/o k18 i/o i/o c3 i/o i/o f1 i/o i/o k19 i/o i/o c4 i/o i/o f2 i/o i/o k20 i/o i/o c5 i/o i/o f3 i/o i/o l1 i/o i/o c6 i/o i/o f4 v ddp v ddp l2 i/o i/o
proasic ? 500k family 48 v3.0 l3 i/o i/o t1 i/o i/o v19 i/o i/o l4 v ddl v ddl t2 i/o i/o v20 i/o i/o l9 gnd gnd t3 i/o i/o w1 i/o i/o l10 gnd gnd t4 v ddp v ddp w2 i/o i/o l11 gnd gnd t17 v ddp v ddp w3 i/o i/o l12 gnd gnd t18 i/o i/o w4 i/o i/o l17 v ddl v ddl t19 i/o i/o w5 i/o i/o l18 i/o i/o t20 i/o i/o w6 i/o i/o l19 i/o i/o u1 i/o i/o w7 i/o i/o l20 i/o i/o u2 i/o i/o w8 i/o i/o m1 i/o i/o u3 i/o i/o w9 i/o i/o m2 i/o i/o u4 v ddp v ddp w10 i/o i/o m3 i/o i/o u5 v ddp v ddp w11 i/o i/o m4 v ddl v ddl u6 v ddp v ddp w12 i/o i/o m9 gnd gnd u7 i/o i/o w13 i/o i/o m10 gnd gnd u8 v ddl v ddl w14 i/o i/o m11 gnd gnd u9 v ddl v ddl w15 i/o i/o m12 gnd gnd u10 v ddl v ddl w16 i/o i/o m17 v ddl v ddl u11 v ddl v ddl w17 tck tck m18 i/o i/o u12 v ddl v ddl w18 v pp v pp m19 i/o i/o u13 v ddl v ddl w19 trst trst m20 i/o i/o u14 i/o i/o w20 i/o i/o n1 i/o i/o u15 v ddp v ddp y1 i/o i/o n2 i/o i/o u16 v ddp v ddp y2 i/o i/o n3 i/o i/o u17 v ddp v ddp y3 i/o i/o n4 v ddl v ddl u18 rck rck y4 i/o i/o n17 v ddl v ddl u19 i/o i/o y5 i/o i/o n18 i/o i/o u20 i/o i/o y6 i/o i/o n19 i/o i/o v1 i/o i/o y7 i/o i/o n20 i/o i/o v2 i/o i/o y8 i/o i/o p1 i/o i/o v3 i/o i/o y9 i/o i/o p2 i/o i/o v4 i/o i/o y10 i/o i/o p3 i/o i/o v5 i/o i/o y11 i/o i/o p4 v ddp v ddp v6 i/o i/o y12 i/o i/o p17 v ddp v ddp v7 i/o i/o y13 i/o i/o p18 i/o i/o v8 i/o i/o y14 i/o i/o p19 i/o i/o v9 i/o i/o y15 i/o i/o p20 i/o i/o v10 i/o i/o y16 i/o i/o r1 i/o i/o v11 i/o i/o y17 i/o i/o r2 i/o i/o v12 i/o i/o y18 tdi tdi r3 i/o i/o v13 i/o i/o y19 v pn v pn r4 v ddp v ddp v14 i/o i/o y20 i/o i/o r17 v ddp v ddp v15 i/o i/o r18 i/o i/o v16 i/o i/o r19 i/o i/o v17 tms tms r20 i/o i/o v18 tdo tdo 272-pin pbga (continued) pin number a500k050 function a500k130 function pin number a500k050 function a500k130 function pin number a500k050 function a500k130 function
v3.0 49 proasic ? 500k family package pin assignments (continued) 456-pin pbga (bottom view) 1 2 3 5 6 7 8 9 10 11 15 14 13 12 16 17 18 19 20 21 22 23 4 24 25 26 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af
proasic ? 500k family 50 v3.0 456-pin pbga pin number a500k130 function a500k180 function a500k270 function pin number a500k130 function a500k180 function a500k270 function a1 v ddp v ddp v ddp ab11 i/o i/o i/o a2 v ddp v ddp v ddp ab12 i/o i/o i/o a3 nc i/o i/o ab13 i/o i/o i/o a4 i/o i/o i/o ab14 i/o i/o i/o a5 i/o i/o i/o ab15 i/o i/o i/o a6 nc i/o i/o ab16 i/o i/o i/o a7 i/o i/o i/o ab17 i/o i/o i/o a8 nc i/o i/o ab18 i/o i/o i/o a9 nc i/o i/o ab19 i/o i/o i/o a10 i/o i/o i/o ab20 v ddl v ddl v ddl a11 nc i/o i/o ab21 v ddl v ddl v ddl a12 nc i/o i/o ab22 v ddl v ddl v ddl a13 i/o i/o i/o ab23 i/o i/o i/o a14 nc i/o i/o ab24 i/o i/o i/o a15 nc i/o i/o ab25 i/o i/o i/o a16 i/o i/o i/o ab26 i/o i/o i/o a17 nc i/o i/o ac1 i/o i/o i/o a18 nc i/o i/o ac2 i/o i/o i/o a19 i/o i/o i/o ac3 i/o i/o i/o a20 nc i/o i/o ac4 v ddp v ddp v ddp a21 nc i/o i/o ac5 i/o i/o i/o a22 i/o i/o i/o ac6 i/o i/o i/o a23 nc i/o i/o ac7 i/o i/o i/o a24 nc i/o i/o ac8 i/o i/o i/o a25 v ddp v ddp v ddp ac9 i/o i/o i/o a26 v ddp v ddp v ddp ac10 i/o i/o i/o aa1 i/o i/o i/o ac11 i/o i/o i/o aa2 i/o i/o i/o ac12 i/o i/o i/o aa3 i/o i/o i/o ac13 i/o i/o i/o aa4 i/o i/o i/o ac14 i/o i/o i/o aa5 v ddl v ddl v ddl ac15 i/o i/o i/o aa22 v ddl v ddl v ddl ac16 i/o i/o i/o aa23 i/o i/o i/o ac17 i/o i/o i/o aa24 i/o i/o i/o ac18 i/o i/o i/o aa25 i/o i/o i/o ac19 i/o i/o i/o aa26 nc i/o i/o ac20 i/o i/o i/o ab1 nc i/o i/o ac21 tms tms tms ab2 i/o i/o i/o ac22 tdo tdo tdo ab3 i/o i/o i/o ac23 v ddp v ddp v ddp ab4 i/o i/o i/o ac24 rck rck rck ab5 v ddl v ddl v ddl ac25 i/o i/o i/o ab6 v ddl v ddl v ddl ac26 nc i/o i/o ab7 v ddl v ddl v ddl ad1 nc i/o i/o ab8 i/o i/o i/o ad2 i/o i/o i/o ab9 i/o i/o i/o ad3 v ddp v ddp v ddp ab10 i/o i/o i/o ad4 i/o i/o i/o
v3.0 51 proasic ? 500k family ad5 i/o i/o i/o ae25 v ddp v ddp v ddp ad6 i/o i/o i/o ae26 v ddp v ddp v ddp ad7 i/o i/o i/o af1 v ddp v ddp v ddp ad8 i/o i/o i/o af2 v ddp v ddp v ddp ad9 i/o i/o i/o af3 nc i/o i/o ad10 i/o i/o i/o af4 nc i/o i/o ad11 i/o i/o i/o af5 i/o i/o i/o ad12 i/o i/o i/o af6 nc i/o i/o ad13 i/o i/o i/o af7 nc i/o i/o ad14 i/o i/o i/o af8 i/o i/o i/o ad15 i/o i/o i/o af9 nc i/o i/o ad16 i/o i/o i/o af10 nc i/o i/o ad17 i/o i/o i/o af11 i/o i/o i/o ad18 i/o i/o i/o af12 nc i/o i/o ad19 i/o i/o i/o af13 nc i/o i/o ad20 i/o i/o i/o af14 i/o i/o i/o ad21 tck tck tck af15 nc i/o i/o ad22 v pp v pp v pp af16 nc i/o i/o ad23 i/o i/o i/o af17 i/o i/o i/o ad24 v ddp v ddp v ddp af18 nc i/o i/o ad25 i/o i/o i/o af19 nc i/o i/o ad26 nc i/o i/o af20 i/o i/o i/o ae1 v ddp v ddp v ddp af21 nc i/o i/o ae2 v ddp v ddp v ddp af22 i/o i/o i/o ae3 i/o i/o i/o af23 tdi tdi tdi ae4 i/o i/o i/o af24 nc i/o i/o ae5 i/o i/o i/o af25 v ddp v ddp v ddp ae6 i/o i/o i/o af26 v ddp v ddp v ddp ae7 i/o i/o i/o b1 v ddp v ddp v ddp ae8 i/o i/o i/o b2 v ddp v ddp v ddp ae9 i/o i/o i/o b3 i/o i/o i/o ae10 i/o i/o i/o b4 i/o i/o i/o ae11 i/o i/o i/o b5 i/o i/o i/o ae12 i/o i/o i/o b6 i/o i/o i/o ae13 i/o i/o i/o b7 i/o i/o i/o ae14 i/o i/o i/o b8 i/o i/o i/o ae15 i/o i/o i/o b9 i/o i/o i/o ae16 i/o i/o i/o b10 i/o i/o i/o ae17 i/o i/o i/o b11 i/o i/o i/o ae18 i/o i/o i/o b12 i/o i/o i/o ae19 i/o i/o i/o b13 i/o i/o i/o ae20 i/o i/o i/o b14 i/o i/o i/o ae21 i/o i/o i/o b15 i/o i/o i/o ae22 i/o i/o i/o b16 i/o i/o i/o ae23 v pn v pn v pn b17 i/o i/o i/o ae24 trst trst trst b18 i/o i/o i/o 456-pin pbga (continued) pin number a500k130 function a500k180 function a500k270 function pin number a500k130 function a500k180 function a500k270 function
proasic ? 500k family 52 v3.0 b19 i/o i/o i/o d13 i/o i/o i/o b20 i/o i/o i/o d14 i/o i/o i/o b21 i/o i/o i/o d15 i/o i/o i/o b22 i/o i/o i/o d16 i/o i/o i/o b23 i/o i/o i/o d17 i/o i/o i/o b24 i/o i/o i/o d18 i/o i/o i/o b25 v ddp v ddp v ddp d19 i/o i/o i/o b26 v ddp v ddp v ddp d20 i/o i/o i/o c1 v ddp v ddp v ddp d21 i/o i/o i/o c2 i/o i/o i/o d22 i/o i/o i/o c3 v ddp v ddp v ddp d23 v ddp v ddp v ddp c4 i/o i/o i/o d24 i/o i/o i/o c5 i/o i/o i/o d25 i/o i/o i/o c6 i/o i/o i/o d26 i/o i/o i/o c7 i/o i/o i/o e1 nc i/o i/o c8 i/o i/o i/o e2 i/o i/o i/o c9 i/o i/o i/o e3 i/o i/o i/o c10 i/o i/o i/o e4 i/o i/o i/o c11 i/o i/o i/o e5 v ddl v ddl v ddl c12 i/o i/o i/o e6 v ddl v ddl v ddl c13 i/o i/o i/o e7 v ddl v ddl v ddl c14 i/o i/o i/o e8 v ddl v ddl v ddl c15 i/o i/o i/o e9 i/o i/o i/o c16 i/o i/o i/o e10 i/o i/o i/o c17 i/o i/o i/o e11 i/o i/o i/o c18 i/o i/o i/o e12 i/o i/o i/o c19 i/o i/o i/o e13 i/o i/o i/o c20 i/o i/o i/o e14 i/o i/o i/o c21 i/o i/o i/o e15 i/o i/o i/o c22 i/o i/o i/o e16 i/o i/o i/o c23 i/o i/o i/o e17 i/o i/o i/o c24 v ddp v ddp v ddp e18 i/o i/o i/o c25 i/o i/o i/o e19 i/o i/o i/o c26 nc i/o i/o e20 v ddl v ddl v ddl d1 nc i/o i/o e21 v ddl v ddl v ddl d2 i/o i/o i/o e22 v ddl v ddl v ddl d3 i/o i/o i/o e23 i/o i/o i/o d4 v ddp v ddp v ddp e24 i/o i/o i/o d5 i/o i/o i/o e25 i/o i/o i/o d6 i/o i/o i/o e26 i/o i/o i/o d7 i/o i/o i/o f1 i/o i/o i/o d8 i/o i/o i/o f2 i/o i/o i/o d9 i/o i/o i/o f3 i/o i/o i/o d10 i/o i/o i/o f4 i/o i/o i/o d11 i/o i/o i/o f5 v ddl v ddl v ddl d12 i/o i/o i/o f22 v ddl v ddl v ddl 456-pin pbga (continued) pin number a500k130 function a500k180 function a500k270 function pin number a500k130 function a500k180 function a500k270 function
v3.0 53 proasic ? 500k family f23 i/o i/o i/o l3 i/o i/o i/o f24 i/o i/o i/o l4 i/o i/o i/o f25 i/o i/o i/o l5 i/o i/o i/o f26 nc i/o i/o l11 gnd gnd gnd g1 nc i/o i/o l12 gnd gnd gnd g2 i/o i/o i/o l13 gnd gnd gnd g3 i/o i/o i/o l14 gnd gnd gnd g4 i/o i/o i/o l15 gnd gnd gnd g5 v ddl v ddl v ddl l16 gnd gnd gnd g22 v ddl v ddl v ddl l22 i/o i/o i/o g23 i/o i/o i/o l23 i/o i/o i/o g24 i/o i/o i/o l24 i/o i/o i/o g25 i/o i/o i/o l25 i/o i/o i/o g26 i/o i/o i/o l26 nc i/o i/o h1 nc i/o i/o m1 gl gl gl h2 i/o i/o i/o m2 gl gl gl h3 i/o i/o i/o m3 i/o i/o i/o h4 i/o i/o i/o m4 i/o i/o i/o h5 v ddl v ddl v ddl m5 i/o i/o i/o h22 v ddl v ddl v ddl m11 gnd gnd gnd h23 i/o i/o i/o m12 gnd gnd gnd h24 i/o i/o i/o m13 gnd gnd gnd h25 i/o i/o i/o m14 gnd gnd gnd h26 nc i/o i/o m15 gnd gnd gnd j1 i/o i/o i/o m16 gnd gnd gnd j2 i/o i/o i/o m22 gl gl gl j3 i/o i/o i/o m23 i/o i/o i/o j4 i/o i/o i/o m24 i/o i/o i/o j5 i/o i/o i/o m25 i/o i/o i/o j22 i/o i/o i/o m26 nc i/o i/o j23 i/o i/o i/o n1 nc i/o i/o j24 i/o i/o i/o n2 i/o i/o i/o j25 i/o i/o i/o n3 i/o i/o i/o j26 nc i/o i/o n4 i/o i/o i/o k1 nc i/o i/o n5 i/o i/o i/o k2 i/o i/o i/o n11 gnd gnd gnd k3 i/o i/o i/o n12 gnd gnd gnd k4 i/o i/o i/o n13 gnd gnd gnd k5 i/o i/o i/o n14 gnd gnd gnd k22 i/o i/o i/o n15 gnd gnd gnd k23 i/o i/o i/o n16 gnd gnd gnd k24 i/o i/o i/o n22 i/o i/o i/o k25 i/o i/o i/o n23 gl gl gl k26 i/o i/o i/o n24 i/o i/o i/o l1 nc i/o i/o n25 i/o i/o i/o l2 i/o i/o i/o n26 i/o i/o i/o 456-pin pbga (continued) pin number a500k130 function a500k180 function a500k270 function pin number a500k130 function a500k180 function a500k270 function
proasic ? 500k family 54 v3.0 p1 nc i/o i/o t23 i/o i/o i/o p2 i/o i/o i/o t24 i/o i/o i/o p3 i/o i/o i/o t25 i/o i/o i/o p4 i/o i/o i/o t26 i/o i/o i/o p5 i/o i/o i/o u1 nc i/o i/o p11 gnd gnd gnd u2 i/o i/o i/o p12 gnd gnd gnd u3 i/o i/o i/o p13 gnd gnd gnd u4 i/o i/o i/o p14 gnd gnd gnd u5 i/o i/o i/o p15 gnd gnd gnd u22 i/o i/o i/o p16 gnd gnd gnd u23 i/o i/o i/o p22 i/o i/o i/o u24 i/o i/o i/o p23 i/o i/o i/o u25 i/o i/o i/o p24 i/o i/o i/o u26 nc i/o i/o p25 i/o i/o i/o v1 i/o i/o i/o p26 nc i/o i/o v2 i/o i/o i/o r1 i/o i/o i/o v3 i/o i/o i/o r2 i/o i/o i/o v4 i/o i/o i/o r3 i/o i/o i/o v5 i/o i/o i/o r4 i/o i/o i/o v22 i/o i/o i/o r5 i/o i/o i/o v23 i/o i/o i/o r11 gnd gnd gnd v24 i/o i/o i/o r12 gnd gnd gnd v25 i/o i/o i/o r13 gnd gnd gnd v26 nc i/o i/o r14 gnd gnd gnd w1 nc i/o i/o r15 gnd gnd gnd w2 i/o i/o i/o r16 gnd gnd gnd w3 i/o i/o i/o r22 i/o i/o i/o w4 i/o i/o i/o r23 i/o i/o i/o w5 v ddl v ddl v ddl r24 i/o i/o i/o w22 v ddl v ddl v ddl r25 i/o i/o i/o w23 i/o i/o i/o r26 nc i/o i/o w24 i/o i/o i/o t1 nc i/o i/o w25 i/o i/o i/o t2 i/o i/o i/o w26 i/o i/o i/o t3 i/o i/o i/o y1 nc i/o i/o t4 i/o i/o i/o y2 i/o i/o i/o t5 i/o i/o i/o y3 i/o i/o i/o t11 gnd gnd gnd y4 i/o i/o i/o t12 gnd gnd gnd y5 v ddl v ddl v ddl t13 gnd gnd gnd y22 v ddl v ddl v ddl t14 gnd gnd gnd y23 i/o i/o i/o t15 gnd gnd gnd y24 i/o i/o i/o t16 gnd gnd gnd y25 i/o i/o i/o t22 i/o i/o i/o y26 nc i/o i/o 456-pin pbga (continued) pin number a500k130 function a500k180 function a500k270 function pin number a500k130 function a500k180 function a500k270 function
v3.0 55 proasic ? 500k family package assignments (continued) 144-fbga (bottom view) 1 2 3 4 5 6 7 8 9 10 11 12 a b c d e f g h j k l m
proasic ? 500k family 56 v3.0 144-pin fbga pin number a500k050 function a500k130 function pin number a500k050 function a500k130 function pin number a500k050 function a500k130 function a1 i/o i/o d1 i/o i/o g1 i/o i/o a2 i/o i/o d2 i/o i/o g2 gnd gnd a3 i/o i/o d3 i/o i/o g3 i/o i/o a4 i/o i/o d4 i/o i/o g4 i/o i/o a5 i/o i/o d5 i/o i/o g5 gnd gnd a6 gnd gnd d6 i/o i/o g6 gnd gnd a7 i/o i/o d7 i/o i/o g7 gnd gnd a8 v ddl v ddl d8 i/o i/o g8 i/o i/o a9 i/o i/o d9 i/o i/o g9 i/o i/o a10 i/o i/o d10 i/o i/o g10 i/o i/o a11 i/o i/o d11 i/o i/o g11 i/o i/o a12 i/o i/o d12 i/o i/o g12 i/o i/o b1 i/o i/o e1 v ddl v ddl h1 v ddl v ddl b2 gnd gnd e2 i/o i/o h2 i/o i/o b3 i/o i/o e3 i/o i/o h3 i/o i/o b4 i/o i/o e4 v ddp v ddp h4 i/o i/o b5 i/o i/o e5 i/o i/o h5 v ddl v ddl b6 i/o i/o e6 v ddp v ddp h6 i/o i/o b7 i/o i/o e7 v ddp v ddp h7 i/o i/o b8 i/o i/o e8 i/o i/o h8 i/o i/o b9 i/o i/o e9 v ddp v ddp h9 i/o i/o b10 i/o i/o e10 v ddl v ddl h10 v ddp v ddp b11 gnd gnd e11 i/o i/o h11 i/o i/o b12 i/o i/o e12 i/o i/o h12 v ddl v ddl c1 i/o i/o f1 gl gl j1 i/o i/o c2 gl gl f2 i/o i/o j2 i/o i/o c3 i/o i/o f3 i/o i/o j3 v ddp v ddp c4 v ddl v ddl f4 i/o i/o j4 i/o i/o c5 i/o i/o f5 gnd gnd j5 i/o i/o c6 i/o i/o f6 gnd gnd j6 i/o i/o c7 i/o i/o f7 gnd gnd j7 v ddl v ddl c8 i/o i/o f8 i/o i/o j8 tck tck c9 i/o i/o f9 gl gl j9 i/o i/o c10 i/o i/o f10 gnd gnd j10 tdo tdo c11 i/o i/o f11 i/o i/o j11 i/o i/o c12 i/o i/o f12 gl gl j12 i/o i/o
v3.0 57 proasic ? 500k family k1 i/o i/o l1 gnd gnd m1 i/o i/o k2 i/o i/o l2 i/o i/o m2 i/o i/o k3 i/o i/o l3 i/o i/o m3 i/o i/o k4 i/o i/o l4 i/o i/o m4 i/o i/o k5 i/o i/o l5 v ddp v ddp m5 i/o i/o k6 i/o i/o l6 i/o i/o m6 i/o i/o k7 gnd gnd l7 i/o i/o m7 i/o i/o k8 i/o i/o l8 i/o i/o m8 i/o i/o k9 i/o i/o l9 tms tms m9 tdi tdi k10 gnd gnd l10 rck rck m10 v ddp v ddp k11 i/o i/o l11 i/o i/o m11 v pp v pp k12 i/o i/o l12 trst trst m12 v pn v pn 144-pin fbga (continued) pin number a500k050 function a500k130 function pin number a500k050 function a500k130 function pin number a500k050 function a500k130 function
proasic ? 500k family 58 v3.0 package assignments (continued) 256-fbga (bottom view) 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 c e g j l n r d f h k m p t b a pin one corner
v3.0 59 proasic ? 500k family 256-pin fbga pin number a500k130 function a500k180 function a500k270 function pin number a500k130 function a500k180 function a500k270 function a1 gnd gnd gnd c8 i/o i/o i/o a2 i/o i/o i/o c9 i/o i/o i/o a3 i/o i/o i/o c10 i/o i/o i/o a4 i/o i/o i/o c11 i/o i/o i/o a5 i/o i/o i/o c12 i/o i/o i/o a6 i/o i/o i/o c13 i/o i/o i/o a7 i/o i/o i/o c14 i/o i/o i/o a8 i/o i/o i/o c15 i/o i/o i/o a9 i/o i/o i/o c16 i/o i/o i/o a10 i/o i/o i/o d1 i/o i/o i/o a11 i/o i/o i/o d2 i/o i/o i/o a12 i/o i/o i/o d3 i/o i/o i/o a13 i/o i/o i/o d4 i/o i/o i/o a14 i/o i/o i/o d5 i/o i/o i/o a15 i/o i/o i/o d6 i/o i/o i/o a16 gnd gnd gnd d7 i/o i/o i/o b1 i/o i/o i/o d8 i/o i/o i/o b2 i/o i/o i/o d9 i/o i/o i/o b3 i/o i/o i/o d10 i/o i/o i/o b4 i/o i/o i/o d11 i/o i/o i/o b5 i/o i/o i/o d12 i/o i/o i/o b6 i/o i/o i/o d13 i/o i/o i/o b7 i/o i/o i/o d14 i/o i/o i/o b8 i/o i/o i/o d15 i/o i/o i/o b9 i/o i/o i/o d16 i/o i/o i/o b10 i/o i/o i/o e1 i/o i/o i/o b11 i/o i/o i/o e2 i/o i/o i/o b12 i/o i/o i/o e3 i/o i/o i/o b13 i/o i/o i/o e4 i/o i/o i/o b14 i/o i/o i/o e5 i/o i/o i/o b15 i/o i/o i/o e6 v ddp v ddp v ddp b16 i/o i/o i/o e7 v ddp v ddp v ddp c1 i/o i/o i/o e8 i/o i/o i/o c2 i/o i/o i/o e9 i/o i/o i/o c3 i/o i/o i/o e10 v ddp v ddp v ddp c4 i/o i/o i/o e11 v ddp v ddp v ddp c5 i/o i/o i/o e12 i/o i/o i/o c6 i/o i/o i/o e13 i/o i/o i/o c7 i/o i/o i/o e14 i/o i/o i/o
proasic ? 500k family 60 v3.0 e15 i/o i/o i/o h6 v ddl v ddl v ddl e16 i/o i/o i/o h7 gnd gnd gnd f1 i/o i/o i/o h8 gnd gnd gnd f2 i/o i/o i/o h9 gnd gnd gnd f3 i/o i/o i/o h10 gnd gnd gnd f4 i/o i/o i/o h11 v ddl v ddl v ddl f5 v ddp v ddp v ddp h12 i/o i/o i/o f6 gnd gnd gnd h13 i/o i/o i/o f7 v ddl v ddl v ddl h14 i/o i/o i/o f8 v ddl v ddl v ddl h15 i/o i/o i/o f9 v ddl v ddl v ddl h16 gl gl gl f10 v ddl v ddl v ddl j1 gl gl gl f11 gnd gnd gnd j2 i/o i/o i/o f12 v ddp v ddp v ddp j3 i/o i/o i/o f13 i/o i/o i/o j4 i/o i/o i/o f14 i/o i/o i/o j5 i/o i/o i/o f15 i/o i/o i/o j6 v ddl v ddl v ddl f16 i/o i/o i/o j7 gnd gnd gnd g1 i/o i/o i/o j8 gnd gnd gnd g2 i/o i/o i/o j9 gnd gnd gnd g3 i/o i/o i/o j10 gnd gnd gnd g4 i/o i/o i/o j11 v ddl v ddl v ddl g5 v ddp v ddp v ddp j12 i/o i/o i/o g6 v ddl v ddl v ddl j13 i/o i/o i/o g7 gnd gnd gnd j14 i/o i/o i/o g8 gnd gnd gnd j15 i/o i/o i/o g9 gnd gnd gnd j16 gl gl gl g10 gnd gnd gnd k1 i/o i/o i/o g11 v ddl v ddl v ddl k2 i/o i/o i/o g12 v ddp v ddp v ddp k3 i/o i/o i/o g13 i/o i/o i/o k4 i/o i/o i/o g14 i/o i/o i/o k5 v ddp v ddp v ddp g15 i/o i/o i/o k6 v ddl v ddl v ddl g16 i/o i/o i/o k7 gnd gnd gnd h1 gl gl gl k8 gnd gnd gnd h2 i/o i/o i/o k9 gnd gnd gnd h3 i/o i/o i/o k10 gnd gnd gnd h4 i/o i/o i/o k11 v ddl v ddl v ddl h5 i/o i/o i/o k12 v ddp v ddp v ddp 256-pin fbga (continued) pin number a500k130 function a500k180 function a500k270 function pin number a500k130 function a500k180 function a500k270 function
v3.0 61 proasic ? 500k family k13 i/o i/o i/o n4 i/o i/o i/o k14 i/o i/o i/o n5 i/o i/o i/o k15 i/o i/o i/o n6 i/o i/o i/o k16 i/o i/o i/o n7 i/o i/o i/o l1 i/o i/o i/o n8 i/o i/o i/o l2 i/o i/o i/o n9 i/o i/o i/o l3 i/o i/o i/o n10 i/o i/o i/o l4 i/o i/o i/o n11 i/o i/o i/o l5 v ddp v ddp v ddp n12 i/o i/o i/o l6 gnd gnd gnd n13 i/o i/o i/o l7 v ddl v ddl v ddl n14 rck rck rck l8 v ddl v ddl v ddl n15 i/o i/o i/o l9 v ddl v ddl v ddl n16 i/o i/o i/o l10 v ddl v ddl v ddl p1 i/o i/o i/o l11 gnd gnd gnd p2 i/o i/o i/o l12 v ddp v ddp v ddp p3 i/o i/o i/o l13 i/o i/o i/o p4 i/o i/o i/o l14 i/o i/o i/o p5 i/o i/o i/o l15 i/o i/o i/o p6 i/o i/o i/o l16 i/o i/o i/o p7 i/o i/o i/o m1 i/o i/o i/o p8 i/o i/o i/o m2 i/o i/o i/o p9 i/o i/o i/o m3 i/o i/o i/o p10 i/o i/o i/o m4 i/o i/o i/o p11 i/o i/o i/o m5 i/o i/o i/o p12 i/o i/o i/o m6 v ddp v ddp v ddp p13 tck tck tck m7 v ddp v ddp v ddp p14 v pp v pp v pp m8 i/o i/o i/o p15 trst trst trst m9 i/o i/o i/o p16 i/o i/o i/o m10 v ddp v ddp v ddp r1 i/o i/o i/o m11 v ddp v ddp v ddp r2 i/o i/o i/o m12 i/o i/o i/o r3 i/o i/o i/o m13 i/o i/o i/o r4 i/o i/o i/o m14 i/o i/o i/o r5 i/o i/o i/o m15 i/o i/o i/o r6 i/o i/o i/o m16 i/o i/o i/o r7 i/o i/o i/o n1 i/o i/o i/o r8 i/o i/o i/o n2 i/o i/o i/o r9 i/o i/o i/o n3 i/o i/o i/o r10 i/o i/o i/o 256-pin fbga (continued) pin number a500k130 function a500k180 function a500k270 function pin number a500k130 function a500k180 function a500k270 function
proasic ? 500k family 62 v3.0 r11 i/o i/o i/o t6 i/o i/o i/o r12 i/o i/o i/o t7 i/o i/o i/o r13 i/o i/o i/o t8 i/o i/o i/o r14 tdi tdi tdi t9 i/o i/o i/o r15 v pn v pn v pn t10 i/o i/o i/o r16 tdo tdo tdo t11 i/o i/o i/o t1 gnd gnd gnd t12 i/o i/o i/o t2 i/o i/o i/o t13 i/o i/o i/o t3 i/o i/o i/o t14 i/o i/o i/o t4 i/o i/o i/o t15 tms tms tms t5 i/o i/o i/o t16 gnd gnd gnd 256-pin fbga (continued) pin number a500k130 function a500k180 function a500k270 function pin number a500k130 function a500k180 function a500k270 function
v3.0 63 proasic ? 500k family package assignments (continued) 676-pin fbga (bottom view) 1 2 3 5 6 7 8 9 10 11 15 14 13 12 16 17 18 19 20 21 22 23 4 24 25 26 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af
proasic ? 500k family 64 v3.0 676-pin fbga pin number a500k270 function pin number a500k270 function pin number a500k270 function pin number a500k270 function pin number a500k270 function a1 gnd aa13 i/o ab25 i/o ad11 i/o ae23 i/o a2 gnd aa14 i/o ab26 i/o ad12 i/o ae24 i/o a3 i/o aa15 i/o ac1 i/o ad13 i/o ae25 gnd a4 i/o aa16 i/o ac2 i/o ad14 i/o ae26 gnd a5 i/o aa17 i/o ac3 i/o ad15 i/o af1 gnd a6 i/o aa18 i/o ac4 i/o ad16 i/o af2 gnd a7 i/o aa19 i/o ac5 gnd ad17 i/o af3 gnd a8 i/o aa20 i/o ac6 i/o ad18 i/o af4 gnd a9 i/o aa21 tdo ac7 i/o ad19 i/o af5 i/o a10 i/o aa22 gnd ac8 i/o ad20 i/o af6 i/o a11 i/o aa23 gnd ac9 gnd ad21 i/o af7 i/o a12 i/o aa24 i/o ac10 i/o ad22 i/o af8 i/o a13 i/o aa25 i/o ac11 i/o ad23 tdi af9 i/o a14 i/o aa26 i/o ac12 i/o ad24 v pn af10 i/o a15 i/o ab1 i/o ac13 i/o ad25 i/o af11 i/o a16 i/o ab2 i/o ac14 i/o ad26 i/o af12 i/o a17 i/o ab3 i/o ac15 i/o ae1 gnd af13 i/o a18 i/o ab4 i/o ac16 i/o ae2 gnd af14 i/o a19 i/o ab5 i/o ac17 i/o ae3 gnd af15 i/o a20 i/o ab6 gnd ac18 i/o ae4 i/o af16 i/o a21 i/o ab7 gnd ac19 i/o ae5 i/o af17 i/o a22 i/o ab8 i/o ac20 i/o ae6 i/o af18 i/o a23 i/o ab9 i/o ac21 i/o ae7 i/o af19 i/o a24 i/o ab10 i/o ac22 tms ae8 i/o af20 i/o a25 gnd ab11 i/o ac23 rck ae9 i/o af21 i/o a26 gnd ab12 i/o ac24 i/o ae10 i/o af22 i/o aa1 i/o ab13 i/o ac25 i/o ae11 i/o af23 i/o aa2 i/o ab14 i/o ac26 i/o ae12 i/o af24 i/o aa3 i/o ab15 i/o ad1 i/o ae13 i/o af25 gnd aa4 i/o ab16 i/o ad2 i/o ae14 i/o af26 gnd aa5 i/o ab17 i/o ad3 i/o ae15 i/o b1 gnd aa6 gnd ab18 i/o ad4 i/o ae16 i/o b2 gnd aa7 i/o ab19 i/o ad5 i/o ae17 i/o b3 gnd aa8 i/o ab20 i/o ad6 i/o ae18 i/o b4 gnd aa9 i/o ab21 tck ad7 i/o ae19 i/o b5 i/o aa10 i/o ab22 trst ad8 i/o ae20 i/o b6 i/o aa11 i/o ab23 i/o ad9 i/o ae21 i/o b7 i/o aa12 i/o ab24 i/o ad10 i/o ae22 i/o b8 i/o
v3.0 65 proasic ? 500k family b9 i/o c21 i/o e7 i/o f19 i/o h5 i/o b10 i/o c22 i/o e8 i/o f20 i/o h6 i/o b11 i/o c23 i/o e9 i/o f21 i/o h7 v ddp b12 i/o c24 i/o e10 i/o f22 i/o h8 v ddl b13 i/o c25 i/o e11 i/o f23 i/o h9 v ddp b14 i/o c26 i/o e12 i/o f24 i/o h10 v ddp b15 i/o d1 i/o e13 i/o f25 i/o h11 v ddp b16 i/o d2 i/o e14 i/o f26 i/o h12 v ddp b17 i/o d3 gnd e15 i/o g1 i/o h13 v ddp b18 i/o d4 i/o e16 i/o g2 i/o h14 v ddp b19 i/o d5 i/o e17 i/o g3 i/o h15 v ddp b20 i/o d6 i/o e18 i/o g4 i/o h16 v ddp b21 i/o d7 i/o e19 i/o g5 i/o h17 v ddp b22 i/o d8 i/o e20 i/o g6 i/o h18 v ddp b23 i/o d9 i/o e21 i/o g7 i/o h19 v ddl b24 i/o d10 i/o e22 i/o g8 v ddl h20 v ddl b25 gnd d11 i/o e23 i/o g9 nc h21 i/o b26 gnd d12 i/o e24 i/o g10 nc h22 i/o c1 gnd d13 i/o e25 i/o g11 nc h23 i/o c2 gnd d14 i/o e26 i/o g12 nc h24 i/o c3 gnd d15 i/o f1 i/o g13 nc h25 i/o c4 gnd d16 i/o f2 i/o g14 nc h26 i/o c5 i/o d17 i/o f3 i/o g15 nc j1 i/o c6 i/o d18 i/o f4 i/o g16 nc j2 i/o c7 i/o d19 i/o f5 gnd g17 nc j3 i/o c8 i/o d20 i/o f6 i/o g18 nc j4 i/o c9 i/o d21 i/o f7 nc g20 nc j5 i/o c10 i/o d22 i/o f8 i/o g19 v ddp j6 i/o c11 i/o d23 i/o f9 i/o g21 i/o j7 nc c12 i/o d24 i/o f10 i/o g22 i/o j8 v ddp c13 i/o d25 i/o f11 i/o g23 i/o j9 v ddl c14 i/o d26 i/o f12 i/o g24 i/o j10 v ddl c15 i/o e1 i/o f13 i/o g25 i/o j11 v ddl c16 i/o e2 i/o f14 i/o g26 i/o j12 v ddl c17 i/o e3 i/o f15 i/o h1 i/o j13 v ddl c18 i/o e4 i/o f16 i/o h2 i/o j14 v ddl c19 i/o e5 i/o f17 i/o h3 i/o j15 v ddl c20 i/o e6 i/o f18 i/o h4 i/o j16 v ddl 676-pin fbga (continued) pin number a500k270 function pin number a500k270 function pin number a500k270 function pin number a500k270 function pin number a500k270 function
proasic ? 500k family 66 v3.0 j17 v ddl l3 i/o m15 gnd p1 gl r13 gnd j18 v ddl l4 i/o m16 gnd p2 i/o r14 gnd j19 v ddp l5 i/o m17 gnd p3 i/o r15 gnd j20 nc l6 i/o m18 v ddl p4 i/o r16 gnd j21 i/o l7 nc m19 v ddp p5 i/o r17 gnd j22 i/o l8 v ddp m20 nc p6 i/o r18 v ddl j23 i/o l9 v ddl m21 i/o p7 nc r19 v ddp j24 i/o l10 gnd m22 i/o p8 v ddp r20 nc j25 i/o l11 gnd m23 i/o p9 v ddl r21 i/o j26 i/o l12 gnd m24 i/o p10 gnd r22 i/o k1 i/o l13 gnd m25 i/o p11 gnd r23 i/o k2 i/o l14 gnd m26 i/o p12 gnd r24 i/o k3 i/o l15 gnd n1 gl p13 gnd r25 i/o k4 i/o l16 gnd n2 i/o p14 gnd r26 i/o k5 i/o l17 gnd n3 i/o p15 gnd t1 i/o k6 i/o l18 v ddl n4 i/o p16 gnd t2 i/o k7 nc l19 v ddp n5 i/o p17 gnd t3 i/o k8 v ddp l20 nc n6 i/o p18 v ddl t4 i/o k9 v ddl l21 i/o n7 nc p19 v ddp t5 i/o k10 gnd l22 i/o n8 v ddp p20 nc t6 i/o k11 gnd l23 i/o n9 v ddl p21 i/o t7 nc k12 gnd l24 i/o n10 gnd p22 i/o t8 v ddp k13 gnd l25 i/o n11 gnd p23 i/o t9 v ddl k14 gnd l26 i/o n12 gnd p24 i/o t10 gnd k15 gnd m1 i/o n13 gnd p25 i/o t11 gnd k16 gnd m2 i/o n14 gnd p26 i/o t12 gnd k17 gnd m3 i/o n15 gnd r1 i/o t13 gnd k18 v ddl m4 i/o n16 gnd r2 i/o t14 gnd k19 v ddp m5 i/o n17 gnd r3 i/o t15 gnd k20 nc m6 i/o n18 v ddl r4 i/o t16 gnd k21 i/o m7 nc n19 v ddp r5 i/o t17 gnd k22 i/o m8 v ddp n20 nc r6 i/o t18 v ddl k23 i/o m9 v ddl n21 i/o r7 nc t19 v ddp k24 i/o m10 gnd n22 gl r8 v ddp t20 nc k25 i/o m11 gnd n23 i/o r9 v ddl t21 i/o k26 i/o m12 gnd n24 i/o r10 gnd t22 i/o l1 i/o m13 gnd n25 gl r11 gnd t23 i/o l2 i/o m14 gnd n26 i/o r12 gnd t24 i/o 676-pin fbga (continued) pin number a500k270 function pin number a500k270 function pin number a500k270 function pin number a500k270 function pin number a500k270 function
v3.0 67 proasic ? 500k family t25 i/o u20 nc v15 v ddl w10 v ddp y5 i/o t26 i/o u21 i/o v16 v ddl w11 v ddp y6 i/o u1 i/o u22 i/o v17 v ddl w12 v ddp y7 i/o u2 i/o u23 i/o v18 v ddl w13 v ddp y8 v ddp u3 i/o u24 i/o v19 v ddp w14 v ddp y9 nc u4 i/o u25 i/o v20 nc w15 v ddp y10 nc u5 i/o u26 i/o v21 i/o w16 v ddp y11 nc u6 i/o v1 i/o v22 i/o w17 v ddp y12 nc u7 nc v2 i/o v23 i/o w18 v ddp y13 nc u8 v ddp v3 i/o v24 i/o w19 v ddl y14 nc u9 v ddl v4 i/o v25 i/o w20 v ddp y15 nc u10 gnd v5 i/o v26 i/o w21 i/o y16 nc u11 gnd v6 i/o w1 i/o w22 i/o y17 nc u12 gnd v7 nc w2 i/o w23 i/o y18 nc u13 gnd v8 v ddp w3 i/o w24 i/o y19 v ddl u14 gnd v9 v ddl w4 i/o w25 i/o y20 v pp u15 gnd v10 v ddl w5 i/o w26 i/o y21 i/o u16 gnd v11 v ddl w6 i/o y1 i/o y22 i/o u17 gnd v12 v ddl w7 v ddl y2 i/o y23 i/o u18 v ddl v13 v ddl w8 v ddl y3 i/o y24 i/o u19 v ddp v14 v ddl w9 v ddp y4 i/o y25 i/o y26 i/o 676-pin fbga (continued) pin number a500k270 function pin number a500k270 function pin number a500k270 function pin number a500k270 function pin number a500k270 function
proasic ? 500k family 68 v3.0 list of changes the following table lists critical changes that were made in the current version of the document. previous version changes in current version (v3.0) page v2.0 wdata has been changed to di, and rdata has been changed to do to make them consistent with the signal names found in the macro library guide . preliminary v1.1 the ? product plan ? on page 3 has been updated to include the 256-fbga package. page 3 the ? plastic device resources ? on page 3 has been updated to include the 256-fbga package. page 3 figure 12 and figure 13 on page 13 have been updated. page 13 the ? design environment ? on page 15 and figure 17 on page 15 have been updated. page 15 package thermal characteristics table on page 16 has been updated to include the 256-fbga package. page 16 the ? calculating power dissipation ? on page 17 has been changed. page 17 the ? programming and storage temperature limits ? on page 18 is new. page 18 the ? dc electrical specifications (v ddp = 2.5v) ? on page 19 has been updated. page 19 the ? dc electrical specifications (v ddp = 3.3v) ? on page 20 has been updated. page 20 the table 4 on page 28 has been updated. page 28 the table 5 on page 34 has been updated. page 34 the ? 256-fbga (bottom view) ? on page 58 is new. page 58 preliminary v1.0 in the ? 676-pin fbga (bottom view) ? on page 63 , the functions for pins n1, n22, n25, and p1 have changed from i/o to gl page 59 advanced v.4 the section, ? clock trees ? on page 8 is new. page 8 the table, ? dc electrical specifications (v ddp = 3.3v) ? on page 20 is new. page 18 the table, ? ac specifications (3.3v pci operation) ? on page 22 is new. page 20 the table, the ? slew rates measured at cout = 10pf (total output load), nominal power supplies and 25 c ? on page 24 is new. page 22 the numbers found in the ? tristate buffer delays (worst-case commercial conditions, v ddp = 3.0v, v ddl = 2.3v, t j = 70 c, fclock = 250 mhz) ? on page 25 have changed. page 23 the numbers found in the ? output buffer delays (worst-case commercial conditions, v ddp = 3.0v, v ddl = 2.3v, t j = 70 c, fclock = 250 mhz) ? on page 26 have changed. page 24 the numbers found in the ? input buffer delays (worst-case commercial conditions, v ddp = 3.0v, v ddl = 2.3v, t j = 70 c, fclock = 250 mhz) ? on page 26 have changed. page 24 the numbers found in the ? global input buffer delays (worst-case commercial conditions, v ddp = 3.0v, v ddl = 2.3v, t j = 70 c, fclock = 250 mhz) ? on page 27 have changed. page 25 the ? 144-fbga (bottom view) ? on page 55 for a500k050 is new. pages 53-55 the ? 676-pin fbga (bottom view) ? on page 63 for a500k130 and a500k270 are new. pages 56-60
v3.0 69 proasic ? 500k family data sheet categories in order to provide the latest information to designers, some data sheets are published before data has been fully characterized. these data sheets are marked as ? advanced ? or preliminary ? data sheets. the definition of these categories are as follows: advanced the data sheet contains initial estimated information based on simulation, other products, devices, or speed grades. this information can be used as estimates, but not for production. preliminary the data sheet contains information based on simulation and/or initial characterization. the information is believed to be correct, but changes are possible. unmarked (production) the data sheet contains information that is considered to be final. web-only versions web-only versions have three numbers in the version number (example: v2.0.1). a web-only version means actel is posting the data sheet so customers have the latest information, but we are not printing the version because some information is going to change shortly after posting.

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